Parallel carrier signal synchronization system for string inverter

Abstract

The application provides a parallel carrier signal synchronization system of a string inverter, and belongs to the technical field of inverter control. The system comprises a host and a plurality of slaves. A first CPLD unit of the host generates a carrier synchronization signal, which is transmitted in two ways. The first way is to send the carrier synchronization signal to a first DSP unit of the host after a first delay of a carrier signal delay unit of the host. The second way is to transmit the carrier synchronization signal to a second DSP unit of the slave in sequence after passing through a first isolation unit of the host, a second isolation unit of the slave, a second CPLD unit of the slave and a carrier signal filter unit of the slave. The delay time of the first delay of the signal matches the sum of the transmission delay time caused by the transmission of the carrier synchronization signal from the first CPLD unit to the second DSP unit and the filter delay time, so as to synchronize the carrier signals of the host and the slave. The system can effectively suppress the high-frequency circulating current when the multiple inverters are connected in parallel, and improve the system operation efficiency and stability.

Description

Technical Field

[0001] This application relates to the field of inverter control technology, specifically to a parallel carrier signal synchronization system for a string inverter. Background Technology

[0002] In the field of new energy power generation and energy storage systems, string inverters, with their flexible power capacity adjustment capabilities, can be easily adapted to energy systems of different scales according to actual needs, while significantly improving the redundancy and operational reliability of energy storage systems. They have become one of the core devices in high-power application scenarios (such as large photovoltaic power plants and centralized energy storage power plants).

[0003] In the actual operation of string inverters, when multiple inverters need to operate in parallel on both AC and DC sides to meet higher power output requirements, a key technical challenge lies in suppressing high-frequency circulating currents between inverters. If the carrier signals of the modulation waves of each inverter are not synchronized, high-frequency circulating currents will be generated in the parallel circuit. This will not only increase equipment losses and reduce energy conversion efficiency, but may also cause problems such as inverter module overheating and shortened service life, and in severe cases, even threaten the stable operation of the entire energy storage system. Therefore, achieving carrier signal synchronization between string inverters is a core prerequisite for ensuring the safe and efficient operation of the system under AC and DC parallel operation conditions.

[0004] Currently, the mainstream carrier synchronization hardware solution in the industry is fiber optic synchronization technology. This technology, due to its strong resistance to electromagnetic interference, long signal transmission distance (meeting the long-distance communication needs between inverters in large power plants), and high synchronization real-time performance (enabling rapid alignment of carrier signals from multiple inverters), has been widely applied in carrier synchronization scenarios of modern photovoltaic and energy storage systems, effectively supporting the stable operation of multi-inverter parallel systems.

[0005] However, in practical engineering applications, fiber optic synchronization technology has limitations such as high cost and difficulty in installation and maintenance. Furthermore, its advantages in anti-interference and long-distance transmission are difficult to fully realize in short-distance scenarios. Therefore, it is necessary to improve existing carrier synchronization technology to address its limitations in short-distance scenarios (such as energy storage cabinets). Summary of the Invention

[0006] The purpose of this invention is to provide a parallel carrier signal synchronization system for a string inverter to solve at least one of the above-mentioned technical problems.

[0007] A parallel carrier signal synchronization system for string inverters, wherein one of the string inverters is set as the master and the remaining inverters are set as slaves;

[0008] The host includes a first CPLD unit, a first isolation unit, a carrier signal delay unit, and a first DSP unit; the slave includes a second CPLD unit, a second isolation unit, a carrier signal filtering unit, and a second DSP unit.

[0009] The first CPLD unit generates a carrier synchronization signal, which is transmitted in two paths: the first path is sent to the first DSP unit after a first signal delay by the carrier signal delay unit, serving as the first synchronization signal source of the first DSP unit; the second path is transmitted to the second DSP unit after passing through the first isolation unit, the second isolation unit, the second CPLD unit, and the carrier signal filtering unit in sequence, serving as the second synchronization signal source of the second DSP unit.

[0010] The delay duration of the first delay of the signal is matched with the sum of the transmission delay duration and the filtering delay duration caused by the transmission of the carrier synchronization signal from the first CPLD unit to the second DSP unit, so as to synchronize the first synchronization signal source with the second synchronization signal source. The filtering delay duration is the delay duration caused by the carrier signal filtering unit filtering the carrier synchronization signal.

[0011] Optionally, the first isolation unit includes a first protection circuit, a first Schmitt inverter, and a first isolator that are connected in sequence.

[0012] The generated carrier synchronization signal is transmitted to the slave device after passing through the first protection circuit, the first Schmitt inverter, and the first isolator in sequence, including:

[0013] After the generated carrier synchronization signal is input from the input terminal of the first protection circuit, the peak current in the carrier synchronization signal is suppressed by the current limiting resistor in the first protection circuit, and then it is input to the first Schmitt inverter.

[0014] The first Schmitt inverter performs edge shaping and noise filtering on the input carrier synchronization signal and then outputs the carrier synchronization signal to the first isolator.

[0015] The first isolator uses magnetic coupling to couple the input carrier synchronization signal to the output side, and then transmits it to the slave device.

[0016] Optionally, the first DSP unit is connected to the second DSP units of each slave unit via a CAN bus; the transmission delay duration is obtained through the following steps:

[0017] Step S11: The first DSP unit sends a delay test command to the second DSP unit of the target slave device through the CAN bus. The delay test command specifies the slave device identifier of the target slave device that needs to participate in the delay test.

[0018] Step S12: The signal input terminal of the first isolation unit is electrically connected to the output terminal of the second isolation unit of the target slave, so that the target slave can feed back the received carrier test signal to the host.

[0019] Step S13: The first CPLD unit of the host generates a carrier test signal and records the generation timestamp of the carrier test signal;

[0020] Step S14: The generated carrier test signal is sent to the second CPLD unit of the target slave after passing through the first isolation unit and the second isolation unit in sequence;

[0021] Step S15: The second CPLD unit of the target slave device forwards the received carrier test signal to the first CPLD unit through the second isolation unit and the first isolation unit in sequence;

[0022] Step S16: The first CPLD unit records the receiving timestamp of the received carrier test signal;

[0023] Step S17: Calculate the transmission delay duration based on the received timestamp and the generated timestamp.

[0024] Optionally, the delay test command includes multiple target slave devices;

[0025] The first CPLD unit records the reception timestamp of the received carrier test signal, including: the first CPLD unit records the reception timestamp of the carrier test signal fed back by each target slave in sequence;

[0026] The step of calculating the transmission delay duration based on the received timestamp and the generated timestamp includes:

[0027] Calculate the average timestamp of each received data.

[0028] The transmission delay duration is calculated based on the received average timestamp and the generated timestamp.

[0029] Optionally, steps S11 to S16 may be repeated multiple times, with the target slave device specified by the delay test instruction being different each time step S11 is executed.

[0030] The step of calculating the transmission delay duration based on the received timestamp and the generated timestamp includes:

[0031] The duration of a single delay is calculated based on the received timestamp and the generated timestamp of each record.

[0032] The average value is calculated based on the duration of each single delay, and the calculated average value is used as the transmission delay duration.

[0033] Optionally, the transmission delay duration is calculated according to the following formula:

[0034] T2 = (T1 - T0) / 2, where T2 represents the transmission delay duration, T1 represents the receiving timestamp, and T0 represents the generating timestamp.

[0035] Optionally, the transmission delay duration is obtained through the following steps:

[0036] Obtain the signal delay parameters of each transmission component;

[0037] The transmission delay duration is calculated based on the signal delay parameter. The transmission component is a component containing a signal delay in the first isolation unit and the second isolation unit when the carrier synchronization signal passes through the first isolation unit and the second isolation unit.

[0038] Optionally, the filtering delay duration is determined based on the pulse width to be removed from the carrier synchronization signal, and the first threshold is determined based on the filtering delay duration and the clock period of the carrier signal filtering unit.

[0039] The carrier signal filtering unit filters the carrier synchronization signal through the following steps:

[0040] Step S21: Clear the first counter to reset it;

[0041] Step S22: The carrier signal filtering unit continuously receives the input pulse signal and detects whether the current input pulse signal is consistent with the previous input pulse signal;

[0042] Step S23: When the current input pulse signal is detected to be inconsistent with the previous input pulse signal, the first counter is cleared to zero. When they are consistent, the continuously input pulse signals are accumulated by the same number of consecutive identical pulse signals through the first counter.

[0043] Step S24: When the number of times the first counter accumulates reaches the preset first count threshold, the output terminal of the carrier signal filtering unit outputs a carrier synchronization signal.

[0044] Optionally, the delay process of the carrier signal delay unit for the carrier synchronization signal includes the following steps:

[0045] Step S31: Clear the second counter to reset it;

[0046] Step S32: The carrier signal delay unit continuously receives the input pulse signal and detects whether the current input pulse signal is consistent with the previous input pulse signal;

[0047] Step S33: When the current input pulse signal is detected to be inconsistent with the previous input pulse signal, the second counter is cleared to zero. When they are consistent, the second counter is used to accumulate the continuously input pulse signals as consecutive identical pulse signals for the same number of times.

[0048] Step S34: When the number of times counted by the second counter reaches the preset second threshold, the output terminal of the carrier signal delay unit outputs a carrier synchronization signal. The second threshold is determined based on the delay duration of the first delay and the clock period of the carrier signal delay unit.

[0049] Optionally, when it is necessary to change the master, one of the multiple slaves is determined as the new master; the second number threshold is written into the carrier signal filtering unit in the new master, so that the carrier signal filtering unit in the new master is changed into a carrier signal delay unit.

[0050] The parallel carrier signal synchronization system for string inverters in this application solves the problem of weak noise immunity in traditional electromagnetic isolation schemes through the synergy of isolation units (electrical isolation) and filtering units (noise removal), adapting to the complex electromagnetic environment of energy storage systems. Compared with fiber optic synchronization schemes, it eliminates the need for dedicated optical fibers and modules, reducing hardware costs, and can simultaneously support multiple slave units in parallel (transmitting signals through the same cable), adapting to the needs of systems with different power scales. The hardware structure of the master and slave units in this system is basically the same, with roles distinguished only by software configuration, facilitating mass production and subsequent maintenance (e.g., a faulty slave unit can be replaced with a backup unit and reconfigured). In addition, this system uses a delay matching mechanism to ensure that the time difference between the DSP units of the master and slave units receiving the synchronization signal is minimal, effectively suppressing high-frequency circulating currents when multiple inverters are connected in parallel, and improving system operating efficiency and stability. Attached Figure Description

[0051] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly described below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation on the scope of this application.

[0052] Figure 1 This is a schematic diagram of the parallel carrier signal synchronization system of a string inverter in one embodiment;

[0053] Figure 2 This is a schematic diagram of the circuit structure of the isolation unit in one embodiment;

[0054] Figure 3 This is a flowchart of a test procedure for transmission delay duration in one embodiment;

[0055] Figure 4This is a schematic diagram of the filtering process of the carrier signal filtering unit on the carrier synchronization signal in one embodiment;

[0056] Figure 5 This is a schematic diagram of the delay process of the carrier signal delay unit for the carrier synchronization signal in one embodiment. Detailed Implementation

[0057] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the scope of this application.

[0058] All terms used in this application (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted in a manner consistent with the context of this specification, and not in an idealized or overly rigid way.

[0059] For example, the terms "first" and "second" used in this application are only used to distinguish similar objects and differentiate the first object from another object, rather than to describe a specific order or sequence, nor should they be interpreted as indicating or implying relative importance.

[0060] This application proposes a parallel carrier signal synchronization system for string inverters. A string inverter is a power electronic conversion device that can achieve power expansion through the combination of multiple modules, used to invert direct current (such as output from photovoltaic panels or energy storage batteries) into alternating current (such as for grid connection or supplying loads). Its core feature is support for "string" operation, meaning that multiple inverters of the same specifications can be electrically connected to form a system with greater power, and the failure of a single module does not affect the overall operation.

[0061] Combination Figure 1 As shown, the system contains multiple inverters. Figure 1An example is given of n inverters (Power Conversion Systems, energy storage converters), designated PCS1, PCS2, ..., PCSn. The AC and DC sides of inverters PCS1, PCS2, ..., PCSn are connected in parallel to form a string inverter group. Each inverter includes an isolation module, a CPLD (Complex Programmable Logic Device) unit, and a DSP (Digital Signal Processor) unit. In addition, each inverter also includes either a carrier signal delay unit or a carrier signal filtering unit, positioned between the corresponding isolation unit and DSP unit. Here, n can be any suitable positive integer greater than or equal to 2.

[0062] The core function of the CPLD unit is to generate and / or receive carrier synchronization signals and coordinate signal delay processing within the inverter. The isolation unit is a circuit module within the inverter that implements electrical isolation and signal transmission. Its function is to electrically isolate the carrier synchronization signal (blocking common-mode interference) and safely transmit it to other units. The carrier signal delay unit adds a fixed delay and filtering to the carrier synchronization signal to compensate for the time difference between signal transmission and processing on the slave side. The carrier signal filtering unit is used to remove narrow pulse noise (such as glitches caused by electromagnetic interference) mixed in the carrier synchronization signal, outputting a clean signal. Both units perform time delay adjustment and noise suppression on the signal. The DSP unit is responsible for the core control of power conversion. It receives the delayed carrier synchronization signal as the synchronization source for its own PWM module, generating pulse signals to drive the inverter's power devices.

[0063] The carrier synchronization signal is a reference signal used to coordinate the operating sequence of multiple devices. In this system, it is a square wave signal with a fixed period and fixed duty cycle, and its frequency is consistent with the carrier frequency of the inverter's PWM module (e.g., 10kHz). This ensures that the power conversion waveforms of all inverters are synchronized. For example, the inverter can generate a square wave signal with a period of 100μs and a duty cycle of 50% as the carrier synchronization signal, and its rising edge can be used as the counting start point of the PWM module.

[0064] In this configuration, one inverter in the string inverter group can be designated as the master inverter, and the remaining inverters as slave inverters. The CPLD unit in the master inverter is designated as the first CPLD unit, the isolation unit as the first isolation unit, and the DSP unit as the first DSP unit; the CPLD unit in the slave inverters is designated as the second CPLD unit, the isolation unit as the second isolation unit, and the DSP unit as the second DSP unit. The master inverter also includes a carrier signal delay unit located between the first isolation unit and the first DSP unit, and each slave inverter also includes a carrier signal filtering unit located between the second isolation unit and the second DSP unit.

[0065] In a multi-device collaborative system, the master unit is the core device responsible for generating reference signals and sending control commands. In this system, the master unit is the "reference source" selected from multiple string inverters, responsible for generating a unified carrier synchronization signal to provide a synchronization reference for all slave units. Slave units in a multi-device collaborative system are subordinate devices that receive the reference signal and operate synchronously with it. In this system, slave units are the inverters other than the master unit. They need to receive the carrier synchronization signal sent by the master unit and maintain operational synchronization with the master unit through signal processing.

[0066] In a parallel system consisting of multiple string inverters, one inverter is selected as the reference control device (master) based on preset rules (such as physical address and power-on sequence), while the others act as follower devices (slave). The hardware structures of the master and slave are basically identical, differing only in software configuration (such as CPLD program parameters). The master has the capability to generate reference signals, while the slave has the capability to receive and process reference signals. Optionally, the inverter in the first position in the system (e.g., Figure 1 In the CPLD configuration, PCS1 is set as the master inverter, and the remaining inverters are set as slave inverters. In master mode, the CPLD unit activates the carrier generation algorithm, and in slave mode, the CPLD unit activates the signal filtering algorithm.

[0067] The first CPLD unit generates a carrier synchronization signal, which is transmitted in two paths: the first path is sent to the first DSP unit after a first signal delay by the carrier signal delay unit, serving as the first synchronization signal source of the first DSP unit; the second path is transmitted to the second DSP unit after passing through the first isolation unit, the second isolation unit, the second CPLD unit, and the carrier signal filtering unit in sequence, serving as the second synchronization signal source of the second DSP unit. The delay duration of the first signal delay is matched with the sum of the transmission delay duration and the filtering delay duration caused by the carrier synchronization signal being transmitted from the first CPLD unit to the second DSP unit, so that the first synchronization signal source and the second synchronization signal source are synchronized. The filtering delay duration is the delay duration caused by the carrier signal filtering unit filtering the carrier synchronization signal.

[0068] In this application, the carrier synchronization signal pins of all inverters are shorted to ensure that after the carrier synchronization signal is sent by the master inverter, all other slave inverters can receive it (the slave inverters are the receiving ends). Specifically, the input pins of the isolation unit (second isolation unit) of the slave inverter are shorted to the output pins of the isolation unit (first isolation unit) of the master inverter through a transmission cable.

[0069] The carrier synchronization signal is generated by the CPLD program algorithm of the host machine. It is output to the local DSP chip as the synchronization signal source for its PWM module, and simultaneously output to the slave machine through the first isolation unit. After receiving the synchronization signal, the slave machine first passes it through the second isolation unit, then inputs it to the CPLD unit for processing, and finally outputs it to the local DSP unit as the synchronization signal source for the slave machine's PWM module. Specifically, the host machine's first CPLD unit is electrically connected to the first DSP unit and the first isolation unit, forming a dual path of "signal generation-delay-local drive" and "signal generation-isolation-external transmission"; the slave machine's second CPLD unit is electrically connected to the second DSP unit and the second isolation unit, forming a single path of "signal reception-isolation-filtering-local drive".

[0070] For the local drive path: the carrier synchronization signal, after being processed by the carrier signal delay unit, is input to the first DSP unit of the host as the synchronization reference for its PWM module. For the external transmission path: the carrier synchronization signal, after being processed sequentially by the first isolation unit of the host, the second isolation unit of the slave, the second CPLD unit of the slave, and the carrier signal filtering unit of the slave, is input to the second DSP unit of the slave as the synchronization reference for its PWM module. For example, the first CPLD generates a 10kHz square wave signal, one path of which is directly sent to the carrier signal delay unit (set with a 150ns delay) and then to the PWM synchronization pin of the first DSP; the other path is transmitted to the slave via shielded twisted-pair cable after passing through the first isolation unit of the host (magnetic isolation + shaping), the second CPLD (filtering), and finally to the PWM synchronization pin of the second DSP.

[0071] By setting the duration of the first signal delay to be equal to the "transmission delay duration + filtering delay duration" on the slave side, it is ensured that the synchronization signals received by the first DSP unit of the host and the second DSP unit of the slave are perfectly aligned in time.

[0072] Since all slave carrier synchronization signals are directly connected to the master, the signal delay of all slaves is the same compared to the master, providing a theoretical basis for the carrier signal delay correction algorithm. Specifically, during system initialization, the transmission delay and filtering delay are determined by testing or preset parameters, and the total delay (the delay duration of the first delay) is calculated. The master's carrier signal delay unit sets the first signal delay to this delay duration, ensuring that the time when the master's first DSP receives the signal is consistent with the time when the slave's second DSP receives the signal.

[0073] The parallel carrier signal synchronization system for string inverters in this embodiment solves the problem of weak noise immunity in traditional electromagnetic isolation schemes through the synergy of isolation units (electrical isolation) and filtering units (noise removal), adapting to the complex electromagnetic environment of energy storage systems. Compared with fiber optic synchronization schemes, it eliminates the need for dedicated optical fibers and modules, reducing hardware costs, and can simultaneously support multiple slave units in parallel (transmitting signals through the same cable), adapting to the needs of systems with different power scales. The hardware structure of the master and slave units in this system is basically the same, with roles distinguished only by software configuration, facilitating mass production and subsequent maintenance (e.g., a faulty slave unit can be replaced with a backup unit and reconfigured). In addition, this system uses a delay matching mechanism to ensure that the time difference between the DSP units of the master and slave units receiving the synchronization signal is minimal, effectively suppressing high-frequency circulating currents when multiple inverters are connected in parallel, and improving system operating efficiency and stability.

[0074] In one embodiment, such as Figure 2 As shown, the first isolation unit includes a first protection circuit 110, a first Schmitt inverter 120, and a first isolator 130 connected in sequence; the generated carrier synchronization signal is transmitted to the slave device after passing through the first protection circuit 110, the first Schmitt inverter 120, and the first isolator 130 in sequence.

[0075] The first protection circuit 110 is a protective unit used to prevent abnormal signals (such as overcurrent and overvoltage) from damaging subsequent circuits. In this system, the first protection circuit 110 is connected in series at the front end of the transmission path of the carrier synchronization signal. It mainly suppresses instantaneous peak current or high voltage pulses in the signal through current limiting, clamping, and other methods, protecting the Schmitt inverter and isolator at the back end. The first Schmitt inverter 120 is a logic gate circuit with hysteresis characteristics, which can convert irregular input signals into standard digital signals. In this system, the first Schmitt inverter 120 receives the carrier synchronization signal processed by the protection circuit. Through its "input level threshold difference" characteristic (the high-level turn-on threshold is higher than the low-level turn-off threshold), it shapes the jitter edges of the signal and filters low-amplitude noise, outputting a standard square wave signal. The first isolator 130 is a device that achieves electrical isolation (no direct conductive connection) between two circuit systems but allows signal transmission. The first isolator 130 can use magnetic coupling (rather than optocoupler photoelectric conversion) to transmit the signal output from the Schmitt inverter to the output side, blocking common-mode interference and ground potential difference between the master and slave devices, while ensuring the integrity of signal transmission.

[0076] The first isolation unit includes a first protection circuit 110, a first Schmitt inverter 120, and a first isolator 130, which are electrically connected sequentially along the signal transmission direction. These three components form a "protection-shaping-isolation" signal processing link, jointly ensuring the safe transmission and quality optimization of the carrier synchronization signal. Specifically, the output of the first protection circuit 110 is electrically connected to the input of the first Schmitt inverter 120, and the output of the first Schmitt inverter 120 is electrically connected to the input of the first isolator 130. The output of the first isolator 130 serves as the external interface of the first isolation unit, connecting to the second isolation unit of the slave device via a transmission cable. For example, one end of the current-limiting resistor of the first protection circuit 110 is connected to the signal output pin of the first CPLD unit, and the other end is connected to the input of the first Schmitt inverter 120; the output of the Schmitt inverter is connected to the input pin (e.g., the INA pin) of the first isolator; the output pin (e.g., the OUTA pin) of the isolator serves as the output of the first isolation unit, connecting to the core wire of the shielded twisted pair cable to transmit the output signal to the slave device.

[0077] Combination Figure 2 As shown, the generated carrier synchronization signal is input from the input terminal of the first protection circuit 110. After the peak current in the carrier synchronization signal is suppressed by the current limiting resistor in the first protection circuit 110, it is input to the first Schmitt inverter 120. The first Schmitt inverter 120 performs edge shaping and noise filtering on the input carrier synchronization signal and outputs the carrier synchronization signal to the first isolator 130. The first isolator 130 internally couples the input carrier synchronization signal to the output side through magnetic coupling and then transmits it to the slave device.

[0078] After the carrier synchronization signal enters from the input terminal of the first protection circuit 110, it first passes through a current-limiting resistor to suppress the peak current in the signal within a preset safe range before being output to the first Schmitt inverter 120. The current-limiting resistor is connected in series in the signal path of the first protection circuit 110, and its resistance value is determined according to the maximum allowable input current of the downstream devices. When a peak current exceeding the safe value appears in the signal, the current-limiting resistor reduces the current through Ohm's law to ensure that the downstream devices are not damaged.

[0079] The first Schmitt inverter 120 receives the carrier synchronization signal processed by the first protection circuit 110, optimizes the transition characteristics of the signal by edge shaping, removes low-amplitude interference by noise filtering, and finally outputs a regular and clean carrier synchronization signal to the first isolator 130.

[0080] Specifically, the Schmitt inverter uses a built-in hysteresis comparator circuit to determine the level of the input signal: when the input signal rises from a low level to the "high level threshold", the output immediately jumps to a high level; when the input signal falls from a high level to the "low level threshold", the output immediately jumps to a low level. This process eliminates signal edge jitter (shaping) and ignores noise within the threshold range (filtering).

[0081] The first isolator 130 receives the carrier synchronization signal processed by the first Schmitt inverter 120 and transmits the signal from the input side to the output side through an internal magnetic coupling mechanism, achieving electrical isolation between the master and slave devices. Finally, the isolated signal is transmitted to the slave device. The input side of the first isolator 130 shares a common ground with the master circuit, and the output side shares a common ground with the slave circuit; there is no electrical connection between the two sides. After the input signal is converted by magnetic coupling, the output side generates a synchronization signal with the same frequency and phase as the input signal, allowing only signal transmission through the magnetic field and blocking the conduction of common-mode interference and ground potential difference.

[0082] like Figure 2 As shown, the first protection circuit 110 includes a capacitor C1 and a resistor R1 connected in parallel, as well as a dual diode D1 and a current-limiting resistor R2. Specifically, the dual diode D1 can be an MMBD7000 / M5C; the first Schmitt inverter 120 can be an NC7WZ14; and the first isolator 130 can be an NSI8242W1-DSWR. One end of the parallel capacitor C1 and resistor R1 is the starting terminal of the first protection circuit 110, and the other end is grounded.

[0083] The common terminal of the dual diode D1 is connected to pin A1 of the first Schmitt inverter 120 via current-limiting resistor R2, and the other terminal of the dual diode is directly connected to pin A2 of the first Schmitt inverter 120. Pin Y1 of the first Schmitt inverter 120 is connected to the input pin IND of the first isolator 130 via resistor R3, and pin Y2 of the first Schmitt inverter 120 is connected to the output pin OUTA of the first isolator 130 via resistor R4. The output pin OUTD of the first isolator 130 is connected to the slave device via resistor R5, specifically to the Sync_In pin of the slave device's isolation unit. The input pin INA of the first isolator 130 is connected to the slave device via resistor R6, specifically to the Sync_Out pin of the slave device's isolation unit.

[0084] Taking a 10kHz periodic square wave as an example, the carrier synchronization signal output by the first CPLD unit is a 3.3V square wave with a period of 100μs, which may contain instantaneous peak current (e.g., 50mA) and high-voltage spikes (e.g., 10V). The current-limiting resistor R3 limits the peak current to 3.3mA (3.3V / 1kΩ) to prevent overcurrent damage to the input of the Schmitt inverter NC7WZ14. When the signal contains a 10V high-voltage spike, the diode of the MMBD7000 / M5C conducts forward, clamping the voltage at 0.7V (diode forward voltage drop) to protect subsequent devices.

[0085] The carrier synchronization signal input to the Schmitt inverter NC7WZ14 may contain edge jitter (rising edge transition time 30ns) and low-amplitude noise (such as random pulses below 1V). The Schmitt inverter utilizes its hysteresis characteristic (high-level threshold 2V, low-level threshold 0.8V) to shape the rising edge transition time from 30ns to 10ns. It does not respond to noise pulses below 1V and only outputs a standard square wave with a high level (3.3V) or a low level (0V). The square wave has steep edges (transition time ≤10ns) and no low-amplitude noise.

[0086] The NSI8242W1-DSWR isolator internally converts electrical signals into magnetic fields through a primary coil, and the secondary coil induces the magnetic field and restores it to an electrical signal, thus achieving electrical isolation between GND1 and GND2. Finally, the carrier synchronization signal is output through the OUTD pin of the NSI8242W1-DSWR and transmitted to the slave device through resistor R5 as the slave device's signal input (Sync_In).

[0087] The isolation unit in this application has the following specific beneficial effects:

[0088] 1. High signal transmission security: The current-limiting resistor of the first protection circuit effectively suppresses peak current and prevents damage to the downstream Schmitt inverter and isolator due to overcurrent; combined with the magnetic coupling isolation of the first isolator, it blocks the high voltage conduction between the master and slave, ensuring the electrical safety of the system.

[0089] 2. Signal quality optimization: The edge shaping function of the first Schmitt inverter shortens the transition time of the carrier synchronization signal, ensuring signal timing accuracy; the noise filtering function eliminates low-amplitude interference, providing a clean signal source for subsequent isolated transmission.

[0090] 3. Enhanced anti-interference capability: Compared with traditional optocoupler isolation, magnetic coupling has a higher anti-electromagnetic interference (EMI) capability, especially immune to high-frequency interference generated by IGBT switches in energy storage systems, ensuring stable transmission of carrier synchronization signals in complex electromagnetic environments.

[0091] 4. Good transmission consistency: The magnetic coupling transmission delay of the isolator is small and stable. Combined with the fixed delay of the protection circuit and the shaping circuit, the signal delay received by the slave device is predictable, providing a reliable parameter basis for the overall delay matching mechanism of the system.

[0092] In one embodiment, the first DSP unit is connected to the second DSP units of each slave unit via a CAN bus. Figure 3 As shown, the transmission delay duration is obtained through the following steps:

[0093] Step S11: The first DSP unit sends a delay test command to the second DSP unit of the target slave device through the CAN bus. The delay test command specifies the slave device identifier of the target slave device that needs to participate in the delay test.

[0094] Step S12: The signal input terminal of the first isolation unit is electrically connected to the output terminal of the second isolation unit of the target slave, so that the target slave can feed back the received carrier test signal to the host.

[0095] Step S13: The first CPLD unit of the host generates a carrier test signal and records the generation timestamp of the carrier test signal.

[0096] Step S14: The generated carrier test signal is sent to the second CPLD unit of the target slave after passing through the first isolation unit and the second isolation unit in sequence.

[0097] Step S15: The second CPLD unit of the target slave device forwards the received carrier test signal to the first CPLD unit through the second isolation unit and the first isolation unit in sequence.

[0098] Step S16: The first CPLD unit records the reception timestamp of the received carrier test signal.

[0099] Step S17: Calculate the transmission delay duration based on the received timestamp and the generated timestamp.

[0100] In this embodiment, the target slave is the slave designated to participate in the latency test. One or more target slaves can be designated in a single test to ensure that the transmission latency of each slave is tested individually or in batches. For example, a slave located in the middle can be designated as the target slave from multiple target slaves, or one or more slaves located in the near end, middle end, and far end regions can be designated as the target slaves. The near end, middle end, and far end regions are the inverter distribution areas defined relative to the master unit.

[0101] The slave identifier is a unique number or address information used to distinguish each slave device. The carrier test signal is a reference signal used to test transmission delay, and its signal characteristics can be consistent with those of the actual carrier synchronization signal. The carrier test signal is generated by the first CPLD of the master unit, for example, a fixed-period square wave (e.g., 10kHz, 50% duty cycle), and its rising edge is used as the reference point for timestamp recording. For example, the carrier test signal is also a square wave signal with a period of 100μs and an amplitude of 3.3V, and the first rising edge is marked as the start of the timestamp at the time of CPLD generation.

[0102] The generation timestamp (denoted as T0) is a timestamp recording the moment the signal is generated, and the reception timestamp (denoted as T1) is a timestamp recording the moment the signal is received by the host after transmission and feedback. Both the generation and reception timestamps are generated by an internal counter in the first CPLD unit within the host, using the CPLD's system clock as the unit. The first CPLD unit latches the counter value when the signal is triggered by its first rising edge, storing it as the generation timestamp T0 in the CPLD's register.

[0103] The transmission delay duration (denoted as T2) represents the single-ended delay of the signal transmission from the master to the slave, that is, the time difference from the generation of the signal by the master CPLD to the reception of the signal by the slave CPLD. The transmission delay duration does not include the delay of the carrier signal delay unit in the master and the delay of the carrier signal filtering unit in the slave.

[0104] The transmission delay can be calculated using the difference between the generated timestamp and the received timestamp (for each round trip, the single-end delay is half of the total difference). Specifically, the transmission delay is calculated using the following formula: T2 = (T1 - T0) / 2, where T2 represents the transmission delay, T1 represents the received timestamp, and T0 represents the generated timestamp. For example, if T1 - T0 = 104 ns, then the transmission delay T2 = 104 ns / 2 = 52 ns.

[0105] The first DSP unit of the host computer sends commands to the slave devices in the system via the CAN bus, explicitly specifying the target slave device to participate in the delay test. The CAN controller of the first DSP unit generates a test command frame, the format of which includes: Start of Frame (SOF), Arbitration Field (containing the target slave identifier), Control Field (data length = 4 bytes), Data Field (test mode = 0x01, number of tests = 3), CRC Field, Acknowledgment Field, and End of Frame (EOF). The command is converted into differential signals (CAN_H = 3.5V, CAN_L = 1.5V) via a CAN transceiver (such as TJA1050) and broadcast on the bus. For example, if the host DSP's eCAN module is configured with a baud rate of 250kbps, the sent command frame would have the following structure: Arbitration Field containing the target slave identifier "0x0002" (representing S2 slave), and Data Field "0x01 0x03 0x000x00" (test mode + 3 tests). Each slave DSP unit, upon receiving the frame, only identifies the response of the matching S2 slave (other slaves are ignored).

[0106] The output of the first isolation unit of the host and the input of the second isolation unit of the target slave are connected by a wire to form a physical path for signal feedback. For example, when the carrier test signal sent by the host passes through a wire... Figure 2 After the isolation unit shown, the signal (Sync_In) output by the first isolator output pin OUTD reaches the target slave device. The target slave device then transmits the signal back to the host's isolation unit through the reverse path of its isolation unit. That is, the host's isolation unit receives the signal (Sync_Out) fed back from the slave device through the input pin INA of its first isolator, and then transmits it to the first DSP unit in sequence through the first isolator, the first Schmitt inverter, and the first protection circuit. The first DSP unit records the received timestamp.

[0107] The first CPLD unit triggers a counter latch on the rising edge of the feedback signal, storing the counter value at this time as the received timestamp T1 in another register. T1 and T0 are based on the same clock reference (ensuring the difference is valid). Based on the difference between the generated timestamp T0 and the received timestamp T1, the single-ended transmission delay of the signal from the master to the slave is calculated.

[0108] This embodiment has the following beneficial effects:

[0109] 1. High testing accuracy: The CPLD records timestamps using a high-precision internal counter, and combined with the symmetrical design of the round-trip path, it can provide accurate parameters for system synchronous calibration.

[0110] 2. High reliability: The delay test command is transmitted via CAN bus. Its differential signal design and error detection mechanism (CRC check) ensure reliable transmission of commands in strong electromagnetic environments, avoiding test failures due to command loss.

[0111] 3. Targeted testing: By specifying the target slave device through the slave device identifier, the transmission latency of a single slave device can be tested individually (such as troubleshooting a faulty slave device), or multiple slave devices can be tested in batches (such as during system initialization), improving testing flexibility.

[0112] 4. Closed-loop verification: The closed-loop path of signal generation from the host → transmission to the slave → feedback back to the host truly simulates the transmission scenario of the actual carrier synchronization signal, and the test results are highly consistent with the delay during actual operation.

[0113] In one embodiment, the delay test instruction includes multiple target slaves; step S16 includes: the first CPLD unit records the reception timestamp of the carrier test signal fed back by each target slave in sequence; step S17 includes: calculating the average reception timestamp based on each reception timestamp; and calculating the transmission delay duration based on the average reception timestamp and the generation timestamp.

[0114] In this embodiment, multiple target slave devices can be designated during the same test, and each target slave device can simultaneously provide feedback to the host. A certain proportion of slave devices with representative distances can be selected as target slave devices, and the host records the reception timestamp of each received carrier test signal. The average of each recorded reception timestamp is calculated to obtain the average reception timestamp. The difference between the average reception timestamp and the generated timestamp is calculated, and half of this difference is the transmission delay duration.

[0115] In one embodiment, steps S11 to S16 are repeated multiple times, and the target slave device specified by the delay test instruction is different each time step S11 is executed; the calculation of the transmission delay duration based on the received timestamp and the generated timestamp includes: calculating the single delay duration based on the received timestamp and the generated timestamp recorded each time; calculating the average of each single delay duration, and using the calculated average as the transmission delay duration.

[0116] Similarly, each slave device can be tested independently, or multiple representative slave devices can be selectively tested independently, with one slave device designated as the target slave device in each test. The transmission delay (i.e., single-pass delay) between the master and the target slave device is calculated for each slave device. After calculating the transmission delay (single-pass delay) between each target slave device and the master, the average of these multiple single-pass delays can be calculated to obtain the transmission delay of the entire system.

[0117] In one embodiment, the transmission delay duration is obtained through the following steps: obtaining the signal delay parameters of each transmission component; calculating the transmission delay duration based on the signal delay parameters, wherein the transmission component is a component containing a signal delay in the first isolation unit and the second isolation unit when the carrier synchronization signal passes through the first isolation unit and the second isolation unit.

[0118] In this embodiment, the signal delay parameter is the inherent time delay of a signal generated by a single transmission component, typically measured in nanoseconds (ns). The signal delay parameter can be recorded in the device datasheet or obtained through field measurement or fine-tuning.

[0119] For example, in the isolation unit described above, the carrier synchronization signal experiences delays when passing through the first Schmitt inverter and the first isolator, but there is virtually no delay when passing through the first protection circuit. The delay duration can be obtained from the relevant manual of the first Schmitt inverter and the product manual of the first isolator. For instance, the signal delay parameter of the first Schmitt inverter can be found to be 10ns, and the signal delay parameter of the first isolator can be found to be 15ns.

[0120] By directly obtaining the signal delay parameters of each transmission component along the carrier synchronization signal during transmission, and summing these signal delay parameters, the transmission delay duration can be quickly obtained.

[0121] In one embodiment, the filtering delay duration is determined based on the pulse width to be removed from the carrier synchronization signal, and the first threshold number is determined based on the filtering delay duration and the clock period of the carrier signal filtering unit.

[0122] In this embodiment, the pulse width to be removed is the maximum width of invalid narrow pulses generated in the system due to electromagnetic interference, signal reflection, etc., and it serves as the basis for determining the filtering delay duration. The pulse width can be obtained by measuring the electromagnetic environment of the system with an oscilloscope, and typically the filtering delay duration is greater than or equal to the pulse width.

[0123] The first count threshold is the counter accumulation threshold used in the carrier signal filtering unit to determine the validity of a pulse. It is calculated from the filter delay duration and the clock cycle of the filtering unit. The first count threshold = filter delay duration / clock cycle, indicating the number of clock cycles that consecutive identical pulses must be maintained before a signal is considered valid.

[0124] For example, interference pulses in the carrier synchronization signal of an energy storage system mainly originate from the inverter IGBT switches, with a width ranging from 15 to 38 ns, and a maximum width of 38 ns. Therefore, the pulse width to be removed is determined to be T_noise = 40 ns. To avoid false filtering of valid signals, the filter delay T_filter is set to 1.2 times T_noise (leaving a 20% margin), i.e., T_filter = 1.2 × T_noise = 48 ns, rounded up to 50 ns (for easier calculation with the clock cycle later). The filtering unit uses a 100MHz system clock (T_clk = 10 ns), so the initial threshold N_th = ceil(50 ns / 10 ns) = 5, meaning that only five consecutive clock cycles (50 ns) of the same pulse are considered valid. This initial threshold is written into the carrier signal filtering unit in the slave unit.

[0125] like Figure 4 As shown, the filtering process of the carrier signal filtering unit for the carrier synchronization signal includes the following steps:

[0126] Step S21: Clear the first counter to reset it.

[0127] Step S22: The carrier signal filtering unit continuously receives the input pulse signal and detects whether the current input pulse signal is consistent with the previous input pulse signal.

[0128] Step S23: When the current input pulse signal is detected to be inconsistent with the previous input pulse signal, the first counter is cleared to zero. When they are consistent, the continuously input pulse signals are accumulated by the first counter as consecutive identical pulse signals for the same number of times.

[0129] Step S24: When the number of times the first counter accumulates reaches the preset first count threshold, the output terminal of the carrier signal filtering unit outputs a carrier synchronization signal.

[0130] In this embodiment, all registers in the carrier signal filtering unit are cleared to perform a reset. These registers may include the aforementioned first counter, ensuring the filtering logic starts operating from its initial state. Specifically, when the filtering unit powers on or receives a reset signal (RST, active high), the CPLD unit's internal logic triggers a clear signal, setting all bits of the register storing the current pulse state (REG1), the register storing the previous pulse state (REG2), and the first counter (CNT) to 0. After the reset is complete, RST is pulled low, and the filtering unit enters a ready state, waiting to receive input pulse signals.

[0131] The filtering unit receives the input pulse signal (output from the second isolation unit) in real time and compares the current input pulse with the pulse state (high level / low level) of the previous moment. Specifically, the input pulse signal is sampled once every clock cycle, and the sampled value is stored in the "current status register (REG1)". Simultaneously, the REG1 value from the previous cycle is moved into the "previous status register (REG2)," and the values ​​of REG1 and REG2 are compared to see if they match.

[0132] The specific timing logic is as follows: Sampling is triggered on the rising edge of the clock: REG1=1 when IN=1 (high level), REG1=0 when IN=0 (low level); after sampling, REG2 is updated to the value of REG1 before sampling (if REG1=1 before sampling, then REG2=1 after sampling); the values ​​of REG1 and REG2 can be compared by an XOR gate. If the result is 0, they are consistent; if it is 1, they are inconsistent.

[0133] Based on the detection result of step S22, the operating state of the first counter is controlled—it is reset to zero when there is inconsistency, and the number of consecutive identical pulses is accumulated when there is consistency. When "inconsistency" (REG1≠REG2) is detected, the internal logic of the CPLD unit triggers the counter reset signal (CNT=0); when "consistency" (REG1=REG2), the counter is incremented by 1 in each clock cycle (CNT=CNT+1), recording the duration of consecutive identical pulses. During the above process, the interference pulse lasts only one cycle (10ns), and the counter is not accumulated but directly reset to zero.

[0134] When the count of the first counter reaches the preset first count threshold (N_th), the filtering unit determines that the current pulse is a valid signal and outputs a stable carrier synchronization signal through the output terminal. Specifically, the comparator inside the CPLD unit compares the counter value (CNT) with the first count threshold (N_th=5) in real time. When CNT≥N_th, the output terminal (OUT) follows the current pulse state (REG1); otherwise, the output maintains the previous valid state (or low level), ensuring that only pulses with a duration ≥ the filter delay are output.

[0135] In this embodiment, by setting a filter delay duration (e.g., 50ns) that matches the interference pulse width, narrow pulse interference in the system can be effectively filtered out. The initial threshold is calculated by "filter delay duration / clock cycle". When the system electromagnetic environment changes (e.g., the interference pulse width increases to 60ns), only the filter delay duration needs to be adjusted (e.g., changed to 60ns) to recalculate the threshold (60ns / 10ns=6). No hardware modification is required, and the system is highly adaptable. Furthermore, the filtering logic in this embodiment is implemented through the internal registers, counters, and comparators of the CPLD unit, eliminating the need for additional chips.

[0136] In one embodiment, such as Figure 5 As shown, the delay process of the carrier signal delay unit for the carrier synchronization signal includes the following steps:

[0137] Step S31: Clear the second counter to reset it.

[0138] Step S32: The carrier signal delay unit continuously receives the input pulse signal and detects whether the current input pulse signal is consistent with the previous input pulse signal.

[0139] Step S33: When the current input pulse signal is detected to be inconsistent with the previous input pulse signal, the second counter is cleared to zero. When they are consistent, the second counter is used to accumulate the continuously input pulse signals as consecutive identical pulse signals for the same number of times.

[0140] Step S34: When the number of times counted by the second counter reaches the preset second threshold, the output terminal of the carrier signal delay unit outputs a carrier synchronization signal. The second threshold is determined based on the delay duration of the first delay and the clock period of the carrier signal delay unit.

[0141] Similarly, the second counter is a counter device in the carrier signal delay unit used to accumulate the "number of consecutive identical pulses". It has the same hardware as the first counter, only the counting target is different (delay instead of filtering). When the input pulse is consistent with the pulse at the previous moment, the second counter is incremented by 1 in each clock cycle; when they are inconsistent, it is reset to zero, until the accumulated number reaches the second threshold, triggering the signal output to achieve precise delay.

[0142] The second threshold (M_th) is the counter accumulation threshold used to trigger signal output in the carrier signal delay unit. It is calculated from the "delay duration of the first delay (T_delay)" and the clock period (T_clk) of the delay unit. The calculation formula is "M_th = T_delay / T_clk", which represents the number of clock cycles the signal needs to be delayed. The signal is output when this number is reached, ensuring that the delay accuracy is consistent with the clock period (e.g., 10ns). For example, if the first delay T_delay = 100ns and the clock period T_clk = 10ns, then M_th = 100ns / 10ns = 10 (i.e., output after a delay of 50 clock cycles).

[0143] In this embodiment, all registers in the carrier signal delay unit are cleared to perform a reset. These registers may include the aforementioned second counter, ensuring the delay logic starts operating from its initial state. Specifically, when the carrier signal delay unit is powered on or receives a reset signal (RST, active high), the CPLD unit's internal logic triggers a clear signal, setting all bits of the register storing the current pulse state (REG3), the register storing the previous pulse state (REG4), and the second counter (CNT2) to 0. After the reset is complete, RST is pulled low, and the filtering unit enters a ready state, waiting to receive the input pulse signal.

[0144] The delay unit receives the input pulse signal (the original carrier synchronization signal generated by the host) in real time and compares the current input pulse with the pulse state (high level / low level) of the previous moment to see if they are consistent. The input pulse signal (IN_delay) is sampled once every clock cycle (10ns), and the sampled value is stored in the "current status register (REG3)". At the same time, the REG3 value of the previous cycle is shifted into the "previous status register (REG4)". The values ​​of REG3 and REG4 are compared by an XOR gate. If the result is 0, they are consistent; if the result is 1, they are inconsistent.

[0145] Based on the detection result of step S32, control the working state of the second counter—clear it when the pulse state changes (is inconsistent), and accumulate the number of consecutive identical pulses when the state remains unchanged (is consistent).

[0146] For example, when REG3=1 and REG4=0 at the rising edge of the pulse, it indicates that the pulse state changes are inconsistent. The internal logic of the CPLD triggers the counter to be cleared (CNT2=0) and starts counting again. When REG3=1 and REG4=1, or REG3=0 and REG4=0, the counter increments by 1 in each clock cycle (CNT2=CNT2+1) to record the number of cycles of the current pulse state.

[0147] When the count of the second counter reaches the preset second count threshold (M_th), the delay unit determines that the preset delay duration has been met and outputs the delayed carrier synchronization signal through the output terminal. The comparator inside the CPLD unit compares the counter value (CNT2) with the second count threshold (M_th) in real time. When CNT2 ≥ M_th, the output terminal (OUT_delay) follows the current pulse state (REG3); otherwise, the output remains at the initial low level to ensure that the signal is output after precise delay.

[0148] In one embodiment, when it is necessary to change the master, one of the multiple slaves is determined as the new master; the second number threshold is written into the carrier signal filtering unit in the new master, so that the carrier signal filtering unit in the new master is changed into a carrier signal delay unit.

[0149] In this embodiment, when the original master fails (such as DSP communication interruption or CPLD no output), the system elects a new master from multiple slaves through a preset "master-slave switching mechanism". For example, PCS2 mentioned above can be selected as the new master.

[0150] For the newly identified host, the second threshold value is written into the carrier signal filtering unit of the new host, turning it into a carrier signal delay unit. The new host (S2) writes the second threshold value into the register of the original "carrier signal filtering unit" through the internal bus (such as SPI), modifying its comparator threshold value to switch it from "filtering function" to "delay function".

[0151] Among them, the carrier signal filtering unit and the carrier signal delay unit in the inverter can be hardware reused (logic modules within the same CPLD). The first counter (CNT1) of the original filtering unit is reconfigured as the second counter (CNT2). The threshold of the comparator is updated from "first count threshold" to "second count threshold". The function changes from "removing short pulses" to "delaying output".

[0152] The specific configuration process is as follows: The DSP unit in the new host sends a configuration frame to the CPLD unit via the SPI bus: address = 0x0003 (comparator threshold register), data = 0x000A (decimal 10); after receiving the frame, the CPLD unit updates the comparator threshold from the original N_th = 5 (0x0005) to M_th_new = 10 (0x000A); at the same time, the DSP unit sends a function switching instruction (address = 0x0004, data = 0x01), and the internal logic of the CPLD unit disables the "filtering mode" and enables the "delay mode"—at this time, the input signal is no longer filtered, but only output after a delay of 50 clock cycles (500ns); after the configuration is completed, the original filtering unit of the new host officially works as a carrier signal delay unit, outputting the delayed carrier synchronization signal to other slaves.

[0153] This embodiment achieves dynamic conversion from slave to master through "parameter writing + function switching", which can improve system robustness.

[0154] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of this application, and are not intended to limit them. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features therein. Such modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of this application.

[0155] Furthermore, those skilled in the art will understand that although some embodiments herein include certain features included in other embodiments but not others, combinations of features from different embodiments are meant to be within the scope of this application and form different embodiments. For example, all the embodiments above can be used in any combination. The information disclosed in this background section is intended only to enhance the understanding of the general background of this application and should not be construed as an admission or in any way implying that such information constitutes prior art known to those skilled in the art.

Claims

1. A parallel carrier signal synchronization system for a string inverter, characterized in that: Set one of the inverters in the string inverter as the master and the rest as slaves; The host includes a first CPLD unit, a first isolation unit, a carrier signal delay unit, and a first DSP unit; the slave includes a second CPLD unit, a second isolation unit, a carrier signal filtering unit, and a second DSP unit. The first CPLD unit generates a carrier synchronization signal, which is transmitted in two paths: the first path is sent to the first DSP unit after the carrier signal delay unit performs a first signal delay, serving as the first synchronization signal source for the first DSP unit. The second path passes sequentially through the first isolation unit, the second isolation unit, the second CPLD unit, and the carrier signal filtering unit before being transmitted to the second DSP unit, serving as the second synchronization signal source for the second DSP unit. The delay duration of the first delay of the signal is matched with the sum of the transmission delay duration and the filtering delay duration caused by the transmission of the carrier synchronization signal from the first CPLD unit to the second DSP unit, so as to synchronize the first synchronization signal source with the second synchronization signal source. The filtering delay duration is the delay duration caused by the carrier signal filtering unit filtering the carrier synchronization signal. The first isolation unit includes a first protection circuit, a first Schmitt inverter, and a first isolator that are connected in sequence. The generated carrier synchronization signal is transmitted to the slave device after passing through the first protection circuit, the first Schmitt inverter, and the first isolator in sequence. The process includes: the generated carrier synchronization signal is input from the input terminal of the first protection circuit, and after the peak current in the carrier synchronization signal is suppressed by the current limiting resistor in the first protection circuit, it is input to the first Schmitt inverter. The first Schmitt inverter performs edge shaping and noise filtering on the input carrier synchronization signal and outputs the carrier synchronization signal to the first isolator. The first isolator internally couples the input carrier synchronization signal to the output side through magnetic coupling and then transmits it to the slave device.

2. The system according to claim 1, characterized in that, The first DSP unit is connected to the second DSP units of each slave unit via a CAN bus; the transmission delay duration is obtained through the following steps: Step S11: The first DSP unit sends a delay test command to the second DSP unit of the target slave device through the CAN bus. The delay test command specifies the slave device identifier of the target slave device that needs to participate in the delay test. Step S12: The signal input terminal of the first isolation unit is electrically connected to the output terminal of the second isolation unit of the target slave, so that the target slave can feed back the received carrier test signal to the host. Step S13: The first CPLD unit of the host generates a carrier test signal and records the generation timestamp of the carrier test signal; Step S14: The generated carrier test signal is sent to the second CPLD unit of the target slave after passing through the first isolation unit and the second isolation unit in sequence; Step S15: The second CPLD unit of the target slave device forwards the received carrier test signal to the first CPLD unit through the second isolation unit and the first isolation unit in sequence; Step S16: The first CPLD unit records the receiving timestamp of the received carrier test signal; Step S17: Calculate the transmission delay duration based on the received timestamp and the generated timestamp.

3. The system according to claim 2, characterized in that, The delay test command includes multiple target slave devices; The first CPLD unit records the reception timestamp of the received carrier test signal, including: the first CPLD unit records the reception timestamp of the carrier test signal fed back by each target slave in sequence; The step of calculating the transmission delay duration based on the received timestamp and the generated timestamp includes: Calculate the average timestamp of each received data. The transmission delay duration is calculated based on the received average timestamp and the generated timestamp.

4. The system according to claim 2, characterized in that, Repeat steps S11 to S16 multiple times, with the target slave device specified by the delay test instruction being different each time step S11 is executed. The step of calculating the transmission delay duration based on the received timestamp and the generated timestamp includes: The duration of a single delay is calculated based on the received timestamp and the generated timestamp of each record. The average value is calculated based on the duration of each single delay, and the calculated average value is used as the transmission delay duration.

5. The system according to claim 2, characterized in that, The transmission delay duration is calculated using the following formula: T2 = (T1 - T0) / 2, where T2 represents the transmission delay duration, T1 represents the receiving timestamp, and T0 represents the generating timestamp.

6. The system according to claim 1, characterized in that, The transmission delay duration is obtained through the following steps: Obtain the signal delay parameters of each transmission component; The transmission delay duration is calculated based on the signal delay parameter. The transmission component is a component containing a signal delay in the first isolation unit and the second isolation unit when the carrier synchronization signal passes through the first isolation unit and the second isolation unit.

7. The system according to claim 1, characterized in that, The filtering delay duration is determined based on the pulse width that needs to be removed from the carrier synchronization signal, and the first threshold number is determined based on the filtering delay duration and the clock period of the carrier signal filtering unit. The carrier signal filtering unit filters the carrier synchronization signal through the following steps: Step S21: Clear the first counter to reset it; Step S22: The carrier signal filtering unit continuously receives the input pulse signal and detects whether the current input pulse signal is consistent with the previous input pulse signal; Step S23: When the current input pulse signal is detected to be inconsistent with the previous input pulse signal, the first counter is cleared to zero. When they are consistent, the continuously input pulse signals are accumulated by the same number of consecutive identical pulse signals through the first counter. Step S24: When the number of times the first counter accumulates reaches the preset first count threshold, the output terminal of the carrier signal filtering unit outputs a carrier synchronization signal.

8. The system according to claim 1, characterized in that, The delay process of the carrier signal delay unit for the carrier synchronization signal includes the following steps: Step S31: Clear the second counter to reset it; Step S32: The carrier signal delay unit continuously receives the input pulse signal and detects whether the current input pulse signal is consistent with the previous input pulse signal; Step S33: When the current input pulse signal is detected to be inconsistent with the previous input pulse signal, the second counter is cleared to zero. When they are consistent, the second counter is used to accumulate the continuously input pulse signals as consecutive identical pulse signals for the same number of times. Step S34: When the number of times counted by the second counter reaches the preset second threshold, the output terminal of the carrier signal delay unit outputs a carrier synchronization signal. The second threshold is determined based on the delay duration of the first delay and the clock period of the carrier signal delay unit.

9. The system according to claim 8, characterized in that, When it is necessary to change the master, one of the multiple slaves is selected as the new master; The second threshold number is written into the carrier signal filtering unit in the new host, so that the carrier signal filtering unit in the new host is changed into a carrier signal delay unit.

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