Programmable hearing aid chip

Abstract

The invention provides a programmable hearing aid chip, which comprises a microprocessor module, a voice accelerator module, a neural network processing module, an analog front-end circuit module and a communication interface module, the microprocessor module is respectively connected with the voice accelerator module, the neural network processing module, the analog front-end circuit module and the communication interface module; the voice accelerator module, the neural network processing module and the analog front-end circuit module are connected in sequence; after the analog front-end circuit module obtains an initial voice signal, converts the initial voice signal and outputs the converted initial voice signal to the microprocessor module for storage, the initial voice signal is processed by the voice accelerator module and the neural network processing module in sequence to be converted into a target voice signal, and the target voice signal is output through the analog front-end circuit module.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of integrated circuits, in particular to a programmable hearing aid chip. BACKGROUND

[0002] With the intensification of global population aging and the popularity of personal audio devices, the number of hearing loss population continues to rise, and the demand for hearing aid market expands rapidly. Modern hearing aid devices generally use digital signal processing (DSP) scheme to process input sound for noise reduction, echo cancellation, dynamic range compression, etc., to improve the hearing experience of the wearer. The hearing aid chips on the market currently mainly face the following problems: high power consumption, as a wearable device, the battery capacity of the hearing aid is limited, the existing scheme has too high power consumption when processing multiple channels and executing complex algorithms, which affects the battery life. Poor flexibility, many hearing aid chips use fixed function hardware logic, which is difficult to adjust flexibly according to different user needs or different hearing environments, which is not conducive to later algorithm upgrade or scene adaptation. Limited processing capacity, under the premise of meeting small size and low power consumption, traditional DSP scheme is difficult to support computationally intensive intelligent enhancement algorithms such as neural networks, limiting the improvement of hearing aid intelligence level. Low integration of analog and digital, the analog front end (such as microphone interface, multi-channel analog-to-digital converter (ADC), traditional digital-to-analog converter (DAC), power amplifier) and the digital processing part often belong to different chips or modules, resulting in complex system design, increased signal chain delay, and increased overall size and cost. SUMMARY

[0003] In view of the above shortcomings, the present application provides a programmable hearing aid chip, which comprises a microprocessor module, a speech accelerator module, a neural network processing module, an analog front-end circuit module and a communication interface module, wherein; the microprocessor module is connected with the speech accelerator module, the neural network processing module, the analog front-end circuit module and the communication interface module respectively; the speech accelerator module, the neural network processing module and the analog front-end circuit module are connected in sequence; after the initial speech signal is obtained in the analog front-end circuit module and converted and output to the microprocessor module for storage, the initial speech signal is processed by the speech accelerator module and the neural network processing module in sequence to convert into a target speech signal, and the target speech signal is output by the analog front-end circuit module again.

[0004] In the above scheme, the microprocessor module comprises a processor and a local storage unit, wherein; the processor is used to run a user-defined control program, to schedule the modules inside the chip, and to be able to interrupt processing and external communication; the local storage unit is used to store data in the chip processing process.

[0005] In the scheme, the voice accelerator module comprises a plurality of acceleration units; the plurality of acceleration units are used for implementing wide dynamic range compression, noise suppression, echo cancellation, feedback cancellation, directivity processing and fast Fourier transform on the initial voice signal.

[0006] In the scheme, the voice accelerator module is designed by using a unified data bus structure and a shared multiplier, so that the plurality of acceleration units reuse resources through a serial structure.

[0007] In the scheme, the plurality of acceleration units comprise a wide dynamic range compression accelerator, which is used for multi-band analysis and gain adjustment on the initial voice signal.

[0008] In the scheme, the neural network processing module comprises a recurrent neural network accelerator, which is used for processing data paths of the initial voice signal in parallel through a matrix multiplication array, and realizing non-linear activation function calculation through a gating function lookup table to perform noise reduction processing on the voice signal.

[0009] In the scheme, the analog front-end circuit module comprises a multi-channel analog-to-digital converter, a down-sampling circuit, an up-sampling circuit, a digital pulse width modulator and a class-D power amplifier, wherein; the multi-channel analog-to-digital converter is used for receiving the initial voice signal; the down-sampling circuit is used for bandwidth compression on the initial voice signal; the up-sampling circuit is used for processing the target voice signal to adapt to the high-frequency working requirement of the digital pulse width modulator; the digital pulse width modulator is used for converting the up-sampled target voice signal into a pulse signal to drive the power amplifier input end of the class-D power amplifier; and the class-D power amplifier is used for amplifying the pulse signal and making the pulse signal have low distortion and high dynamic range.

[0010] In the scheme, the down-sampling circuit is composed of a three-level structure, and the three-level structure comprises a cascaded integral comb CIC decimation filter, a CIC compensation filter and a half-band filter.

[0011] In the scheme, the up-sampling circuit comprises a plurality of cascaded half-band filters, a CIC compensation filter and a CIC interpolation filter.

[0012] In the scheme, the communication interface module comprises a first interface, a second interface, a third interface and a fourth interface, wherein; the first interface is used for realizing data transmission with an external audio codec; the second interface is used for realizing external expansion and program parameter loading; and the third interface and the fourth interface are both used for external device control, debugging and configuration interaction.

[0013] The technical scheme of the embodiment of the application has at least the following beneficial effects:

[0014] (1) Reduce system power consumption: through low-power processor architecture, module sharing mechanism and data flow optimization design, reduce the overall energy consumption of the chip, prolong the use time of the hearing aid, adapt to the strict requirements of battery life in wearable scenarios.

[0015] (2) Improve algorithm flexibility: introduce embedded programmable processor and instruction control mechanism, so that users can configure and update the speech enhancement algorithm according to different hearing impairment types and acoustic environment, improve adaptability and upgradeability.

[0016] (3) Support intelligent processing capability: integrate lightweight neural network acceleration module to realize deep learning tasks such as speech scene recognition and adaptive noise suppression, and provide stronger semantic understanding and context adaptation capability for hearing aids.

[0017] (4) High integration: integrate ADC, DAC, earphone driver (Class-D) and other analog parts with digital processing modules in a single chip to simplify system design, reduce cost and size, and improve overall system signal integrity and processing efficiency. BRIEF DESCRIPTION OF DRAWINGS

[0018] Figure 1 The overall architecture schematic diagram of the programmable hearing aid chip according to the embodiment of the application is shown;

[0019] Figure 2 The system structure schematic diagram of the RISC-V processor and multiple acceleration units working together according to the embodiment of the application is shown;

[0020] Figure 3 The RFFT / RIFFT accelerator structure schematic diagram according to the embodiment of the application is shown;

[0021] Figure 4 The processing process schematic diagram of the neural network noise suppression algorithm according to the embodiment of the application is shown;

[0022] Figure 5 The recurrent neural network accelerator structure schematic diagram according to the embodiment of the application is shown;

[0023] Figure 6 The down-sampling circuit structure schematic diagram according to the embodiment of the application is shown;

[0024] Figure 7 The structure schematic diagram of the CIC decimation filter according to the embodiment of the application is shown;

[0025] Figure 8 The up-sampling circuit structure schematic diagram according to the embodiment of the application is shown;

[0026] Figure 9FIG. 4 shows a schematic structural diagram of a CIC interpolation filter according to an embodiment of the present invention. DETAILED DESCRIPTION

[0027] In order to make the objectives, technical solutions and advantages of the present invention more clearly understood, the present invention is further described in detail below in conjunction with specific embodiments and with reference to the accompanying drawings.

[0028] Figure 1 FIG. 4 is a schematic diagram showing the overall architecture of a programmable hearing aid chip according to an embodiment of the present invention. Figure 2 A schematic diagram of the system structure of a RISC-V processor working in collaboration with multiple acceleration units according to an embodiment of the present invention is shown.

[0029] like Figure 1 As shown, according to an embodiment of the present invention, the programmable hearing aid chip includes a microprocessor module 1, a speech accelerator module 2, a neural network processing module 3, an analog front-end circuit module 4, and a communication interface module 5. The microprocessor module 1 is connected to the speech accelerator module 2, the neural network processing module 3, the analog front-end circuit module 4, and the communication interface module 5, respectively; and the speech accelerator module 2, the neural network processing module 3, and the analog front-end circuit module 4 are connected in sequence.

[0030] In an embodiment of the present invention, after the analog front-end circuit module 4 acquires the initial voice signal and outputs it to the microprocessor module 1 for storage after conversion, the initial voice signal is processed in turn by the voice accelerator module 2 and the neural network processing module 3 to be converted into a target voice signal, and the target voice signal is then output by the analog front-end circuit module 4.

[0031] The programmable hearing aid chip, as implemented in the embodiments of the present invention, represents an integrated digital hearing aid processing chip architecture. The chip integrates a microprocessor module 1, a speech accelerator module 2, a neural network processing module 3, an analog front-end circuit module 4, and a communication interface module 5, completing the complete link from analog audio input acquisition to digital processing and audio output. This programmable hearing aid chip achieves low power consumption, a small footprint, low latency, and high flexibility, making it suitable for embedded applications in wearable hearing aids and a variety of other scenarios.

[0032] The programmable hearing aid chip is described in detail below.

[0033] In an embodiment of the present invention, the microprocessor module 1 includes a processor and a local storage unit. The processor is used to run user-defined control programs, schedule various modules within the chip, and interrupt processing and external communication; the local storage unit is used to store data during chip processing.

[0034] Exemplarily, the processor of the microprocessor module 1 is a RISC-V core with a two-stage pipeline structure, which is used to run a user-defined control program, schedule various functional modules inside the chip, and support interrupt handling and external communication.

[0035] Further, the RISC-V processor can also support instruction set extension, allowing users to customize the speech processing flow according to the hearing aid algorithm requirements, and configure the parameters of each accelerator through register mapping.

[0036] Based on the above, it can be understood that the RISC-V core with a two-stage pipeline has the following functions, including: running a user-defined hearing aid control program; managing internal resources of the chip, including accelerator scheduling, parameter configuration, and interrupt response; providing a programmable interface to support different algorithm combinations and hearing scene configurations; and supporting basic debugging and communication functions for product maintenance and upgrading.

[0037] In an embodiment of the present application, the speech accelerator module 2 includes a plurality of acceleration units. Among them, the plurality of acceleration units are used to implement wide dynamic range compression, noise suppression, echo cancellation, feedback cancellation, directivity processing and fast Fourier transform on the initial speech signal.

[0038] Specifically, the plurality of units in the speech accelerator module 2 include a wide dynamic range compression (WDRC) accelerator, a noise suppression (NR) accelerator, an echo cancellation (AEC) unit, a feedback cancellation unit, a directivity unit, and a real signal fast Fourier transform / inverse transform (RFFT / RIFFT) accelerator. The speech accelerator module 2 is designed by adopting a unified data bus structure and sharing multipliers, so that the plurality of acceleration units are resource-reused through a serial structure to reduce area and power consumption.

[0039] Exemplarily, the wide dynamic range compression (WDRC) accelerator is used for multi-band analysis and gain adjustment of the initial speech signal, and adopts a hardware-implemented fast envelope tracking and compression function to realize real-time loudness adjustment.

[0040] Exemplarily, the noise suppression (NR) accelerator is used for spectral subtraction based on the characteristics of the speech signal to reduce the background noise of the initial speech signal.

[0041] Exemplarily, the echo cancellation (AEC) unit is used to improve the communication clarity of the initial speech signal.

[0042] Exemplarily, the feedback cancellation unit is used to detect and suppress the howling in the hearing aid caused by the closed loop in real time.

[0043] Exemplarily, the directivity unit is used to combine multi-channel input and sound source positioning algorithm to optimize the initial speech signal enhancement strategy.

[0044] Exemplarily, the RFFT / RIFFT accelerator is used to implement fast Fourier transform and inverse transform, supporting frequency domain algorithm operation.

[0045] As shown in Figure 2 The microprocessor module 1 adopts RISC-V processor architecture as the core control module of the chip, has a two-stage simplified pipeline design, and is used for completing system-level task scheduling, parameter configuration, debugging communication, module control and the like. The processor of the microprocessor module 1 configures each acceleration unit in the voice accelerator module 2 through an interrupt mechanism, and can dynamically adjust the working state to realize power consumption management. The RISC-V core supports custom instruction extension, can flexibly extend the function according to different algorithm requirements, and thus improves the overall system customizability and application adaptability.

[0046] Further, as shown in Figure 2 The plurality of acceleration units of the voice accelerator module 2 are composed of a plurality of custom circuits for voice processing, and correspond to different algorithm modules, such as a wide dynamic range compression (WDRC) accelerator, a noise suppression (NR) accelerator, an acoustic echo cancellation (AEC) unit, a feedback cancellation unit, a directivity unit and a real signal fast Fourier transform / inverse transform (RFFT / RIFFT) accelerator. The acceleration units are connected through an on-chip bus and a processor, and are equipped with respective local storage units (such as independent RAM or dual-port RAM) to improve access efficiency and support parallel processing. Meanwhile, the multiplication operation structures of the accelerators share four groups of configurable bit-width multiplier arrays.

[0047] Figure 3 An RFFT / RIFFT accelerator structure diagram according to an embodiment of the application is shown.

[0048] As shown in Figure 3 The RFFT / RIFFT accelerator is designed using a structure reuse mechanism, uses the same hardware resources to implement efficient processing of forward and inverse fast Fourier transform, greatly improves the utilization rate of hardware and saves chip area. The module is mainly composed of three core sub-modules, which are ① complex FFT module, ② reverse order storage unit, and ③ real number operation module.

[0049] Specifically, when performing RFFT, the hardware modules work in the order of ①→②→③. First, the voice signal is input to module ①, and direct complex FFT operation is performed to complete the main calculation process of frequency domain transform; then, the FFT result is stored in reverse order and rearranged by module ②, and the output order is arranged; finally, the real number format conversion and compression are performed by module ③, and the final real spectrum result is output. In the whole process, the data is transmitted in a streaming manner between the modules, realizing an efficient pipeline processing architecture.

[0050] In the execution of the RIFFT, the system is configured in the order of ②→③→②→① and operated in sequence. First, the frequency domain input data enters module ② for preliminary reverse buffering processing; then, it is subjected to real symmetric structure unfolding and complex format recovery through module ③; then, the intermediate data is temporarily stored and the sequence is adjusted again through module ②; finally, the complex IFFT operation is performed by module ① to restore the original time domain signal. In this process, module ② is called twice to process the data structure organization before and after the RIFFT, and module ③ plays a key role in format conversion to ensure seamless switching between real numbers and complex numbers.

[0051] In an embodiment of the application, the neural network processing module 3 comprises a recurrent neural network (RNN) accelerator for processing the data path of the initial voice signal in parallel through a matrix multiplication array and implementing a non-linear activation function calculation through a gating function lookup table to perform noise reduction processing on the voice signal.

[0052] It can be understood that the neural network processing module 3 integrates a lightweight recurrent neural network accelerator for implementing an intelligent noise reduction function in voice enhancement. Its main features include: supporting a GRU structure with reset gate, update gate and candidate hidden state calculation unit; using a gating function lookup table (LUT) to replace complex activation function operations (such as sigmoid, tanh) to improve hardware efficiency; supporting parallel computation of gating units and resource reuse to improve throughput.

[0053] By way of example, the recurrent neural network accelerator adopts a gated recurrent unit (GRU) structure, has a built-in special parallel operation unit (such as a MAC (multiply-accumulate unit)), supports at least 65-dimensional input and output channels, and implements sigmoid and tanh functions through a gating function lookup table (LUT).

[0054] Figure 4 A processing process schematic diagram of a neural network noise suppression algorithm according to an embodiment of the application is shown. Figure 5 A recurrent neural network accelerator structure schematic diagram according to an embodiment of the application is shown.

[0055] As shown in Figure 4 The processing process of the neural network noise suppression algorithm includes preprocessing, an RNN main network (based on a GRU structure) and post-processing. For example, the input is a frame-level 65-dimensional voice energy feature vector, and the output is a gain factor of the same dimension, which is used to adjust the frequency band energy to achieve the purpose of adaptive noise reduction. The network structure has a time sequence memory capability and can better distinguish between voice and background noise, and is suitable for hearing aid scenes in real environments.

[0056] Further, as shown in Figure 5As shown, the embodiment of the present application implements the above-mentioned noise reduction algorithm through an RNN accelerator. The accelerator includes a matrix multiplication array, a gating function lookup table (LUT), a register stack, a control state machine, and other modules. The multiplication array can process multiple input features and weight matrix data paths in parallel; the LUT module is used to quickly implement nonlinear activation functions such as Sigmoid and Tanh, reducing power consumption and delay. The RNN accelerator supports flexible configuration of input and output channels and has good scalability.

[0057] In the embodiment of the present application, the analog front-end circuit module 4 includes a multi-channel analog-to-digital converter, a down-sampling circuit, an up-sampling circuit, a digital pulse width modulator, and a class-D power amplifier. The multi-channel analog-to-digital converter is used to receive the initial speech signal; the down-sampling circuit compresses the bandwidth of the initial speech signal; the up-sampling circuit is used to process the target speech signal to adapt to the high-frequency working requirements of the digital pulse width modulator; the digital pulse width modulator is used to convert the up-sampled target speech signal into a pulse signal to drive the power amplifier input end of the class-D power amplifier; the class-D power amplifier is used to amplify the pulse signal and make the pulse signal have low distortion and high dynamic range.

[0058] It can be understood that the analog front-end circuit module 4 is used to realize the analog / digital conversion and output driving of the speech signal, and is a key module for connecting the sound input and output of the hearing aid chip.

[0059] Exemplarily, the analog front-end circuit module 4 mainly includes a multi-channel analog-to-digital converter (ADC) for receiving analog speech signals (i.e., initial speech signals) from a microphone array, supporting high-resolution and high-signal-to-noise ratio sampling, ensuring speech input clarity and fidelity, and having reference voltage stabilization and front-end gain control inside. Exemplarily, a three-channel ADC analog front-end module is integrated to collect the initial speech signals of multiple microphone inputs.

[0060] The analog front-end circuit module 4 also includes a down-sampling circuit: the sampling rate of the input initial speech signal is usually much higher than the frequency required for final speech processing, in order to reduce power consumption and computational load, a multi-stage down-sampling structure is used to compress the bandwidth of the initial speech signal output by the ADC. Exemplarily, the down-sampling circuit is composed of a three-stage structure, which is a cascaded integral comb CIC decimation filter, a CIC compensation filter, and a half-band filter, and the filter coefficients are CSD encoded to reduce hardware resource consumption.

[0061] Figure 6 A down-sampling circuit structure diagram according to an embodiment of the present application is shown. Figure 7 A structure diagram of a CIC decimation filter according to an embodiment of the present application is shown.

[0062] As Figure 6 AndFigure 7 The down-sampling circuit is used to down-sample the initial speech signal sampled by the high-frequency ADC output to a lower sampling rate required for speech processing. The overall structure adopts a three-stage structure: the first stage is a CIC decimation filter based on the cascade of integrator and comb filter (e.g., 6-stage cascade), which realizes the primary down-sampling; the second stage is a CIC compensation filter, which is used to compensate for the passband attenuation; and the third stage is a half-band FIR filter, which is used to further reduce the sampling rate and improve the spectral characteristics. By using a shift-adder instead of a multiplier and combining CSD coding to optimize the coefficient representation, the hardware complexity and power consumption are effectively reduced.

[0063] The analog front-end circuit module 4 also includes an up-sampling circuit: used to process the digital output signal (i.e., the target speech signal) to increase its sampling rate to adapt to the high-frequency working requirement of the digital PWM modulator. For example, a multi-stage half-band filter, a CIC compensation filter, and a CIC interpolation filter are usually cascaded.

[0064] Figure 8 A structure diagram of the up-sampling circuit according to an embodiment of the present application is shown. Figure 9 A structure diagram of the CIC interpolation filter according to an embodiment of the present application is shown.

[0065] As Figure 8 With Figure 9 The up-sampling circuit structure is mainly used to increase the target speech signal after speech processing to the high sampling rate required for PWM modulation. The structure includes two half-band FIR filters, a CIC compensation filter, and a multi-stage cascaded CIC interpolation filter (e.g., 6-stage cascade). The CIC interpolator realizes high-ratio interpolation through the cascade of comb filter and integrator, which has a compact structure and high resource utilization rate.

[0066] The analog front-end circuit module 4 also includes a digital pulse width (PWM) modulator: the up-sampling circuit is used in cascade with the digital PWM modulator, and the digital PWM modulator converts the up-sampled target speech signal into a pulse form, so that it can directly drive the input end of the Class-D power amplifier, thereby saving the traditional digital-to-analog converter (DAC) circuit and further saving the area and power consumption.

[0067] The analog front-end circuit module 4 also includes a Class-D power amplifier: used to drive the internal loudspeaker of the earphone or hearing aid, which has a high-efficiency output stage and an integrated feedback control mechanism, and has high efficiency and low total harmonic distortion. The PWM modulation output module is used to drive the external Class-D power amplifier, which improves the energy efficiency ratio and adapts to different acoustic output loads.

[0068] Based on the above, it can be understood that after the initial speech signal is acquired by the analog front-end circuit module 4 and converted and output to the microprocessor module 1 for storage, the initial speech signal is subjected to wide dynamic range compression, noise suppression, echo cancellation, feedback cancellation, directivity processing and fast Fourier transform by the speech accelerator module 2. Then, the speech signal processed by the speech accelerator module 2 enters the neural network processing module 3 for processing, and noise reduction processing is performed in the neural network processing module 3 to obtain a target speech signal. Finally, the target speech signal is converted into a pulse signal by the up-sampling circuit and the PWM modulator in the analog front-end circuit module 4 and output.

[0069] In the embodiment of the present application, the communication interface module 5 includes a first interface, a second interface, a third interface and a fourth interface. Among them; the first interface is used to realize data transmission with an external audio codec; the second interface is used to realize external expansion and program parameter loading; the third interface and the fourth interface are both used for external device control, debugging and configuration interaction.

[0070] Exemplarily, the first interface is an I 2 S (audio serial) interface, which is used for data transmission with an external audio codec.

[0071] Exemplarily, the second interface is a QSPI (quad serial peripheral) interface, which is used to load a speech program in an external Flash expansion to the chip for internal running.

[0072] Exemplarily, the third interface is an I 2 C (serial peripheral interface bus), and the fourth interface is a UART (universal asynchronous receiver transmitter), which are both used for external device control, debugging and configuration interaction.

[0073] Through the embodiment of the present application, the programmable hearing aid chip integrates multiple advantages such as low-power optimization, speech algorithm special acceleration, neural network processing and analog front-end integration, has high configurability, expandability and practicality, and is particularly suitable for a new generation of wearable smart hearing aid system. For example, it is applied to a wearable hearing aid device, has low power consumption, low delay and programmability, and is suitable for personalized speech enhancement processing in various hearing impairment types and environmental scenarios.

[0074] Based on the programmable hearing aid chip, the embodiment of the present application further provides an implementation method of the programmable hearing aid chip, including: constructing a low-power microprocessor module based on a RISC-V kernel; designing a plurality of hearing aid speech algorithm accelerators and realizing serial multiplexing through a shared structure; integrating a GRU type light neural network processing module and optimizing the hardware structure thereof; integrating an ADC, a down-sampling circuit, an up-sampling circuit, a PWM modulator and a Class-D amplifier; and configuring a communication interface to realize peripheral interaction, algorithm updating and remote debugging.

[0075] Further, the voice accelerator module adopts a shared 24*24 bit multiplier to realize time multiplexing of multiple acceleration functions such as WDRC, NR, RFFT, etc., and improve resource utilization.

[0076] Further, the sigmoid and tanh activation functions in the GRU neural network are realized by a lookup table, which reduces hardware overhead and improves the speed of non-linear function calculation.

[0077] Further, the coefficients in the down-sampling and up-sampling filters are realized by CSD coding, which reduces the number of multiplication operations and optimizes power consumption and area.

[0078] Further, the hearing aid algorithm is configured by a processor internal instruction control mechanism, and users can switch different parameter configurations or algorithm combinations according to scene requirements.

[0079] Through the embodiments of the present application, an integrated, low-power, programmable hearing aid chip architecture is provided, which is systematically optimized in terms of structural design, algorithm acceleration, circuit optimization and power consumption control, and is suitable for high-performance, low-delay and low-power wearable voice auxiliary devices. Through the collaborative design and resource sharing of multiple modules, the chip area and power consumption are significantly reduced while ensuring the performance of the hearing aid algorithm, which has wide application prospects and industrial value.

[0080] The above specific embodiments further illustrate the purpose, technical solutions and beneficial effects of the present application. It should be understood that the above are only specific embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the protection scope of the present application.

Claims

1. A programmable hearing aid chip, characterized in that: It includes a microprocessor module (1), a voice accelerator module (2), a neural network processing module (3), an analog front-end circuit module (4) and a communication interface module (5), wherein; The microprocessor module (1) is respectively connected to the voice accelerator module (2), the neural network processing module (3), the analog front-end circuit module (4), and the communication interface module (5); The speech accelerator module (2), the neural network processing module (3) and the analog front-end circuit module (4) are connected in sequence; After the analog front-end circuit module (4) acquires the initial voice signal and outputs it to the microprocessor module (1) for storage after conversion, the initial voice signal is processed by the voice accelerator module (2) and the neural network processing module (3) in sequence to be converted into a target voice signal, and the target voice signal is then output by the analog front-end circuit module (4).

2. The programmable hearing aid chip according to claim 1, characterized in that: The microprocessor module (1) comprises a processor and a local storage unit, wherein; The processor is used to run user-defined control programs, schedule various modules inside the chip, and can interrupt processing and external communication; The local storage unit is used to store data during the chip processing process.

3. The programmable hearing aid chip according to claim 1, characterized in that: The speech accelerator module (2) includes a plurality of acceleration units; The multiple acceleration units are used to implement wide dynamic range compression, noise suppression, echo cancellation, feedback cancellation, directionality processing and fast Fourier transform on the initial speech signal.

4. The programmable hearing aid chip according to claim 3, characterized in that: The speech accelerator module (2) is designed with a unified data bus structure and a shared multiplier, so that the multiple acceleration units can reuse resources through a serial structure.

5. The programmable hearing aid chip according to claim 3, characterized in that: The multiple acceleration units include a wide dynamic range compression accelerator, which is used to perform multi-band analysis and gain adjustment on the initial speech signal.

6. The programmable hearing aid chip according to claim 1, characterized in that: The neural network processing module (3) includes a recurrent neural network accelerator, which is used to process the data path of the initial speech signal in parallel through a matrix multiplication array, and to implement nonlinear activation function calculation through a gate function lookup table to perform noise reduction processing on the speech signal.

7. The programmable hearing aid chip according to claim 1, characterized in that: The analog front-end circuit module (4) includes a multi-channel analog-to-digital converter, a down-sampling circuit, an up-sampling circuit, a digital pulse width modulator and a class D power amplifier, wherein; The multi-channel analog-to-digital converter is used to receive the initial voice signal; The down-sampling circuit performs bandwidth compression on the initial speech signal; The up-sampling circuit is used to process the target voice signal to adapt to the high-frequency working requirements of the digital pulse width modulator; The digital pulse width modulator is used to convert the upsampled target voice signal into a pulse signal to drive the power amplifier input end of the class D power amplifier; The class D power amplifier is used to amplify the pulse signal and make the pulse signal have low distortion and high dynamic range.

8. The programmable hearing aid chip according to claim 7, characterized in that: The down-sampling circuit is composed of a three-stage structure, which includes a cascaded integrator comb CIC decimation filter, a CIC compensation filter and a half-band filter.

9. The programmable hearing aid chip according to claim 7, characterized in that: The up-sampling circuit includes a cascaded multi-stage half-band filter, a CIC compensation filter and a CIC interpolation filter.

10. The programmable hearing aid chip according to claim 1, characterized in that: The communication interface module (5) comprises a first interface, a second interface, a third interface and a fourth interface, wherein; The first interface is used to realize data transmission with an external audio codec; The second interface is used to implement external extension and program parameter loading; The third interface and the fourth interface are both used for external device control, debugging and configuration interaction.

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