Chip, preparation method thereof and electronic equipment
By adopting a dual-channel parallel structure and a low dielectric constant isolation layer in the vertical transistor, the problem of channel mobility attenuation is solved, and the on-state current is increased and the storage density is increased.
Patent Information
- Application Number
- CN202410407272.7
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-04-03
- Publication Date
- 2025-10-17
AI Technical Summary
In the prior art, the channel mobility of back-end vertical transistors is attenuated, resulting in insufficient on-state current, and it is difficult to increase it without increasing the area.
A dual-channel structure is adopted, by connecting the channels of vertical transistors in parallel and using a shallow trench isolation layer with a low dielectric constant and a capacitor structure to optimize resistance, increase current and reduce electric field coupling.
Without increasing the area of the vertical transistor, the on-state current is significantly increased, the resistance is reduced, and the storage density and performance are improved.
Smart Images
Figure CN120812945A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application relates to the technical field of semiconductor technology, and in particular to a chip, a preparation method thereof, and an electronic device. BACKGROUND
[0002] With the rapid development of the chip industry, the performance and storage density of the memory gradually become important factors that limit the performance of the chip. Under the background of the demand for large capacity and large bandwidth storage today, the storage unit needs to be continuously miniaturized and stacked to achieve high-density storage.
[0003] The vertical transistor prepared by the back-end process (hereinafter referred to as the back-end vertical transistor) can be applied to future high-density stackable storage units. The area of the storage unit containing the back-end vertical transistor is reduced from 6F 2 to 4F 2 However, due to the reasons of materials and processes, the mobility of the channel in the back-end vertical transistor is attenuated to different degrees. Therefore, improvements need to be made to the structure of the device to increase the on-state current of the back-end vertical transistor. SUMMARY
[0004] To solve the above technical problems, the present application provides a chip, a preparation method thereof, and an electronic device, which increases the on-state current of the vertical transistor without additionally increasing the area occupied by the vertical transistor.
[0005] In a first aspect, the present application provides a chip, which comprises a first conductive layer and a vertical transistor stacked on a substrate. The vertical transistor comprises a gate, a gate dielectric layer, a first channel, a second channel, a first electrode, and a second electrode. In the direction from the first conductive layer to the vertical transistor, the gate, the gate dielectric layer, and the second electrode are sequentially stacked, and the gate dielectric layer covers the sidewall of the gate and the surface of the gate facing the second electrode. The first electrode comprises a first sub-electrode and a second sub-electrode, and the first sub-electrode and the second sub-electrode are respectively arranged on the opposite sides of the sidewall of the gate dielectric layer and are electrically connected by the first conductive layer. The first channel is adjacent to the first sub-electrode and the second electrode, and the second channel is adjacent to the second sub-electrode and the second electrode.
[0006] The on-state vertical transistor is equivalent to a circuit, in which the first channel and the first conductive layer are electrically connected to node S0 (the first sub-electrode), the second channel and the first conductive layer are electrically connected to node S1 (the second sub-electrode), and node S0 and node S1 are electrically connected. The first channel and the second channel are also electrically connected to node S2 (the second electrode). In this way, the first channel and the second channel form a parallel relationship. Compared with the resistance value of the first channel alone and the resistance value of the second channel alone, the total resistance value of the first channel and the second channel in parallel is smaller. The total resistance value on the channel is reduced, and the on-state current of the vertical transistor is increased.
[0007] Also, although the embodiments of the present application adopt a double-channel (first channel and second channel) scheme, the first channel and the second channel of the present application are derived from one channel that is isolated by the first electrode and the second electrode to form the disconnected first channel and the second channel. In other words, the existing channel is divided into the first channel and the second channel by the first electrode and the second electrode. Therefore, the double-channel scheme proposed by the embodiments of the present application does not increase the area occupied by the vertical transistor.
[0008] In some possible implementations, the number of vertical transistors is multiple, and the multiple vertical transistors are arranged in an array. Along the row direction, the second sub-electrode of any vertical transistor is multiplexed as the first sub-electrode of the vertical transistor adjacent thereto.
[0009] Suppose that the first vertical transistor and the second vertical transistor are arranged and adjacent along the row direction, the second sub-electrode of the first vertical transistor can be multiplexed as the first sub-electrode of the second vertical transistor.
[0010] In the case that the spacing between the first vertical transistor and the second vertical transistor is fixed, compared with the scheme that the second sub-electrode of the first vertical transistor and the first sub-electrode of the second vertical transistor are disconnected (not multiplexed), by multiplexing the second sub-electrode of the first vertical transistor as the first sub-electrode of the second vertical transistor, the multiplexed second sub-electrode of the first vertical transistor and the first sub-electrode of the second vertical transistor (hereinafter referred to as the target electrode) can occupy a larger area at the position between the first vertical transistor and the second vertical transistor. For example, in the scheme of not multiplexing, the sum of the area of the second sub-electrode of the first vertical transistor, the disconnected area between the second sub-electrode of the first vertical transistor and the first sub-electrode of the second vertical transistor, and the first sub-electrode of the second vertical transistor is the area occupied by the target electrode of the embodiments of the present application.
[0011] Since the area occupied by the target electrode of the present application is increased, the contact area between the target electrode and the first conductive layer is increased. According to the resistance formula R = pL / S, the greater the contact area S between the target electrode and the first conductive layer, the smaller the resistance R between the target electrode and the first conductive layer. Therefore, by multiplexing the second sub-electrode of the first vertical transistor as the first sub-electrode of the second vertical transistor, the resistance R between the target electrode and the first conductive layer can also be reduced, thereby improving the on-state current of the first vertical transistor and the second vertical transistor.
[0012] In some possible implementation manners, the chip further includes a shallow trench isolation layer, the shallow trench isolation layer is arranged on a side of the first sub-electrode and the second sub-electrode away from the first conductive layer, and the shallow trench isolation layer is configured to electrically isolate the second channel of any vertical transistor from the first channel of a vertical transistor adjacent to the vertical transistor. The dielectric constant of the shallow trench isolation layer is less than the dielectric constant of silicon dioxide, that is, the material of the shallow trench isolation layer is a low-K dielectric.
[0013] The shallow trench isolation layer with low-K is configured to electrically isolate the second channel of the first vertical transistor from the first channel of the second vertical transistor, so as to reduce the electric field coupling between the second channel of the first vertical transistor and the first channel of the second vertical transistor, so that the second channel of the first vertical transistor and the first channel of the second vertical transistor are two electrically independent channels, thereby avoiding mutual influence between the second channel of the first vertical transistor and the first channel of the second vertical transistor.
[0014] The smaller the dielectric constant of the shallow trench isolation layer is, the lower the electric field coupling between the second channel of the first vertical transistor and the first channel of the second vertical transistor is. Therefore, optionally, the dielectric constant of the shallow trench isolation layer can be less than 3.
[0015] In some possible implementation manners, the chip further includes a capacitor, the capacitor is arranged along a direction of the vertical transistor pointing to the first conductive layer, and the capacitor includes a first electrode and a second electrode arranged in a stack, and the first electrode is electrically connected to the second electrode.
[0016] The chip including the vertical transistor and the capacitor can be a memory chip, and the memory chip includes a memory array, and the memory array includes a plurality of memory cells, each of which includes the vertical transistor and the capacitor. Of course, the chip including the vertical transistor and the capacitor can also be applied to other circuits, which is not limited in the present application.
[0017] In some possible implementation manners, the capacitor is arranged on a side of the vertical transistor away from the substrate; and along a direction of the vertical transistor pointing to the substrate, the gate electrode, the gate dielectric layer and the second electrode are arranged in a stack in sequence. In this way, along the direction of the vertical transistor pointing to the substrate, the first electrode, the dielectric layer and the second electrode are also arranged in a stack in sequence.
[0018] Alternatively, the capacitor is arranged between the substrate and the vertical transistor; and along a direction of the vertical transistor pointing to the substrate, the second electrode, the gate dielectric layer and the gate electrode are arranged in a stack in sequence. In this way, along the direction of the vertical transistor pointing to the substrate, the second electrode, the dielectric layer and the first electrode are arranged in a stack in sequence.
[0019] In some possible implementation manners, the second electrode and the first electrode both completely cover the surface of the gate dielectric layer away from the gate. In other words, the orthographic projection of the second electrode and the first electrode on the gate dielectric layer can completely cover the surface of the gate dielectric layer away from the gate. This solution can greatly increase the overlapping area of the second electrode and the first electrode. As can be known from the resistance formula R = pL / S, the overlapping area of the second electrode and the first electrode is increased, and the resistance R of the second electrode and the first electrode is reduced, thereby improving the on-state current of the vertical transistor.
[0020] In some possible implementation manners, the first conductive layer includes a bit line, and the first sub-electrode and the second sub-electrode are electrically connected through the bit line. The chip can further include a second conductive layer, which is arranged on the side of the second electrode away from the substrate, and the second conductive layer can include a plate line. In this way, it can be understood that the first sub-electrode and the second sub-electrode are electrically connected through the bit line, and the second electrode of the capacitor is electrically connected to the plate line.
[0021] In some possible implementation manners, the vertical transistor and the capacitor constitute a storage array group, and the chip includes a plurality of storage array groups; and the plurality of storage array groups are arranged in a stacked manner along the direction in which the vertical transistor is directed to the substrate. For example, a plurality of vertical transistors constitute a first group of vertical transistors, and a plurality of vertical transistors constitute a second group of vertical transistors; and the first group of vertical transistors and the second group of vertical transistors are arranged in two layers in a stacked manner along the direction in which the substrate is directed to the first conductive layer.
[0022] In a second aspect, the present application provides an electronic device, which includes a circuit board and the chip of the first aspect, and the chip is arranged on the circuit board.
[0023] The second aspect and any one of the implementation manners of the second aspect correspond to the first aspect and any one of the implementation manners of the first aspect respectively. The technical effects corresponding to the second aspect and any one of the implementation manners of the second aspect can refer to the technical effects corresponding to the first aspect and any one of the implementation manners of the first aspect, which will not be described herein again.
[0024] In a third aspect, the present application provides a preparation method of a chip, which includes: forming a first conductive layer and a vertical transistor arranged in a stacked manner on a substrate; the vertical transistor includes a gate, a gate dielectric layer, a first channel, a second channel, a first electrode and a second electrode; the gate, the gate dielectric layer and the second electrode are sequentially arranged in a stacked manner along the direction in which the first conductive layer is directed to the vertical transistor, and the gate dielectric layer covers the side wall of the gate and the surface of the gate facing the second electrode; the first electrode includes a first sub-electrode and a second sub-electrode, the first sub-electrode and the second sub-electrode are arranged on opposite sides of the side wall of the gate dielectric layer, and the first sub-electrode and the second sub-electrode are electrically connected through the first conductive layer; the first channel is adjacent to the second electrode and the first sub-electrode, and the second channel is adjacent to the second electrode and the second sub-electrode.
[0025] In some possible implementation manners, the method further includes: forming a shallow trench isolation layer on a side of the first sub-electrode and the second sub-electrode away from the first conductive layer; the shallow trench isolation layer is used to electrically isolate a second channel of any vertical transistor from a first channel of a vertical transistor adjacent to the vertical transistor; and a dielectric constant of the shallow trench isolation layer is less than a dielectric constant of silicon dioxide.
[0026] In some possible implementation manners, after the first conductive layer and the vertical transistor are formed in the stack on the substrate, the method further includes: forming a capacitor; and in a direction in which the first conductive layer points to the vertical transistor, the capacitor includes the first electrode and the second electrode arranged in the stack, and the first electrode is electrically connected to the second electrode. Forming the first conductive layer and the vertical transistor in the stack on the substrate includes: forming the first conductive layer on the substrate; and forming the vertical transistor on a side of the first conductive layer away from the substrate.
[0027] In some possible implementation manners, before the first conductive layer and the vertical transistor are formed in the stack on the substrate, the method further includes: forming a capacitor; and in a direction in which the first conductive layer points to the vertical transistor, the capacitor includes the first electrode and the second electrode arranged in the stack, and the first electrode is electrically connected to the second electrode. Forming the first conductive layer and the vertical transistor in the stack on the substrate includes: forming the vertical transistor on a side of the capacitor away from the substrate; and forming the first conductive layer on a side of the vertical transistor away from the substrate.
[0028] The third aspect and any one of the implementation manners of the third aspect correspond to the first aspect and any one of the implementation manners of the first aspect respectively. For details, refer to the technical effects of the first aspect and any one of the implementation manners of the first aspect, which will not be described herein again. BRIEF DESCRIPTION OF DRAWINGS
[0029] Figure 1 An interaction diagram of a logic circuit and a storage array provided by an embodiment of the present application;
[0030] Figure 2 A top view of a storage array provided by an embodiment of the present application;
[0031] Figure 3 A structure diagram of a vertical transistor provided by an embodiment of the present application;
[0032] Figure 4 A structure diagram of a vertical transistor provided by an embodiment of the present application and an equivalent circuit diagram thereof;
[0033] Figure 5 A structure diagram of a vertical transistor provided by an embodiment of the present application;
[0034] Figure 6A structure diagram of a vertical transistor and a capacitor provided for an embodiment of the present application;
[0035] Figure 7 A structure diagram of a vertical transistor and a capacitor provided for an embodiment of the present application;
[0036] Figure 8 A structure diagram of a vertical transistor and a capacitor provided for an embodiment of the present application;
[0037] Figure 9 A structure diagram of a vertical transistor and a capacitor provided for an embodiment of the present application;
[0038] Figure 10a A structure diagram of a vertical transistor and a capacitor provided for an embodiment of the present application;
[0039] Figure 10b A structure diagram of a vertical transistor and a capacitor provided for an embodiment of the present application;
[0040] Figure 10c A structure diagram of a vertical transistor and a capacitor provided for an embodiment of the present application;
[0041] Figure 11a A preparation process diagram of a chip provided for an embodiment of the present application;
[0042] Figure 11b A preparation process diagram of a chip provided for an embodiment of the present application;
[0043] Figure 11c A preparation process diagram of a chip provided for an embodiment of the present application;
[0044] Figure 11d A preparation process diagram of a chip provided for an embodiment of the present application;
[0045] Figure 11e A preparation process diagram of a chip provided for an embodiment of the present application;
[0046] Figure 11f A preparation process diagram of a chip provided for an embodiment of the present application;
[0047] Figure 12 A preparation process diagram of a chip provided for an embodiment of the present application;
[0048] Figure 13a A preparation process diagram of a chip provided for an embodiment of the present application;
[0049] Figure 13b A preparation process diagram of a chip provided for an embodiment of the present application. DETAILED DESCRIPTION
[0050] With reference to the drawings and the embodiments of the present application, the technical solutions in the embodiments of the present application will be described clearly and completely. Obviously, the described embodiments are some of the embodiments of the present application, but not all of the embodiments of the present application. Based on the embodiments of the present application, all other embodiments obtained by those of ordinary skill in the art without creative efforts should fall within the scope of the present application.
[0051] The term "and / or" used herein is merely used to describe an associated relationship with associated objects, and means that three relationships can exist, for example, A and / or B can mean that A exists alone, A and B exist together, and B exists alone.
[0052] The terms "first" and "second" and the like in the description and claims of the embodiments of the present application are used to distinguish different objects, and are not used to describe a specific order of the objects. For example, the first target object and the second target object are used to distinguish different target objects, and are not used to describe a specific order of the target objects.
[0053] In the embodiments of the present application, the words "exemplary" or "for example" are used to mean serving as an example, instance, or illustration. Any embodiment or design solution described as "exemplary" or "for example" in the embodiments of the present application should not be construed as being more preferred or advantageous than other embodiments or design solutions. Rather, the use of the words "exemplary" or "for example" is intended to present concepts in a particular manner.
[0054] In the description of the embodiments of the present application, unless otherwise specified, the meaning of "a plurality of" is two or more. For example, a plurality of processing units means two or more processing units; a plurality of systems means two or more systems.
[0055] The embodiments of the present application provide an electronic device, which can be a consumer electronic product, a home electronic product, a vehicle-mounted electronic product, a financial terminal product, a communication electronic product, and the like, and is a device containing a vertical transistor.
[0056] Consumer electronic products such as mobile phones, tablet computers, notebook computers, personal computers (PCs), personal digital assistants (PDAs), smart wearable products (e.g., smart watches, smart bands, etc.), virtual reality (VR) terminal devices, augmented reality (AR) terminal devices, drones, etc. Household electronic products such as smart door locks, televisions, smart speakers, refrigerators, robotic vacuum cleaners, etc. Vehicle-mounted electronic products such as vehicle-mounted navigation devices, vehicle-mounted displays, etc. Financial terminal products such as automated teller machines (ATMs), self-service terminals, etc. Communication electronic products such as servers, memories, radars, base stations, etc. Communication equipment containing transistors.
[0057] For the convenience of description, the following takes a mobile phone as an example of an electronic device. The mobile phone can include a circuit board on which a processor, a logic circuit, and a memory are disposed, as shown in FIG. 1. Figure 1 As shown, the memory includes a memory array, a memory controller, a row decoder, a column decoder, etc. The processor can send an address of a selected memory cell to the row decoder and the column decoder through the logic circuit. The row decoder and the column decoder determine the memory cell in the memory array after decoding the received address, and then cause the selected memory cell to perform a read / write operation.
[0058] The memory cell includes a transistor and a capacitor, and the performance and size of the transistor determine the performance and size of the memory.
[0059] As mentioned in the background, in order to achieve high-density storage, the area of the memory cell using a back-end vertical transistor is reduced from 6F 2 to 4F 2 . As shown in FIG. 2, 4F 2 means that, assuming that the pitches between adjacent memory cells are all the same, the sum of the single-side size of any memory cell and the pitch between the memory cell and the adjacent memory cell is 2F, then the area occupied by the memory cell is 4F 2 . Figure 2
[0060] However, due to material and process reasons, the mobility of the channel in the back-end vertical transistor is attenuated to varying degrees. Therefore, improvements need to be made to the structure of the device to increase the on-state current of the back-end vertical transistor.
[0061] In order to increase the on-state current of the back-end vertical transistor, the related art has proposed a dual-gate back-end vertical transistor, that is, the back-end vertical transistor includes two gates, and the two gates are usually located on opposite sides of the channel. The two gates are used to strengthen the gate control and at the same time increase the on-state current of the back-end vertical transistor. However, due to size limitations, in order not to increase the area occupied by the back-end vertical transistor, the thickness of the two gates should be reduced compared to the solution in which the back-end vertical transistor includes one gate. However, the reduction in the thickness of the two gates will lead to an increase in the resistance of the word line electrically connected to the gate. If the area occupied by the back-end vertical transistor is not increased and the thickness of the two gates is not reduced, the spacing between adjacent memory cells needs to be reduced. However, due to manufacturing process limitations, reducing the spacing between adjacent memory cells will sharply increase the process difficulty of the back-end vertical transistor.
[0062] Based on this, the present application provides a chip comprising a substrate and a vertical transistor disposed on the substrate. The vertical transistor comprises a channel, wherein the channel comprises a first channel and a second channel. Without increasing additional area, a dual-channel solution is adopted, such that the first channel and the second channel are connected in parallel to reduce the parallel resistance of the channels, thereby increasing the on-state current of the vertical transistor. The vertical transistor of the present application can be manufactured through a front-end process or a back-end process, and the embodiments of the present application are not limited thereto.
[0063] The structure of the chip is described in detail below with reference to the accompanying drawings.
[0064] like Figure 3 As shown, the chip includes, in addition to a substrate 10 and a vertical transistor 12, a first conductive layer 11 disposed between the substrate 10 and the vertical transistor 12. In addition to a first channel 121 and a second channel 122, the vertical transistor also includes a gate 13, a gate dielectric layer 14, a first electrode, and a second electrode 16. The first electrode is the source of the vertical transistor, and the second electrode 16 is the drain of the vertical transistor; alternatively, the first electrode is the drain of the vertical transistor, and the second electrode 16 is the source of the vertical transistor.
[0065] Along the direction of the first conductive layer pointing vertically to the transistor, the gate 13, the gate dielectric layer 14, and the second pole 16 are stacked in sequence, and the gate dielectric layer 14 covers the side walls of the gate 13 and the first surface of the gate 13, wherein the first surface of the gate 13 is the surface of the gate 13 facing the second pole 16.
[0066] The first electrode includes a first sub-electrode 151 and a second sub-electrode 152, which are disposed on opposite sides of the sidewalls of the gate dielectric layer 14. That is, the gate dielectric layer 14 includes a first sidewall and a second sidewall, which are disposed on opposite sides of the gate 13. The first sub-electrode 151 is located on the side of the first sidewall facing away from the gate 13, and the second sub-electrode 152 is located on the side of the second sidewall facing away from the gate 13. Furthermore, the first sub-electrode 151 and the second sub-electrode 152 are electrically connected via the first conductive layer 11.
[0067] The first channel 121 is adjacent to the second electrode 16 and the first sub-electrode 151 , and the second channel 122 is adjacent to the second electrode 16 and the second sub-electrode 152 .
[0068] like Figure 4 As shown, the turned-on vertical transistor is equivalent to a circuit, wherein the first channel 121 is electrically connected to the first conductive layer 11 at node S0 (first sub-electrode 151), the second channel 122 is electrically connected to the first conductive layer 11 at node S1 (second sub-electrode 152), and node S0 is electrically connected to node S1. The first channel 121 and the second channel 122 are also electrically connected to node S2 (second electrode 16). In this way, the first channel 121 and the second channel 122 form a parallel relationship. Compared with the resistance value of the first channel 121 alone and the resistance value of the second channel 122 alone, after the first channel 121 and the second channel 122 are connected in parallel, the total parallel resistance value of the first channel 121 and the second channel 122 is smaller. The total resistance value on the channel decreases, and the on-state current of the vertical transistor increases.
[0069] Furthermore, although the embodiment of the present application adopts a dual-channel solution (first channel 121 and second channel 122), the origin of the first channel 121 and second channel 122 of the present application is that a single channel is separated by the first and second electrodes 16 to form disconnected first and second channels 121, 122. In other words, the first and second electrodes 16 are used to divide the existing channel into the first and second channels 121, 122. Therefore, the dual-channel solution proposed in the embodiment of the present application does not increase the area occupied by the vertical transistor.
[0070] In some possible implementations, given that the gate 13 cannot be electrically connected to the first sub-electrode 151 and the second sub-electrode 152 through the first conductive layer 11, the chip may further include an insulating layer 21, which is disposed between the first conductive layer 11 and the gate 13 to electrically isolate the first conductive layer 11 from the gate 13. Furthermore, the insulating layer 21 may include vias, through which the first sub-electrode 151 and the second sub-electrode 152 are electrically connected to the first conductive layer 11.
[0071] In some possible implementations, the materials of the gate 13, the first electrode, and the second electrode 16 include but are not limited to at least one of tungsten (W), titanium nitride (TiN), and molybdenum (Mo); the materials of the first channel 121 and the second channel 122 include but are not limited to single crystal silicon / germanium, polycrystalline silicon / germanium, oxide semiconductors (IGZO, IWO, etc.), organic semiconductors (pentacene, P3HT, etc.), two-dimensional material semiconductors (MoS2, WSe2, etc.), one-dimensional semiconductors (CNT, etc.), etc.; the materials of the gate dielectric layer 14 include but are not limited to SiO2, SiN x , high dielectric constant High-K materials (HfO2, ZrO2, etc.), etc.
[0072] In some embodiments, as Figure 3 As shown, there are multiple vertical transistors arranged in an array. Along the row direction, the second sub-electrode 152 of any vertical transistor is reused as the first sub-electrode 151 of the adjacent vertical transistor. Assuming that the first vertical transistor and the second vertical transistor are arranged and adjacent along the row direction, the second sub-electrode 152 of the first vertical transistor can be reused as the first sub-electrode 151 of the second vertical transistor.
[0073] When the spacing between the first vertical transistor and the second vertical transistor is constant, compared to the solution in which the second sub-electrode 152 of the first vertical transistor is disconnected from the first sub-electrode 151 of the second vertical transistor (non-reuse), by reusing the second sub-electrode 152 of the first vertical transistor as the first sub-electrode 151 of the second vertical transistor, the second sub-electrode 152 reused as the first sub-electrode 151 of the second vertical transistor (hereinafter referred to as the target electrode) can occupy a relatively large area at a position between the first vertical transistor and the second vertical transistor. For example, in the solution without reuse, the sum of the areas of the second sub-electrode 152 of the first vertical transistor, the disconnected area between the second sub-electrode 152 of the first vertical transistor and the first sub-electrode 151 of the second vertical transistor, and the first sub-electrode 151 of the second vertical transistor is the area occupied by the target electrode in the embodiment of the present application.
[0074] Because the target electrode of this application occupies a larger area, the contact area between the target electrode and the first conductive layer 11 increases. According to the resistance formula R = ρL / S, the larger the contact area S between the target electrode and the first conductive layer 11, the smaller the resistance R between the target electrode and the first conductive layer 11. Therefore, by reusing the second sub-electrode 152 of the first vertical transistor as the first sub-electrode 151 of the second vertical transistor, the resistance R between the target electrode and the first conductive layer 11 can be reduced, thereby increasing the on-state current of the first and second vertical transistors.
[0075] In some embodiments, asFigure 5 As shown, the chip further comprises a shallow trench isolation (STI) layer 22, which is disposed on the side of the first sub-electrode 151 and the second sub-electrode 152 away from the first conductive layer 11. The shallow trench isolation layer 22 is used to electrically isolate the second channel 122 of the first vertical transistor from the first channel 121 of the second vertical transistor adjacent to the first vertical transistor. In addition, the dielectric constant of the shallow trench isolation layer 22 is less than that of silicon dioxide, i.e., the material of the shallow trench isolation layer 22 is a low-K dielectric.
[0076] By using the low-K shallow trench isolation layer 22 to electrically isolate the second channel 122 of the first vertical transistor from the first channel 121 of the second vertical transistor, the electric field coupling between the second channel 122 of the first vertical transistor and the first channel 121 of the second vertical transistor can be reduced, so that the second channel 122 of the first vertical transistor and the first channel 121 of the second vertical transistor are two electrically independent channels, thereby avoiding mutual influence between the second channel 122 of the first vertical transistor and the first channel 121 of the second vertical transistor.
[0077] The smaller the dielectric constant of the shallow trench isolation layer 22, the lower the electric field coupling between the second channel 122 of the first vertical transistor and the first channel 121 of the second vertical transistor. Therefore, optionally, the dielectric constant of the shallow trench isolation layer 22 can be less than 3.
[0078] In some embodiments, as shown in Figure 6 As shown, the chip further comprises a capacitor, which is arranged in the direction of the vertical transistor along the first conductive layer 11, and the capacitor comprises a first electrode 31, a dielectric layer 33, and a second electrode 32 which are sequentially stacked, and the first electrode 31 is electrically connected to the second electrode 16 of the vertical transistor.
[0079] The chip comprising the vertical transistor and the capacitor can be a memory chip, and the memory chip comprises a memory array, and the memory array comprises a plurality of memory cells, and each memory cell comprises a vertical transistor and a capacitor. Of course, the chip comprising the vertical transistor and the capacitor can also be applied to other circuits, and the embodiments of the present application do not limit this.
[0080] Taking the vertical transistor and the capacitor as a memory cell, as shown in Figure 7 As shown, the chip can further comprise a second conductive layer 41, which is disposed on the side of the second electrode 32 away from the substrate 10, and the second conductive layer 41 can comprise a plate line (PL), and the first conductive layer 11 can comprise a bit line (BL). In this way, it can be understood that the first sub-electrode 151 and the second sub-electrode 152 are electrically connected through the bit line BL, and the second electrode 32 of the capacitor is electrically connected to the plate line PL.
[0081] In some possible implementation manners, as shown in Figure 7 the capacitor is arranged on the side of the vertical transistor away from the substrate 10, and the gate 13, the gate dielectric layer 14 and the second electrode 16 are sequentially stacked in the direction of the vertical transistor along the substrate 10. In this way, the first electrode 31, the dielectric layer 33 and the second electrode 32 are sequentially stacked in the direction of the vertical transistor along the substrate 10.
[0082] Alternatively, as shown in Figure 8 the capacitor is arranged between the substrate 10 and the vertical transistor, and the second electrode 16, the gate dielectric layer 14 and the gate 13 are sequentially stacked in the direction of the vertical transistor along the substrate 10. In this way, the second electrode 32, the dielectric layer 33 and the first electrode 31 are sequentially stacked in the direction of the vertical transistor along the substrate 10.
[0083] In some possible implementation manners, taking the application of the ferroelectric capacitor in the chip as an example, the capacitor can be a ferroelectric capacitor, and the material of the ferroelectric layer between the first electrode and the second electrode in the ferroelectric capacitor can include hafnium-based, zirconium-based oxide, hafnium-based, zirconium-based oxide containing a doping element (such as Hf, Zr, Si, Y, La, Ce, etc.), and the like. The ferroelectric layer can be one layer, or multiple layers of ferroelectric / anti-ferroelectric materials with different components. The thickness of the ferroelectric layer can range from 2 nm to 15 nm, and the projection area of the ferroelectric layer on the substrate 10 can range from 0.04 um 2 to 0.25 um 2 .
[0084] In some embodiments, as shown in Figure 9 the capacitor is arranged on the chip, and the first electrode 31 of the capacitor is electrically connected to the second electrode 16 of the vertical transistor, and the second electrode 16 and the first electrode 31 can both completely cover the surface of the side of the gate dielectric layer 14 away from the gate 13. In other words, the orthographic projection of the second electrode 16 and the first electrode 31 on the gate dielectric layer 14 can completely cover the surface of the side of the gate dielectric layer 14 away from the gate 13. This scheme can greatly increase the overlapping area of the second electrode 16 and the first electrode 31. As known from the resistance formula R = pL / S, the overlapping area of the second electrode 16 and the first electrode 31 is increased, and the resistance R of the second electrode 16 and the first electrode 31 is reduced, thereby improving the on-state current of the vertical transistor.
[0085] The foregoing introduces the structure of a single vertical transistor. In some possible implementation manners, a plurality of vertical transistors can be included on a chip, and the plurality of vertical transistors can be arranged in an array and arranged on the substrate 10 in the same layer; or, at least one vertical transistor is stacked with at least one vertical transistor in a direction in which the substrate 10 points to the first conductive line layer 11, for example, a plurality of vertical transistors constitute a first group of vertical transistors, a plurality of vertical transistors constitute a second group of vertical transistors, and the first group of vertical transistors and the second group of vertical transistors are stacked in two layers in the direction in which the substrate 10 points to the first conductive line layer 11. Of course, a plurality of groups of vertical transistors can be stacked in more layers in the direction in which the substrate 10 points to the first conductive line layer 11, and embodiments of the present application do not limit this.
[0086] By stacking a plurality of groups of vertical transistors in the direction in which the substrate 10 points to the first conductive line layer 11, the integration density of the vertical transistors can be improved. Further, the stacking structure scheme is also applicable to a case where the chip includes a plurality of vertical transistors and a plurality of capacitors, and the plurality of vertical transistors and the plurality of capacitors constitute a plurality of memory cells. For example, a plurality of memory cells constitute a first memory array, a plurality of memory cells constitute a second memory array, and the first memory array and the second memory array are stacked in the direction in which the substrate 10 points to the first conductive line layer 11, to improve the storage density. Of course, a plurality of memory cells can be stacked in more layers in the direction in which the substrate 10 points to the first conductive line layer 11, and embodiments of the present application do not limit this.
[0087] Figure 10a - Figure 10c A schematic diagram in which the first memory array and the second memory array are stacked in the direction in which the substrate 10 points to the first conductive line layer 11 is shown.
[0088] As shown in FIG. 1, in any one of the memory cells of the first memory array and the second memory array, the vertical transistor is arranged between the substrate 10 and the capacitor. Figure 10a As shown in FIG. 1, in any one of the memory cells of the first memory array and the second memory array, the capacitor is arranged between the substrate 10 and the vertical transistor. Figure 10b As shown in FIG. 1, the memory cells in the first memory array and the memory cells in the second memory array are arranged in a mirror image, for example, in the memory cells of the first memory array, the vertical transistor is arranged between the substrate 10 and the capacitor; and in the memory cells of the second memory array, the capacitor is arranged between the substrate 10 and the vertical transistor. Figure 10c
[0089] In another embodiment, the present application further provides a preparation method of a chip, as shown in FIG. 2. Figure 3 As shown, a first conductive layer 11 and a vertical transistor can be stacked on a substrate 10. In addition to a first channel 121 and a second channel 122, the vertical transistor also includes a gate 13, a gate dielectric layer 14, a first electrode, and a second electrode 16. The first electrode is the source of the vertical transistor, and the second electrode 16 is the drain of the vertical transistor; alternatively, the first electrode is the drain of the vertical transistor, and the second electrode 16 is the source of the vertical transistor.
[0090] Along the direction of the first conductive layer pointing vertically to the transistor, the gate 13, the gate dielectric layer 14, and the second pole 16 are stacked in sequence, and the gate dielectric layer 14 covers the side walls of the gate 13 and the first surface of the gate 13, wherein the first surface of the gate 13 is the surface of the gate 13 facing the second pole 16.
[0091] The first electrode includes a first sub-electrode 151 and a second sub-electrode 152, which are disposed on opposite sides of the sidewalls of the gate dielectric layer 14. That is, the gate dielectric layer 14 includes a first sidewall and a second sidewall, which are disposed on opposite sides of the gate 13. The first sub-electrode 151 is located on the side of the first sidewall facing away from the gate 13, and the second sub-electrode 152 is located on the side of the second sidewall facing away from the gate 13. Furthermore, the first sub-electrode 151 and the second sub-electrode 152 are electrically connected via the first conductive layer 11.
[0092] The first channel 121 is adjacent to the second electrode 16 and the first sub-electrode 151 , and the second channel 122 is adjacent to the second electrode 16 and the second sub-electrode 152 .
[0093] like Figure 4 As shown, the turned-on vertical transistor is equivalent to a circuit, wherein the electrically connected first sub-electrode 151, the first conductive layer 11, and the second sub-electrode 152 can be compared to the first wire, the second electrode 16 can be compared to the second wire, the first channel 121 can be compared to the first resistor, and the second channel 122 can be compared to the second resistor. The first resistor and the second resistor are connected in parallel through the first wire and the second wire. Compared with the resistance value of the first resistor alone and the resistance value of the second resistor alone, after the first resistor and the second resistor are connected in parallel, the total parallel resistance value of the first resistor and the second resistor is smaller. The total resistance value on the channel is reduced, and the on-state current of the vertical transistor is increased.
[0094] And, although the embodiments of the present application adopt the scheme of double channels (the first channel 121 and the second channel 122), the first channel 121 and the second channel 122 of the present application are derived from the fact that one channel is isolated by the first pole and the second pole 16 to form the disconnected first channel 121 and the second channel 122. It can also be said that the existing channel is divided into the first channel 121 and the second channel 122 by the first pole and the second pole 16. Therefore, the double channel scheme proposed by the embodiments of the present application does not increase the area occupied by the vertical transistor.
[0095] In some embodiments, as shown in Figure 6 the chip further includes a capacitor in the direction of the vertical transistor along the first conductive layer 11, and the capacitor includes a first electrode 31, a dielectric layer 33, and a second electrode 32 which are sequentially stacked, and the first electrode 31 is electrically connected with the second pole 16 of the vertical transistor.
[0096] The chip containing the vertical transistor and the capacitor can be a memory chip, and the memory chip includes a memory array, and the memory array includes a plurality of memory cells, and each memory cell includes a vertical transistor and a capacitor. Of course, the chip containing the vertical transistor and the capacitor can also be applied to other circuits, and the embodiments of the present application do not limit this.
[0097] In some possible implementations, as shown in Figure 7 the capacitor is arranged on the side of the vertical transistor away from the substrate 10, and the gate 13, the gate dielectric layer 14, and the second pole 16 are sequentially stacked in the direction of the vertical transistor along the substrate 10. In this way, the first electrode 31, the dielectric layer 33, and the second electrode 32 are also sequentially stacked in the direction of the vertical transistor along the substrate 10.
[0098] Alternatively, as shown in Figure 8 the capacitor is arranged between the substrate 10 and the vertical transistor, and the second pole 16, the gate dielectric layer 14, and the gate 13 are sequentially stacked in the direction of the vertical transistor along the substrate 10. In this way, the second electrode 32, the dielectric layer 33, and the first electrode 31 are sequentially stacked in the direction of the vertical transistor along the substrate 10.
[0099] The preparation steps of the chip are different when the positions of the capacitor and the vertical transistor are different. The preparation steps of the chip when the capacitor is arranged on the side of the vertical transistor away from the substrate 10 are exemplarily introduced below in combination with the drawings:
[0100] As shown in Figure 11a first, the first conductive layer 11 and the insulating layer 21 are formed on the substrate 10, and the insulating layer 21 includes a first through hole, and the first conductive layer 11 also fills the first through hole of the insulating layer 21 so as to be in contact with the first sub-electrode 151 and the second sub-electrode 152 in the subsequent process.
[0101] Then, if Figure 11b As shown, a gate 13 is formed on the side of the insulating layer 21 facing away from the substrate 10 , and the gate 13 is electrically isolated from the first conductive layer 11 by the insulating layer 21 .
[0102] Then, if Figure 11c and Figure 11d As shown, a gate dielectric layer 141 is formed on the side of the gate 13 facing away from the substrate 10 , and the gate dielectric layer 141 exposes a portion of the first conductive layer 11 located in the first through hole, so that the first conductive layer 11 can subsequently contact the first sub-electrode 151 and the second sub-electrode 152 .
[0103] Then, if Figure 11e As shown, a semiconductor layer 120 is formed on the side of the gate dielectric layer 141 facing away from the substrate 10 , and the semiconductor layer 120 completely covers the first conductive layer 11 and the surface of the gate dielectric layer 141 facing away from the substrate 10 .
[0104] Then, if Figure 11f As shown, the semiconductor layer 120 is patterned to remove portions of the semiconductor layer 120 except for the region where the vertical transistor is located. Furthermore, portions of the semiconductor layer 120 located in the source and drain regions are heavily doped. The heavily doped portions of the semiconductor layer 120 are the first sub-electrode 151, the second sub-electrode 152, and the second electrode 16. The remaining portions of the semiconductor layer 120 are the first channel 121 and the second channel 122.
[0105] Among some possible implementations, Figure 5 As shown, after forming the first sub-electrode 151, the second sub-electrode 152, the second electrode 16, the first channel 121, and the second channel 122, the chip fabrication method further includes forming a shallow trench isolation layer 22 where the first sub-electrode 151 and the second sub-electrode 152 face away from the first conductive layer 11. The shallow trench isolation layer 22 is used to electrically isolate the second channel 122 of the first vertical transistor from the first channel 121 of the second vertical transistor adjacent to the first vertical transistor. Furthermore, the dielectric constant of the shallow trench isolation layer 22 is less than that of silicon dioxide; that is, the material of the shallow trench isolation layer 22 is a low-K dielectric.
[0106] By using a low-K shallow trench isolation layer 22 to electrically isolate the second channel 122 of the first vertical transistor from the first channel 121 of the second vertical transistor, the electric field coupling between the second channel 122 of the first vertical transistor and the first channel 121 of the second vertical transistor can be reduced, so that the second channel 122 of the first vertical transistor and the first channel 121 of the second vertical transistor are two electrically independent channels, thereby avoiding mutual influence between the second channel 122 of the first vertical transistor and the first channel 121 of the second vertical transistor.
[0107] The smaller the dielectric constant of the shallow trench isolation layer 22, the lower the electric field coupling between the second channel 122 of the first vertical transistor and the first channel 121 of the second vertical transistor. Therefore, the dielectric constant of the shallow trench isolation layer 22 can be less than 3, optionally.
[0108] Next, as shown in FIG. 4, a second via is formed in the shallow trench isolation layer 22. Figure 12 Figure 13a and Figure 13b As shown in FIG. 5, a first electrode 31, a dielectric layer 33, and a second electrode 32 are sequentially formed in the second via to obtain a capacitor.
[0109] The embodiments of the present application are described above with reference to the accompanying drawings, but the present application is not limited to the specific embodiments described above, which are merely illustrative but not restrictive. Those skilled in the art can make many modifications to the embodiments of the present application without departing from the spirit and scope of the present application and the claims, and all such modifications are within the scope of the present application.
Claims
1. A chip, characterized in that: It includes a first conductive layer and a vertical transistor stacked on a substrate, wherein the vertical transistor includes a gate, a gate dielectric layer, a first channel, a second channel, a first electrode, and a second electrode; Along the direction of the first conductive layer pointing to the vertical transistor, the gate, the gate dielectric layer, and the second electrode are stacked in sequence, and the gate dielectric layer covers the sidewall of the gate and the surface facing the second electrode; The first electrode includes a first sub-electrode and a second sub-electrode, the first sub-electrode and the second sub-electrode are respectively arranged on opposite sides of the sidewall of the gate dielectric layer, and the first sub-electrode and the second sub-electrode are electrically connected through the first conductive layer; The first channel is adjacent to the second electrode and the first sub-electrode, and the second channel is adjacent to the second electrode and the second sub-electrode.
2. The chip according to claim 1, characterized in that There are multiple vertical transistors, and the multiple vertical transistors are arranged in an array; Along the row direction, the second sub-electrode of any vertical transistor is reused as the first sub-electrode of the vertical transistor adjacent thereto.
3. The chip according to claim 2, characterized in that The chip further includes a shallow trench isolation layer, wherein the shallow trench isolation layer is arranged on a side of the first sub-electrode and the second sub-electrode away from the first conductive layer; The shallow trench isolation layer is used to electrically isolate the second channel of any vertical transistor from the first channel of the vertical transistor adjacent to the vertical transistor; Wherein, the dielectric constant of the shallow trench isolation layer is smaller than the dielectric constant of silicon dioxide.
4. The chip according to any one of claims 1 to 3, characterized in that: The chip further includes a capacitor, which is arranged along the first conductive layer and points in the direction of the vertical transistor, and the capacitor includes a first electrode and a second electrode which are stacked; The first electrode is electrically connected to the second electrode.
5. The chip according to claim 4, characterized in that The capacitor is arranged on the side of the vertical transistor away from the substrate; the gate, the gate dielectric layer, and the second electrode are stacked in sequence along the direction from the substrate to the vertical transistor; or, The capacitor is arranged between the substrate and the vertical transistor; along the direction from the substrate to the vertical transistor, the second electrode, the gate dielectric layer and the gate are stacked in sequence.
6. The chip according to claim 4 or 5, characterized in that: The second electrode and the first electrode completely cover the surface of the gate dielectric layer facing away from the gate.
7. The chip according to any one of claims 4 to 6, characterized in that: The first conductive layer includes a bit line, and the first sub-electrode and the second sub-electrode are electrically connected through the bit line.
8. The chip according to any one of claims 4 to 7, characterized in that: The vertical transistors and the capacitors constitute a memory array group, and the chip includes a plurality of the memory array groups; A plurality of memory array groups are stacked along a direction from the substrate to the vertical transistor.
9. An electronic device, characterized in that: The invention comprises a circuit board and the chip according to any one of claims 1 to 8, wherein the chip is arranged on the circuit board.
10. A method for preparing a chip, characterized in that: include: A first conductive layer and a vertical transistor are stacked on a substrate; the vertical transistor includes a gate, a gate dielectric layer, a first channel, a second channel, a first electrode, and a second electrode; Along the direction of the first conductive layer pointing to the vertical transistor, the gate, the gate dielectric layer, and the second electrode are stacked in sequence, and the gate dielectric layer covers the sidewall of the gate and the surface facing the second electrode; the first electrode includes a first sub-electrode and a second sub-electrode, and the first sub-electrode and the second sub-electrode are respectively arranged on opposite sides of the sidewall of the gate dielectric layer, and the first sub-electrode and the second sub-electrode are electrically connected through the first conductive layer; the first channel is adjacent to the second electrode and the first sub-electrode, and the second channel is adjacent to the second electrode and the second sub-electrode.
11. The preparation method according to claim 10, characterized in that: The chip preparation method further includes: A shallow trench isolation layer is formed on the side of the first sub-electrode and the second sub-electrode facing away from the first conductive layer; the shallow trench isolation layer is used to electrically isolate the second channel of any vertical transistor from the first channel of the vertical transistor adjacent to the vertical transistor; wherein the dielectric constant of the shallow trench isolation layer is less than the dielectric constant of silicon dioxide.
12. The preparation method according to claim 10 or 11, characterized in that: After forming the stacked first conductive layer and the vertical transistor on the substrate, the chip manufacturing method further includes: forming a capacitor; wherein the capacitor includes a stacked first electrode and a second electrode along a direction of the first conductive layer toward the vertical transistor, and the first electrode is electrically connected to the second electrode; The method of forming a stacked first conductive layer and a vertical transistor on a substrate includes: forming a first conductive layer on the substrate; The vertical transistor is formed on a side of the first conductive layer facing away from the substrate.
13. The preparation method according to claim 10 or 11, characterized in that: Before forming the stacked first conductive layer and the vertical transistor on the substrate, the chip manufacturing method further includes: forming a capacitor; wherein the capacitor includes a stacked first electrode and a second electrode along a direction of the first conductive layer toward the vertical transistor, and the first electrode is electrically connected to the second electrode; The method of forming a stacked first conductive layer and a vertical transistor on a substrate includes: forming the vertical transistor on a side of the capacitor facing away from the substrate; A first conductive layer is formed on a side of the vertical transistor facing away from the substrate.