Preparation method of nonvolatile memory based on rram+fcm structure

Abstract

The application provides a preparation method of a nonvolatile memory based on an RRAM+FCM structure. The preparation method comprises the following steps: generating a SiO2 layer on a substrate by passivation, depositing an amorphous HZO layer on the SiO2, and converting the amorphous HZO layer into a ferroelectric phase HZO by heat annealing; sputtering a metal layer on the ferroelectric layer, depositing a resistive layer on the metal layer, sputtering TaTiN metal to form a top electrode; and forming a gate pattern window through photolithography; performing ion implantation on a junction region, annealing, growing a SiO2 layer, forming a bottom electrode window through photolithography, and sputtering to form a bottom electrode. The memory formed by the preparation method of the nonvolatile memory based on the RRAM+FCM structure adopts a series connection of FCM and RRAM structures, and the advantages of high write speed, high durability, low power consumption, high storage density and new storage mechanism of the two structures are used to make up for the shortcomings of a traditional ferroelectric capacitor memory, so that a solid foundation is laid for related storage technologies and sufficient preparation is made for industrialization.

Description

TECHNICAL FIELD

[0001] The application provides a preparation method of a nonvolatile memory based on an RRAM+FCM structure, and belongs to the technical field of component preparation. BACKGROUND

[0002] The FCM has excellent application potential in real-time data evidence and high-frequency writing scenes such as automobile safety systems and industrial control due to nanosecond-level writing speed, ultra-low power consumption and ultra-high durability. The RRAM becomes a core carrier for breaking through the storage density bottleneck and the integrated hardware of storage and calculation by virtue of its simplified metal-insulator-metal (MIM) structure, theoretically unlimited stacking capacity and 4F² unit size. Both of them are facing the key challenges of industrialization: the FCM is limited by insufficient device switching ratio, and is easy to cause data storage errors in high-density storage; the RRAM is still a difficult problem for high-yield mass production due to its resistance randomness, operation voltage fluctuation and selector integration problem. The current RRAM is in the parallel stage of technical breakthrough and scene landing: it mainly focuses on data center storage class memory (SCM) and neuromorphic computing acceleration. The FCM has not realized industrial application at present. SUMMARY

[0003] The application provides a preparation method of a nonvolatile memory based on an RRAM+FCM structure, and belongs to the technical field of component preparation.

[0004] The preparation method of the nonvolatile memory based on the RRAM+FCM structure comprises the following steps:

[0005] An SiO2 layer is generated on a substrate, and an amorphous HZO layer is deposited on the SiO2 and is converted into a ferroelectric phase HZO through thermal annealing, comprising the following steps:

[0006] The Si substrate is cleaned by using an RCA cleaning process;

[0007] A heat accumulation type thermal incinerator is used to passivate the SiO2 layer on the surface of the Si substrate;

[0008] An atomic deposition method is used to deposit an amorphous HZO layer on the SiO2 layer;

[0009] A thermal annealing method of 300-600 DEG C is used to form a ferroelectric phase HZO on the amorphous HZO layer of the SiO2 layer in a nitrogen N2 atmosphere.

[0010] Further, the thickness of the SiO2 layer ranges from 1 to 3 nm.

[0011] Further, the heat accumulating thermal incinerator adopts a preset temperature control strategy to passivate the SiO2 layer on the surface of the Si substrate; wherein, the temperature control strategy comprises a preheating stage, a first ladder oxidation stage, a pulse high temperature stage, a second ladder oxidation stage and a cooling stage.

[0012] Further, the target temperature corresponding to the preheating stage is 400℃; the target temperature corresponding to the first ladder oxidation stage is 560℃; the target temperature corresponding to the pulse high temperature stage is 800℃ and 650℃; and the target temperature corresponding to the cooling stage is 25℃.

[0013] Further, the temperature control strategy corresponding to the SiO2 layer is as follows:

[0014] Preheating stage: from room temperature 25℃ to 400℃ at a rate not less than 18℃ / min, and keep the temperature at 400℃ for 10min.

[0015] First ladder oxidation stage: increase the temperature to 560℃ at a first temperature gradient, keep the temperature for 15min, and gradually carry out passivation reaction at 560℃;

[0016] Pulse high temperature stage: rapidly increase the temperature to 800℃ within 1min, maintain for 30s, then decrease the temperature to 650℃ within 2min, maintain for 15s, and repeat the temperature control process for 3 times;

[0017] Second ladder oxidation stage: keep the temperature at 650℃ for 18min;

[0018] Cooling stage: decrease the temperature to room temperature 25℃ at a second temperature gradient.

[0019] Further, the first temperature gradient is obtained by the following formula:

[0020] T 01 =[1+norm((D m ×K) / (G0×t 01 ))]×T a

[0021] Wherein, T 01 represents the first temperature gradient; D m represents the target thickness of the SiO2 layer; K represents the effective heat capacity of the circulating gas in the heat accumulating thermal incinerator; G0 represents the initial oxygen adsorption amount on the surface of the Si substrate, which is obtained by XPS detection in the pretreatment stage; t 01 represents the maximum allowed temperature rise time corresponding to the first ladder oxidation stage; T a represents the preset initial temperature rise gradient; norm() represents the normalization processing of the physical quantity in the parentheses.

[0022] Further, the second temperature gradient is obtained by the following formula:

[0023]

[0024] Wherein, T 02 represents the second temperature gradient; D s represents the actual growth thickness of the SiO2 layer after the end of the pulse high-temperature stage; J represents the heat loss coefficient of the heat accumulating thermal incinerator; a represents the difference between the thermal expansion coefficients of the Si substrate and the SiO2 film; t 02 represents the maximum allowed cooling time; T b represents the preset initial cooling gradient; norm() represents the normalization processing of the physical quantity in the parentheses.

[0025] Further, a metal layer is sputtered on the ferroelectric phase, a resistive switching layer is deposited on the metal layer, a metal layer is deposited on the resistive switching layer, and a gate pattern window is formed by photolithography, comprising:

[0026] Pt metal is sputtered and grown on the ferroelectric layer by a physical vapor deposition method to form a gate metal layer;

[0027] TaO2 resistive switching layer is deposited on the metal layer by an atomic deposition method;

[0028] TaTiN metal is sputtered and grown on the TaO2 resistive switching layer by a physical vapor deposition method;

[0029] A gate pattern window is formed by photolithography to define a junction region, and the excess material is etched and removed.

[0030] Further, TiN metal is sputtered in the bottom electrode window, comprising:

[0031] Ion implantation is performed in the junction region to form a heavily doped junction region, and then rapid annealing is performed to activate the doped ions in the junction region;

[0032] A layer of SiO2 is grown on the surface of the TaTiN metal and the exposed Si layer, a bottom electrode window is formed by photolithography, TiN metal is sputtered by a physical vapor deposition method, and then the photoresist and SiO2 are removed.

[0033] The present application has the following beneficial effects:

[0034] The memory formed by the preparation method of the nonvolatile memory based on the RRAM+FCM structure aims at the shortage of the traditional ferroelectric capacitor memory technology, and improves the discrimination of different storage states by proposing a device structure.

[0035] The memory formed by the preparation method of the nonvolatile memory based on the RRAM+FCM structure adopts the series connection of the FCM and the RRAM structure, utilizes the advantages of high write speed, high durability, low power consumption, high storage density and new storage mechanism of the two to make up for the shortage of the traditional ferroelectric capacitor memory, lays a solid foundation for the related storage technology, and makes full preparation for industrialization. BRIEF DESCRIPTION OF DRAWINGS

[0036] Figure 1 It is a RRAM-FCM device process flow chart.

[0037] Figure 2 It is a schematic view after the Si substrate is cleaned.

[0038] Figure 3 It is a schematic view of growing an oxide passivation layer on the Si substrate.

[0039] Figure 4 It is a schematic view of growing HZO material on the passivation layer and forming a ferroelectric phase after annealing.

[0040] Figure 5 It is a schematic view of growing a gate electrode on the FCM ferroelectric dielectric layer.

[0041] Figure 6 It is a schematic view of depositing a RRAM resistive switching dielectric layer on the gate electrode.

[0042] Figure 7 It is a schematic view of preparing a RRAM top electrode.

[0043] Figure 8 It is a schematic view of patterning after photolithography.

[0044] Figure 9 It is a schematic view of ion implantation and thermal annealing of the junction region after patterning.

[0045] Figure 10 Schematic diagram for growing bottom electrode above junction region. DETAILED DESCRIPTION

[0046] The preferred embodiments of the present application will be described herein below with reference to the drawings, in which it should be understood that the preferred embodiments described herein are intended for explaining and illustrating the present application, and are not intended for limiting the present application.

[0047] Embodiment 1

[0048] The preparation method of the nonvolatile memory based on the RRAM+FCM structure comprises:

[0049] forming a SiO2 layer on a substrate, and depositing an amorphous HZO layer on the SiO2 and converting into a ferroelectric phase HZO through thermal annealing;

[0050] sputtering a metal layer on the ferroelectric layer, depositing a resistive layer on the metal layer, sputtering a metal layer on the resistive layer, and forming a gate pattern window through photolithography;

[0051] after ion implantation on the junction region and annealing;

[0052] growing a SiO2 layer above the device, forming a bottom electrode window through photolithography, and sputtering a metal to form a bottom electrode.

[0053] Specifically, forming a SiO2 layer on a substrate, and depositing an amorphous HZO layer on the SiO2 and converting into a ferroelectric phase HZO through thermal annealing comprises:

[0054] S1, cleaning the Si substrate (100) by using RCA cleaning process, as shown in Figure 2 ;

[0055] S2, generating a SiO2 layer (101) on the surface of the Si substrate (100) by using a heat accumulation type thermal incinerator (RTO) for passivation; wherein the thickness of the SiO2 layer (101) ranges from 1-3nm. The SiO2 layer (101) has the functions of preventing diffusion pollution between the ferroelectric layer and the Si substrate and serving as a photolithographic patterning sacrificial layer, as shown in Figure 3 .

[0056] S3, depositing an amorphous HZO layer on the SiO2 layer (101) by using an atomic deposition method (ALD); and forming a ferroelectric phase (102) on the amorphous HZO layer of the SiO2 layer (101) by using a rapid thermal annealing method (RTA) at 300-600℃ in a nitrogen N2 atmosphere, as shown in Figure 4 .

[0057] Meanwhile, a metal layer is sputtered on the ferroelectric layer, a resistive switching layer is deposited on the metal layer, a metal layer is sputtered on the resistive switching layer and a gate pattern window is formed by photolithography, comprising:

[0058] S4, a Pt metal is sputtered on the ferroelectric layer (102) by a physical vapor deposition method (PVD) to form a metal layer (103); wherein the metal layer (103) serves as a shared electrode connecting the ferroelectric layer and the resistive switching layer, as shown in Figure 5

[0059] S5, a TaO2 resistive switching layer (104) is deposited on the metal layer (103) by an atomic layer deposition method (ALD), as shown in Figure 6

[0060] S6, a TaTiN metal (105) is sputtered on the TaO2 resistive switching layer (104) by a physical vapor deposition method (PVD), as shown in Figure 7

[0061] S7, a gate pattern window is formed by photolithography to define a junction region, and the excess material is etched away, as shown in Figure 8

[0062] Specifically, a TiN metal is sputtered in the gate pattern window, comprising:

[0063] S8, ion implantation is performed on the junction region corresponding to the gate pattern window to form a heavily doped junction region, as shown in Figure 9

[0064] S9, the doped ions in the junction region are activated by rapid annealing.

[0065] S10, a SiO2 layer is grown on the TaTiN metal (105) and the exposed Si layer (101) surface, a bottom electrode window is formed by photolithography, and a TiN metal (106) is sputtered by a physical vapor deposition method (PVD), and then the photoresist and SiO2 are removed, as shown in Figure 10

[0066] Semiconductor doping includes ion implantation, diffusion doping and epitaxial growth doping, etc.

[0067] ​​​​​​The working principle and effects of the technical solution are as follows: the preparation method of the nonvolatile memory based on the RRAM+FCM structure is a new device structure in which a memristor (RRAM) and a ferroelectric capacitor memory (FCM) are connected in series. To manufacture the structure, a SiO2 layer is first formed on a Si substrate material by passivation, and then a HZO ferroelectric dielectric layer and a gate electrode are deposited on the SiO2 material to form a FCM structure; a metal bottom electrode, a hafnium oxide resistance variable material and a top electrode metal are deposited at the FCM gate electrode, and finally a MIM structure on the original FCM port is formed by photolithography and etching processing to complete the integration of the RRAM and the FCM. The nonvolatile memory has the advantages of simple structure, high writing speed, high durability, low power consumption and CMOS compatibility. The high and low capacitance ratio of the traditional capacitor is not large enough, and the state misjudgment is easily caused by external noise signal interference; the durability is reduced and the device erasing and writing cycle number is small due to the influence of the defects of the ferroelectric material and the electrode interface effect; and the memory formed by the preparation method of the embodiment uses the FCM and RRAM structure in series, and uses the advantages of high writing speed, high durability, low power consumption, high storage density and new storage mechanism of the two to make up for the shortcomings of the traditional ferroelectric capacitor memory, thereby laying a solid foundation for related storage technology and making full preparation for industrialization.

[0068] The above technical solution proposed in the embodiment solves the defect that the ferroelectric capacitor is easily interfered by external signals when used for designing a memory.

[0069] Embodiment 2

[0070] In the embodiment, the RTO (Regenerative Thermal Oxidizer) generates a SiO2 layer (101) on the surface of a Si substrate (100) by using a preset temperature control strategy; wherein the temperature control strategy includes a preheating stage, a first ladder oxidation stage, a pulse high temperature stage, a second ladder oxidation stage and a cooling stage.

[0071] The target temperature corresponding to the preheating stage is 400℃; the target temperature corresponding to the first ladder oxidation stage is 560℃; the target temperatures corresponding to the pulse high temperature stage are 800℃ and 650℃; and the target temperature corresponding to the cooling stage is 25℃.

[0072] Specifically, the temperature control strategy corresponding to the generation of the SiO2 layer is as follows:

[0073] Preheating stage: from room temperature 25℃ to 400℃ at a rate of not less than 18℃ / min, and keep the temperature at 400℃ for 10min; the purpose of this stage is to uniformly raise the overall temperature of the Si substrate (100) by slow heating, so as to reduce the initial temperature difference and lay a good foundation for the subsequent oxidation reaction.

[0074] First-step oxidation stage: The temperature is increased to 560℃ at the first temperature gradient (unit: ℃ / min), held for 15 min, and passivation reaction is carried out step by step at 560℃. The slower heating rate and appropriate holding time help the SiO2 layer to form initially and ensure its initial uniform distribution on the substrate surface.

[0075] Pulsed high-temperature stage: The temperature is rapidly increased to 800℃ within 1 minute, maintained for 30 seconds, and then cooled to 650℃ within 2 minutes, maintained for 15 seconds. This temperature adjustment process is repeated 3 times. Rapidly heating to high temperature can promote the oxidation reaction in a short time and increase the thickness of the SiO2 layer, while short-term holding and rapid cooling can avoid the increase of interface defects caused by prolonged high temperature.

[0076] The second-stage oxidation process involves maintaining a constant temperature of 650℃ for 18 minutes. This stage primarily optimizes the SiO2 layer to ensure a more complete and stable oxidation reaction, thereby further improving the quality of the SiO2 layer.

[0077] Cooling stage: The temperature is reduced to room temperature (25°C) at a rate of the second temperature gradient (unit: °C / min). The slow cooling rate can reduce the internal stress caused by sudden temperature changes and prevent defects such as cracks in the SiO2 layer.

[0078] The first temperature gradient is obtained by the following formula:

[0079] T 01 =[1+norm((D m ×K) / (G0×t 01 ))]×T a

[0080] Among them, T 01 D represents the first temperature gradient; m The target thickness of the SiO2 layer is indicated by K; the effective heat capacity of the circulating gas in the regenerative thermal incinerator is indicated by G0; the initial oxygen adsorption amount on the Si substrate surface is indicated by XPS detection during the pretreatment stage; t 01 T represents the maximum allowable temperature rise time corresponding to the first stage of oxidation; a This indicates the preset initial temperature gradient; norm() indicates the normalization of the physical quantities within the parentheses.

[0081] Furthermore, the second temperature gradient is obtained using the following formula:

[0082]

[0083] Among them, T 02 D represents the second temperature gradient; srepresents the actual growth thickness of the SiO2 layer after the end of the pulse high-temperature stage, obtained by real-time optical ellipsometry detection; J represents the heat loss coefficient of the heat accumulating thermal incinerator, calculated from the thermal conductivity coefficient of the heat insulation material of the furnace body and the surface area; a represents the difference between the thermal expansion coefficients of the Si substrate and the SiO2 film; t 02 represents the maximum allowed cooling time; T b represents the preset initial cooling gradient; norm() represents the normalization processing of the physical quantity in the parentheses.

[0084] The working principle and effects of the above technical solution: The above technical solution proposed in this embodiment is different from the continuous high-temperature or monotonic temperature rising mode in the prior art. Through the pulse cycle of "rapid rising-short holding-sudden dropping", the directional diffusion of oxygen atoms in the Si lattice is promoted by using the thermal shock effect, and the Si atom outward diffusion phenomenon caused by long time high temperature is avoided. It is verified by experiments that the interface state density can be reduced to below. This embodiment solves the contradiction between thickness uniformity and density in the traditional constant temperature process by designing an asymmetric step of 400℃→560℃→800℃→650℃ and respectively regulating the nucleation rate and growth rate of SiO2 in different temperature intervals, so that the film thickness deviation is controlled within 1.5%. At the same time, the slow temperature rising in the preheating stage and the gradient cooling in the cooling stage form a temperature stress buffer, which, combined with the instantaneous activation effect of the pulse high temperature, realizes the whole process optimization of "low-temperature nucleation-high-temperature growth-medium-temperature densification-cold setting", which is essentially different from the single temperature regulation logic of the prior art.

[0085] At the same time, the first temperature gradient is dynamically associated with the target thickness, the heat capacity of the circulating gas, and the initial oxygen adsorption amount, and is combined with the constraint of the maximum allowed heating time, so that the heating rate is self-adaptive to the initial state of the substrate surface, avoiding the thickness sudden increase caused by too fast reaction in this area, and finally controlling the in-plane thickness deviation of the SiO2 layer within ±2%, which is more than 50% higher than the traditional fixed rate process. At the same time, the connection from preliminary setting to rapid growth of the SiO2 film is formed by the pulse cycle of 800℃ and 650℃ and the first step oxidation controlled by the first temperature gradient, and the normalization processing ensures the consistency of the reaction activity of different batches of substrates in the pulse stage, so that the batch difference of the film thickness is reduced to less than 3%.

[0086] On the other hand, the first temperature gradient formula combines the initial heating gradient with a dynamic correction term, avoiding the "over-oxidation" phenomenon in the first step oxidation stage. When the oxygen adsorption amount on the substrate surface is low, the formula will increase the heating rate through normalization processing, shorten the low-temperature reaction time below 560℃, and reduce the disordered diffusion of oxygen atoms in the Si lattice; while the short-time 800℃ heating in the pulse high-temperature stage promotes the directional migration of oxygen atoms, so that the Si / SiO2 interface state density is reduced to The following is reduced by 40% compared with the traditional process. At the same time, the association between the heat loss coefficient and the actual thickness in the second temperature gradient formula ensures that the rate of the cooling stage matches the actual growth state of the film. Further, the film is fully crystallized during the slow cooling process, and the density (refractive index measured by an ellipsometer) is stabilized at 1.46±0.01, close to the theoretical value of SiO2.

[0087] At the same time, the second temperature gradient formula dynamically matches the cooling rate with the stress accumulation state of the film by the difference in the thermal expansion coefficient, the constraint of the maximum allowed cooling time, and the feedback of the actual thickness. When the difference (α) in the thermal expansion coefficient between the Si substrate and SiO2 increases due to temperature fluctuations, the formula will reduce the second temperature gradient through normalization to avoid the concentration of tensile stress caused by the difference in shrinkage rate. The incidence of micro-cracks on the surface of the film is reduced to below 0.1‰, detected by a laser confocal microscope. At the same time, the rapid heating (≥18℃ / min) in the preheating stage and the slow cooling controlled by the second temperature gradient form a stress balance mechanism of "quick heating-slow cooling", combined with the holding stages at 560℃ and 650℃, so that the internal stress (measured by Raman spectroscopy) of the film is controlled within 150MPa, reduced by 60% compared with the traditional process, meeting the requirements of high-frequency devices for low-stress insulating layers.

[0088] Obviously, those skilled in the art can make various modifications and variations to the present application without departing from the spirit and scope of the present application. Thus, if these modifications and variations of the present application fall within the scope of the claims of the present application and their equivalent technologies, the present application also intends to include these modifications and variations.

Claims

1. A method for fabricating a nonvolatile memory based on a RRAM+FCM structure, characterized in that, The nonvolatile memory preparation method comprises: generating a SiO2 layer on a substrate, and depositing an amorphous HZO layer on the SiO2 and converting into a ferroelectric phase HZO through thermal annealing; sputtering a metal layer on the ferroelectric layer, depositing a resistive layer on the metal layer, sputtering a metal layer on the resistive layer, and forming a gate pattern window through photolithography; after semiconductor doping on the junction region and annealing; growing a SiO2 layer above the device, forming a bottom electrode window through photolithography, and sputtering a bottom electrode metal in the bottom electrode window; wherein, the generating a SiO2 layer on a substrate, and depositing an amorphous HZO layer on the SiO2 and converting into a ferroelectric phase HZO through thermal annealing comprises: cleaning the Si substrate (100) by using RCA cleaning process; passivating the surface of the Si substrate (100) to generate a SiO2 layer (101) by using a heat accumulation type thermal incinerator; depositing an amorphous HZO layer on the SiO2 layer (101) by using atomic deposition method; forming a ferroelectric phase HZO (102) on the amorphous HZO layer of the SiO2 layer (101) by using thermal annealing at 300-600℃ in a nitrogen N2 atmosphere; wherein, the heat accumulation type thermal incinerator uses a preset temperature control strategy to passivate the surface of the Si substrate (100) to generate a SiO2 layer (101); wherein, the temperature control strategy comprises a preheating stage, a first ladder oxidation stage, a pulse high temperature stage, a second ladder oxidation stage and a cooling stage.

2. The method of claim 1, wherein the method further comprises: The thickness of the SiO2 layer (101) ranges from 1-3nm.

3. The method of claim 1, wherein the method further comprises: The target temperature corresponding to the preheating stage is 400℃; the target temperature corresponding to the first ladder oxidation stage is 560℃; the target temperatures corresponding to the pulse high temperature stage are 800℃ and 650℃; and the target temperature corresponding to the cooling stage is 25℃.

4. The method of claim 2, wherein the method further comprises: The temperature control strategy corresponding to generating the SiO2 layer is as follows: the preheating stage: increasing the temperature from room temperature 25℃ to 400℃ at a rate not lower than 18℃ / min, and maintaining the temperature at 400℃ for 10min; the first ladder oxidation stage: increasing the temperature to 560℃ at a first temperature gradient, maintaining the temperature for 15min, and gradually performing passivation generation reaction at 560℃; the pulse high temperature stage: rapidly increasing the temperature to 800℃ within 1min, maintaining the temperature for 30s, then decreasing the temperature to 650℃ within 2min, maintaining the temperature for 15s, and repeating the temperature adjustment process for 3 times; the second ladder oxidation stage: maintaining the temperature at 650℃ for 18min; the cooling stage: decreasing the temperature to room temperature 25℃ at a second temperature gradient.

5. The method of claim 1, wherein the method further comprises: The sputtering a metal layer on the ferroelectric layer, depositing a resistive layer on the metal layer, sputtering a metal layer on the resistive layer, and forming a gate pattern window through photolithography comprises: sputtering and growing Pt metal on the ferroelectric layer (102) to form a metal layer (103) by using physical vapor deposition method; depositing TaO2 resistive layer (104) on the metal layer (103) by using atomic deposition method; sputtering and growing TaTiN metal (105) on the TaO2 resistive layer (104) by using physical vapor deposition method; forming a gate pattern window by using photolithography, defining a junction region, and etching to remove excess materials.

6. The method of claim 1, wherein the method further comprises: Sputtering a bottom electrode metal in the bottom electrode window, including: Ion implantation in the junction region to form a heavily doped junction region, and then rapid annealing to activate the doped ions in the junction region; Growth of a SiO2 layer on the surface of the TaTiN metal (105) and the exposed Si layer (101), photolithography to form a bottom electrode window, sputtering of a TiN metal (106) by physical vapor deposition, and removal of the photoresist and SiO2.

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