Multi-current path bidirectional scr device for esd protection

Abstract

The application provides a multi-current-path bidirectional SCR device for ESD protection, comprising a P-type substrate, an N-type epitaxial layer, a first P-type buried layer, an N-type buried layer, a second P-type buried layer, a first P-type well region, an N-type well region, a second P-type well region, an anode P+ region, an anode N+ region, a floating N+ region, a cathode N+ region and a cathode P+ region; the application introduces a buried layer structure on the basis of the structure of a conventional bidirectional SCR device for ESD protection, divides the internal current path of the device into a well region current path and a buried layer current path, optimizes the heat distribution in the device, makes the heat distribution of the device more uniform, improves the failure current of the device without increasing the area of the device, increases the performance of the device per unit area, and enhances the anti-electric surge capability of the device.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device technology, and in particular to a multi-current-path bidirectional SCR device for ESD protection. Background Technology

[0002] ESD, or electrostatic discharge, is an ancient natural phenomenon. ESD exists in every corner of daily life. However, this seemingly commonplace electrical phenomenon poses a fatal threat to delicate integrated circuits. Electric surges / transient voltages refer to sudden, random, and abnormally high voltages or currents exceeding normal conditions in a circuit. They are characterized by their short duration and extremely high instantaneous energy. Electric surges are highly destructive to electronic components and integrated circuits. At best, they induce malfunctions in logic circuits; at worst, they cause secondary breakdowns of transistors, latch-up effects in CMOS devices (Complementary Metal Oxide Semiconductors), and other severe thermal effects that lead to device or integrated circuit failure. Electric surges typically have two random sources: the first is instability in the power grid, such as sudden switching on / off, sudden starting of capacitive or inductive loads, hot-plugging of related equipment, and unstable operation of related power supplies. The second is sudden external interference, such as lightning or electrostatic discharge.

[0003] With advancements in integrated circuit manufacturing processes, the minimum linewidth has decreased to the submicron or even nanometer level. While this has led to improved chip performance, it has also significantly reduced the chip's resistance to ESD (Electrostatic Discharge), making electrostatic damage more severe. Most ESD incidents cause non-fatal damage to integrated circuits, reducing their lifespan and reliability, and ultimately leading to system functional degradation. This poses a significant obstacle to achieving large-scale, highly reliable integration. Summary of the Invention

[0004] To achieve an ESD protection device with excellent heat dissipation and surge protection capabilities, this invention provides a multi-current-path bidirectional SCR device for ESD protection, which optimizes the internal heat distribution and enhances the device's surge protection capability. To achieve the above technical objectives, the technical solution adopted in this invention is as follows:

[0005] This invention provides a multi-current-path bidirectional SCR device for ESD protection, comprising:

[0006] P-type substrate, N-type epitaxial layer, first P-type buried layer, N-type buried layer, second P-type buried layer, first P-type well region, N-type well region, second P-type well region, anode P+ region, anode N+ region, floating N+ region, cathode N+ region, cathode P+ region;

[0007] The anode P+ region and the anode N+ region are located inside the first P-type well region, with their upper edges tangent to the upper edge of the first P-type well region and their lower edges higher than the lower edge of the first P-type well region. The anode P+ region is located to the left of the anode N+ region, and its right edge is tangent to the left edge of the anode N+ region. Both are on the same horizontal line as the lower edge of the floating N+ region. The left edge of the anode P+ region is spaced apart from the left edge of the first P-type well region. The right edge of the anode N+ region is spaced apart from the left edge of the floating N+ region.

[0008] The floating N+ region is located inside the N-type well region. Its upper edge is tangent to the upper edge of the N-type well region, and its lower edge is higher than the lower edge of the N-type well region. The left edge of the floating N+ region is a certain distance from the right edge of the anode N+ region, and the right edge of the floating N+ region is a certain distance from the left edge of the cathode N+ region.

[0009] The cathode N+ region and cathode P+ region are located inside the second P-type well region. Their upper edges are tangent to the upper edge of the second P-type well region, and their lower edges are higher than the lower edge of the second P-type well region. The cathode N+ region is located to the left of the cathode P+ region, and its right edge is tangent to the left edge of the cathode P+ region. Both are on the same horizontal line as the lower edge of the floating N+ region. The right edge of the cathode P+ region is separated from the right edge of the second P-type well region. The left edge of the cathode N+ region is separated from the right edge of the floating N+ region.

[0010] The first P-type well region, the N-type well region, and the second P-type well region are all located inside the N-type epitaxial layer. The left edge of the first P-type well region is tangent to the left edge of the N-type epitaxial layer, its right edge is tangent to the left edges of the floating N+ region and the N-type well region, and its lower edge is tangent to the upper edge of the first P-type buried layer. The left edge of the N-type well region is tangent to the right edge of the first P-type well region, its lower edge is tangent to the upper edge of the N-type buried layer, and its right edge is tangent to the left edge of the second P-type well region. The left edge of the second P-type well region is tangent to the right edges of the floating N+ region and the N-type well region, its right edge is tangent to the right edge of the N-type epitaxial layer, and its lower edge is tangent to the upper edge of the second P-type buried layer.

[0011] The first P-type buried layer, the N-type buried layer, and the second P-type buried layer are all located inside the N-type epitaxial layer. The lower edges of the three layers are on the same horizontal line and are higher than the lower edge of the N-type epitaxial layer. The left edge of the first P-type buried layer is tangent to the left edge of the N-type epitaxial layer, its upper edge is tangent to the lower edge of the first P-type well region, and its right edge is tangent to the left edge of the N-type buried layer. The upper edge of the N-type buried layer is tangent to the lower edge of the N-type well region. The left edge of the second P-type buried layer is tangent to the right edge of the N-type buried layer, its upper edge is tangent to the lower edge of the second P-type well region, and its right edge is tangent to the right edge of the N-type epitaxial layer.

[0012] The lower edge of the N-type epitaxial layer is tangent to the upper edge of the P-type substrate, and its lower edge is higher than the lower edge of the P-type substrate.

[0013] Furthermore, the reverse breakdown voltage of the PN junction formed by the floating N+ region and the second P-type well region is less than the reverse breakdown voltage of the PN junction formed by the N-type buried layer and the second P-type buried layer.

[0014] Furthermore, the reverse breakdown voltage of the PN junction formed by the floating N+ region and the second P-type well region is V. B1 The reverse breakdown voltage of the PN junction formed by the N-type buried layer and the second P-type buried layer is V. B2 V B2 / V B1 =n (n>1), then the reduced concentration N0 of the PN junction formed by the floating N+ region and the second P-type well region is related to V. B2 V B1 The relationship is shown in formula (1):

[0015] (1).

[0016] Furthermore, the range of n is 1.1 < n < 2.

[0017] Furthermore, the donor impurity concentration N in the N-type buried layer nB Second P-type buried layer acceptor impurity concentration N pB The proportional relationship is shown in formula (2):

[0018] (2)

[0019] Wherein, N0 is the reduced concentration of the PN junction formed by the floating N+ region and the second P-type well region.

[0020] The beneficial effects of the technical solution provided by the embodiments of the present invention are as follows: Based on the traditional bidirectional SCR device structure for ESD protection, this application introduces a buried layer structure, which divides the internal current path of the device into a well current path and a buried layer current path, optimizes the internal heat distribution of the device, makes the heat distribution of the device more uniform, improves the failure current of the device without increasing the device area, increases the performance of the device per unit area, and enhances the surge protection capability of the device. Attached Figure Description

[0021] Figure 1 This is a schematic diagram of a traditional bidirectional SCR device used for ESD protection.

[0022] Figure 2 This is a schematic diagram of a multi-current-path bidirectional SCR device structure for ESD protection in an embodiment of the present invention.

[0023] Figure 3 This is a schematic diagram of a new current path for a multi-current-path bidirectional SCR device for ESD protection in an embodiment of the present invention.

[0024] Figure 4 This is a schematic diagram of the IV characteristic curve of a traditional bidirectional SCR device used for ESD protection.

[0025] Figure 5 This is a schematic diagram of the IV characteristic curve of a multi-current-path bidirectional SCR device for ESD protection in an embodiment of the present invention. Detailed Implementation

[0026] To make the objectives, technical solutions, and advantages of this invention clearer, the invention will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative and not intended to limit the invention.

[0027] In the description of the embodiments of the present invention, it should be noted that the terms "center," "upper," "lower," "left," "right," "vertical," "horizontal," "inner," and "outer," etc., indicate the orientation or positional relationship based on the orientation or positional relationship shown in the accompanying drawings. They are only for the convenience of describing the present invention and simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation. Therefore, they should not be construed as limitations on the present invention. In addition, the terms "first," "second," and "third" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0028] In the description of the embodiments of the present invention, it should be noted that, unless otherwise explicitly specified and limited, the terms "installation," "connection," and "linking" should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral connection; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can also refer to the internal connection of two components; and they can refer to a wireless connection or a wired connection. Those skilled in the art can understand the specific meaning of the above terms in the present invention based on the specific circumstances.

[0029] Furthermore, the technical features involved in the different embodiments of the present invention described below can be combined with each other as long as they do not conflict with each other.

[0030] Traditional bidirectional SCR devices for ESD protection, such as Figure 1 As shown, it includes a P-type substrate 001, an N-type epitaxial layer 100, a first P-type well region 301, an N-type well region 302, a second P-type well region 303, an anode P+ region 401, an anode N+ region 402, a floating N+ region 403, a cathode N+ region 404, and a cathode P+ region 405.

[0031] The multi-current-path bidirectional SCR device (hereinafter referred to as bidirectional SCR device) for ESD protection proposed in this embodiment of the invention, compared with the traditional bidirectional SCR device, adds a buried layer structure, namely a first P-type buried layer 201, an N-type buried layer 202, and a second P-type buried layer 203; as shown Figure 2 As shown; an embodiment of the present invention proposes a multi-current-path bidirectional SCR device for ESD protection, comprising:

[0032] P-type substrate 001, N-type epitaxial layer 100, first P-type buried layer 201, N-type buried layer 202, second P-type buried layer 203, first P-type well region 301, N-type well region 302, second P-type well region 303, anode P+ region 401, anode N+ region 402, floating N+ region 403, cathode N+ region 404, cathode P+ region 405;

[0033] Anode P+ region 401 and anode N+ region 402 are located inside the first P-type well region 301. Their upper edges are tangent to the upper edge of the first P-type well region 301, and their lower edges are higher than the lower edge of the first P-type well region 301. Anode P+ region 401 is located to the left of anode N+ region 402, and its right edge is tangent to the left edge of anode N+ region 402. Both are on the same horizontal line as the lower edge of floating N+ region 403. The left edge of anode P+ region 401 is spaced apart from the left edge of the first P-type well region 301. The right edge of anode N+ region 402 is spaced apart from the left edge of floating N+ region 403.

[0034] The floating N+ region 403 is inside the N-type well region 302. Its upper edge is tangent to the upper edge of the N-type well region 302, and its lower edge is higher than the lower edge of the N-type well region 302. The left edge of the floating N+ region 403 is a certain distance from the right edge of the anode N+ region 402, and the right edge of the floating N+ region 403 is a certain distance from the left edge of the cathode N+ region 404.

[0035] The cathode N+ region 404 and cathode P+ region 405 are located inside the second P-type well region 303. Their upper edges are tangent to the upper edge of the second P-type well region 303, and their lower edges are higher than the lower edge of the second P-type well region 303. The cathode N+ region 404 is located to the left of the cathode P+ region 405, and its right edge is tangent to the left edge of the cathode P+ region 405. Both are on the same horizontal line as the lower edge of the floating N+ region 403. The right edge of the cathode P+ region 405 is separated from the right edge of the second P-type well region 303. The left edge of the cathode N+ region 404 is separated from the right edge of the floating N+ region 403.

[0036] The first P-type well region 301, the N-type well region 302, and the second P-type well region 303 are all located inside the N-type epitaxial layer 100. The left edge of the first P-type well region 301 is tangent to the left edge of the N-type epitaxial layer 100, its right edge is tangent to the left edge of the floating N+ region 403 and the N-type well region 302, and its lower edge is tangent to the upper edge of the first P-type buried layer 201. The left edge of the N-type well region 302 is tangent to the right edge of the first P-type well region 301, its lower edge is tangent to the upper edge of the N-type buried layer 202, and its right edge is tangent to the left edge of the second P-type well region 303. The left edge of the second P-type well region 303 is tangent to the right edge of the floating N+ region 403 and the N-type well region 302, its right edge is tangent to the right edge of the N-type epitaxial layer 100, and its lower edge is tangent to the upper edge of the second P-type buried layer 203.

[0037] The first P-type buried layer 201, the N-type buried layer 202, and the second P-type buried layer 203 are all located inside the N-type epitaxial layer 100. The lower edges of the three are on the same horizontal line and are higher than the lower edge of the N-type epitaxial layer 100. The left edge of the first P-type buried layer 201 is tangent to the left edge of the N-type epitaxial layer 100, its upper edge is tangent to the lower edge of the first P-type well region 301, and its right edge is tangent to the left edge of the N-type buried layer 202. The upper edge of the N-type buried layer 202 is tangent to the lower edge of the N-type well region 302. The left edge of the second P-type buried layer 203 is tangent to the right edge of the N-type buried layer 202, its upper edge is tangent to the lower edge of the second P-type well region 303, and its right edge is tangent to the right edge of the N-type epitaxial layer 100.

[0038] The lower edge of the N-type epitaxial layer 100 is tangent to the upper edge of the P-type substrate 001, and its lower edge is higher than the lower edge of the P-type substrate 001.

[0039] This application introduces a buried layer structure on the basis of the traditional bidirectional SCR device for ESD protection, which divides the internal current path of the device into a well current path and a buried layer current path, optimizes the internal heat distribution of the device, makes the heat distribution of the device more uniform, improves the failure current of the device without increasing the device area, increases the performance of the device per unit area, and enhances the surge protection capability of the device.

[0040] like Figure 3 As shown, when the ESD voltage arrives, when the voltage is relatively small, the PN junction formed by the floating N+ region 403 and the second P-type well region 303 breaks down in reverse. The current starts from the anode P+ region 401, flows through the first P-type well region 301, the N-type well region 302, the floating N+ region 403, and the second P-type well region 303 in sequence, and is finally discharged through the cathode P+ region 405. At this time, the current is relatively small.

[0041] As holes accumulate in the second P-type well region 303, the PN junction formed by the second P-type well region 303 and the cathode N+ region 404 partially conducts forward, and the current further increases. At this time, the first trigger voltage of the device is reached, forming the current path when the conventional bidirectional SCR device is turned on: the current starts from the anode P+ region 401, flows through the first P-type well region 301, the N-type well region 302, and the second P-type well region 303 in sequence, and is finally discharged through the cathode N+ region 404;

[0042] The above two paragraphs describe the well region current path; the internal current path of a traditional bidirectional SCR device is only the well region current path.

[0043] like Figure 3 As shown by the dashed line a, when the voltage increases further, the PN junction formed by the N-type buried layer 202 and the second P-type buried layer 203 in the buried layer structure breaks down in the reverse direction. At this time, a new non-conductive SCR structure is formed below the well region. The new current path is as follows: the current starts from the anode P+ region 401, flows through the first P-type well region 301, the first P-type buried layer 201, the N-type buried layer 202, the second P-type buried layer 203, and the second P-type well region 303 in sequence, and is finally discharged through the cathode P+ region 405.

[0044] like Figure 3 As shown by the dashed line b, when the voltage increases further, as holes accumulate in the second P-type well region 303, the PN junction formed in the vertical direction by the second P-type well region 303 and the cathode N+ region 404 becomes conductive, and the current increases further. At this time, the second trigger voltage of the device is reached, and a new conductive SCR structure is formed below the well region. The new current path is as follows: the current starts from the anode P+ region 401, flows through the first P-type well region 301, the first P-type buried layer 201, the N-type buried layer 202, the second P-type buried layer 203, and the second P-type well region 303 in sequence, and is finally discharged through the cathode N+ region 404.

[0045] The above two paragraphs describe the buried current path added in this application; the IV characteristic curve of a traditional bidirectional SCR device is as follows: Figure 4 As shown, the IV characteristic curve of the bidirectional SCR device proposed in this application is as follows: Figure 5 As shown, this application divides the internal current path of the device into a well current path and a buried layer current path. The new current path enables the device to perform an additional snapback (fast recovery) when the current is high.

[0046] The reverse breakdown voltage of the PN junction formed by the floating N+ region 403 and the second P-type well region 303 is slightly less than that of the PN junction formed by the N-type buried layer 202 and the second P-type buried layer 203. This causes the generation of the well region current path to precede the buried layer current path. The buried layer current path is a supplement to the well region current path, making the current path area larger, optimizing the internal heat distribution of the device, making the heat distribution within the device more uniform, and enhancing the device's surge protection capability.

[0047] The reverse breakdown voltage of the PN junction formed by the floating N+ region 403 and the second P-type well region 303 is V. B1 The reverse breakdown voltage of the PN junction formed by the N-type buried layer 202 and the second P-type buried layer 203 is V. B2 V B2 / V B1 =n (n>1), then the reduced concentration N0 of the PN junction formed by the floating N+ region 403 and the second P-type well region 303 is related to V. B2 V B1 The relationship is shown in formula (1):

[0048] (1)

[0049] For example, the reverse breakdown voltage V of the PN junction formed by the floating N+ region 403 and the second P-type well region 303. B1 The reverse breakdown voltage V of the PN junction formed by the N-type buried layer 202 and the second P-type buried layer 203 is approximately 7.5V. B2 For V B1 If 1.2 times is 9V, then the reduced concentration N0 of the PN junction formed by the floating N+ region 403 and the second P-type well region 303 is 1.3 × 10⁻⁶. 17 cm -3 The range of n is 1.1 < n < 2, for example, 1.2, 1.4, 1.6, 1.8, etc.

[0050] Furthermore, embodiments of this application also propose a donor impurity concentration N for the N-type buried layer 202. nB The concentration of acceptor impurities N in the second P-type buried layer 203 pB The proportional relationship is shown in formula (2):

[0051] (2)

[0052] Wherein, N0 is the reduced concentration of the PN junction formed by the floating N+ region 403 and the second P-type well region 303; this ratio is not a simple application of traditional empirical formulas, but a structural parameter specifically designed in this application to ensure the stable operation of ESD protection devices; by precisely setting the doping concentration ratio of the PN junction formed between the N-type buried layer 202 and the second P-type buried layer 203, that is, the donor impurity concentration N of the N-type buried layer 202... nB The concentration of acceptor impurities N in the second P-type buried layer 203 pB The proportional relationship enables controllability of reverse breakdown voltage, conduction characteristics, and triggering behavior.

[0053] Finally, it should be noted that the above specific embodiments are only used to illustrate the technical solutions of the present invention and not to limit it. Although the present invention has been described in detail with reference to the embodiments, those skilled in the art should understand that modifications or equivalent substitutions can be made to the technical solutions of the present invention without departing from the spirit and scope of the technical solutions of the present invention, and all such modifications or substitutions should be covered within the scope of the claims of the present invention.

Claims

1. A multi-current-path bidirectional SCR device for ESD protection, characterized by, Comprise: P-type substrate (001), N-type epitaxial layer (100), first P-type buried layer (201), N-type buried layer (202), second P-type buried layer (203), first P-type well region (301), N-type well region (302), second P-type well region (303), anode P+ region (401), anode N+ region (402), floating N+ region (403), cathode N+ region (404), cathode P+ region (405); The anode P+ region (401) and the anode N+ region (402) are located inside the first P-type well region (301), the upper edge thereof is tangent to the upper edge of the first P-type well region (301), and the lower edge thereof is higher than the lower edge of the first P-type well region (301); the anode P+ region (401) is located on the left side of the anode N+ region (402) and the right edge thereof is tangent to the left edge of the anode N+ region (402), both of which are located on the same horizontal line with the lower edge of the floating N+ region (403); the left edge of the anode P+ region (401) is spaced apart from the left edge of the first P-type well region (301); the right edge of the anode N+ region (402) is spaced apart from the left edge of the floating N+ region (403); The floating N+ region (403) is inside the N-type well region (302), the upper edge thereof is tangent to the upper edge of the N-type well region (302), and the lower edge thereof is higher than the lower edge of the N-type well region (302); the left edge of the floating N+ region (403) is spaced apart from the right edge of the anode N+ region (402), and the right edge of the floating N+ region (403) is spaced apart from the left edge of the cathode N+ region (404); The cathode N+ region (404) and the cathode P+ region (405) are located inside the second P-type well region (303), the upper edge thereof is tangent to the upper edge of the second P-type well region (303), and the lower edge thereof is higher than the lower edge of the second P-type well region (303); the cathode N+ region (404) is located on the left side of the cathode P+ region (405) and the right edge thereof is tangent to the left edge of the cathode P+ region (405), both of which are located on the same horizontal line with the lower edge of the floating N+ region (403); the right edge of the cathode P+ region (405) is spaced apart from the right edge of the second P-type well region (303); the left edge of the cathode N+ region (404) is spaced apart from the right edge of the floating N+ region (403); The first P-type well region (301) and the N-type well region (302) and the second P-type well region (303) are located inside the N-type epitaxial layer (100); the left edge of the first P-type well region (301) is tangent to the left edge of the N-type epitaxial layer (100), the right edge is tangent to the left edge of the floating N+ region (403) and the N-type well region (302), and the lower edge is tangent to the upper edge of the first P-type buried layer (201); the left edge of the N-type well region (302) is tangent to the right edge of the first P-type well region (301), the lower edge is tangent to the upper edge of the N-type buried layer (202), and the right edge is tangent to the left edge of the second P-type well region (303); the left edge of the second P-type well region (303) is tangent to the right edge of the floating N+ region (403) and the N-type well region (302), the right edge is tangent to the right edge of the N-type epitaxial layer (100), and the lower edge is tangent to the upper edge of the second P-type buried layer (203); The first P-type buried layer (201) and the N-type buried layer (202) and the second P-type buried layer (203) are located inside the N-type epitaxial layer (100), and the lower edges of the three are located on the same horizontal line and are higher than the lower edge of the N-type epitaxial layer (100); the left edge of the first P-type buried layer (201) is tangent to the left edge of the N-type epitaxial layer (100), the upper edge is tangent to the lower edge of the first P-type well region (301), and the right edge is tangent to the left edge of the N-type buried layer (202); the upper edge of the N-type buried layer (202) is tangent to the lower edge of the N-type well region (302); the left edge of the second P-type buried layer (203) is tangent to the right edge of the N-type buried layer (202), the upper edge is tangent to the lower edge of the second P-type well region (303), and the right edge is tangent to the right edge of the N-type epitaxial layer (100); The lower edge of the N-type epitaxial layer (100) is tangent to the upper edge of the P-type substrate (001), and the lower edge is higher than the lower edge of the P-type substrate (001).

2. The multi-current-path bi-directional SCR device for ESD protection of claim 1, wherein The reverse breakdown voltage of the PN junction formed by the floating N+ region (403) and the second P-type well region (303) is less than the reverse breakdown voltage of the PN junction formed by the N-type buried layer (202) and the second P-type buried layer (203).

3. The multi-current-path bi-directional SCR device for ESD protection of claim 2, wherein The reverse breakdown voltage of the PN junction formed by the floating N+ region (403) and the second P-type well region (303) is V B1 , the reverse breakdown voltage of the PN junction formed by the N-type buried layer (202) and the second P-type buried layer (203) is V B2 ; V B2 / V B1 =n (n>1), the relationship between the reduced concentration N0 of the PN junction formed by the floating N+ region (403) and the second P-type well region (303) and V B2 , V B1 is shown in formula (1): (1)。 4. The multi-current-path bi-directional SCR device for ESD protection of claim 2, wherein The n is in the range of 1.1 < n < 2.

5. The multi-current-path bi-directional SCR device for ESD protection of claim 2, wherein The donor impurity concentration N of the N-type buried layer (202) nB The acceptor impurity concentration N of the second P-type buried layer (203) pB in a proportional relationship, as shown in equation (2): (2) wherein N0 is the reduced concentration of the PN junction formed by the floating N+ region (403) and the second P-type well region (303).

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