Double-gate controlled gallium nitride high electron mobility transistor and preparation method thereof

Abstract

The invention discloses a double-gate-control gallium nitride high-electron-mobility transistor and a preparation method thereof, and relates to the field of semiconductor devices, and the gallium nitride high-electron-mobility transistor comprises a substrate; the semi-insulating high-resistance layer, the n-type doped layer, the back barrier layer and the channel layer are sequentially formed on the same side of the substrate; the electrode structure is located on the side, away from the substrate, of the channel layer; the electrode structure comprises a back gate electrode, a source electrode, a front gate electrode and a drain electrode which are sequentially arranged along a first direction; the source electrode, the front gate electrode and the drain electrode are all located on the surface of the channel layer; a groove extending to the n-type doping layer is formed in the channel layer, and the back gate electrode is arranged in the groove; the first direction is parallel to the plane of the substrate; wherein the channel layer and the back barrier layer are constructed as a heterojunction. According to the technical scheme, the control capability of the grid electrode in the gallium nitride high-electron-mobility transistor on channel electrons can be improved, the stability of a device is improved, and the performance of the gallium nitride high-electron-mobility transistor is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor devices, in particular to a dual-gate controlled gallium nitride high electron mobility transistor and a preparation method thereof. BACKGROUND

[0002] With the increasing demand for high-frequency, high-power and high-efficiency radio frequency devices in mobile communication, satellite communication, radar and 5G base stations, etc., gallium nitride (GaN) high electron mobility transistors (HEMTs) have become one of the preferred technologies for radio frequency power devices due to their wide bandgap, high saturation electron velocity and high breakdown voltage, etc. The traditional gallium nitride high electron mobility transistor usually adopts an AlGaN / GaN heterostructure to form a two-dimensional electron gas (2DEG) channel, and the channel carriers are regulated by a top gate electrode, which can achieve tens of watts to hundreds of watts output power in tens of GHz frequency band.

[0003] However, with the evolution of wireless communication technology to higher frequency bands (such as Sub-6GHz to millimeter wave frequency bands) and higher power density, the device structure of the traditional gallium nitride high electron mobility transistor gradually exposes technical bottlenecks in terms of gate control ability, linearity, temperature stability, etc. For example, the short channel effect causes the increase of off-state leakage and the threshold voltage drift. One of the main reasons for these problems is the insufficient control ability of the gate on the channel electrons.

[0004] Therefore, how to enhance the control ability of the gate on the channel electrons in the gallium nitride high electron mobility transistor is a problem to be solved in the field of semiconductor technology. SUMMARY

[0005] In view of the above problems, the present application provides a dual-gate controlled gallium nitride high electron mobility transistor and a preparation method thereof to achieve the purpose of improving the control ability of the gate on the channel electrons in the gallium nitride high electron mobility transistor. The specific scheme is as follows:

[0006] The first aspect of the present application provides a dual-gate controlled gallium nitride high electron mobility transistor, which comprises:

[0007] a substrate;

[0008] a semi-insulating high resistance layer, an n-type doped layer, a back barrier layer and a channel layer formed in sequence on the same side of the substrate;

[0009] an electrode structure located on the side of the channel layer away from the substrate; the electrode structure comprises a back gate electrode, a source electrode, a front gate electrode and a drain electrode arranged in sequence along a first direction; the source electrode, the front gate electrode and the drain electrode are all located on the surface of the channel layer; the channel layer has a groove extending to the n-type doped layer, and the back gate electrode is arranged in the groove; the first direction is parallel to the plane in which the substrate lies.

[0010] The channel layer and the back barrier layer are configured as a heterojunction, and a two-dimensional electron gas exists at the interface of the heterojunction.

[0011] Optionally, in the double-gate controlled GaN high electron mobility transistor, the semi-insulating high-resistance layer, the n-type doped layer, the back barrier layer and the channel layer are all III-V nitride semiconductor materials and all have a nitrogen polarity surface.

[0012] Optionally, in the double-gate controlled GaN high electron mobility transistor, the band gap of the back barrier layer is greater than the band gap of the channel layer and the band gap of the n-type doped layer.

[0013] Optionally, in the double-gate controlled GaN high electron mobility transistor, the n-type doped layer and the channel layer are both GaN.

[0014] The back barrier layer is any one of InAlN, AlGaN, InAlGaN, AlScN and AlN.

[0015] Optionally, in the double-gate controlled GaN high electron mobility transistor, the n-type doped layer is an n-type GaN layer doped with silicon or germanium.

[0016] The doping concentration of the n-type GaN layer is 5×10 17 / cm 3 ~1×10 19 / cm 3 .

[0017] The thickness of the n-type GaN layer is 2nm~50nm.

[0018] Optionally, in the double-gate controlled GaN high electron mobility transistor, the back gate electrode is electrically connected to the n-type doped layer, and a dielectric layer exists between the back gate electrode and the channel layer and the back barrier layer to form electrical isolation.

[0019] Optionally, in the double-gate controlled GaN high electron mobility transistor, along the first direction, the distance between the front gate electrode and the drain is not less than the distance between the front gate electrode and the source.

[0020] Optionally, in the double-gate controlled GaN high electron mobility transistor, along the first direction, the distance between the back gate electrode and the source is less than the distance between the front gate electrode and the source.

[0021] The back gate electrode and the source are at the same potential.

[0022] Optionally, in the double-gate controlled GaN high electron mobility transistor, further comprising:

[0023] An isolation layer is located between the semi-insulating high resistance layer and the substrate.

[0024] The second aspect of the present application provides a preparation method of the double-gate controlled gallium nitride high electron mobility transistor.

[0025] A substrate is provided.

[0026] A semi-insulating high resistance layer, an n-type doped layer, a back barrier layer and a channel layer are sequentially formed on the surface of the substrate.

[0027] An electrode structure is formed on the side of the channel layer away from the substrate; the electrode structure includes a back gate electrode, a source electrode, a front gate electrode and a drain electrode arranged in the first direction; the source electrode, the front gate electrode and the drain electrode are all located on the surface of the channel layer; the channel layer has a groove extending to the n-type doped layer, and the back gate electrode is arranged in the groove; the first direction is parallel to the plane in which the substrate is located.

[0028] The channel layer and the back barrier layer are configured as a heterojunction.

[0029] In the double-gate controlled gallium nitride high electron mobility transistor and the preparation method thereof provided by the present application, the channel layer and the back barrier layer are configured as a heterojunction, and the interface between the channel layer and the back barrier layer can form a two-dimensional electron gas (2DEG) as a conductive channel connecting the source electrode and the drain electrode. In addition, the back gate electrode is arranged on the side of the source electrode away from the front gate electrode, the back gate electrode is electrically connected to the n-type doped layer through the groove extending to the n-type semiconductor layer, and the control bias voltage is applied to the back gate electrode to enhance the control ability of the threshold voltage, thereby compensating for the threshold voltage drift caused by the thermal effect or the short channel effect. Further, through the cooperative work of the back gate electrode and the front gate electrode, the control ability of the channel electrons can be enhanced, thereby improving the stability and output performance of the device. BRIEF DESCRIPTION OF DRAWINGS

[0030] In order to more clearly illustrate the technical solutions in the embodiments or the related art, the following will briefly introduce the drawings needed to be used in the embodiments or the prior art description. Obviously, the drawings in the following description are only embodiments of the present application, and for those skilled in the art, other drawings can be obtained without creative labor on the basis of the provided drawings.

[0031] The structures, proportions, sizes, etc. shown in the drawings of the present specification are only used to cooperate with the content disclosed in the specification, to enable those skilled in the art to understand and read, and are not used to limit the conditions that can be implemented by the present application, so they do not have technical significance. Any modification of structure, change of proportion relationship or adjustment of size, without affecting the effect and purpose that can be achieved by the present application, should still fall within the scope of the technical content disclosed by the present application.

[0032] Figure 1 A device structure schematic diagram of an AlN thin barrier HEMT;

[0033] Figure 2 A device structure schematic diagram of an HEMT with a recessed gate structure;

[0034] Figure 3 A device structure schematic diagram of a double-gate-controlled gallium nitride high electron mobility transistor provided by an embodiment of the present application;

[0035] Figure 4 A device structure schematic diagram of another double-gate-controlled gallium nitride high electron mobility transistor provided by an embodiment of the present application;

[0036] Figure 5 A device structure schematic diagram of still another double-gate-controlled gallium nitride high electron mobility transistor provided by an embodiment of the present application;

[0037] Figure 6 A transmission curve simulation result schematic diagram of a double-gate-controlled gallium nitride high electron mobility transistor provided by an embodiment of the present application;

[0038] Figure 7 A transconductance simulation result schematic diagram of a double-gate-controlled gallium nitride high electron mobility transistor provided by an embodiment of the present application;

[0039] Figure 8 A flowchart of a preparation method of a double-gate-controlled gallium nitride high electron mobility transistor provided by an embodiment of the present application.

[0040] Reference signs:

[0041] 11-sapphire substrate; 12-gallium nitride layer; 13-barrier layer; 14-source electrode; 15-drain electrode; 16-gate electrode; 17-gallium aluminum nitride layer; 18-substrate; 19-semi-insulating high resistance layer; 20-n-type doped layer; 21-back barrier layer; 22-channel layer; 23-front gate electrode; 24-back gate electrode; 25-dielectric layer; 26-isolation layer; X-first direction. DETAILED DESCRIPTION

[0042] The embodiments in the present application will be described clearly and completely below with reference to the drawings in the embodiments of the present application. Those skilled in the art can know that the technical solutions provided by the embodiments of the present application are also applicable to similar technical problems as technology develops and new scenarios appear.

[0043] In order to enhance the control ability of the gate electrode on the channel electrons, one technical solution is to shorten the distance between the gate electrode and the channel, i.e., to reduce the thickness of the barrier layer, and the implementation principle is as follows: Figure 1shown.

[0044] Reference is made to Figure 1 , Figure 1 Fig. 1 is a schematic diagram of a device structure of an AlN thin barrier HEMT, Figure 1 The HEMT shown in Fig. 1 comprises:

[0045] a sapphire substrate 11;

[0046] a gallium nitride layer 12 located on one side surface of the sapphire substrate 11;

[0047] a source electrode 14 and a drain electrode 15, which are located on one side surface of the gallium nitride layer 12 away from the sapphire substrate 11;

[0048] A barrier layer 13 is coated on the surface of the gallium nitride layer 12 between the source electrode 14 and the drain electrode 15; one side of the gallium nitride layer 12 close to the barrier layer 13 forms a 2DEG (as shown by the horizontal dashed line in Figure 1 Fig. 1).

[0049] A gate electrode 16 is provided on one side surface of the barrier layer 13 away from the gallium nitride layer 12.

[0050] In this case, the material of the barrier layer 13 can be AlN or AlScN with a strong polarization intensity, so that the channel electron concentration will not be reduced while the thickness of the barrier layer 13 is reduced. Figure 1 If AlN with a thickness of 3.5 nm is used as the barrier layer 13 in the manner shown in Fig. 1, the channel sheet resistance can be reduced to below 140 Ω / □, and if AlScN is used as the barrier layer 13, the output current density can be increased to a high level of 4 A / mm.

[0051] Figure 1 Although the manner shown in Fig. 1 can enhance the control ability of the gate electrode on the channel electrons to some extent, both AlN and AlScN have a large lattice mismatch with the GaN material, and this manner faces challenges in material growth, such as large material stress and high defect density. In addition, the channel electron concentration is also more susceptible to the influence of the defect states on the surface of the thin barrier layer, which may cause reliability problems such as current collapse.

[0052] Another scheme for enhancing the control ability of the gate electrode on the channel electrons is to etch part of the barrier layer under the gate electrode to form a recessed gate structure, so as to shorten the distance between the gate electrode and the channel. The device structure is shown in Fig. 2. Figure 2

[0053] Reference is made to Figure 2 , Figure 2 Fig. 2 is a schematic diagram of a device structure of an HEMT with a recessed gate structure, Figure 2 The HEMT shown in Fig. 2 comprises:

[0054] a sapphire substrate 11;​

[0055] A gallium nitride layer 12 located on one surface of the sapphire substrate 11;

[0056] A gallium aluminum nitride layer 17 located on the side of the gallium nitride layer 12 facing away from the sapphire substrate 11;

[0057] A source electrode 14 and a drain electrode 15 , the source electrode 14 and the drain electrode 15 are located on a surface of the aluminum gallium nitride layer 17 facing away from the sapphire substrate 11 ;

[0058] The surface of the aluminum gallium nitride layer 17 between the source 14 and the drain 15 is covered with a barrier layer 13;

[0059] A gate 16 is provided on a surface of the barrier layer 13 facing away from the AlGaN layer 17 . The gate 16 extends into the AlGaN layer 17 based on a trench penetrating the barrier layer 13 .

[0060] exist Figure 2 In the illustrated embodiment, the barrier layer 13 can be made of SiN. This embodiment not only shortens the distance between the gate 16 and the channel due to the trench penetrating the barrier layer 13, but also allows a relatively thick barrier layer 13 to be retained between the gate and source, and between the gate and drain, thereby reducing the channel square resistance.

[0061] Figure 2 Although the method shown can improve the gate's ability to control channel electrons to a certain extent, due to the lack of an etch stop layer, the process uniformity and consistency are difficult to control; on the other hand, the etching of the gate groove structure is damaged, which easily causes reliability problems such as threshold voltage drift.

[0062] In view of this, an embodiment of the present application provides a dual-gate controlled gallium nitride high electron mobility transistor, comprising:

[0063] substrate;

[0064] A semi-insulating high-resistance layer, an n-type doped layer, a back barrier layer, and a channel layer are sequentially formed on the same side of the substrate;

[0065] An electrode structure, the electrode structure is located on a side of the channel layer facing away from the substrate; the electrode structure includes: a back gate electrode, a source electrode, a front gate electrode, and a drain electrode arranged in sequence along a first direction; the source electrode, the front gate electrode, and the drain electrode are all located on the surface of the channel layer; a trench extending to the n-type doped layer is provided in the channel layer, and the back gate electrode is disposed in the trench; the first direction is parallel to the plane of the substrate;

[0066] The channel layer and the back barrier layer are constructed as a heterojunction.

[0067] In the embodiment of the present application, the channel layer and the back barrier layer are configured as a heterojunction, and the interface between the channel layer and the back barrier layer can form a two-dimensional electron gas (2DEG) to form a 2DEG channel. In addition, the back gate electrode is arranged on the side of the source away from the front gate electrode, and the back gate electrode can be electrically connected with the n-type semiconductor layer based on the trench extending to the n-type semiconductor layer, so as to improve the output current density and transconductance of the gallium nitride high electron mobility transistor, better adjust the gate voltage of the gallium nitride high electron mobility transistor, enhance the control ability of the threshold voltage, thereby compensating the threshold voltage drift problem caused by thermal effect or short channel effect, improving the control ability of the gate on the channel electrons in the gallium nitride high electron mobility transistor, improving the stability of the device, and improving the performance of the gallium nitride high electron mobility transistor.

[0068] In the embodiment of the present application, the back barrier layer, the channel layer and the n-type doped layer are all N-polar surface ternary nitride semiconductor materials. Since the back barrier layer has a larger band gap than the channel layer, it can provide better confinement for channel electrons, enhance the high voltage resistance of the device and reduce the leakage current in the off state. The channel electron concentration is determined by the thickness and Al component of the back barrier layer, unlike the traditional Ga-polar surface gallium nitride high electron mobility transistor (HEMT) (see Figure 1 and Figure 2 ), the channel electron concentration is affected by the thickness of the surface barrier layer, so in the embodiment of the present application, the distance between the gate and the channel electron can be shortened, thereby enhancing the control ability of the gate on the channel electron.

[0069] In addition, in the present application, the back gate electrode is electrically connected with the n-type doped layer based on the trench or is capacitively coupled based on the field effect, so that the n-type doped layer is equivalent to a bottom gate located below the channel layer, and the front gate electrode acts as a top gate above the channel layer, thereby simultaneously controlling the channel electron through the bottom gate and the top gate located on both sides of the channel layer, and improving the control ability of the channel electron.

[0070] Furthermore, when the back gate electrode is electrically connected with the n-type doped layer based on the trench, the n-type doped layer actually acts as the bottom gate, that is, among the back gate electrode and the n-type doped layer, the back gate electrode is an access end of a back gate voltage, and the n-type doped layer forms an electric field for controlling the channel electron, so the important parameter of the connection performance of the back gate electrode and the n-type doped layer is the reliability of the electrical connection. The etching depth and the etching morphology of the trench have little effect on the electrical connection performance between the back gate electrode and the n-type doped layer. When the back gate electrode is capacitively coupled with the n-type doped layer based on the field effect, the n-type doped layer controls the channel electron as a bottom gate, and the back gate electrode controls the carrier concentration of the n-type doped layer based on the field effect. At this time, the etching depth and the etching morphology of the trench are less required. Therefore, the technical problem of the scheme shown in the present application does not exist. Figure 2 ​

[0071] In order to make the above objectives, characteristics and advantages of the present application more apparent, further specific embodiments of the present application will be described in detail with reference to the accompanying drawings.

[0072] Reference Figure 3 , Figure 3 A device structure diagram of a double-gate controlled gallium nitride high electron mobility transistor provided by an embodiment of the present application is shown in the figure, Figure 3 The gallium nitride high electron mobility transistor shown in the figure comprises:

[0073] a substrate 18;

[0074] a semi-insulating high-resistance layer 19, an n-type doped layer 20, a back barrier layer 21 and a channel layer 22 are sequentially formed on the same side of the substrate 18;

[0075] an electrode structure, the electrode structure is located on the side of the channel layer 22 away from the substrate 18; the electrode structure comprises: a back gate electrode 24, a source electrode 14, a front gate electrode 23 and a drain electrode 15 arranged in a first direction X in sequence; the source electrode 14, the front gate electrode 23 and the drain electrode 15 are all located on the surface of the channel layer 22; the channel layer 22 has a groove extending to the n-type doped layer 20 in the channel layer 22, and the back gate electrode 24 is arranged in the groove; the first direction X is parallel to the plane in which the substrate 18 is located;

[0076] Among them, the channel layer 22 and the back barrier layer 21 are configured as a heterojunction, can form a 2DEG, to form a 2DEG channel, so as to improve the output power of the device.

[0077] In the embodiment of the present application, the back gate electrode 24 is arranged on the side of the source electrode 14 away from the front gate electrode 23, and the back gate electrode 24 can be electrically connected with the n-type semiconductor layer 20 based on the groove extending to the n-type semiconductor layer 20, so as to improve the output current density and transconductance of the gallium nitride high electron mobility transistor, better adjust the gate voltage of the gallium nitride high electron mobility transistor, enhance the control ability of the threshold voltage, thereby compensating the threshold voltage drift problem caused by thermal effect or short channel effect, improving the control ability of the gate on the channel electrons in the gallium nitride high electron mobility transistor, improving the stability of the device, and improving the performance of the gallium nitride high electron mobility transistor.

[0078] Optionally, the substrate 18 can adopt a high-resistivity material, such as any one of high-resistivity silicon, sapphire, silicon carbide and ceramic materials. The resistivity of the substrate 18 is greater than 1 kΩ·cm.

[0079] Optionally, the material of the semi-insulating high-resistance layer 19 can be a III-V nitride semiconductor material with high resistivity. For example, GaN or AlGaN with high concentration of iron or carbon doping. The iron or carbon doping in the semi-insulating high-resistance layer 19 can form internal defects in the semi-insulating high-resistance layer 19 to trap electrons, which can improve the voltage withstanding performance of the device.

[0080] In some embodiments, the n-type doped layer 20 is heavily n-type doped to form a reliable electrical connection with the back gate electrode 24. The n-type doped layer 20 can be a high-concentration silicon-doped or germanium-doped n-type GaN layer. Optionally, the doping concentration of the n-type GaN layer can be 5x1018 / cm3~1x1020 / cm3. The thickness of the n-type GaN layer can be 2nm~50nm. In the embodiments of the present application, the doping concentration and thickness of the n-type GaN layer are optimized within the provided ranges, which can optimize the control efficiency of the back gate field of the back gate electrode 24 on the channel electrons, thereby further improving the performance of the device. 17 / cm 3 / cm 19 / cm 3 The thickness of the n-type GaN layer can be 2nm~50nm. In the embodiments of the present application, the doping concentration and thickness of the n-type GaN layer are optimized within the provided ranges, which can optimize the control efficiency of the back gate field of the back gate electrode 24 on the channel electrons, thereby further improving the performance of the device.

[0081] Referring to Figure 4 , Figure 4 Fig. 4 shows another device structure of a double-gate controlled GaN high electron mobility transistor provided by the embodiments of the present application, which is based on the manner shown in Fig. 3. Figure 3 Figure 4 In the manner shown in Fig. 4, the GaN high electron mobility transistor further comprises an isolation layer 26 located between the semi-insulating high-resistance layer 19 and the substrate 18.

[0082] Optionally, the material of the isolation layer 26 can be any one of SiO2, SiN, AlN, Al2O3, and HfO2.

[0083] On the one hand, the isolation layer 26 can serve as an intermediate material connecting the semi-insulating high-resistance layer 19 and the substrate 18 (the connection can be achieved by bonding), and on the other hand, the isolation layer 26 can isolate the device layer above it from the substrate 18, reducing the influence of the noise of the substrate 18 on the device. For example, when the device is working in a radio frequency state, the isolation layer 26 can prevent the radio frequency signal of the device from being absorbed by the substrate 18.

[0084] In one embodiment of the embodiments of the present application, the semi-insulating high-resistance layer 19, the n-type doped layer 20, the back barrier layer 21, and the channel layer 22 are all III-V nitride semiconductor materials, all of which have a nitrogen polarity surface. Based on this, the barrier layer can be arranged below the channel layer 22 to form the back barrier layer 21, to enhance the control ability of the bottom gate on the channel layer. The nitrogen polarity surface refers to the surface of the gallium nitride crystal with a <000-1> direction. Figure 3 and Figure 4 ​The middle arrow is used to indicate the crystal orientation of the nitrogen polarity surface. Since the back barrier layer 21 has a larger band gap than the channel layer 22, it can provide better confinement for the channel electrons, enhance the high voltage resistance of the device, and reduce the leakage current in the off state. The channel electron concentration is determined by the thickness and Al composition of the back barrier layer 21, unlike the conventional Ga polarity surface gallium nitride high electron mobility transistor (GaN-HEMT) in which the channel electron concentration is affected by the surface barrier layer thickness, so in the embodiments of the present application, the distance between the gate and the channel electrons can be shortened, thereby enhancing the control ability of the gate on the channel electrons. Figure 1 and Figure 2 The channel electron concentration is determined by the thickness and Al composition of the back barrier layer 21, unlike the conventional Ga polarity surface gallium nitride high electron mobility transistor (GaN-HEMT) in which the channel electron concentration is affected by the surface barrier layer thickness, so in the embodiments of the present application, the distance between the gate and the channel electrons can be shortened, thereby enhancing the control ability of the gate on the channel electrons.

[0085] Based on the above description, in the embodiments of the present application, the gallium nitride high electron mobility transistor made of nitrogen polarity surface material, since the back barrier layer 21 is located below the channel layer 22, compared with the conventional gallium polarity surface device, the back barrier layer 21 can form a better confinement effect on the channel electrons, which can improve the output power of the device, so that the gallium nitride high electron mobility transistor has a higher output power density.

[0086] In one embodiment of the present application, the band gap of the back barrier layer 21 is greater than the band gap of the channel layer 22 and the band gap of the n-type doped layer 20.

[0087] Since the band gap of the back barrier layer 21 is greater than the band gap of the channel layer 22, a heterojunction can be formed by the adjacent back barrier layer 21 and channel layer 22, thereby forming a 2DEG channel to improve the output power of the device.

[0088] In addition, since the band gap of the back barrier layer 21 is greater than the band gap of the n-type doped layer 20, the n-type doped layer 20 with a smaller band gap can reduce the contact resistance with the back gate electrode 24, thereby enhancing the control ability of the back gate electrode 24.

[0089] Furthermore, the n-type doped layer 20 with a smaller band gap can also reduce the capture of electrons by interface deep level defects, maintain the stability of 2DEG density in high frequency switching or high voltage working conditions, avoid the increase of dynamic resistance, and can suppress the current collapse problem.

[0090] In one way, the back barrier layer 21 can be a III-nitride semiconductor material with a larger band gap than the channel layer 22 and the n-type doped layer 20, for example, when the n-type doped layer 20 and the channel layer 22 are both GaN, the back barrier layer 21 can be any one of InAlN, AlGaN, InAlGaN, AlScN and AlN. This way not only makes the n-type doped layer 20 and the channel layer 22 both have a nitrogen polarity surface, but also makes the band gap of the back barrier layer 21 greater than the band gap of the channel layer 22, so as to construct a heterojunction with a 2DEG channel.

[0091] The channel layer 22 can be a III-V nitride semiconductor material, and the barrier width of the channel layer 22 is smaller than that of the back barrier layer 21. The channel layer 22 is not limited to GaN material, and can also be InGaN or InN, etc.

[0092] The back gate electrode 24 is electrically connected to the n-doped layer 20, and a dielectric layer 25 is provided between the back gate electrode 24 and the channel layer 22 and the back barrier layer 21 to form electrical isolation. As shown in Figure 3 and Figure 4 The front gate electrode 23 is arranged between the source 14 and the drain 15, and the back gate electrode 24 is arranged close to the source 14 and is electrically connected to the n-doped layer 20 through a trench passing through the channel layer 22 and the back barrier layer 21. The back gate electrode 24 is electrically isolated from the channel layer 22 and the back barrier layer 21 by the dielectric layer 25. The front gate electrode 23 also has a dielectric layer 25 between it and the channel layer 22.

[0093] Optionally, the dielectric layer 25 covers the sidewall of the trench, and exposes the n-doped layer 20 at the bottom of the trench. In this way, the dielectric layer 25 based on the sidewall of the trench can achieve electrical isolation between the back gate electrode 24 and the channel layer 22 and the back barrier layer 21, and the dielectric layer 25 based on the n-doped layer 20 exposed at the bottom of the trench can achieve electrical connection between the back gate electrode 24 and the n-doped layer 20.

[0094] In an embodiment, the dielectric layer 25 can form an opening at the bottom of the trench to expose the n-doped layer 20, so that the back gate electrode 24 directly contacts the n-doped layer 20 at the bottom of the trench, forming an effective and reliable electrical connection.

[0095] In another way, if the thickness of the dielectric layer 25 is relatively thin, the dielectric layer 25 can be retained at the bottom of the trench, i.e., the back gate electrode 24 and the n-doped layer 20 have a dielectric layer 25 therebetween, and the back gate electrode 24 can control the carrier concentration of the n-doped layer 20 based on the field effect, to improve the control ability of the back gate electrode 24 over the channel electrons.

[0096] In an embodiment, as shown in Figure 3 and Figure 4 In the first direction X, the spacing L3 between the front gate electrode 23 and the drain 15 is not less than the spacing L2 between the front gate electrode 23 and the source 14, i.e., L3≥L2, and preferably L3>L2.

[0097] In the working of the GaN high electron mobility transistor, the source 14 is grounded, and the drain 15 is connected to a high voltage. Due to L3>L2, the front gate electrode 23 located between the source 14 and the drain 15 is closer to the source 14, which can reduce the interference of the high voltage connected to the drain 15 on the front gate electrode 23, and can also increase the withstand voltage performance between the source and the drain.

[0098] In other implementations, if the layout space of the device is sufficient and L3 meets the withstand voltage requirement, L2 can be made equal to L3.

[0099] In one embodiment, Figure 3 and Figure 4 As shown, along the first direction X, the distance L1 between the back-gate electrode 24 and the source 14 is less than the distance L2 between the front-gate electrode 23 and the source 14. On the one hand, because L1 is less than L2, the back-gate electrode 24 can significantly improve its ability to control channel electrons. On the other hand, the back-gate electrode 24 is located close to the source 14 of the GaN-HEMT. Positioning the back-gate electrode 24 away from the drain 15 prevents interference with the back-gate electrode 24 caused by the high voltage connected to the drain 15, thereby ensuring that the back-gate electrode 24 effectively improves its ability to control channel electrons.

[0100] In other implementations, L1=L2 may also be set according to the actual layout space size of the device.

[0101] refer to Figure 5 , Figure 5 This is a schematic diagram of the device structure of another dual-gate controlled gallium nitride high electron mobility transistor provided in an embodiment of the present application. Based on the other embodiments described above, Figure 5 In the illustrated embodiment, the back gate electrode 24 and the source electrode 14 are at the same potential. In this embodiment, the distance between the back gate electrode 24 and the source electrode 14 is zero, so that the back gate electrode 24 and the source electrode 14 form a circuit interconnection, thereby achieving the same potential between the two. In this case, the distance between the front gate electrode 23 and the source electrode 14 is greater than zero.

[0102] In other embodiments, the distance between the back gate electrode 24 and the source electrode 14 may be set to be greater than 0, and the electrical connection between the two may be achieved through a metal interconnection layer to achieve equipotential between the two.

[0103] When the back-gate electrode 24 and the source 14 are at the same potential, it is equivalent to connecting the source 14 to the n-type doped layer 20. At this point, the potential of the back-gate electrode 24 is equal to that of the source 14, and the potential of the n-type doped layer 20 is fixed to the potential of the source 14. When the potential of the source 14 is zero, the n-type doped layer 20 is effectively grounded. This improves the stability of the threshold voltage, particularly during dynamic operation, and reduces the current collapse effect (a phenomenon in which the two-dimensional electron gas concentration decreases and the output current decreases due to trapping during dynamic operation).

[0104] Based on the above description, it can be seen that the GaN high electron mobility transistor provided in the embodiments of the present application has at least the following beneficial effects:

[0105] First, compared with the scheme of arranging a barrier layer between the gate and the channel layer 22, the technical scheme of the present application adds a back barrier layer 21 between the n-type doped layer 20 and the channel layer 22. The back barrier layer 21 does not increase the distance between the front gate electrode 23 and the channel, so that the front gate electrode 23 has a smaller distance from the channel layer 22, and the control ability of the front gate electrode 23 on the channel electrons can be effectively improved.

[0106] Second, the back barrier layer 21 and the channel layer 22 are both III-nitride semiconductor materials, and a heterojunction is formed between them. Not only can a 2DEG channel be formed based on the heterojunction to improve the output power of the device, but also the back barrier layer 21 can form a better limiting effect on the channel electrons compared with the traditional gallium polar surface device, so that the output power of the device can be improved, and the gallium nitride high electron mobility transistor has a higher output power density.

[0107] Third, the back gate electrode 24 is arranged on the side of the front gate electrode 23 away from the source 14, so that a double-gate-controlled gallium nitride high electron mobility transistor device structure can be formed. The control ability on the channel electrons can be improved through the back gate electrode 24. In addition, since the back gate electrode 24 is located on the side close to the source 14, the back gate electrode 24 is away from the drain 15, so that the interference of the high voltage input to the drain 15 on the back gate electrode 24 is reduced, thereby reducing the leakage current between the drain 15 and the back gate electrode 24, and the effect of improving the control ability of the back gate electrode 24 on the channel electrons can be ensured.

[0108] The beneficial effects of the double-gate-controlled gallium nitride high electron mobility transistor provided by the embodiments of the present application will be further described below in combination with specific simulation data.

[0109] Reference Figure 6 , Figure 6 is a simulation result diagram of the transfer curve of the double-gate-controlled gallium nitride high electron mobility transistor provided by the embodiments of the present application. Figure 6 In the diagram, the horizontal axis is the voltage of the front gate electrode of the gallium nitride high electron mobility transistor, and the vertical axis is the drain output current. The left vertical axis is a linear coordinate, and the right vertical axis is a logarithmic coordinate. Figure 6 The diagram shows the transfer curve of the back gate electrode under different voltages (-2V to 3V) when the source is grounded and the drain voltage Vd=5V.

[0110] Based on Figure 6 It can be seen that when the voltage of the back gate electrode is positive, increasing the voltage of the back gate electrode can improve the output current density of the gallium nitride high electron mobility transistor. For example, when the voltage of the back gate electrode increases from 0V to 3V, the output current density increases by 24%.

[0111] Reference Figure 7 , Figure 7A schematic diagram of a simulation result of transconductance of the double-gate controlled GaN-HEMT provided in the embodiments of the present application is shown. Figure 7 In the figure, the horizontal axis is the voltage of the front gate electrode of the GaN-HEMT, and the vertical axis is the transconductance. The transconductance is the differential value of the drain current and the voltage of the front gate electrode, ΔId / ΔVg. Figure 7 The transconductance curves of the back gate electrode at different voltages (-2V to 3V) are shown when the source is grounded and the drain voltage Vd=5V.

[0112] Based on the above description, Figure 7 It can be seen that when the voltage of the back gate electrode is positive, increasing the voltage of the back gate electrode can increase the transconductance of the GaN-HEMT. For example, when the voltage of the back gate electrode increases from 0V to 3V, the transconductance increases by 19%. Since the transconductance of the GaN-HEMT increases with the increase of the voltage of the back gate electrode, it is shown that a larger change in output current (ΔId) can be achieved under the same change in voltage of the front gate electrode (ΔVg) by adjusting the voltage of the back gate electrode.

[0113] As can be seen from the above description, the GaN-HEMT provided in the embodiments of the present application not only can improve the output current density and the output transconductance, but also has better device stability. The GaN-HEMT can adjust the threshold voltage through the back gate electrode, thereby compensating for the threshold voltage drift caused by thermal effects or short channel effects.

[0114] The GaN-HEMT provided in the embodiments of the present application is suitable for high-frequency and high-power radio frequency (RF) application scenarios, such as 5G communication base stations, radar systems, and power amplifiers.

[0115] On the basis of the double-gate controlled GaN-HEMT provided in the above embodiments, another embodiment of the present application further provides a preparation method of a double-gate controlled GaN-HEMT, which is as shown in Figure 8 .

[0116] Reference is made to Figure 8 , Figure 8 A flowchart of a preparation method of a double-gate controlled GaN-HEMT provided in the embodiments of the present application is shown. The preparation method comprises the following steps:

[0117] Step S11: providing a substrate 18;

[0118] Step S12: sequentially forming a semi-insulating high-resistance layer 19, an n-type doped layer 20, a back barrier layer 21, and a channel layer 22 on the surface of the substrate 18.

[0119] An electrode structure is formed on a side of the channel layer 22 away from the substrate 18; the electrode structure comprises, in sequence along a first direction X, a back gate electrode 24, the source electrode 14, a front gate electrode 23, and the drain electrode 15; the source electrode 14, the front gate electrode 23, and the drain electrode 15 are all located on a surface of the channel layer 22; the channel layer 22 has a groove extending to the n-type doped layer 20 therein, and the back gate electrode 24 is arranged in the groove; the first direction X is parallel to a plane in which the substrate 18 is located.

[0120] The channel layer 22 and the back barrier layer 21 are configured as a heterojunction.

[0121] Optionally, the n-type doped layer 20 can be an n-type GaN layer doped with high-concentration silicon or germanium. Optionally, the doping concentration of the n-type GaN layer can be 5*1018 / cm3~1*1020 / cm3. 17 / cm 3 ~1*1020 / cm3. 19 / cm 3 The thickness of the n-type GaN layer can be 2nm~50nm.

[0122] Optionally, the semi-insulating high-resistance layer 19, the n-type doped layer 20, the back barrier layer 21, and the channel layer 22 are all III-nitride semiconductor materials and all have a nitrogen polarity surface.

[0123] The preparation method provided by the embodiments of the present application can be used to prepare the double-gate controlled GaN high electron mobility transistor described above, and the preparation method is simple in process, and the double-gate controlled GaN high electron mobility transistor prepared thereby has stronger control ability of the gate on the channel electrons.

[0124] In the description of the present application, each embodiment is described in a progressive, parallel, or progressive and parallel manner, and each embodiment focuses on the difference from other embodiments, and the same or similar parts of each embodiment can be referred to. The embodiments provided by the embodiments of the present application can be combined with each other without contradiction.

[0125] It should be noted that in the description of the present application, it should be understood that the drawings and the description of the embodiments are illustrative rather than limiting. The same reference numerals in the embodiments throughout the description indicate the same structure. In addition, for the purpose of understanding and ease of description, the thickness of some layers, films, panels, regions, etc. may be exaggerated in the drawings. It can be understood that when an element such as a layer, film, region, or substrate is referred to as "on" another element, the element can be directly on the other element or there can be an intermediate element. In addition, "on" means positioning an element on another element or below another element, but not essentially positioning on the upper side of another element according to the direction of gravity.

[0126] The terms "upper", "lower", "top", "bottom", "inner", "outer" and the like, indicate an orientation or positional relationship based on the orientation or positional relationship as shown in the drawings, and are used only to facilitate description of the application and are not a declaration of or limitation on the position or orientation of the device or element in use or operation, and thus can not be construed as limiting the application. When one component is considered to be "connected" to another component, it can be directly connected to the other component or a component disposed therebetween can be present.

[0127] It is also to be noted that, as used in the specification and the appended claims, the singular forms "a", "an" and "the" include plural referents unless the context clearly dictates otherwise. Furthermore, the terms "comprising", "containing", or any other similar term are intended to encompass non-exclusive inclusions, such that a device or article that comprises a list of elements is not necessarily limited to those elements, but can include other elements not expressly listed, or even other elements that are inherent to such device or article. The term "comprising" is not intended to exclude other elements that are not specifically listed.

[0128] The above description of disclosed embodiments provides enabling disclosure sufficient for one of ordinary skill in the art to practice or use the application. Various modifications to these embodiments will be readily apparent to those skilled in the art, and generic principles defined herein can be applied to other embodiments without departing from the spirit or scope of the application. Thus, the present application is not to be limited to the embodiments shown herein but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A dual-gate controlled gallium nitride high electron mobility transistor, characterized in that: include: substrate; forming a semi-insulating high-resistance layer, an n-type doped layer, a back barrier layer, and a channel layer in sequence on the same side of the substrate; an electrode structure, the electrode structure being located on a side of the channel layer facing away from the substrate; the electrode structure comprising: a back gate electrode, a source electrode, a front gate electrode, and a drain electrode arranged in sequence along a first direction; the source electrode, the front gate electrode, and the drain electrode being all located on a surface of the channel layer; a trench extending to the n-type doped layer being provided in the channel layer, the back gate electrode being disposed in the trench; the first direction being parallel to the plane of the substrate; The channel layer and the back barrier layer are constructed as a heterojunction.

2. The dual-gate controlled gallium nitride high electron mobility transistor according to claim 1, characterized in that: The semi-insulating high-resistance layer, the n-type doped layer, the back barrier layer, and the channel layer are all made of Group III nitride semiconductor materials and have nitrogen polarity surfaces.

3. The dual-gate controlled gallium nitride high electron mobility transistor according to claim 1 or 2, characterized in that: The band gap width of the back barrier layer is greater than the band gap width of the channel layer and the band gap width of the n-type doping layer.

4. The dual-gate controlled gallium nitride high electron mobility transistor according to claim 3, characterized in that: The n-type doping layer and the channel layer are both GaN; The back barrier layer is any one of InAlN, AlGaN, InAlGaN, AlScN and AlN.

5. The dual-gate controlled gallium nitride high electron mobility transistor according to claim 3, characterized in that: The n-type doped layer is a silicon-doped or germanium-doped n-type GaN layer; The doping concentration of the n-type GaN layer is 5×10 17 / cm 3 ~1×10 19 / cm 3 ; The thickness of the n-type GaN layer is 2nm-50nm.

6. The dual-gate controlled gallium nitride high electron mobility transistor according to claim 1, characterized in that: The back gate electrode is electrically connected to the n-type doping layer, and a dielectric layer is present between the back gate electrode and both the channel layer and the back barrier layer to form electrical isolation.

7. The dual-gate controlled gallium nitride high electron mobility transistor according to claim 1, characterized in that: Along the first direction, a distance between the front gate electrode and the drain electrode is not less than a distance between the front gate electrode and the source electrode.

8. The dual-gate controlled gallium nitride high electron mobility transistor according to claim 1, characterized in that: Along the first direction, the distance between the back gate electrode and the source electrode is smaller than the distance between the front gate electrode and the source electrode; Wherein, the back gate electrode and the source electrode are at the same potential.

9. The dual-gate controlled gallium nitride high electron mobility transistor according to claim 1, characterized in that: Also includes: An isolation layer is located between the semi-insulating high-resistance layer and the substrate.

10. A method for preparing a dual-gate controlled gallium nitride high electron mobility transistor according to any one of claims 1 to 9, characterized in that: include: providing a substrate; forming a semi-insulating high-resistance layer, an n-type doping layer, a back barrier layer and a channel layer in sequence on the surface of the substrate; An electrode structure is formed on a side of the channel layer facing away from the substrate; the electrode structure includes: a back gate electrode, a source electrode, a front gate electrode, and a drain electrode arranged in sequence along a first direction; the source electrode, the front gate electrode, and the drain electrode are all located on a surface of the channel layer; a trench extending to the n-type doped layer is provided in the channel layer, and the back gate electrode is disposed in the trench; the first direction is parallel to the plane of the substrate; The channel layer and the back barrier layer are constructed as a heterojunction.

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