Solar cell and manufacturing method thereof

Abstract

The invention provides a solar cell and a manufacturing method thereof. The manufacturing method comprises the steps that a semiconductor substrate is provided, the semiconductor substrate comprises a first surface and a second surface, and the second surface comprises a first area, a second area and a third area between the first area and the second area; forming an isolation layer on the second region; removing the semiconductor substrate with the first thickness corresponding to the first region and the third region; removing the isolating layer; forming a whole first carrier collection layer and an insulating layer on the second surface; removing the insulating layer corresponding to the second region, the first carrier collection layer and the semiconductor substrate with a second thickness; forming a whole second carrier collection layer on the second surface; portions of the second carrier collection layer and the insulating layer on the first region are selectively removed. The height difference between the surface of the first region and the surface of the second region of the solar cell obtained by the manufacturing method can be within 2 microns, and the use amount of electrode slurry can be reduced.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of semiconductor technology, and in particular, to a solar cell and a manufacturing method thereof. BACKGROUND

[0002] A solar cell, as an advanced semiconductor device for photoelectric conversion, its core function is to convert solar energy into electrical energy. The back contact solar cell (Interdigitated Back Contact, IBC for short) is a kind of high-efficiency cell technology at present, and its front surface has no grid line shielding, and has higher incident light utilization. As a platform technology, the back contact solar cell can be combined with a heterojunction solar cell or a tunnel oxide passivated contact cell to form a heterojunction back contact solar cell (HBC) or a tunnel oxide passivated contact back contact cell (TBC) with higher theoretical efficiency limit.

[0003] The common back contact solar cell at present mainly includes: a semiconductor substrate, the semiconductor substrate includes a first surface and a second surface opposite to the first surface, wherein the second surface includes alternately arranged first regions and second regions, and a third region between adjacent first regions and second regions. A first carrier collection layer is arranged on the first region, and a second carrier collection layer is arranged on the second region. The conductive type between the first carrier collection layer and the second carrier collection layer is opposite, and the conductive type of one of the two is the same as the conductive type of the semiconductor substrate. Electrodes are further arranged on the first carrier collection layer and the second carrier collection layer.

[0004] The first region and the second region of the existing back contact solar cell have a large height difference, and the amount of paste used for forming the electrode is large. SUMMARY

[0005] One of the technical problems solved by the present disclosure is that the amount of paste used for forming the electrode of the solar cell in the related art is large.

[0006] According to one aspect of the present disclosure, a method for manufacturing a solar cell is provided, including: providing a semiconductor substrate including a first surface and a second surface opposite to the first surface, the second surface including a first region, a second region, and a third region between the first region and the second region; forming an isolation layer on the second region; removing a first thickness of semiconductor substrate corresponding to the first region and the third region; removing the isolation layer; forming a first full-surface carrier collection layer on the second surface, and forming an insulating layer on the first full-surface carrier collection layer; removing the insulating layer, the first full-surface carrier collection layer, and a second thickness of semiconductor substrate corresponding to the second region; forming a second full-surface carrier collection layer on the second surface; and selectively removing a portion of the second full-surface carrier collection layer on the first region and a portion of the insulating layer on the first region.

[0007] In some embodiments, forming the isolation layer on the second region includes performing a laser scanning ablation process on the second region by a first laser to form the isolation layer, wherein the isolation layer is an oxidation isolation layer.

[0008] In some embodiments, the first laser is at least one of an infrared laser, a green laser, or an ultraviolet laser, a pulse width of the first laser is at least one of nanoseconds or picoseconds, and a power of the first laser is 10 W to 300 W.

[0009] In some embodiments, a cleaning and polishing process is performed on the semiconductor substrate to remove the first thickness of semiconductor substrate corresponding to the first region and the third region.

[0010] In some embodiments, the isolation layer is removed by cleaning with an acidic solution.

[0011] In some embodiments, the first thickness is 2 microns to 5 microns, i.e., during processing of the second surface, the second region is higher than the first region and the third region by 2 microns to 5 microns in a direction from the first surface to the second surface.

[0012] In some embodiments, the first full-surface carrier collection layer includes a tunneling layer on the first region and the third region, and a doped semiconductor layer on the tunneling layer; the second full-surface carrier collection layer includes an intrinsic silicon-containing thin film on a surface of the second region and on the insulating layer, and a doped silicon-containing thin film on the intrinsic silicon-containing thin film; and a conductivity type of the doped silicon-containing thin film is opposite to a conductivity type of the doped semiconductor layer.

[0013] In some embodiments, the conductive type of the doped silicon-containing thin film is opposite to the conductive type of the semiconductor substrate, and the conductive type of the doped semiconductor layer is the same as the conductive type of the semiconductor substrate.

[0014] In some embodiments, the semiconductor substrate is an n-type silicon substrate, the tunneling layer is a silicon oxide layer, the doped semiconductor layer is an n-type doped polysilicon layer, and the doped silicon-containing thin film is a p-type doped silicon thin film.

[0015] In some embodiments, forming a full-surface first carrier collection layer on the second surface and forming an insulating layer on the first carrier collection layer comprises: forming a tunneling layer on the second surface of the semiconductor substrate, forming a doped semiconductor layer on the tunneling layer, and forming an insulating layer on the doped semiconductor layer.

[0016] In some embodiments, removing the second thickness of semiconductor substrate corresponding to the second region, and the insulating layer and the first carrier collection layer corresponding to the second region comprises: selectively performing an opening film process on the second region by a second laser to remove the part of the insulating layer on the second region and the part of the doped semiconductor layer on the second region; and performing polishing and texturing processes on the first surface and the second surface of the semiconductor substrate, so that the second region of the first surface and the second surface forms a textured surface.

[0017] In some embodiments, removing the second thickness of semiconductor substrate corresponding to the second region makes the surface of the remaining semiconductor substrate corresponding to the second region level with the insulating layer on the first region.

[0018] In some embodiments, during the texturing process performed on the second region of the first surface and the second surface, the etching time of the first surface and the second region of the second surface of the semiconductor substrate is 400 seconds to 600 seconds.

[0019] In some embodiments, selectively removing the part of the second carrier collection layer on the first region and the part of the insulating layer on the first region comprises: selectively performing a laser scanning ablation process on the first region by a third laser to remove the part of the intrinsic silicon-containing thin film on the first region, the part of the doped silicon-containing thin film on the first region, and the part of the insulating layer on the first region.

[0020] In some embodiments, the manufacturing method further comprises: before selectively removing the part of the second carrier collection layer on the first region and the part of the insulating layer on the first region, forming a passivation layer on the first surface of the semiconductor substrate, and forming an anti-reflection layer on the passivation layer.

[0021] In some embodiments, the manufacturing method further comprises: forming a conductive layer on the exposed first carrier collecting layer and the remaining second carrier collecting layer; removing a portion of the conductive layer on at least a portion of the third region; forming a first electrode connected to a portion of the conductive layer located in the first region and a second electrode connected to a portion of the conductive layer located in the second region.

[0022] In some embodiments, the manufacturing method further comprises: in the process of removing the portion of the conductive layer on at least a portion of the third region, also removing a portion of the doped silicon-containing film on at least a portion of the third region.

[0023] In some embodiments, the manufacturing method further comprises: in the process of removing the portion of the conductive layer on at least a portion of the third region, also removing a portion of the conductive layer on a portion of the second region close to the third region, or also removing a portion of the conductive layer and a portion of the doped silicon-containing film on a portion of the second region close to the third region.

[0024] In some embodiments, removing the portion of the conductive layer on at least a portion of the third region comprises: ablation processing at least a portion of the third region with a fourth laser to remove the portion of the conductive layer on at least a portion of the third region.

[0025] In some embodiments, the ablation width of the ablation processing with the fourth laser ranges from 20 microns to 150 microns.

[0026] In some embodiments, the first carrier collecting layer comprises a diffusion layer on the first region; the second carrier collecting layer comprises a tunneling layer on the second region and a doped semiconductor layer on the tunneling layer; the conduction type of the diffusion layer is opposite to the conduction type of the doped semiconductor layer.

[0027] In some embodiments, the conduction type of the diffusion layer is opposite to the conduction type of the semiconductor substrate, and the conduction type of the doped semiconductor layer is the same as the conduction type of the semiconductor substrate.

[0028] In some embodiments, the semiconductor substrate is an n-type silicon substrate, the tunneling layer is a silicon oxide layer, the diffusion layer is a p-type diffusion layer, and the doped semiconductor layer is an n-type doped polysilicon layer.

[0029] In some embodiments, forming a full-surface first carrier collection layer on the second surface and forming an insulating layer on the first carrier collection layer includes diffusing dopant atoms to the second surface of the semiconductor substrate to form the diffusion layer, and forming the insulating layer on the diffusion layer.

[0030] In some embodiments, removing the second region corresponding insulating layer, the first carrier collection layer, and the second thickness of semiconductor substrate includes removing the second region and the third region corresponding insulating layer using a fifth laser, and then removing the second region and the third region corresponding second thickness of semiconductor substrate by a wet process to remove the diffusion layer.

[0031] In some embodiments, the manufacturing method further includes forming a passivation layer and an anti-reflective layer on the first carrier collection layer corresponding to the first region and the second carrier collection layer corresponding to the second region; forming a first electrode in contact with the first carrier collection layer and a second electrode in contact with the second carrier collection layer on the anti-reflective layer.

[0032] According to another aspect of the present disclosure, there is provided a solar cell, comprising: a semiconductor substrate including a first surface and a second surface opposite to the first surface, the second surface including a first region, a second region, and a third region between the first region and the second region, wherein the first surface and the second region of the second surface have a texturing surface; a first carrier collection layer on the first region and the third region; an insulating layer on a portion of the first carrier collection layer on the third region; a second carrier collection layer on the texturing surface of the second region and the insulating layer; a conductive layer on a portion of the first carrier collection layer on the first region and on a portion of the second carrier collection layer on the second region, wherein the portion of the conductive layer on the first region is spaced apart from the portion of the conductive layer on the second region, and a height difference between the portion of the conductive layer on the first region, a surface of the semiconductor substrate away from a side of the semiconductor substrate, the portion of the conductive layer on the second region, and a portion of the second carrier collection layer on the third region away from the side of the semiconductor substrate is less than or equal to 2 microns; and a first electrode connected to the portion of the conductive layer on the first region and a second electrode connected to the portion of the conductive layer on the second region.

[0033] In some embodiments, a portion of the conductive layer is also on a portion of the second carrier collection layer on the third region.

[0034] In some embodiments, the first carrier collection layer includes: a diffusion layer on the first region; and a doped semiconductor layer on the diffusion layer.

[0035] In some embodiments, the second carrier collection layer includes: an intrinsic silicon-containing thin film on the texturized surface of the second region and the insulating layer; and a doped silicon-containing thin film on the intrinsic silicon-containing thin film, wherein the doped silicon-containing thin film has a conductivity type opposite to that of the doped semiconductor layer.

[0036] In some embodiments, the solar cell further includes: a passivation layer on the first surface of the semiconductor substrate; and an anti-reflective layer on the passivation layer.

[0037] According to yet another aspect of the present disclosure, a solar cell is provided, including: a semiconductor substrate including a first surface and a second surface opposite to the first surface, the second surface including a first region, a second region, and a third region between the first region and the second region, wherein the first surface and the first and third regions of the second surface have a texturized surface; a first carrier collection layer on the first region; a second carrier collection layer on the second region; a passivation layer on the first carrier collection layer, the texturized surface of the third region, and the second carrier collection layer; an anti-reflective layer on the passivation layer, wherein a height difference between a portion of the anti-reflective layer on the first region and a portion of the conductive layer on the second region is less than or equal to 2 microns; and a first electrode on the portion of the anti-reflective layer on the first region and in contact with the first carrier collection layer, and a second electrode on the portion of the anti-reflective layer on the second region and in contact with the second carrier collection layer.

[0038] In some embodiments, the first carrier collection layer includes: a diffusion layer on the first region.

[0039] In some embodiments, the second carrier collection layer includes: a tunneling layer on the second region and a doped semiconductor layer on the tunneling layer; the diffusion layer has a conductivity type opposite to that of the doped semiconductor layer.

[0040] In the manufacturing method, by forming the isolation layer on the second region of the second surface of the semiconductor substrate first, and then in the process of processing the second surface, the second region can be made higher than the first region and the third region in the direction from the first surface to the second surface, so that in the subsequent process of performing texturing or polishing on the second region, the height of the second region can be made substantially the same as the height of the first region, so that the height difference between different functional regions of the formed solar cell can be within 2 microns, and the amount of paste used for forming the electrode can be reduced.

[0041] Other features of the present disclosure, and their advantages, will become apparent from the following detailed description of exemplary embodiments of the present disclosure with reference to the drawings. BRIEF DESCRIPTION OF DRAWINGS

[0042] The accompanying drawings, which are incorporated in and constitute a part of this specification, illustrate embodiments of the present disclosure and, together with the description, serve to explain the principles of the present disclosure.

[0043] The present disclosure can be more clearly understood with reference to the following detailed description in conjunction with the accompanying drawings, in which:

[0044] Figure 1 is a flow chart showing a manufacturing method of a solar cell according to some embodiments of the present disclosure;

[0045] Figure 2 is a cross-sectional schematic view showing the structure at one stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0046] Figure 3 is a cross-sectional schematic view showing the structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0047] Figure 4 is a cross-sectional schematic view showing the structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0048] Figure 5 is a cross-sectional schematic view showing the structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0049] Figure 6 is a cross-sectional schematic view showing the structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0050] Figure 7 is a cross-sectional schematic view showing the structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0051] Figure 8is a cross-sectional schematic view showing a structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0052] Figure 9 is a cross-sectional schematic view showing a structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0053] Figure 10 is a cross-sectional schematic view showing a structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0054] Figure 11 is a cross-sectional schematic view showing a structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0055] Figure 12 is a cross-sectional schematic view showing a structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0056] Figure 13 is a cross-sectional schematic view showing a structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0057] Figure 14 is a cross-sectional schematic view showing a structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure;

[0058] Figure 15 is a cross-sectional schematic view showing a structure at another stage in the manufacturing process of a solar cell according to some embodiments of the present disclosure.

[0059] It should be understood that the dimensions of the various portions shown in the drawings are chosen for purposes of illustration only, and are not intended to be limiting. Furthermore, like or similar reference numerals are intended to refer to like or similar components. DETAILED DESCRIPTION

[0060] Various exemplary embodiments of the present disclosure will now be described in detail with reference to the accompanying drawings. The description of the exemplary embodiments is merely illustrative in nature and is in no way intended to limit the disclosure, its application or uses, nor is the disclosure to be construed as in any way limited to the embodiments set forth herein. The disclosure can be implemented in numerous ways, including, but not limited to, the embodiments described herein. These embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art. It should be noted that the relative

[0061] The terms "first", "second", and similar terms used in the present disclosure do not denote any order, quantity, or importance, but are used to distinguish different parts. The terms "include", "comprise", and similar terms mean that the elements before the term encompass the elements listed after the term, and do not exclude the possibility of also encompassing other elements. "Up", "down", "left", "right", and the like are used only to indicate relative positional relationships, and when the absolute positions of the described objects are changed, the relative positional relationships can also be changed accordingly.

[0062] In the present disclosure, when it is described that a specific device is located between a first device and a second device, there can be an intervening device between the specific device and the first device or the second device, or there can be no intervening device. When it is described that a specific device is connected to other devices, the specific device can be directly connected to the other devices without an intervening device, or can not be directly connected to the other devices with an intervening device.

[0063] All terms used in the present disclosure, including technical or scientific terms, have the same meanings as those understood by those skilled in the art to which the present disclosure pertains, unless otherwise specifically defined. It should also be understood that the terms defined in commonly used dictionaries should be interpreted as having meanings consistent with their meanings in the context of the relevant art, and should not be interpreted in an idealized or overly formal sense, unless specifically defined otherwise herein.

[0064] Techniques, methods, and devices known to those of ordinary skill in the relevant art can not be discussed in detail, but should be considered part of the specification where appropriate.

[0065] The currently common back contact solar cell mainly includes a semiconductor substrate, the semiconductor substrate includes a first surface and a second surface opposite to the first surface, wherein the second surface includes alternately arranged first regions and second regions, and a third region between adjacent first regions and second regions. A first carrier collection layer is arranged on the first region, and a second carrier collection layer is arranged on the second region. The conduction type of the first carrier collection layer and the second carrier collection layer is opposite, and the conduction type of one of the two is the same as the conduction type of the semiconductor substrate. Electrodes are further arranged on the first carrier collection layer and the second carrier collection layer.

[0066] In the manufacturing process of the above-mentioned back contact solar cell, the first carrier collecting layer is first prepared on the second surface of the semiconductor substrate, and then the first carrier collecting layer corresponding to the second region is removed. When the first carrier collecting layer corresponding to the second region is removed, the surface of the second region of the semiconductor substrate is usually damaged, and thus the surface of the second region needs to be polished or textured to remove a certain thickness of the second region to remove the damaged layer. Then, the second carrier collecting layer is formed on the second surface, and then the second carrier collecting layer corresponding to the first region is removed. Since a part of the thickness of the second region needs to be removed in the manufacturing process, the first region and the second region of the second surface of the semiconductor substrate usually have a certain height difference in the finally obtained back contact solar cell. Although the height difference between the first region and the second region can be reduced by reducing the damage to the semiconductor substrate corresponding to the second region when the first carrier collecting layer corresponding to the second region is removed, so as to reduce the thickness of the second region to be removed, there is still a thickness difference of more than 2 microns. When printing the electrode paste, a certain pressure needs to be applied to the paste by the printing screen, which makes it necessary to print more paste at the position with lower height, so that the amount of paste used is large, and the printing screen is also prone to damage.

[0067] In view of this, the embodiments of the present disclosure provide a manufacturing method of a solar cell. Before the first carrier collecting layer is formed, a part of the thickness of the first region and the third region of the second surface of the semiconductor substrate is removed, so that after a part of the thickness of the second region of the second surface of the semiconductor substrate is further removed, the height of the first region and the second region of the second surface of the semiconductor substrate is basically flat, and the height difference is 2 microns or less.

[0068] In the embodiments of the present disclosure, for the surface formed as a textured surface, the height difference is evaluated with reference to the plane where the point farthest from the semiconductor substrate (the highest point of the textured surface) of the textured surface.

[0069] The preparation method provided by the embodiments of the present disclosure can be applied to HBC solar cells or TBC solar cells, etc.

[0070] Figure 1 is a flow chart showing a manufacturing method of a solar cell according to some embodiments of the present disclosure. As shown in Figure 1 The manufacturing method includes steps S101 to S108. The manufacturing method

[0071] In step S101, a semiconductor substrate is provided, which includes a first surface and a second surface opposite to the first surface, and the second surface includes a first region, a second region and a third region between the first region and the second region. For example, the semiconductor substrate can be a silicon substrate. The first surface of the semiconductor substrate can be a surface for receiving solar light, i.e. a front surface; correspondingly, the second surface can be a back surface.

[0072] In step S102, an isolation layer is formed on the second region.

[0073] For example, the step S102 can include performing a laser scanning ablation process on the second region by a first laser to form the isolation layer, wherein the isolation layer is an oxidation isolation layer. The isolation layer can play a role in reducing subsequent etching.

[0074] In step S103, a first thickness of the semiconductor substrate corresponding to the first region and the third region is removed.

[0075] For example, the step S103 can include performing a cleaning and polishing process on the semiconductor substrate so that the second region is higher than the first region and the third region in a direction from the first surface to the second surface.

[0076] Here, since the isolation layer is formed on the second region in step S102, during the cleaning and polishing process on the semiconductor substrate, etching of the second region can be reduced, so that the second region can be made higher than the first region and the third region. Thus, during a subsequent texturing process performed on the second region, the height of the textured second region can be made substantially the same as the height of the first region and the third region, so that the height difference between different functional regions of the final formed solar cell is reduced, thereby improving the photoelectric conversion efficiency of the solar cell.

[0077] In step S104, the isolation layer is removed.

[0078] For example, cleaning is performed by an acidic solution (hydrofluoric acid HF solution) to remove the isolation layer.

[0079] In step S105, a first carrier collection layer is formed on the second surface, and an insulating layer is formed on the first carrier collection layer.

[0080] The first carrier collection layer can have different structures according to different types of back contact solar cells. In some embodiments, for an HBC cell, the first carrier collection layer can include a tunneling layer on the first region and the third region, and a doped semiconductor layer on the tunneling layer. For example, the doped semiconductor layer can be a doped polysilicon layer. The insulating layer can be silicon oxide or silicon nitride. In other embodiments, for a TBC cell, the first carrier collection layer can include a diffusion layer on the first region, i.e., doped atoms diffuse into the semiconductor substrate to form. The insulating layer can be a silicon glass layer containing doped atoms.

[0081] In step S106, the insulating layer, the first carrier collection layer, and a second thickness of the semiconductor substrate corresponding to the second region are removed.

[0082] In some embodiments, the step S106 can include performing polishing and texturing processes on the first surface and the second surface of the semiconductor substrate, so that the second region of the first surface and the second surface forms a textured surface.

[0083] Since in the previous step S103, the second region is higher than the first region and the third region, after the semiconductor substrate of the second thickness corresponding to the second region is removed in this step S106, the height of the second region is substantially consistent with the height of the first region and the third region, so that the height difference between different functional regions of the finally formed solar cell is reduced, thereby improving the photoelectric conversion efficiency of the solar cell. For example, for the HBC cell, the surface of the second region can be substantially leveled with the plane of the side of the insulating layer away from the semiconductor substrate on the first region and the third region.

[0084] It should be noted that the "leveling" described herein includes but is not limited to absolute leveling, and there can be some error. For example, the error of the height difference between the textured surface of the second region and the plane of the side of the insulating layer away from the semiconductor substrate on the first region and the third region can be within ±2 microns. Therefore, "leveling" herein can be understood as "substantially leveling".

[0085] In step S107, a full-surface second carrier collection layer is formed on the second surface.

[0086] In some embodiments, for the HBC cell, the second carrier collection layer can include: an intrinsic silicon-containing thin film on the textured surface of the second region and on the insulating layer; and a doped silicon-containing thin film on the intrinsic silicon-containing thin film, wherein the conductivity type of the doped silicon-containing thin film is opposite to the conductivity type of the doped semiconductor layer. In other embodiments, for the TBC cell, the second carrier collection layer can include: a tunneling layer on the second region and a doped semiconductor layer on the tunneling layer; the conductivity type of the diffusion layer is opposite to the conductivity type of the doped semiconductor layer. The doped semiconductor layer can be a doped polysilicon layer. And for the TBC cell, an insulating layer, such as a silicon glass layer containing doped atoms, can also be formed on the second carrier collection layer.

[0087] In step S108, the part of the second carrier collection layer on the first region and the part of the insulating layer on the first region are selectively removed.

[0088] In some embodiments, the step S108 can include: using a third laser to selectively perform laser scanning ablation processing on the first region, so as to remove the part of the intrinsic silicon-containing thin film on the first region, the part of the doped silicon-containing thin film on the first region, and the part of the insulating layer on the first region.

[0089] So far, a manufacturing method of a solar cell according to some embodiments of the present disclosure is provided. The manufacturing method comprises: providing a semiconductor substrate, the semiconductor substrate comprising a first surface and a second surface opposite to the first surface, the second surface comprising a first region, a second region and a third region between the first region and the second region; forming an isolation layer on the second region; removing a first thickness of the semiconductor substrate corresponding to the first region and the third region; removing the isolation layer; forming a first carrier collection layer on the second surface and forming an insulating layer on the first carrier collection layer; removing the insulating layer, the first carrier collection layer and a second thickness of the semiconductor substrate corresponding to the second region; forming a second carrier collection layer on the second surface; and selectively removing a part of the second carrier collection layer on the first region and a part of the insulating layer on the first region. In the manufacturing method, by forming the isolation layer on the second region of the second surface of the semiconductor substrate first, and then processing the second surface, the second region can be higher than the first region and the third region in the direction from the first surface to the second surface, so that the height of the second region can be substantially the same as the height of the first region in the process of performing texturing or polishing on the second region, thereby reducing the height difference between different functional regions of the formed solar cell.

[0090] For example, the manufacturing method can make the height difference between the p and n functional regions within a range of 0 to 2 microns, thereby reducing the height difference between the p and n functional regions as much as possible.

[0091] The manufacturing method can reduce the paste loss in the printing-related process by making the p and n functional regions have a similar height difference, thereby increasing the service life of the screen plate and reducing the manufacturing cost of the solar cell.

[0092] In some embodiments, the manufacturing method can further comprise: before step S108, forming a passivation layer on the first surface of the semiconductor substrate, and forming an anti-reflection layer on the passivation layer. By sequentially forming the passivation layer and the anti-reflection layer on the first surface of the semiconductor substrate, the photoelectric conversion efficiency of the solar cell can be further improved.

[0093] Figures 2 to 15 FIG. 1 is a cross-sectional schematic view showing the structure of some stages in the manufacturing process of an HBC solar cell according to some embodiments of the present disclosure. The following will be described in combination with Figures 2 to 15 The manufacturing process of a solar cell according to some embodiments of the present disclosure will be described in detail.

[0094] First, as shown in FIG. 1, a semiconductor substrate 100 is provided. The semiconductor substrate 100 comprises a first surface 101 and a second surface 102 opposite to the first surface 101. The second surface 102 comprises a first region 102a, a second region 102b and a third region 102c between the first region 102a and the second region 102b. Figure 2As shown, a semiconductor substrate 1 is provided. The semiconductor substrate 1 includes a first surface la and a second surface lb opposite to the first surface la. The second surface lb includes a first region A, a second region B, and a third region (may also be referred to as a cross region) C between the first region and the second region. The first region A and the second region B are arranged alternately, and the third region C is located between adjacent first region A and second region B. For example, the first region A, the second region B, and the third region C are arranged in the arrangement of ACBC. For example, the width of the third region C is greater than or equal to 50 microns. The third region C can subsequently play an insulating isolation role, and can also reduce the thermal damage to the second region when the third laser scanning ablation is performed.

[0095] For example, the semiconductor substrate is a silicon substrate. For example, the conductivity type of the silicon substrate is n-type or p-type, and can be a single crystal silicon wafer or a polycrystalline silicon wafer.

[0096] Next, an isolation layer is formed on the second region.

[0097] For example, as shown in FIG. 1C, a first laser 12 is used to perform laser scanning ablation processing on the second region B to form an isolation layer 13 on the second region B. The isolation layer 13 is an oxidation isolation layer (for example, silicon oxide). The laser ablation method is relatively simple and easy to implement. Moreover, using a laser of a certain wavelength and energy to perform a pre-scanning ablation processing on the surface of the second region can form an ablation melting region with partially heavily doped elements on the surface of the semiconductor substrate, which can further achieve the effect of removing impurities (for example, metals, bulk defects, etc.) in the substrate. Figure 3 Figure 4 For example, as shown in FIG. 1C, a first laser 12 is used to perform laser scanning ablation processing on the second region B to form an isolation layer 13 on the second region B. The isolation layer 13 is an oxidation isolation layer (for example, silicon oxide). The laser ablation method is relatively simple and easy to implement. Moreover, using a laser of a certain wavelength and energy to perform a pre-scanning ablation processing on the surface of the second region can form an ablation melting region with partially heavily doped elements on the surface of the semiconductor substrate, which can further achieve the effect of removing impurities (for example, metals, bulk defects, etc.) in the substrate.

[0098] In some embodiments, the first laser 12 is an infrared laser (for example, with a wavelength of 780 nm to 1064 nm), a green laser (for example, with a wavelength of 532 nm or 533 nm), or an ultraviolet laser (for example, with a wavelength of 193 nm to 355 nm). The pulse width of the first laser can be at least one of nanoseconds (for example, 1 ns to 100 ns) or picoseconds (for example, 1 ps to 50 ps). For example, the pulse width of the first laser can be at least one of nanoseconds, picoseconds, or a combination or mixture thereof. The power of the first laser is 10 W to 300 W. Of course, the first laser here is only exemplary, and the scope of the present disclosure is not limited thereto.

[0099] For example, the first laser can be an ultraviolet laser (for example, with a wavelength of 248 nm), the pulse width is 20 ns, the laser energy density is 5 J / cm 2 , and the laser frequency is 10 Hz.

[0100] ​In other embodiments, other processes may be used to form the isolation layer. For example, the area outside the second region B may be shielded, and an oxidized isolation layer may be formed on the second region B by chemical oxidation.

[0101] Next, if Figure 5 As shown, the semiconductor substrate 1 is cleaned and polished, and the isolation layer 13 is stripped so that the second region B is formed in a direction from the first surface 1a to the second surface 1b (ie, Figure 5 In the direction from top to bottom in the middle, it is higher than the first region A and the third region C. In this way, the semiconductor substrate of the first thickness corresponding to the first region and the third region is removed.

[0102] In this step, the semiconductor substrate is cleaned and polished, and the isolation layer is stripped, so that a polished surface structure with a certain height difference is formed on the second surface 1b of the semiconductor substrate. For example, HF solution (i.e., hydrofluoric acid solution) is used to strip the isolation layer.

[0103] Here, before the isolation layer is stripped, the second area B is protected by an isolation layer (e.g., an oxide layer), while the first area is bare silicon. During the polishing process, an alkaline solution is used to treat the second surface, and the bare silicon in the first area is more easily etched by the alkaline solution, resulting in a certain height difference between the two areas.

[0104] For example, Figure 5 As shown, the first thickness can be 2 μm to 5 μm, for example, 2.5 μm, 3 μm, 3.5 μm, 4 μm, 4.5 μm, etc., that is, the height difference H between the second region B and the first region A (or the third region C) can be 2 μm to 5 μm. In other words, during the processing of the second surface 1 b, in the direction from the first surface 1 a to the second surface 1 b, the second region B is 2 μm to 5 μm higher than the first region A and the third region C.

[0105] Next, a first carrier collection layer is formed on the first region and the third region, and an insulating layer is formed on the first carrier collection layer.

[0106] The conductivity type of the doped semiconductor layer may be the same as the conductivity type of the semiconductor substrate. For example, for an n-type silicon substrate, the doped semiconductor layer is an n-type doped polysilicon layer.

[0107] The following combination Figure 6 and Figure 7 The process of forming the first carrier collection layer and the insulating layer is described in detail.

[0108] A first carrier collection layer is formed on the entire surface of the second surface, and an insulating layer is formed on the first carrier collection layer. Figure 6As shown, a tunneling layer 2 is formed on the second surface 1b of the semiconductor substrate 1, a doped semiconductor layer 3 is formed on the tunneling layer 2, and an insulating layer 4 is formed on the doped semiconductor layer 3. For example, the tunneling layer 2 is a tunneling oxide layer (e.g., silicon oxide), the doped semiconductor layer 3 is a doped polysilicon layer 3, and the insulating layer 4 is an insulating isolation layer. For example, the insulating layer 4 includes silicon nitride or silicon oxide, or a stacked structure thereof. In other words, the tunneling oxide layer 2, the doped polysilicon layer 3, and the insulating isolation layer 4 are sequentially formed on the second surface 1b of the semiconductor substrate 1.

[0109] Then, the insulating layer, the first carrier collection layer and the second thickness of the semiconductor substrate corresponding to the second region are removed. Figure 7 As shown, the second region B is selectively opened by the second laser 14 to remove the portion of the insulating layer 4 on the second region B and the portion of the doped semiconductor layer 3 on the second region B. Here, the portion of the insulating layer 4 on the first region A and the third region C and the portion of the doped semiconductor layer 3 on the first region A and the third region C remain.

[0110] In this way, the first carrier collection layer 61 and the insulating layer 4 are formed. The first carrier collection layer 61 may include: a tunneling layer 2 on the first region A and the third region C; and a doped semiconductor layer 3 on the tunneling layer 2.

[0111] In some embodiments, the second laser 14 is a green laser (e.g., with a wavelength of 532 nm or 533 nm) or an ultraviolet laser (e.g., with a wavelength of 193 nm to 355 nm). The pulse width of the second laser is at least one of picoseconds (e.g., 1 ps to 50 ps) or femtoseconds (less than 1 ps). For example, the pulse width can be at least one of picoseconds and femtoseconds, or a combination thereof. For example, the power of the second laser 14 is 5 W to 200 W.

[0112] For example, the second laser 14 can be a green laser with a pulse width of 15 ps and a laser energy density of 2 J / cm 2 , the laser frequency is 500KHz (kilohertz).

[0113] The above-mentioned "film opening" refers to laser ablation. The laser sublimates the film layer through high-temperature heat or changes the properties of the film layer, which can be etched away by subsequent chemical solutions.

[0114] Next, if Figure 8 As shown, the first surface 1a and the second surface 1b of the semiconductor substrate 1 are polished and textured so that the second area B of the first surface 1a and the second surface 1b forms a textured surface. In this step, the surface of the semiconductor substrate is polished and textured so that the second area B of the first surface 1a and the second surface 1b of the semiconductor substrate exposes the semiconductor substrate 1 and forms a textured surface.

[0115] During the polishing and texturing process, the portion of the tunneling layer 2 on the second area B is removed. Since the doped semiconductor layer 3 and the insulating layer 4 exist on the first area A and the third area C, the first area A and the third area C will not be made into a texturing surface. In addition, during the polishing and texturing process, the height of the second area B will also be reduced. In this way, the texturing surface of the second area B is basically level with the insulating layer 4 on the first area A and the third area C.

[0116] The above steps can make the textured surface of the second region B substantially flush with the plane of the remaining insulating layer 4 on the side away from the semiconductor substrate (which can be called the lower surface). In other words, the height of the second region is substantially consistent with the heights of the first and third regions. This reduces the height difference between the different functional regions of the ultimately formed solar cell, thereby improving the photoelectric conversion efficiency of the solar cell. Similar to the previous description, the term "flat" here can be understood as "substantially flat."

[0117] In some embodiments, during the texturing process on the second region B of the first surface 1a and the second surface 1b, the time for etching the first surface and the second region of the second surface of the semiconductor substrate 1 is 400 seconds to 600 seconds. This etching time range can ensure that the texturing surface of the second region B is substantially flush with the lower surface of the insulating layer 4 on the first region A and the third region C.

[0118] It should be noted that the above corrosion time is exemplary, and the scope of the present disclosure is not limited thereto.

[0119] Texturing can be performed using an etchant. This refers to a liquid that chemically reacts with a substance. Here, the etchant is a mixture of an alkaline solution (e.g., KOH or NaOH) and a texturing additive. For example, the concentration of the alkaline solution is 1% to 3%. The amount of texturing additive can be determined experimentally.

[0120] Next, if Figure 9 As shown, the second carrier collection layer 62 is formed on the textured surface of the second region B and on the insulating layer 4 on the first region A and the third region B. That is, the second carrier collection layer is formed on the entire surface of the second surface.

[0121] For example, the second carrier collection layer 62 may include: an intrinsic silicon-containing thin film 7 on the textured surface of the second region B and on the insulating layer 4; and a doped silicon-containing thin film 8 on the intrinsic silicon-containing thin film 7. The conductivity type of the doped silicon-containing thin film 8 is opposite to the conductivity type of the doped semiconductor layer 3. For example, the conductivity type of the doped semiconductor layer 3 is n-type, and the conductivity type of the doped silicon-containing thin film 8 is p-type. For another example, the conductivity type of the doped semiconductor layer 3 is p-type, and the conductivity type of the doped silicon-containing thin film 8 is n-type.

[0122] The intrinsic silicon-containing film 7 can play a passivation role. For example, the intrinsic silicon-containing film 7 can be a single layer of microcrystalline, nanocrystalline, amorphous silicon, silicon oxide, or silicon carbide thin film layers with the same properties, or a multilayer or mixed silicon-containing film with different properties.

[0123] For example, the doped silicon-containing film 8 can be a single layer of a thin film layer of microcrystalline, nanocrystalline, or amorphous silicon, silicon oxide, or silicon carbide, with the same properties, or multiple layers of a thin film layer with different properties, or a stacked or mixed silicon-containing film. For example, the sheet resistance of the doped silicon-containing film 8 is ≥500 Ω / sq (Ohm per square).

[0124] In some embodiments, an intrinsic silicon-containing thin film 7 and a doped silicon-containing thin film 8 may be sequentially formed on the second surface 1 b of the semiconductor substrate 1 by deposition or other processes.

[0125] Next, if Figure 10 As shown, a passivation layer 5 is formed on the first surface 1a of the semiconductor substrate 1, and an anti-reflection layer 6 is formed on the passivation layer 5. That is, the passivation layer 5 and the anti-reflection layer 6 are sequentially formed on the first surface 1a of the semiconductor substrate 1.

[0126] Next, the portion of the second carrier collection layer 62 on the first region A and the portion of the insulating layer 4 on the first region A are selectively removed.

[0127] In some embodiments, as Figure 11 As shown, the first region A can be selectively subjected to laser scanning ablation processing using the third laser 15 to remove the portion of the intrinsic silicon-containing film 7 on the first region, the portion of the doped silicon-containing film 8 on the first region, and the portion of the insulating layer 4 on the first region, thereby forming a Figure 12 Thus, the first carrier collection layer 61 (eg, the doped semiconductor layer 3 of the first carrier collection layer 61 ) in the first region A is exposed.

[0128] In some embodiments, the third laser 15 is a green laser (e.g., with a wavelength of 532 nm or 533 nm) or an ultraviolet laser (e.g., with a wavelength of 193 nm to 355 nm). The pulse width of the third laser 15 can be at least one of picoseconds (1 ps to 50 ps) and femtoseconds (less than 1 ps). For example, the pulse width of the third laser 15 can be at least one of picoseconds and femtoseconds, or a combination thereof. The power of the third laser 15 can be 1 W to 150 W.

[0129] For example, the third laser 15 can be a green laser with a pulse width of 15 ps and a laser energy density of 0.5 J / cm 2, the laser frequency is 500 KHz.

[0130] In other embodiments, other processes (e.g., printing or inkjet printing of etching paste) can also be used to remove the portion of the intrinsic silicon-containing thin film 7, the portion of the doped silicon-containing thin film 8, and the portion of the insulating layer 4 on the first region.

[0131] Next, as shown in FIG. 6, for example, a conductive layer 11 is formed on the exposed first carrier collection layer 61 and the remaining second carrier collection layer 62 by a deposition process. That is, the conductive layer 11 is deposited on the second surface lb of the semiconductor substrate 1. Figure 13

[0132] In some embodiments, the conductive layer 11 is a transparent conductive thin film layer. For example, the transparent conductive thin film layer is a doped one or more of a plurality of layers or a stack of layers or a mixture of one or more of a metal oxide or a metal nitride, the metal oxide can be indium oxide, tin oxide, zinc oxide, cadmium oxide, titanium nitride, the metal nitride can be titanium nitride, and the doping element can be indium, tin, calcium, aluminum, cadmium, zinc, cerium, fluorine, etc.

[0133] Next, a portion of the conductive layer 11 on at least a portion of the third region C is removed. For example, as shown in FIG. 7, an ablation process is performed on at least a portion of the third region C using a fourth laser 16 to remove a portion of the conductive layer 11 on at least a portion of the third region. In this way, the conductive layer on the first region is isolated from the conductive layer on the second region, preventing short circuiting between the first region and the second region. Figure 14

[0134] For example, the ablation width of the ablation process performed using the fourth laser 16 is in the range of 20 microns to 150 microns. This width range can both isolate the conductive layer on the first region from the conductive layer on the second region and not make the ablation width too large to affect the first region and the second region.

[0135] In some embodiments, the fourth laser 16 is an ultraviolet laser (e.g., a wavelength of 193 nm to 355 nm). The pulse width of the fourth laser 16 is at least one of picoseconds (1 ps to 50 ps) or femtoseconds (less than 1 ps). For example, the pulse width of the fourth laser 16 is at least one of or a combination of picoseconds or femtoseconds. The power of the fourth laser 16 can be 1 W to 100 W.

[0136] For example, the fourth laser 16 can be an ultraviolet laser (e.g., a wavelength of 355 nm), the pulse width is 20 ps, and the laser energy density is 5 J / cm 2 , the laser frequency is 30 KHz.

[0137] ​​In some embodiments, during the process of removing the portion of the conductive layer 11 on at least a portion of the third region C, the portion of the doped silicon-containing film 8 on at least a portion of the third region C is also removed. This can further isolate the first region from the second region.

[0138] In some embodiments, the manufacturing method may further include: during the process of removing the portion of the conductive layer on at least a portion of the third region, also removing a portion of the conductive layer on a portion of the second region adjacent to the third region, or further removing a portion of the conductive layer and a portion of the doped silicon-containing film on a portion of the second region adjacent to the third region. In other words, during the process of removing the portion of the conductive layer on at least a portion of the third region, also removing a portion of the conductive layer on a portion of the second region adjacent to the third region, or, in addition to removing a portion of the conductive layer on a portion of the second region adjacent to the third region, also removing a portion of the doped silicon-containing film on a portion of the second region adjacent to the third region, which can further isolate the conductive layer on the first region from the conductive layer on the second region.

[0139] In the above embodiment, the fourth laser 16 can be used to perform ablation treatment (i.e., ablation treatment) on a portion of the second region B close to the third region C, and the third region C or a portion of the third region C close to the second region B to remove the conductive layer 11 or the conductive layer 11 and a portion of the doped silicon-containing film 8.

[0140] In other embodiments, other processes (for example, printing etching slurry or inkjet printing etching slurry) may be used to perform the removal process on the third region.

[0141] Next, if Figure 15 As shown, a first electrode 9 connected to the portion of the conductive layer 11 located in the first region A and a second electrode 10 connected to the portion of the conductive layer 11 located in the second region B are formed. That is, the first electrode 9 and the second electrode 10 are respectively formed on the first region A and the second region B of the second surface 1b of the semiconductor substrate 1. Here, the first electrode 9 and the second electrode 10 are both metal electrodes.

[0142] The method for manufacturing the HBC solar cell is described above.

[0143] For TBC batteries, the following preparation method can be used.

[0144] First, an isolation layer 13 is formed on the second region B of the second surface 1 b of the semiconductor substrate 1 . For example, the second region B is laser ablated by the first laser 12 to form an oxidized isolation layer on the surface of the second region B.

[0145] Next, a cleaning and texturing process is performed on the semiconductor substrate 1, and the first thickness of the semiconductor substrate 1 corresponding to the first region A and the third region C is removed, so that the second region B is higher than the first region A and the third region C in the direction from the first surface la to the second surface lb, and at the same time, the surfaces of the first region A and the third region C are formed into textured surfaces. Then the isolation layer 13 is removed. For example, the oxide isolation layer can be removed by an acidic solution (HF solution).

[0146] Next, a diffusion layer is formed by diffusing dopant atoms into the semiconductor substrate 1 as a first carrier collecting layer. At the same time, the diffusion layer is formed, a first insulating layer is formed on the diffusion layer. For example, for an n-type silicon substrate, boron atoms can be doped to form a p-type diffusion layer, and a silicon glass layer containing boron atoms (i.e., a boron-silicon glass layer BSG) can be used as the first insulating layer; for a p-type silicon substrate, phosphorus atoms can be doped to form an n-type diffusion layer, and a silicon glass layer containing phosphorus atoms (i.e., a phosphorus-silicon glass layer PSG) can be used as the first insulating layer. In this step, the structure of the diffusion layer / first insulating layer is usually formed on both surfaces of the semiconductor substrate 1.

[0147] Next, the first insulating layer corresponding to the second region B and the third region C is removed by using a fifth laser. The fifth laser can be a green light band (e.g., wavelength 532 nm) laser with a power of 40 W to 50 W, and the laser pulse width can be picoseconds. Then the first insulating layer on the first surface is removed by a wet process (e.g., by an HF solution). Then the second thickness of the semiconductor substrate 1 corresponding to the second region B and the third region C is removed by a wet process, for example, by polishing with an alkaline solution, to remove the diffusion layer of the second region B and the third region C, and at the same time, to remove the diffusion layer on the first surface la. For a TBC solar cell, the second thickness is determined so that after the second carrier collecting layer and the second insulating layer are formed on the second region B, the outermost surface of the second insulating layer on the second region B is substantially level with the outermost surface of the first insulating layer on the first region A.

[0148] Next, a tunneling layer is formed on both surfaces of the semiconductor substrate 1, a doped semiconductor layer is formed on the tunneling layer, and a second insulating layer is formed on the doped semiconductor layer. The tunneling layer can be a silicon oxide layer. For an n-type silicon substrate, the doped semiconductor layer can be an n-type doped polysilicon layer, and the second insulating layer can be a PSG layer; for a p-type silicon substrate, the doped semiconductor layer can be a p-type doped polysilicon layer, and the second insulating layer can be a BSG layer.

[0149] Next, a sixth laser (e.g., a 30W green picosecond laser) is used to remove the second insulating layer corresponding to the first region A and the third region C. A wet process (e.g., an HF solution) is used to remove the second insulating layer on the first surface 1a. Then, a wet process (e.g., an alkaline texturing solution) is used to remove the doped semiconductor layer and tunneling layer corresponding to the first region A and the third region C of the first surface 1a and the second surface 1b, forming a texturing surface on the surfaces of the first surface 1a and the third region C. A wet process (e.g., an HF solution) is then used to remove the first insulating layer on the first region A and the second insulating layer on the second region B.

[0150] Next, a passivation layer and an anti-reflection layer are formed on the first surface 1a and the second surface 1b. For the first region A of the second surface 1b, the passivation layer and anti-reflection layer are formed on the diffusion layer. For the second region B of the second surface 1b, the passivation layer and anti-reflection layer are formed on the doped semiconductor layer. For the third region C of the second surface 1b, the passivation layer and anti-reflection layer are formed on the surface of the semiconductor substrate 1. The passivation layer may be an aluminum oxide layer, and the anti-reflection layer may be a silicon nitride layer. Next, a first electrode is formed on the anti-reflection layer, contacting the first carrier collection layer (diffusion layer), and a second electrode is formed on the second carrier collection layer (doped semiconductor layer). It will be appreciated that for TBC cells, the manufacturing method provided in the embodiments of the present disclosure achieves substantially flush surfaces between the first region A and the second region B. However, to isolate the first region A from the second region B, the third region C remains lower than the surfaces of the first and second regions A and B.

[0151] Thus, a method for manufacturing a solar cell according to some embodiments of the present disclosure is provided. In this manufacturing method, an isolation layer is first formed on the second region of the second surface of the semiconductor substrate, and then, during the process of processing the second surface, the second region can be made higher than the first region and the third region in the direction from the first surface to the second surface. In this way, during the process of performing a texturing or polishing process on the second region, the height of the second region can be made substantially consistent with the height of the first region. In this way, the height difference between different functional regions of the formed solar cell can be reduced, the slurry loss in the printing-related process is reduced, the service life of the stencil is increased, and the manufacturing cost of the solar cell is reduced.

[0152] The above manufacturing method also forms a HBC solar cell. Figure 15 The structure of the HBC solar cell according to some embodiments of the present disclosure is described in detail.

[0153] For example, Figure 15As shown, the solar cell includes a semiconductor substrate 1. The semiconductor substrate 1 includes a first surface 1a and a second surface 1b opposite to the first surface 1a. The second surface 1b includes a first region A, a second region B, and a third region C between the first region A and the second region B. The first surface 1a and the second region B of the second surface 1b have a textured surface.

[0154] For example, the semiconductor substrate 1 may be a silicon substrate. For example, the silicon substrate is an n-type silicon substrate. The n-type silicon substrate has a first surface and a second surface opposite to each other. The second surface includes first regions A and second regions B alternately arranged, and the third region C is located between adjacent first regions A and second regions B.

[0155] like Figure 15 As shown, the solar cell further includes a first carrier collection layer 61 on the first region A and the third region C. For example, the first carrier collection layer 61 may include: a tunneling layer 2 on the first region A and the third region C, and a doped semiconductor layer 3 on the tunneling layer 2.

[0156] For example, the tunneling layer 2 is a tunneling oxide layer. For example, the tunneling oxide layer is silicon oxide. For example, the thickness of the tunneling layer 2 can be 0.5 nm to 3 nm.

[0157] For example, the doped semiconductor layer 3 may be a doped polysilicon layer. For example, the doped polysilicon layer may be an n-type doped polysilicon layer. For example, the thickness of the doped semiconductor layer 3 may be 30 nm to 300 nm.

[0158] like Figure 15 As shown, the solar cell further includes an insulating layer 4 on a portion of the first carrier collection layer 61 located on the third region C. For example, the insulating layer 4 includes at least one of silicon nitride or silicon oxide.

[0159] like Figure 15 As shown, the solar cell further includes a second carrier collection layer 62 on the textured surface of the second region B and the insulating layer 4. For example, the second carrier collection layer may include: an intrinsic silicon-containing thin film 7 on the textured surface of the second region B and the insulating layer 4, and a doped silicon-containing thin film 8 on the intrinsic silicon-containing thin film 7. The conductivity type of the doped silicon-containing thin film 8 is opposite to the conductivity type of the doped semiconductor layer 3. For example, the doped silicon-containing thin film 8 may be a p-type doped silicon-containing thin film.

[0160] like Figure 15As shown, the solar cell further includes a conductive layer 11 on the portion of the first carrier collection layer 61 located on the first region A and on the portion of the second carrier collection layer 62 located on the second region B. For example, the conductive layer 11 can be a transparent conductive film layer. The portion of the conductive layer 11 located on the first region A is spaced apart from the portion of the conductive layer 11 located on the second region B, and the height difference between the surface of the portion of the conductive layer 11 located on the first region A away from the semiconductor substrate 1, the surface of the portion of the conductive layer 11 located on the second region B away from the semiconductor substrate 1, and the surface of the portion of the second carrier collection layer 62 located on the third region C away from the semiconductor substrate 1 is less than or equal to 2 microns.

[0161] As shown, Figure 15 The solar cell further includes a first electrode 9 connected to the portion of the conductive layer 11 located on the first region A and a second electrode 10 connected to the portion of the conductive layer 11 located on the second region B. The first electrode 9 is a first metal electrode, and the second electrode 10 is a second metal electrode.

[0162] So far, the solar cell according to some embodiments of the present disclosure has been provided. The solar cell includes a semiconductor substrate, a first carrier collection layer, an insulating layer, a second carrier collection layer, a conductive layer, a first electrode, and a second electrode. In the solar cell, the height difference between the surface of the portion of the conductive layer located on the first region away from the semiconductor substrate, the surface of the portion of the conductive layer located on the second region away from the semiconductor substrate, and the surface of the portion of the second carrier collection layer located on the third region away from the semiconductor substrate is less than or equal to 2 microns, that is, the height difference of each structure layer on the first region, the second region, and the third region is as small as possible, which makes the structure layer on the second region not only substantially level with the structure layer on the first region, but also substantially level with the structure layer on the third region, so that the height difference between different functional regions of the solar cell can be reduced, and the amount of electrode paste can be reduced.

[0163] In some embodiments, a portion of the conductive layer 11 can also be located on a portion of the second carrier collection layer 62 located on the third region C. That is, the conductive layer 11 is not only located on the first region and the second region, but also a portion of the conductive layer is located on the third region C, as long as this portion of the conductive layer is isolated from the conductive layer on the first region A or the second region B.

[0164] For example, in some cases, each layer on the third region C may include two structures. (1) The third region C includes: a tunneling layer 2, a doped semiconductor layer 3, an insulating layer 4, an intrinsic silicon-containing thin film 7, and a fully or partially doped silicon-containing thin film 8. (2) The third region C adjacent to the second region B includes: a tunneling layer 2, a doped semiconductor layer 3, an insulating layer 4, an intrinsic silicon-containing thin film 7, and a fully or partially doped silicon-containing thin film 8; the portion of the third region C adjacent to the first region A includes: a tunneling layer 2, a doped semiconductor layer 3, an insulating layer 4, an intrinsic silicon-containing thin film 7, a doped silicon-containing thin film 8, and a conductive layer 11.

[0165] In some embodiments, as Figure 15 As shown, the solar cell may further include a passivation layer 5 on the first surface 1a of the semiconductor substrate 1. For example, the passivation layer 5 is an intrinsic silicon-containing thin film or a combination of an intrinsic silicon-containing thin film and a doped silicon-containing thin film (for example, an n-type doped silicon-containing thin film). For example, the intrinsic silicon-containing thin film has a thickness of 1 nm to 15 nm, and the doped silicon-containing thin film (for example, an n-type doped silicon-containing thin film) has a thickness of 0 to 15 nm. For another example, the passivation layer 5 may include a doped silicon layer (for example, an n-type doped silicon layer) or aluminum oxide.

[0166] In some embodiments, as ​ As shown, the solar cell may further include an antireflection layer 6 on the passivation layer 5. For example, the antireflection layer 6 may include at least one of aluminum oxide, silicon oxide, gallium oxide, silicon nitride, aluminum nitride, silicon oxynitride, aluminum oxynitride, magnesium fluoride, lithium fluoride, ITO (Indium Tin Oxide), and zinc oxide. For example, the thickness of the antireflection layer 6 may be 40 nm to 200 nm.

[0167] That is, the passivation layer 5 and the anti-reflection layer 6 are sequentially arranged on the first surface 1 a of the semiconductor substrate 1 in a direction away from the semiconductor substrate 1 .

[0168] In some embodiments of the present disclosure, taking a semiconductor substrate as a silicon substrate as an example, a solar cell includes: a silicon substrate having a first surface and a second surface opposite to each other, the second surface including a first region, a second region, and a third region arranged alternately. A passivation layer and an anti-reflection layer are sequentially disposed on the first surface of the silicon substrate in a direction away from the silicon substrate; a tunneling oxide layer, a doped polysilicon layer, a transparent conductive film layer, and a first metal electrode are sequentially disposed on the first region of the second surface of the silicon substrate in a direction away from the silicon substrate; an intrinsic silicon-containing film, a doped silicon-containing film, a transparent conductive film layer, and a second metal electrode are sequentially disposed on the second region of the second surface of the silicon substrate in a direction away from the silicon substrate; and a tunneling oxide layer, a doped polysilicon layer, an insulating layer, an intrinsic silicon-containing film, and a doped silicon-containing film are sequentially disposed on the third region of the second surface of the silicon substrate in a direction away from the silicon substrate. Alternatively, a transparent conductive film layer may also be disposed.

[0169] The manufacturing method provided by the embodiments of the present disclosure can also obtain a TBC battery. The TBC battery can include:

[0170] A semiconductor substrate 1 includes a first surface 1a and a second surface 1b opposite to the first surface 1a, the second surface 1b includes a first region A, a second region B and a third region C between the first region A and the second region B, wherein the first region A and the third region C of the first surface 1a and the second surface 1b have a texturing surface. Wherein the semiconductor substrate 1 can be an n-type silicon substrate or a p-type silicon substrate.

[0171] The TBC battery further includes a first carrier collection layer on the first region A. The first carrier collection layer can include a diffusion layer on the first region A. The conduction type of the diffusion layer can be opposite to the conduction type of the semiconductor substrate 1. For example, for an n-type silicon substrate, the diffusion layer can be a p-type diffusion layer. For a p-type silicon substrate, the diffusion layer can be an n-type diffusion layer.

[0172] The TBC battery further includes a second carrier collection layer on the second region B. The second carrier collection layer can include a tunneling layer on the second region and a doped semiconductor layer on the tunneling layer. The conduction type of the doped semiconductor layer can be opposite to the conduction type of the diffusion layer and the same as the conduction type of the semiconductor substrate. For example, the tunneling layer can be a silicon oxide layer. For another example, for an n-type silicon substrate, the doped semiconductor layer can be an n-type doped polysilicon layer; for a p-type silicon substrate, the doped semiconductor layer can be a p-type doped polysilicon layer.

[0173] The TBC battery further includes a passivation layer on the first carrier collection layer, the texturing surface of the third region and the second carrier collection layer; an anti-reflection layer on the passivation layer; and a first electrode on the part of the anti-reflection layer located in the first region and in contact with the first carrier collection layer, and a second electrode on the part of the anti-reflection layer located in the second region and in contact with the second carrier collection layer.

[0174] Wherein the height difference between the surface of the part of the anti-reflection layer located in the first region away from the semiconductor substrate side and the surface of the part of the conductive layer located in the second region away from the semiconductor substrate side is less than or equal to 2 microns.

[0175] The passivation layer can be an aluminum oxide layer, and the anti-reflection layer can be a silicon nitride layer.

[0176] The present disclosure provides a solar cell and a preparation method thereof. By using a laser to pre-treat a silicon substrate, the height difference between the surface of the n-type functional region and the p-type functional region is within 2 microns, which can solve the problem of slurry loss and reduced screen life in the printing (metal or insulating ink, etc.) process due to the large height difference between the p-type and n-type functional regions in the related art. The solar cell and the preparation method thereof of the present disclosure can reduce the height of the n-type functional region, and use a laser with a certain wavelength and energy to pre-scan and ablate the functional region, forming an ablation melting area with partial element re-doping on the surface of the silicon substrate. This can further remove impurities (e.g., metals, bulk defects, etc.) in the substrate, and the similar interface height and relatively flat cell surface can reduce the amount of slurry used in the printing process and increase the service life of the screen, which can not only further improve the photoelectric conversion efficiency of the solar cell, but also reduce the manufacturing cost.

[0177] So far, the embodiments of the present disclosure have been described in detail. In order to avoid obscuring the concept of the present disclosure, some details known in the art are not described. Those skilled in the art can fully understand how to implement the technical solutions disclosed herein according to the above description.

[0178] Although some specific embodiments of the present disclosure have been described in detail through examples, those skilled in the art should understand that the above examples are only for illustration, not for limiting the scope of the present disclosure. Those skilled in the art should understand that the above embodiments can be modified or some technical features can be replaced equivalently without departing from the scope and spirit of the present disclosure. The scope of the present disclosure is defined by the appended claims.

Claims

1. A method for manufacturing a solar cell, comprising: Providing a semiconductor substrate, the semiconductor substrate including a first surface and a second surface opposite to the first surface, the second surface including a first region, a second region, and a third region between the first region and the second region; forming an isolation layer on the second region; removing the semiconductor substrate having a first thickness corresponding to the first region and the third region; removing the isolation layer; forming a first carrier collection layer on the entire surface of the second surface, and forming an insulating layer on the first carrier collection layer; removing the insulating layer, the first carrier collection layer, and the semiconductor substrate of the second thickness corresponding to the second region; forming a second carrier collection layer on the entire surface of the second surface; A portion of the second carrier collection layer on the first region and a portion of the insulating layer on the first region are selectively removed.

2. The manufacturing method according to claim 1, wherein Forming an isolation layer on the second region includes: performing a laser scanning ablation process on the second region using a first laser to form the isolation layer, wherein the isolation layer is an oxidized isolation layer; Preferably, the first laser is an infrared laser, a green laser or an ultraviolet laser, the pulse width of the first laser is at least one of nanoseconds or picoseconds, and the power of the first laser is 10W to 300W. Preferably, the semiconductor substrate is cleaned and polished to remove the semiconductor substrate having a first thickness corresponding to the first region and the third region; Preferably, the isolation layer is removed by cleaning with an acidic solution. Preferably, the first thickness is 2 micrometers to 5 micrometers.

3. The manufacturing method according to claim 1, wherein The first carrier collection layer includes: a tunneling layer on the first region and the third region; and a doped semiconductor layer on the tunneling layer; The second carrier collection layer comprises: an intrinsic silicon-containing film on the surface of the second region and on the insulating layer; and a doped silicon-containing film on the intrinsic silicon-containing film; wherein the conductivity type of the doped silicon-containing film is opposite to the conductivity type of the doped semiconductor layer; Preferably, the conductivity type of the doped silicon-containing film is opposite to that of the semiconductor substrate, and the conductivity type of the doped semiconductor layer is the same as that of the semiconductor substrate; Preferably, the semiconductor substrate is an n-type silicon substrate, the tunneling layer is a silicon oxide layer, the doped semiconductor layer is an n-type doped polysilicon layer, and the doped silicon-containing film is a p-type doped silicon film.

4. The manufacturing method according to claim 3, wherein: Forming a first carrier collection layer on the entire surface of the second surface, and forming an insulating layer on the first carrier collection layer, comprising: forming a tunneling layer on the second surface of the semiconductor substrate, forming a doped semiconductor layer on the tunneling layer, and forming an insulating layer on the doped semiconductor layer; Preferably, removing the insulating layer, the first carrier collection layer, and the semiconductor substrate of the second thickness corresponding to the second region includes: selectively performing a film opening process on the second region by using a second laser to remove a portion of the insulating layer on the second region and a portion of the doped semiconductor layer on the second region; Performing polishing and texturing on the first surface and the second surface of the semiconductor substrate so that the second areas of the first surface and the second surface form texturing surfaces; Preferably, the semiconductor substrate of the second thickness corresponding to the second region is removed, so that the surface of the remaining semiconductor substrate corresponding to the second region is flush with the insulating layer on the first region; Preferably, in the process of performing the texturing treatment on the first surface and the second area of ​​the second surface, the time for etching the first surface and the second area of ​​the second surface of the semiconductor substrate is 400 seconds to 600 seconds; Preferably, selectively removing a portion of the second carrier collection layer on the first region and a portion of the insulating layer on the first region comprises: selectively performing a laser scanning ablation process on the first region using a third laser to remove a portion of the intrinsic silicon-containing thin film on the first region, a portion of the doped silicon-containing thin film on the first region, and a portion of the insulating layer on the first region; Preferably, before selectively removing the portion of the second carrier collection layer on the first region and the portion of the insulating layer on the first region, a passivation layer is formed on the first surface of the semiconductor substrate, and an anti-reflection layer is formed on the passivation layer.

5. The manufacturing method according to claim 4, further comprising: forming a conductive layer on the exposed first carrier collection layer and the remaining second carrier collection layer; removing a portion of the conductive layer on at least a portion of the third region; forming a first electrode connected to the portion of the conductive layer located in the first region and a second electrode connected to the portion of the conductive layer located in the second region; Preferably, in the process of removing the portion of the conductive layer on at least a portion of the third region, the portion of the doped silicon-containing thin film on at least a portion of the third region is also removed; Preferably, in the process of removing the portion of the conductive layer on at least a portion of the third region, a portion of the conductive layer on a portion of the second region close to the third region is also removed, or a portion of the conductive layer and a portion of the doped silicon-containing film on a portion of the second region close to the third region are also removed; Preferably, removing the portion of the conductive layer on at least a portion of the third region comprises: ablating at least a portion of the third region using a fourth laser to remove a portion of the conductive layer on at least a portion of the third region; Preferably, the ablation width of the ablation process performed by using the fourth laser is in a range of 20 micrometers to 150 micrometers.

6. The manufacturing method according to claim 1, wherein: The first carrier collection layer includes: a diffusion layer on the first region; The second carrier collection layer includes: a tunneling layer on the second region and a doped semiconductor layer on the tunneling layer; the conductivity type of the diffusion layer is opposite to the conductivity type of the doped semiconductor layer; Preferably, the conductivity type of the diffusion layer is opposite to the conductivity type of the semiconductor substrate, and the conductivity type of the doped semiconductor layer is the same as the conductivity type of the semiconductor substrate; Preferably, the semiconductor substrate is an n-type silicon substrate, the tunneling layer is a silicon oxide layer, the diffusion layer is a p-type diffusion layer, and the doped semiconductor layer is an n-type doped polysilicon layer.

7. The manufacturing method according to claim 6, wherein: Forming a first carrier collection layer on the entire surface of the second surface, and forming an insulating layer on the first carrier collection layer includes: diffusing dopant atoms into the second surface of the semiconductor substrate to form the diffusion layer, and forming the insulating layer on the diffusion layer; Preferably, removing the insulating layer, the first carrier collection layer, and the semiconductor substrate of the second thickness corresponding to the second region includes: The insulating layer corresponding to the second region and the third region is removed by using a fifth laser, and then the semiconductor substrate having a second thickness corresponding to the second region and the third region is removed by a wet process to remove the diffusion layer.

8. The manufacturing method according to claim 6, further comprising: forming a passivation layer and an anti-reflection layer on the first carrier collection layer corresponding to the first region and the second carrier collection layer corresponding to the second region; A first electrode in contact with the first carrier collection layer and a second electrode in contact with the second carrier collection layer are formed on the anti-reflection layer.

9. A solar cell comprising: A semiconductor substrate comprising a first surface and a second surface opposite to the first surface, wherein the second surface comprises a first region, a second region, and a third region between the first region and the second region, wherein the first surface and the second region of the second surface have a textured surface; a first carrier collection layer on the first region and the third region; an insulating layer on a portion of the first carrier collecting layer located on the third region; a second carrier collection layer on the textured surface of the second region and the insulating layer; a conductive layer on a portion of the first carrier collection layer located on the first region and on a portion of the second carrier collection layer located on the second region, wherein the portion of the conductive layer located in the first region is spaced apart from the portion of the conductive layer located in the second region, and a height difference between a surface of the portion of the conductive layer located in the first region away from the semiconductor substrate, a surface of the portion of the conductive layer located in the second region away from the semiconductor substrate, and a surface of the portion of the second carrier collection layer located in the third region away from the semiconductor substrate is less than or equal to 2 micrometers; and A first electrode is connected to a portion of the conductive layer located in the first region, and a second electrode is connected to a portion of the conductive layer located in the second region.

10. A solar cell comprising: A semiconductor substrate comprising a first surface and a second surface opposite to the first surface, wherein the second surface comprises a first region, a second region, and a third region between the first region and the second region, wherein the first region and the third region of the first surface and the second surface have a textured surface; a first carrier collection layer on the first region; a second carrier collection layer on the second region; a passivation layer on the first carrier collection layer, on the textured surface of the third region, and on the second carrier collection layer; an anti-reflection layer on the passivation layer, wherein a height difference between a surface of a portion of the anti-reflection layer located in the first region and away from the semiconductor substrate and a surface of a portion of the conductive layer located in the second region and away from the semiconductor substrate is less than or equal to 2 micrometers; and A first electrode is located on a portion of the anti-reflection layer located in the first region and in contact with the first current collecting layer, and a second electrode is located on a portion of the anti-reflection layer located in the second region and in contact with the second current collecting layer.

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