TBC battery, preparation method thereof and photovoltaic module

Abstract

The invention discloses a TBC battery, a preparation method thereof and a photovoltaic module, and relates to the technical field of photovoltaics. According to the invention, gallium (Ga) is doped in the P-PolySi layer of the P-type doped region, the atomic radius of Si is about 0.117 nm, the atomic radius of Ga is about 0.135 nm, and the deformation quantity caused by Ga in Si is small. Ga has a high separation coefficient, low implicit solubility and a large atomic radius, so that the damage of the oxide layer is reduced, and the Voc (open voltage) is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of photovoltaic, in particular to a TBC cell, a preparation method thereof and a photovoltaic module. BACKGROUND

[0002] IBC (Interdigitated Back Contact) cell appeared in the 1970s, which respectively carries out local phosphorus and boron diffusion on the back of the cell to form P region and N region with interdigitated cross arrangement; the positive and negative electrodes of the IBC cell are both on the back of the cell, and the front surface is free of metal shading, which greatly improves the optical absorption of the cell. TOPCon (Tunnel Oxide Passivated Contact) cell is a new type of silicon solar cell proposed in 2013, which adopts a tunnel oxide layer and a doped polysilicon layer to form a passivated contact structure, effectively reducing the recombination rate of the silicon surface and the metal contact. At present, a new TBC cell combining TOPCon and IBC technologies has become a hot spot, and the process flow of the existing TBC cell is as follows: alkali polishing → tunnel oxide layer + PolySi deposition → doping and crystallization → back laser local removal of PSG (P region) → single-sided removal of front PSG → alkali texturing + cleaning → surface passivation → screen printing → sintering and metallization.

[0003] The P-PolySi of the P region of the TBC cell is doped with B, and since the B-doped PolySi, the B atoms have a certain influence on the interface oxide layer: (1) the separation coefficient of B is only 0.1-0.3, which leads to the aggregation of B in the oxide layer, the decay of the interface oxide layer, the increase of the interface state density and the distortion of the film layer; (2) the atomic radius of B is about 0.087 nm, and the atomic radius of silicon is about 0.117 nm, and the deformation caused by B in Si is large) which reduces the passivation performance of the structure and finally reduces the conversion efficiency of the cell.

[0004] In view of this, the present application is proposed. SUMMARY

[0005] The present application aims to provide a TBC cell, a preparation method thereof and a photovoltaic module, which aims to reduce the damage of B doping to the oxide layer and achieve the purpose of significantly reducing the contact resistivity and improving the conversion efficiency of the cell.

[0006] The present application is implemented as follows:

[0007] In a first aspect, the present application provides a TBC cell, comprising: an N-type crystalline silicon substrate, the N-type crystalline silicon substrate having a front surface and a back surface opposite to the front surface;

[0008] P-type doped regions and N-type doped regions are alternately and spaced apart on the back surface of the N-type crystalline silicon substrate;

[0009] In the P-type doped region, a first tunneling oxide layer, a P-PolySi layer and a P-region passivation layer are sequentially arranged from the surface of the N-type crystalline silicon substrate;

[0010] In the N-type doped region, a second tunneling oxide layer, an N-PolySi layer and an N-region passivation layer are sequentially arranged from the surface of the N-type crystalline silicon substrate;

[0011] The P-PolySi layer is doped with gallium.

[0012] In an optional embodiment, the doping concentration of gallium in the P-PolySi layer is 1E18cm -3 -10E18cm -3 , and the sheet resistance is 30Ω / sqr-60Ω / sqr.

[0013] Preferably, the thickness of the first tunneling oxide layer is 0.8nm-2.0nm.

[0014] The thickness of the P-PolySi layer is 100nm-300nm.

[0015] The thickness of the second tunneling oxide layer is 0.8nm-2.0nm.

[0016] The thickness of the N-PolySi layer is 100nm-300nm.

[0017] The thickness of the N-type crystalline silicon substrate is 100μm-120μm.

[0018] In an optional embodiment, the P-region passivation layer and the N-region passivation layer each include an aluminum oxide passivation layer and a silicon nitride passivation layer, and in the P-type doped region, the aluminum oxide passivation layer is located between the P-PolySi layer and the silicon nitride passivation layer; in the N-type doped region, the aluminum oxide passivation layer is located between the N-PolySi layer and the silicon nitride passivation layer.

[0019] Preferably, in the P-type doped region and the N-type doped region, the thickness of the aluminum oxide passivation layer is 5nm-10nm, and the thickness of the silicon nitride passivation layer is 100nm-150nm.

[0020] In an optional embodiment, an aluminum oxide passivation layer, a silicon nitride passivation layer and a silicon oxide passivation layer are sequentially arranged on the front surface of the N-type crystalline silicon substrate.

[0021] Preferably, the thickness of the aluminum oxide passivation layer is 5nm-10nm.

[0022] The thickness of the silicon nitride passivation layer is 100nm-150nm.

[0023] The thickness of the silicon oxide passivation layer is 100nm-150nm.

[0024] Preferably, the P-type doped region and the N-type doped region are separated by a trench, the area ratio of the P-type doped region and the N-type doped region is (0.8-1.2):1, and the width of the trench is 100-300 μm.

[0025] Preferably, a P-type electrode is arranged in the P-type doped region, and an N-type electrode is arranged in the N-type doped region.

[0026] In a second aspect, the present application provides a preparation method of the TBC cell in any one of the preceding embodiments, comprising:

[0027] A tunneling oxide layer and an i-PolySi layer are sequentially deposited on the back surface of the N-type crystalline silicon substrate;

[0028] An oxide layer containing gallium is formed on the surface of the i-PolySi layer, and nanosecond pulsed laser melting treatment is performed on the oxide layer to form boron doping, so as to form a P-PolySi layer and a BSG layer;

[0029] The P-type doped region and the N-type doped region are formed by using a patterning process and a deposition process.

[0030] In an optional embodiment, the oxide layer containing gallium is formed on the surface of the i-PolySi layer by using an atomic layer deposition method, the thickness of the oxide layer is 30-100 nm, the deposition temperature is 200-400℃, and the deposition pressure is 200-400 mtor.

[0031] Preferably, the formation process of the oxide layer comprises: a single introduction process, a first purification process, an oxidation process and a second purification process are performed at one time, and the number of repeated cycles is 50-150 times.

[0032] The introduction process comprises: using a gallium-containing precursor gas to perform deposition on the surface of the i-PolySi layer by using an atomic layer deposition method.

[0033] The first purification process comprises: using a purification gas to perform surface blowing to remove unreacted gallium-containing precursor gas and / or reaction by-products.

[0034] The oxidation process comprises: introducing an oxidizing agent to react with the surface-adsorbed gallium source and the PolySi, so as to form an oxide layer containing gallium.

[0035] The second purification process comprises: using a purification gas to perform surface blowing to remove unreacted oxidizing agent and / or reaction by-products.

[0036] Preferably, the gallium-containing precursor gas is selected from at least one of trimethyl gallium and triethyl gallium, and more preferably is trimethyl gallium; and the flow rate of the gallium-containing precursor gas is controlled to be 14-16 slm.

[0037] Preferably, the purging gas used in the primary purging process and the secondary purging process is selected from at least one of nitrogen and argon, and the flow rate of the purging gas is 4 slm-6 slm;

[0038] Preferably, the oxidizing agent is selected from at least one of oxygen, water vapor and ozone; more preferably, the oxidizing agent is ozone; and the flow rate of the oxidizing agent is 14 slm-16 slm.

[0039] Preferably, the time required for a single cycle is 30 s-50 s.

[0040] In an optional embodiment, the tunneling oxide layer and the i-PolySi layer are formed by a low pressure chemical vapor deposition method.

[0041] Preferably, the thickness of the tunneling oxide layer is 0.8 nm-2.0 nm, the deposition temperature is 500℃-650℃, and the deposition time is 6 min-20 min.

[0042] Preferably, the thickness of the i-PolySi layer is 100 nm-300 nm, the deposition temperature is 500℃-650℃, and the deposition time is 15 min-30 min.

[0043] In an optional embodiment, the process of forming the P-PolySi layer includes: pushing gallium in the oxide layer into the i-PolySi by laser to form the P-PolySi.

[0044] In the process, the laser power is controlled to be 30 w-100 w, and the slot depth is 30 nm-80 nm.

[0045] In an optional embodiment, the process of forming the P-type doped region and the N-type doped region by using a patterning process and a deposition process includes: sequentially performing a primary patterning process, polishing, depositing a tunneling oxide layer, depositing an N-PolySi layer and a PSG layer, annealing, a secondary patterning process, cleaning texturing, passivation processing and printing electrodes.

[0046] The primary patterning process includes: removing part of the BSG layer to form a patterned groove, the width of the patterned groove being equal to the sum of the width of the N-type doped region and the width of the two side trenches, the width of the patterned groove being 400 nm-600 nm, and the depth of the patterned groove being 30 nm-80 nm.

[0047] The polishing step includes: removing the P-PolySi layer and the tunneling oxide layer directly above the patterned groove, so that the depth of the patterned groove is increased to 200 nm-300 nm.

[0048] The step of depositing the tunnel oxide layer comprises: forming the second tunnel oxide layer by using a low pressure chemical vapor deposition method; preferably, the thickness of the second tunnel oxide layer is 0.8 nm-2.0 nm, the deposition temperature is 500 DEG C-800 DEG C, the deposition pressure is 730-760 torr, the deposition time is 1 h-2 h, and the oxygen flow rate during the deposition is 30 slm-50 slm;

[0049] The step of depositing the N-PolySi layer and the PSG layer comprises: forming the N-PolySi layer on the back surface of the silicon substrate by using a plasma enhanced chemical vapor deposition method, and simultaneously introducing a phosphorus source gas to deposit the PSG layer on the back surface of the silicon substrate; preferably, a mixed gas of SiH4 and H2 is introduced to deposit the N-PolySi layer on the back surface of the silicon substrate, and then PH3 gas is introduced to deposit the PSG layer on the back surface of the silicon substrate; more preferably, the flow rate ratio of SiH4, H2 and PH3 is 1:(1-3):(0.2-0.5); more preferably, the power for depositing the N-PolySi layer and the PSG layer is 12 kW-15 kW, the temperature is 400 DEG C-500 DEG C, and the pressure in the furnace tube is 2 torr-5 torr;

[0050] The step of annealing comprises: controlling the annealing temperature to be 800 DEG C-950 DEG C, and the annealing time to be 0.5 h-2 h;

[0051] The step of secondary patterning comprises: retaining the PSG layer in the N-type doped region on the back surface of the silicon substrate, and removing the PSG layer in the remaining region;

[0052] The step of cleaning and texturing comprises: retaining the N-PolySi layer in the N-type doped region on the back surface of the silicon substrate, removing the N-PolySi layer in the remaining region, and removing the BSG layer and the PSG layer on the back surface of the silicon substrate;

[0053] The step of passivation comprises: depositing an aluminum oxide passivation layer on both surfaces of the silicon substrate, depositing a silicon nitride passivation layer on the back surface, and sequentially depositing a silicon nitride passivation layer and a silicon oxide passivation layer on the front surface.

[0054] In a third aspect, the present application provides a photovoltaic module comprising the TBC cell according to any one of the preceding embodiments or prepared by the preparation method according to any one of the preceding embodiments.

[0055] The present application has the following beneficial effects: the present application dopes gallium (Ga) in the P-PolySi layer in the P-type doped region, the atomic radius of Si is about 0.117 nm, the atomic radius of Ga is about 0.135 nm, and the deformation caused by Ga in Si is small. Ga has a high separation coefficient, a low implicit solubility and a large atomic radius, which helps to reduce the damage to the oxide layer and improve Voc (open voltage).

[0056] In a preferred embodiment, nanosecond pulsed laser melting technology can be used in the preparation process to dope Ga in the polysilicon layer beyond the equilibrium solid solubility, significantly reduce the contact resistivity, improve the FF (fill factor), and ultimately improve the conversion efficiency of the cell sheet. BRIEF DESCRIPTION OF DRAWINGS

[0057] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some embodiments of the present application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0058] Figure 1 The structural diagram of the TBC cell provided for the embodiments of the present application;

[0059] Figure 2 The process flow diagram provided for the embodiments of the present application;

[0060] Figure 3 The intermediate process diagram of the preparation method provided for the embodiments of the present application.

[0061] Legend: 100-TBC cell; 001-P-type doped region; 002-N-type doped region; 003-trench; 110-N-type crystalline silicon substrate; 121-first tunneling oxide layer; 122-P-PolySi layer; 123-second tunneling oxide layer; 124-N-PolySi layer; 125-first aluminum oxide passivation layer; 126-first silicon nitride passivation layer; 131-second aluminum oxide passivation layer; 132-second silicon nitride passivation layer; 133-silicon oxide passivation layer; 141-P-region electrode; 142-N-region electrode. DETAILED DESCRIPTION

[0062] In order to make the purpose, technical solutions and advantages of the embodiments of the present application more clear, the technical solutions in the embodiments of the present application will be described clearly and completely. The specific conditions not mentioned in the embodiments are carried out according to the conventional conditions or the conditions recommended by the manufacturer. The reagents or instruments not mentioned by the manufacturer are all conventional products that can be purchased on the market.

[0063] The prior art B-doped PolySi can cause interface oxide layer attenuation, interface state density increase, and further cause film layer distortion due to the easy aggregation of B in the oxide layer. B doping can also reduce the passivation performance of the structure, and ultimately reduce the conversion efficiency of the cell. In view of the above problems existing in B doping, the inventors optimize the structure of the TBC cell, and introduce gallium (Ga) in the P-PolySi layer 122, which helps to reduce the damage to the oxide layer and improve Voc.

[0064] As Figure 1 shown, the embodiment of the present application provides a TBC battery 100, comprising: an N-type crystalline silicon substrate 110, the N-type crystalline silicon substrate 110 has a front surface and a back surface opposite to the front surface, and a P-type doped region 001 and an N-type doped region 002 are alternately and spacedly arranged on the back surface of the N-type crystalline silicon substrate 110.

[0065] In the P-type doped region 001, a first tunneling oxide layer 121, a P-PolySi layer 122 and a P region passivation layer are sequentially arranged from the surface of the N-type crystalline silicon substrate 110, the inventors optimize the preparation process of the P-PolySi layer 122, and gallium (Ga) is doped in the P-PolySi layer, the atomic radius of Si is about 0.117 nm, and the atomic radius of Ga is about 0.135 nm, the deformation caused by Ga in Si is small. Ga has high separation coefficient, low implicit solubility and large atomic radius, which helps to reduce the damage of the oxide layer and improve Voc.

[0066] In some embodiments, the doping concentration of gallium in the P-PolySi layer 122 is 1E18cm -3 -10E18cm -3 , and the square resistance is 30Ω / sqr-60Ω / sqr, by adjusting the doping concentration of gallium and the square resistance, the damage of B to the oxide layer is better reduced, and Voc is improved. Specifically, the doping concentration of gallium can be 1E18cm -3 , 3E18cm -3 , 5E18cm -3 , 8E18cm -3 , 10E18cm -3 , etc.; and the square resistance can be 30Ω / sqr, 40Ω / sqr, 50Ω / sqr, 60Ω / sqr, etc.

[0067] In the N-type doped region 002, a second tunneling oxide layer 123, an N-PolySi layer 124 and an N region passivation layer are sequentially arranged from the surface of the N-type crystalline silicon substrate 110, and the N-PolySi layer 124 can be doped or not doped with gallium.

[0068] In some embodiments, the thickness of the N-type crystalline silicon substrate 110 is 100-120 μm, the thickness of the first tunneling oxide layer 121 is 0.8-2.0 nm, and the thickness of the P-PolySi layer 122 is 100-300 nm; the thickness of the second tunneling oxide layer 123 is 0.8-2.0 nm, and the thickness of the N-PolySi layer 124 is 100-300 nm. The thickness of each layer is adjusted to improve the light-to-electricity conversion efficiency of the cell. Specifically, the thickness of the N-type crystalline silicon substrate 110 can be 100 μm, 105 μm, 110 μm, 115 μm, 120 μm, etc.; the thickness of the first tunneling oxide layer 121 can be 0.8 nm, 1.0 nm, 1.3 nm, 1.5 nm, 1.8 nm, 2.0 nm, etc.; the thickness of the P-PolySi layer 122 can be 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm, etc.; the thickness of the second tunneling oxide layer 123 can be 0.8 nm, 1.0 nm, 1.3 nm, 1.5 nm, 1.8 nm, 2.0 nm, etc.; and the thickness of the N-PolySi layer 124 can be 100 nm, 130 nm, 150 nm, 180 nm, 200 nm, 230 nm, 250 nm, 280 nm, 300 nm, etc.

[0069] Specifically, the "thickness" referred to in the embodiments of the present application is the thickness in the conventional understanding, Figure 1 Only the thickness direction and the width direction are shown in FIG. 1, and the length direction is not shown.

[0070] Further, the P-region passivation layer and the N-region passivation layer each include a first aluminum oxide passivation layer 125 and a first silicon nitride passivation layer 126. In the P-type doped region 001, the first aluminum oxide passivation layer 125 is located between the P-PolySi layer 122 and the first silicon nitride passivation layer 126; and in the N-type doped region 002, the first aluminum oxide passivation layer 125 is located between the N-PolySi layer 124 and the first silicon nitride passivation layer 126. By providing the first aluminum oxide passivation layer 125 and the first silicon nitride passivation layer 126 in the P-region passivation layer and the N-region passivation layer, the passivation effect is improved.

[0071] Further, in the P-type doped region 001 and the N-type doped region 002, the thickness of the first aluminum oxide passivation layer 125 is 5-10 nm (e.g., 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc.), and the thickness of the first silicon nitride passivation layer 126 is 100-150 nm (e.g., 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, etc.). The first aluminum oxide passivation layer 125 in the P-type doped region 001 and the N-type doped region 002 can be the same or different, and is preferably the same, which makes the preparation process more simple and easy to implement; similarly, the first silicon nitride passivation layer 126 in the P-type doped region 001 and the N-type doped region 002 can be the same or different, and is preferably the same.

[0072] In some embodiments, the front surface of the N-type crystalline silicon substrate 110 is sequentially provided with a second aluminum oxide passivation layer 131, a second silicon nitride passivation layer 132, and a silicon oxide passivation layer 133, the thickness of the second aluminum oxide passivation layer 131 is 5-10 nm (e.g., 5 nm, 6 nm, 7 nm, 8 nm, 9 nm, 10 nm, etc.), the thickness of the second silicon nitride passivation layer 132 is 100-150 nm (e.g., 100 nm, 110 nm, 120 nm, 130 nm, 140 nm, 150 nm, etc.), and the thickness of the silicon oxide passivation layer 133 is 10-30 nm (e.g., 10 nm, 15 nm, 20 nm, 25 nm, 30 nm, etc.). The second aluminum oxide passivation layer 131, the second silicon nitride passivation layer 132, and the silicon oxide passivation layer 133 are provided on the front surface of the N-type crystalline silicon substrate 110 and the thickness of each layer is controlled to achieve better passivation effect on the front surface, which is conducive to improving the photoelectric conversion efficiency of the battery.

[0073] Further, the P-type doped region 001 and the N-type doped region 002 are separated by a groove 003, the area ratio of the P-type doped region 001 and the N-type doped region 002 is (0.8-1.2):1 (e.g., 0.8:1, 0.9:1, 1.0:1, 1.1:1, 1.2:1, etc.), and the width of the groove 003 is 100-300 μm (e.g., 100 μm, 200 μm, 300 μm, etc.). The P-type doped region 001 and the N-type doped region 002 are separated by the groove 003, and by adjusting the ratio of the P-type doped region 001 and the N-type doped region 002 and the width of the groove 003, the positions of the two doped regions are more reasonable.

[0074] Specifically, the area of the groove 003 can be a flat surface or a textured surface. Figure 1The horizontal direction of the trench is the width direction, which is consistent with the width direction of the P-type doped region and the N-type doped region; the depth of the trench refers to the height difference of the end of the N-type doped region.

[0075] Further, the P-type doped region 001 is provided with a P-zone electrode 141, and the N-type doped region 002 is provided with an N-zone electrode 142; the composition and structure of the P-zone electrode 141 and the N-zone electrode 142 are not limited, and can be an existing electrode, such as a silver electrode.

[0076] The application also provides a preparation method of the TBC battery. Figure 2 A tunneling oxide layer and an i-PolySi layer are sequentially deposited on the back surface of the N-type crystalline silicon substrate 110; a gallium-containing oxide layer is formed on the surface of the i-PolySi layer, and nanosecond pulse laser melting treatment is performed on the oxide layer to form boron doping, so as to form a P-PolySi layer 122 and a BSG layer; finally, a P-type doped region 001 and an N-type doped region 002 are formed by using a patterning process and a deposition process.

[0077] It should be noted that, in the application, Ga is used as a substitutional dopant; the atomic radius of Si is about 0.117 nm, and the atomic radius of Ga is about 0.135 nm; the deformation amount caused by Ga in Si is small; Ga has a high segregation coefficient, a low implicit solubility and a large atomic radius, which helps to reduce the damage of the oxide layer and improve Voc; then, the nanosecond pulse laser melting technology is used to make Ga doped in the polysilicon layer beyond the equilibrium solid solubility, so as to significantly reduce the contact resistivity and improve FF, and finally improve the conversion efficiency of the battery piece.

[0078] In some embodiments, the tunneling oxide layer and the i-PolySi layer can be formed by a low pressure chemical vapor deposition (LPCVD) method, the thickness of the tunneling oxide layer is controlled to be 0.8 nm-2.0 nm, the deposition temperature is 500-650 ℃, and the deposition time is 6-20 min; the thickness of the i-PolySi layer is 100-300 nm, the deposition temperature is 500-650 ℃, and the deposition time is 15-30 min. Specifically, the thickness of the tunneling oxide layer can be 0.8 nm, 1.0 nm, 1.3 nm, 1.5 nm, 1.8 nm, 2.0 nm, etc., the deposition temperature of the tunneling oxide layer can be 500 ℃, 550 ℃, 600 ℃, 650 ℃, etc., and the deposition time of the tunneling oxide layer can be 6 min, 10 min, 13 min, 15 min, 18 min, 20 min, etc. The thickness of the i-PolySi layer can be 100 nm, 150 nm, 200 nm, 250 nm, 300 nm, etc., the deposition temperature of the i-PolySi layer can be 500 ℃, 550 ℃, 600 ℃, 650 ℃, etc., and the deposition time of the i-PolySi layer can be 15 min, 18 min, 20 min, 25 min, 30 min, etc. Before forming the tunneling oxide layer and the i-PolySi layer, the N-type crystalline silicon substrate 110 can be double polished to improve the bonding effect.

[0079] In some embodiments, the atomic layer deposition (ALD) method can be used to form a gallium-containing oxide layer on the surface of the i-PolySi layer, the thickness of the oxide layer is controlled to be 30-100 nm, the deposition temperature is 200-400 ℃, and the deposition pressure is 200-400 mtor. By adjusting the thickness of the oxide layer, the amount of gallium introduced is further adjusted, the damage to the oxide layer is further reduced, and the Voc is improved. Specifically, the thickness of the oxide layer can be 30 nm, 50 nm, 80 nm, 100 nm, etc., the deposition temperature can be 200 ℃, 250 ℃, 300 ℃, 350 ℃, 400 ℃, etc., and the deposition pressure can be 200 mtor, 250 mtor, 300 mtor, 350 mtor, 400 mtor, etc.

[0080] Further, the formation process of the oxide layer includes: a single introduction process, a primary purification process, an oxidation process, and a secondary purification process are performed once, and the number of repeated cycles is 50-150. That is, a single cycle includes four processes of the introduction process, the primary purification process, the oxidation process, and the secondary purification process, the time required for a single cycle is 30-50 s, and the cycle is repeated for 50-150 times until the Ga-doped oxide layer with the desired film thickness is formed.

[0081] The introduction process includes depositing gallium on the surface of the i-PolySi layer using an atomic layer deposition method using a gallium-containing precursor gas. The gallium-containing precursor gas can be introduced into an atomic layer deposition device for deposition. The gallium-containing precursor gas is selected from at least one of trimethylgallium (TMGa, Ga(CH3)3) and triethylgallium (TEGa, Ga(C2H5)3), and can be any one or more of the above, preferably trimethylgallium. During the deposition process, the flow rate of the gallium-containing precursor gas is controlled to be 14slm-16slm, such as 14slm, 15slm, 16slm, etc.

[0082] The primary purge process involves using a purge gas to purge the surface of the atomic layer deposition equipment chamber to remove unreacted gallium-containing precursor gas and / or reaction byproducts, thereby preventing the precursor gas and / or reaction byproducts from entering the oxidation process. The purge gas used in the primary purge process is selected from at least one of nitrogen and argon, and the purge gas may be any one or more of the aforementioned gases. The purge gas flow rate is 4 slm to 6 slm, such as 4 slm, 5 slm, or 6 slm.

[0083] The oxidation process involves introducing an oxidant into the chamber of the atomic layer deposition apparatus to react with the adsorbed gallium source and polysilicon on the surface, forming a gallium-containing oxide layer. The oxidant is selected from at least one of oxygen, water vapor, and ozone. The oxidant may be any one or more of these, with ozone being preferred due to its stronger oxidizing properties and more efficient reaction. The oxidant flow rate is 14-16 slm, for example, 14, 15, or 16 slm.

[0084] The secondary purge process involves using a purge gas to purge the surface of the atomic layer deposition apparatus chamber to remove unreacted oxidant and / or reaction byproducts, thereby preventing them from entering the next cycle. The purge gas used in the secondary purge process is selected from at least one of nitrogen and argon, and may be any one or more of these. The purge gas flow rate is 4 slm to 6 slm, such as 4 slm, 5 slm, or 6 slm.

[0085] In some embodiments, the process of forming the P-PolySi layer 122 includes: using a laser to push gallium in the oxide layer into the i-PolySi to form the P-PolySi; wherein the laser power is controlled to be 30W-100W (e.g., 30W, 50W, 80W, 100W, etc.), and the groove depth is 30nm-80nm (e.g., 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, etc.). Specifically, the laser emitting device can be a laser ablation device or a laser doping device.

[0086] Furthermore, the process of forming the P-type doped region 001 and the N-type doped region 002 by patterning and deposition process includes: performing a primary patterning process, polishing, depositing a tunneling oxide layer, depositing an N-PolySi layer and a PSG layer, annealing, a secondary patterning process, cleaning and texturing, passivation treatment and printing electrodes in sequence. The following describes each step in sequence:

[0087] A graphical processing process includes: Figure 3 On the basis of the BSG layer, part of the BSG layer is removed to form a patterned groove, the width of the patterned groove is equal to Figure 1 The sum of the widths of the middle N-type doped region 002 and the trenches 003 on both sides, the width of the patterned groove is 400nm-600nm, and the depth of the patterned groove is 30nm-80nm. Specifically, a picosecond laser can be used to remove part of the BSG layer. The width of the patterned groove can be 400nm, 450nm, 500nm, 550nm, 600nm, etc., and the depth of the patterned groove can be 30nm, 40nm, 50nm, 60nm, 70nm, 80nm, etc.

[0088] The polishing step includes: removing the P-PolySi layer and the tunneling oxide layer directly above the patterned groove, so that the depth of the patterned groove is increased to 200nm-300nm, in preparation for the subsequent formation of the N-type doped region 002.

[0089] The step of depositing a tunnel oxide layer includes forming a second tunnel oxide layer 123 using a low-pressure chemical vapor deposition method. LPCVD can be used to form the second tunnel oxide layer 123. All regions except the N region are removed by subsequent cleaning and texturing. The thickness of the formed second tunnel oxide layer 123 can be 0.8 nm to 2.0 nm, and the thickness can be 0.8 nm, 1.0 nm, 1.5 nm, 2.0 nm, etc. In a preferred embodiment, the deposition temperature of the LPCVD method is 500°C-800°C (such as 500°C, 600°C, 700°C, 800°C, etc.), the deposition pressure is 730-760torr (such as 730torr, 740torr, 750torr, 760torr, etc.), the deposition time is 1h-2h (such as 1.0h, 1.5h, 2.0h, etc.), and the oxygen flow rate during the deposition process is 30slm-50slm (such as 30slm, 40slm, 50slm, etc.). By adjusting the deposition process parameters, a uniform tunneling oxide layer is formed.

[0090] The step of depositing the N-PolySi layer 124 and the PSG layer includes: forming the N-PolySi layer on the back surface of the silicon substrate by using a plasma enhanced chemical vapor deposition method (PECVD method), and simultaneously introducing a phosphorus source gas to deposit the PSG layer on the back surface of the silicon substrate. In actual operation, a mixed gas of SiH4 and H2 is introduced to deposit the N-PolySi layer on the back surface of the silicon substrate, and then PH3 gas is introduced to deposit the PSG layer on the back surface of the silicon substrate. In a preferred embodiment, the flow rate ratio of SiH4, H2 and PH3 is controlled to be 1:(1-3):(0.2-0.5), the power for depositing the N-PolySi layer and the PSG layer is 12-15 kW, the temperature is 400-500°C, and the pressure in the furnace tube is 2-5 torr. By adjusting the raw material ratio and the deposition parameters, a uniform N-PolySi layer and PSG layer are formed. Specifically, the flow rate ratio of SiH4, H2 and PH3 can be 1:1.0:0.2, 1:2.0:0.3, 1:2.5:0.4, 1:3.0:0.5, etc., the deposition power can be 12 kW, 13 kW, 14 kW, 15 kW, etc., the deposition temperature can be 400°C, 430°C, 450°C, 480°C, 500°C, etc., and the pressure in the furnace tube can be 2 torr, 3 torr, 4 torr, 5 torr, etc.

[0091] The step of annealing includes: controlling the annealing temperature to be 800-950°C, and the annealing time to be 0.5-2 h. By annealing, the density of each layer can be increased, and the performance of the battery can be improved. Specifically, the annealing temperature can be 800°C, 850°C, 900°C, 950°C, etc., and the annealing time can be 0.5 h, 1.0 h, 1.5 h, 2.0 h, etc.

[0092] The step of secondary patterning processing includes: retaining the PSG layer of the N-type doped area 002 on the back surface of the silicon substrate, and removing the PSG layer in the remaining area. The pico-second laser can be used for removal, but is not limited thereto.

[0093] The step of cleaning and texturing includes: retaining the N-PolySi layer 124 of the N-type doped area 002 on the back surface of the silicon substrate, removing the N-PolySi layer in the remaining area, and removing the BSG layer and the PSG layer on the back surface of the silicon substrate.

[0094] The step of passivation processing includes: depositing aluminum oxide passivation layers (i.e., the first aluminum oxide passivation layer 125 and the second aluminum oxide passivation layer 131) on both surfaces of the silicon substrate, depositing the first silicon nitride passivation layer 126 on the back surface, sequentially depositing the second silicon nitride passivation layer 132 and the silicon oxide passivation layer 133 on the front surface, to form a battery structure of Figure 1 .

[0095] The embodiment of the present application provides a photovoltaic module, which comprises the TBC cell 100 provided by the embodiment of the present application, and can be prepared by using a traditional module interconnection method. Due to the improvement of the solar cell structure and process, the photoelectric conversion performance of the photovoltaic module is improved.

[0096] The features and performances of the present application are further described in detail in combination with the embodiments.

[0097] Embodiment 1

[0098] The embodiment also provides a preparation method of the TBC cell, as shown in the following steps. Figure 2 The preparation method of the TBC cell comprises the following steps.

[0099] (1) An N-type crystalline silicon substrate with a thickness of 100 μm, a length of 210 μm and a width of 210 μm is prepared and polished on both sides. A first tunneling oxide layer and an i-PolySi layer are formed on the back of the N-type crystalline silicon substrate by using an LPCVD method.

[0100] The deposition step of the first tunneling oxide layer is as follows: the N-type crystalline silicon substrate is placed in an LPCVD furnace tube, heated to a deposition temperature, and oxygen is introduced, the deposition temperature is controlled to be 550 ℃, the gas flow is 50 slm, the deposition time is 10 min, and the thickness of the first tunneling oxide layer is 1.5 nm.

[0101] The deposition step of the i-PolySi layer is as follows: the introduced gas is changed to silane, the flow is 900 sccm, the deposition temperature is controlled to be 600 ℃, the gas flow is 1500 sccm, the deposition time is 20 min, and the thickness of the i-PolySi layer is 200 nm.

[0102] (2) An ALD method is used to form a Ga-containing oxide layer on the surface of the i-PolySi layer, the thickness of the oxide layer is 80 nm, the deposition temperature is 300 ℃, the deposition pressure is 300 mtor, and the time for a single step of precursor introduction, purification, oxidation and purification is 40 s.

[0103] The specific steps are: repeating the steps of precursor introduction, purification, oxidation, and purification on the back surface after step (1) until the Ga-doped oxide layer with the desired film thickness is formed: ① introduce a gallium-containing precursor gas (trimethyl gallium), and the flow rate of the gallium-containing precursor gas is 15 slm; introduce for 10 s; ② the purification step specifically includes: introducing nitrogen to remove unreacted gallium-containing precursor gas and / or byproducts, and the flow rate of the nitrogen is 5 slm, and the introduction time is 10 s; ③ the oxidation step specifically includes: introducing an oxidizing agent (ozone) to react with the surface-adsorbed gallium source and PolySi to form a Ga-containing oxide layer, and the flow rate of the oxygen-containing gas is 15 slm, and the introduction time is 10 s; ④ the purification step specifically includes: introducing nitrogen to remove unreacted oxidizing agent and / or byproducts, and the flow rate of the nitrogen is 5 slm, and the introduction time is 10 s.

[0104] (3) The battery piece treated in step (2) is treated by nanosecond pulse laser melting technology, and the specific steps are as follows: the gallium in the oxide layer is pushed into the i-PolySi by laser to form a P-PolySi and a BSG layer; wherein the laser power is controlled to be 70 w, and the slot depth is 50 nm.

[0105] The P-PolySi layer and the BSG layer are formed in this step, and the doping concentration of gallium in the P-PolySi layer is 5E18 cm -3 , and the square resistance is 40 Ω / sqr.

[0106] (4) The N-type crystalline silicon substrate obtained in step (3) is sequentially subjected to a first patterning, polishing, deposition of a second tunneling oxide layer, deposition of an N-PolySi layer and a PSG layer, annealing, second patterning, cleaning and texturing, passivation treatment, and electrode printing to obtain the TBC battery.

[0107] ① The first patterning step specifically includes: removing part of the BSG layer on the back surface of the N-type crystalline silicon substrate obtained in step (3) by picosecond laser to form a patterned groove, and the depth of the patterned groove is 60 nm, and the width of the patterned groove is 500 nm.

[0108] ② The polishing step specifically includes: removing the P-PolySi layer and the second tunneling oxide layer directly above the patterned groove, and the depth of the patterned groove is increased to 250 nm.

[0109] ③ The step of depositing a second tunneling oxide layer specifically includes: depositing a second tunneling oxide layer on the region where the N-type doped region 002 is located on the back surface of the N-type crystalline silicon substrate by LPCVD method. The gas introduced in step (1) is used, and the thickness of the second tunneling oxide layer formed is 1.5 nm. The temperature of the LPCVD is 600°C, the pressure of the LPCVD is 740 torr, the time of the LPCVD is 2 h, and the flow rate of the oxygen gas in the LPCVD is 40 slm.

[0110] (4) The step of depositing the N-PolySi layer and the PSG layer is specifically as follows: PECVD is used to deposit on the back surface of the silicon substrate to form the N-PolySi layer, and phosphorus source gas is introduced to deposit on the back surface of the silicon substrate to form the PSG layer. The step of deposition is specifically as follows: a mixed gas of SiH4 and H2 is introduced to deposit on the back surface of the silicon substrate to form the PolySi layer; then PH3 gas is introduced to deposit on the back surface of the silicon substrate to form the PSG layer. The flow rate ratio of SiH4, H2 and PH3 is 1:2:0.3, the power for depositing the N-PolySi layer and the PSG layer is 13 kW, the temperature is 450°C, and the pressure in the furnace tube is 3 torr. The thickness of the N-PolySi layer is 200 nm.

[0111] (5) Annealing: the temperature for annealing is 850°C, and the time for annealing is 1.0 h.

[0112] (6) The step of secondary patterning is specifically as follows: the PSG layer in the N region on the back surface of the silicon substrate is reserved, and the picosecond laser is used to remove the PSG layer in the remaining region.

[0113] (7) The cleaning and texturing are specifically as follows: the N-PolySi layer in the N region on the back surface of the silicon substrate is reserved, the N-PolySi layer in the remaining region, and the BSG layer and the PSG layer on the back surface of the silicon substrate are removed.

[0114] (8) The passivation treatment includes the following steps in sequence: depositing an aluminum oxide passivation layer (4 nm in thickness) on both surfaces of the silicon substrate by PECVD, depositing a silicon nitride passivation layer (120 nm in thickness) on the back surface of the silicon substrate, depositing a silicon nitride passivation layer (120 nm in thickness) and a silicon oxide passivation layer (15 nm in thickness) on the front surface of the silicon substrate, and depositing a silicon nitride passivation layer (120 nm in thickness) on the back surface of the silicon substrate.

[0115] (9) The step of printing the electrode is as follows: commercially available silver paste is used as the raw material, and a patterned electrode is formed on the back surface of the cell by screen printing.

[0116] Example 2

[0117] The present embodiment also provides a preparation method of the TBC cell, as shown in Figure 2 The steps are as follows:

[0118] (1) An N-type crystalline silicon substrate with a thickness of 100 μm, a length of 210 μm and a width of 210 μm is prepared and is subjected to double-sided polishing. A first tunneling oxide layer and an i-PolySi layer are formed on the back surface of the double-sided polished N-type crystalline silicon substrate by LPCVD.

[0119] The deposition step of the first tunneling oxide layer is as follows: the N-type crystalline silicon substrate is placed in the LPCVD furnace tube, the temperature is raised to the deposition temperature, oxygen is introduced, the deposition temperature is controlled at 500℃, the gas flow is 50slm, the deposition time is 10min, and the thickness of the first tunneling oxide layer is 0.8nm.

[0120] The deposition step of the i-PolySi layer is as follows: the introduced gas is changed to silane, the flow is 900sccm, the deposition temperature is controlled at 500℃, the gas flow is 1500sccm, the deposition time is 20min, and the thickness of the i-PolySi layer is 100nm.

[0121] (2) An ALD method is used to form a Ga-containing oxide layer on the surface of the i-PolySi layer, the thickness of the oxide layer is 30nm, the deposition temperature is 200℃, the deposition pressure is 200mtor, and the time for each step of precursor introduction, purification, oxidation, and purification is 40s.

[0122] The specific steps are as follows: the back surface treated in step (1) is repeatedly cycled through the steps of precursor introduction, purification, oxidation, and purification until a Ga-doped oxide layer with the desired film thickness is formed: ① Introduce a gallium-containing precursor gas (trimethyl gallium), and the flow of the gallium-containing precursor gas is 14slm; introduce for 10s; ② The purification step specifically involves: introducing nitrogen gas to remove unreacted gallium-containing precursor gas and / or byproducts, and the flow of the nitrogen gas is 5slm, introduced for 10s; ③ The oxidation step specifically involves: introducing an oxidizing agent (ozone) to react with the surface-adsorbed gallium source and PolySi to form a Ga-containing oxide layer, and the flow of the oxygen-containing gas is 14slm, introduced for 10s; ④ The purification step specifically involves: introducing nitrogen gas to remove unreacted oxidizing agent and / or byproducts, and the flow of the nitrogen gas is 4slm, introduced for 10s.

[0123] (3) The cell piece treated in step (2) is treated by nanosecond pulse laser melting technology, and the specific steps are as follows: the gallium in the oxide layer is pushed into the i-PolySi by laser to form a P-PolySi layer and a BSG layer; wherein the laser power is controlled at 30w, and the slot depth is 30nm.

[0124] This step forms a P-PolySi layer and a BSG layer, and the doping concentration of gallium in the P-PolySi layer is 1E18cm -3 , and the square resistance is 160Ω / sqr.

[0125] (4) The N-type crystalline silicon substrate obtained in step (3) is sequentially subjected to one-time patterning, polishing, deposition of a second tunneling oxide layer, deposition of an N-PolySi layer and a PSG layer, annealing, second-time patterning, cleaning and texturing, passivation treatment, and electrode printing to obtain the TBC cell.

[0126] The step of the first patterning specifically comprises: removing part of the BSG layer on the back surface of the N-type crystalline silicon substrate obtained in step (3) by using a picosecond laser to form a patterned groove, wherein the depth of the patterned groove is 30 nm, and the width of the patterned groove is 400 nm.

[0127] The step of polishing specifically comprises: removing the P-PolySi layer and the second tunneling oxide layer above the patterned groove, and increasing the depth of the patterned groove to 200 nm.

[0128] The step of depositing the second tunneling oxide layer specifically comprises: depositing the second tunneling oxide layer on the region where the N-type doped region 002 is located on the back surface of the N-type crystalline silicon substrate by using an LPCVD method. The gas introduced is the same as that in step (1), and the thickness of the second tunneling oxide layer formed is 0.8 nm. The temperature of the LPCVD is 500 °C, the pressure of the LPCVD is 730 torr, the time of the LPCVD is 2 h, and the flow rate of the oxygen gas in the LPCVD is 30 slm.

[0129] The step of depositing the N-PolySi layer and the PSG layer specifically comprises: depositing the N-PolySi layer on the back surface of the silicon substrate by using a PECVD method, and simultaneously depositing the PSG layer on the back surface of the silicon substrate by introducing a phosphorus source gas. The step of depositing specifically comprises: depositing the PolySi layer on the back surface of the silicon substrate by introducing a mixed gas of SiH4 and H2, and then depositing the PSG layer on the back surface of the silicon substrate by introducing PH3 gas. The flow rate ratio of SiH4, H2 and PH3 is 1:1:0.2, the power for depositing the N-PolySi layer and the PSG layer is 12 kW, the temperature is 400 °C, and the pressure in the furnace tube is 2 torr. The thickness of the N-PolySi layer is 100 nm.

[0130] Step ⑤ annealing: the temperature of the annealing is 800 °C, and the time of the annealing is 2.0 h.

[0131] The step of the second patterning specifically comprises: retaining the PSG layer on the N region of the back surface of the silicon substrate, and removing the PSG layer in the remaining region by using a picosecond laser.

[0132] The step of cleaning and texturing specifically comprises: retaining the N-PolySi layer on the N region of the back surface of the silicon substrate, removing the N-PolySi layer in the remaining region, and removing the BSG layer and the PSG layer on the back surface of the silicon substrate.

[0133] The passivation treatment comprises the following steps in sequence: depositing an aluminum oxide passivation layer (5 nm thick) on both surfaces of the silicon substrate by using a PECVD method, depositing a silicon nitride passivation layer (100 nm thick) on the back surface of the silicon substrate, depositing a silicon nitride passivation layer (100 nm thick) on the front surface of the silicon substrate, and depositing a silicon oxide passivation layer (10 nm thick) on the front surface of the silicon substrate.

[0134] Step of printing electrode: using commercially available silver paste as raw material, forming patterned electrode on the back of the battery sheet by screen printing.

[0135] Example 3

[0136] The embodiment also provides a preparation method of the TBC battery, as shown in the figure, the steps are as follows: Figure 2

[0137] (1) Prepare an N-type crystalline silicon substrate with a thickness of 120 μm, a length of 210 μm, and a width of 210 μm, and polish both sides. A first tunneling oxide layer and an i-PolySi layer are formed on the back of the double-side polished N-type crystalline silicon substrate by using an LPCVD method.

[0138] The deposition step of the first tunneling oxide layer is as follows: place the N-type crystalline silicon substrate in an LPCVD furnace tube, heat to a deposition temperature, and introduce oxygen, control the deposition temperature to be 650 ℃, the gas flow to be 50 slm, and the deposition time to be 10 min, so that the first tunneling oxide layer with a thickness of 2.0 nm is formed.

[0139] The deposition step of the i-PolySi layer is as follows: change the introduced gas to silane, the flow to be 900 sccm, control the deposition temperature to be 650 ℃, the gas flow to be 1500 sccm, and the deposition time to be 20 min, so that the i-PolySi layer with a thickness of 300 nm is formed.

[0140] (2) Form a Ga-containing oxide layer on the surface of the i-PolySi layer by using an ALD method, the thickness of the oxide layer is 100 nm, the deposition temperature is 400 ℃, the deposition pressure is 400 mtor, and the time for each step of precursor introduction, purification, oxidation, and purification is 40 s;

[0141] The specific steps are as follows: repeatedly cycle the steps of precursor introduction, purification, oxidation, and purification on the back surface treated in step (1) until the Ga-doped oxide layer with the required film thickness is formed: ① introduce a gallium-containing precursor gas (trimethyl gallium), the flow of the gallium-containing precursor gas is 16 slm; introduce for 10 s; ② the purification step is specifically: introduce nitrogen to remove unreacted gallium-containing precursor gas and / or byproducts, the flow of the nitrogen is 5 slm, and the introduction time is 10 s; ③ the oxidation step is specifically: introduce an oxidizing agent (ozone) to react with the surface-adsorbed gallium source and PolySi to form a Ga-containing oxide layer, the flow of the oxygen-containing gas is 16 slm, and the introduction time is 10 s; ④ the purification step is specifically: introduce nitrogen to remove unreacted oxidizing agent and / or byproducts, the flow of the nitrogen is 6 slm, and the introduction time is 10 s.

[0142] ​(3) The battery piece treated in step (2) is treated by nanosecond pulse laser melting technology, and the specific steps are as follows: the gallium in the oxide layer is pushed into i-PolySi by laser to form P-PolySi and BSG layers; wherein the laser power is controlled to be 100w, and the slot depth is 80nm.

[0143] This step forms P-PolySi layer and BSG layer, and the doping concentration of gallium in P-PolySi layer is 10E18cm -3 , and the square resistance is 170Ω / sqr.

[0144] (4) The N-type crystalline silicon substrate obtained in step (3) is sequentially subjected to first patterning, polishing, deposition of a second tunneling oxide layer, deposition of an N-PolySi layer and a PSG layer, annealing, second patterning, cleaning and texturing, passivation treatment, and electrode printing to obtain the TBC battery.

[0145] ①The first patterning step specifically comprises: removing part of the BSG layer on the back surface of the N-type crystalline silicon substrate obtained in step (3) by picosecond laser to form a patterned groove, wherein the depth of the patterned groove is 80nm, and the width of the patterned groove is 600nm.

[0146] ②The polishing step specifically comprises: removing the P-PolySi layer and the second tunneling oxide layer directly above the patterned groove, and increasing the depth of the patterned groove to 300nm.

[0147] ③The step of depositing the second tunneling oxide layer specifically comprises: depositing on the region where the N-type doped region 002 is located on the back surface of the N-type crystalline silicon substrate by using the LPCVD method to form a second tunneling oxide layer. The gas is introduced according to step (1), and the thickness of the formed second tunneling oxide layer is 2.0nm. The temperature of the LPCVD is 800℃, the pressure of the LPCVD is 760torr, the time of the LPCVD is 1h, and the flow rate of oxygen gas in the LPCVD is 50slm.

[0148] ④The step of depositing the N-PolySi layer and the PSG layer specifically comprises: depositing on the back surface of the silicon substrate by using the PECVD method to form an N-PolySi layer, and simultaneously introducing a phosphorus source gas to deposit on the back surface of the silicon substrate to form a PSG layer. The deposition step specifically comprises: introducing a mixed gas of SiH4 and H2 to deposit on the back surface of the silicon substrate to form a PolySi layer; and then introducing PH3 gas to deposit on the back surface of the silicon substrate to form a PSG layer. The flow rate ratio of SiH4, H2 and PH3 is 1:3:0.5, the power for depositing the N-PolySi layer and the PSG layer is 15kW, the temperature is 500℃, and the pressure in the furnace tube is 5torr. The thickness of the N-PolySi layer is 300nm.

[0149] ⑤Annealing: annealing temperature is 950℃, annealing time is 0.5h.

[0150] ⑥The second patterning step is: keeping the N region PSG layer on the back of the silicon substrate, and removing the PSG layer in the remaining region by picosecond laser.

[0151] ⑦The cleaning and texturing step is: keeping the N-PolySi layer on the back of the N region of the silicon substrate, removing the N-PolySi layer in the remaining region, and removing the BSG layer and the PSG layer on the back of the silicon substrate.

[0152] ⑧The passivation treatment includes the following steps in sequence: depositing an aluminum oxide passivation layer (10nm thick) on both sides of the silicon substrate, depositing a silicon nitride passivation layer (150nm thick) on the back, depositing a silicon nitride passivation layer (150nm thick) on the front, and depositing a silicon oxide passivation layer (30nm thick), and the deposition method is PECVD.

[0153] ⑨The step of printing electrodes: using commercially available silver paste as raw material, forming a patterned electrode on the back of the cell by screen printing.

[0154] Example 4 differs from Example 1 only in that: the doping concentration of gallium in the P-PolySi layer in step (3) is 1E18cm -3 .

[0155] Example 5

[0156] Example 5 differs from Example 1 only in that: the doping concentration of gallium in the P-PolySi layer in step (3) is 10E18cm -3 .

[0157] Example 6

[0158] Example 6 differs from Example 1 only in that: the thickness of the P-PolySi layer is 180nm.

[0159] Example 7

[0160] Example 7 differs from Example 1 only in that: the thickness of the P-PolySi layer is 220nm.

[0161] Example 8

[0162] Example 8 differs from Example 1 only in that: the thickness of the Ga-containing oxide layer formed in step (2) is 60nm.

[0163] Example 9

[0164] Example 9 differs from Example 1 only in that: the thickness of the Ga-containing oxide layer formed in step (2) is 120nm.

[0165] Comparative Example 1

[0166] The difference from Example 1 is only that step (2) is not performed.

[0167] Comparative Example 2

[0168] The difference from Example 1 is only that the doping concentration of gallium in the P-PolySi layer in step (3) is 1E17 cm -3 .

[0169] Comparative Example 3

[0170] The difference from Example 1 is only that the doping concentration of gallium in the P-PolySi layer in step (3) is 1E20 cm -3 .

[0171] Test Example

[0172] The performance of the TBC cells prepared in the test examples and comparative examples was tested, and the results are shown in Table 1.

[0173] Test method and conditions: The samples were tested by Halm test.

[0174] Table 1 Performance of TBC cells prepared in the test examples and comparative examples

[0175] Group Conversion efficiency Example 1 26.96％ Example 2 26.91％ Example 3 26.88％ Example 4 26.87％ Example 5 26.83％ Example 6 26.78％ Example 7 26.80％ Example 8 26.74％ Example 9 26.76％ Comparative Example 1 26.01％ Comparative Example 2 26.22％ Comparative Example 3 26.18％

[0176] The preferred embodiments of the present application have been described above with reference to the drawings, but the present application is not limited to the above examples, and various changes and modifications can be made by those skilled in the art. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the scope of the present application.

Claims

1. A TBC battery, characterized in that: include: An N-type crystalline silicon substrate having a front surface and a back surface opposite to the front surface; P-type doped regions and N-type doped regions are alternately arranged on the back side of the N-type crystalline silicon substrate; In the P-type doped region, a first tunneling oxide layer, a P-PolySi layer and a P-region passivation layer are sequentially provided from the surface of the N-type crystalline silicon substrate; In the N-type doped region, a second tunneling oxide layer, an N-PolySi layer and an N-region passivation layer are sequentially provided from the surface of the N-type crystalline silicon substrate; The P-PolySi layer is doped with gallium.

2. The TBC battery according to claim 1, characterized in that The doping concentration of gallium in the P-PolySi layer is 1E18 cm -3 -10E18cm -3 , square resistance is 30Ω / sqr-60Ω / sqr; Preferably, the thickness of the first tunnel oxide layer is 0.8 nm-2.0 nm; The thickness of the P-PolySi layer is 100nm-300nm; The thickness of the second tunnel oxide layer is 0.8 nm to 2.0 nm; The thickness of the N-PolySi layer is 100nm-300nm; The thickness of the N-type crystalline silicon substrate is 100 μm-120 μm.

3. The TBC battery according to claim 1, characterized in that The P-region passivation layer and the N-region passivation layer both include an aluminum oxide passivation layer and a silicon nitride passivation layer. In the P-type doping region, the aluminum oxide passivation layer is located between the P-PolySi layer and the silicon nitride passivation layer; in the N-type doping region, the aluminum oxide passivation layer is located between the N-PolySi layer and the silicon nitride passivation layer. Preferably, in the P-type doping region and the N-type doping region, the thickness of the aluminum oxide passivation layer is 5 nm-10 nm, and the thickness of the silicon nitride passivation layer is 100 nm-150 nm.

4. The TBC battery according to claim 1, characterized in that An aluminum oxide passivation layer, a silicon nitride passivation layer, and a silicon oxide passivation layer are sequentially provided on the front surface of the N-type crystalline silicon substrate; Preferably, the thickness of the aluminum oxide passivation layer is 5 nm to 10 nm; The thickness of the silicon nitride passivation layer is 100nm-150nm; The thickness of the silicon oxide passivation layer is 10nm-30nm; Preferably, a trench is formed between the P-type doping region and the N-type doping region, the area ratio of the P-type doping region to the N-type doping region is (0.8-1.2):1, and the width of the trench is 100 μm-300 μm; Preferably, a P-region electrode is provided in the P-type doping region, and an N-region electrode is provided in the N-type doping region.

5. A method for preparing a TBC battery according to any one of claims 1 to 4, characterized in that: include: A tunneling oxide layer and an i-PolySi layer are sequentially deposited on the back side of an N-type crystalline silicon substrate; forming an oxide layer containing gallium on the surface of the i-PolySi layer, and performing nanosecond pulse laser melting on the oxide layer to form boron doping to form a P-PolySi layer and a BSG layer; The P-type doping region and the N-type doping region are formed by patterning and deposition processes.

6. The preparation method according to claim 5, characterized in that A gallium-containing oxide layer is formed on the surface of the i-PolySi layer by atomic layer deposition, wherein the thickness of the oxide layer is 30 nm to 100 nm, the deposition temperature is 200° C. to 400° C., and the deposition pressure is 200 mtor to 400 mtor. Preferably, the formation process of the oxide layer includes: a single introduction process, a primary purification process, an oxidation process and a secondary purification process, and the number of repeated cycles is 50-150 times; The introducing step includes: depositing gallium on the surface of the i-PolySi layer by atomic layer deposition using a gallium-containing precursor gas; The primary purification process includes: using a purification gas to purge the surface to remove unreacted gallium-containing precursor gas and / or reaction by-products; The oxidation process includes: introducing an oxidant to react with the gallium source and PolySi adsorbed on the surface to form a gallium-containing oxide layer; The secondary purification process includes: using a purification gas to purge the surface to remove unreacted oxidant and / or reaction by-products; Preferably, the gallium-containing precursor gas is selected from at least one of trimethyl gallium and triethyl gallium, more preferably trimethyl gallium; the flow rate of the gallium-containing precursor gas is controlled to be 14 slm-16 slm; Preferably, the purge gas used in the primary purge process and the secondary purge process is selected from at least one of nitrogen and argon, and the flow rate of the purge gas is 4slm-6slm; Preferably, the oxidant is selected from at least one of oxygen, water vapor and ozone; more preferably ozone; the flow rate of the oxidant is 14slm-16slm; Preferably, the time required for a single cycle is 30s-50s.

7. The preparation method according to claim 5, characterized in that forming the tunnel oxide layer and the i-PolySi layer by a low-pressure chemical vapor deposition method; Preferably, the thickness of the tunnel oxide layer is 0.8 nm to 2.0 nm, the deposition temperature is 500° C. to 650° C., and the deposition time is 6 min to 20 min; Preferably, the thickness of the i-PolySi layer is 100 nm-300 nm, the deposition temperature is 500° C.-650° C., and the deposition time is 15 min-30 min.

8. The preparation method according to claim 5, characterized in that The process of forming the P-PolySi layer includes: pushing gallium in the oxide layer into the i-PolySi by laser to form the P-PolySi; The laser power is controlled to be 30W-100W, and the groove depth is 30nm-80nm.

9. The preparation method according to claim 8, characterized in that The process of forming the P-type doped region and the N-type doped region by patterning and deposition process includes: sequentially performing a patterning process, polishing, depositing a tunneling oxide layer, depositing an N-PolySi layer and a PSG layer, annealing, a secondary patterning process, cleaning and texturing, passivation treatment and printing electrodes; The one-time patterning process includes: removing a portion of the BSG layer to form a patterned groove, wherein the width of the patterned groove is equal to the sum of the widths of the N-type doped region and the trenches on both sides, the width of the patterned groove is 400nm-600nm, and the depth of the patterned groove is 30nm-80nm; The polishing step includes: removing the P-PolySi layer and the tunneling oxide layer directly above the patterned groove to increase the depth of the patterned groove to 200nm-300nm; The step of depositing the tunnel oxide layer comprises: forming a second tunnel oxide layer by low pressure chemical vapor deposition; preferably, the thickness of the second tunnel oxide layer is 0.8 nm-2.0 nm, the deposition temperature is 500° C.-800° C., the deposition pressure is 730-760 Torr, the deposition time is 1 h-2 h, and the oxygen flow rate during the deposition process is 30 slm-50 slm; The steps of depositing the N-PolySi layer and the PSG layer include: forming an N-PolySi layer on the back of the silicon substrate by a plasma enhanced chemical vapor deposition method, and simultaneously introducing a phosphorus source gas to deposit a PSG layer on the back of the silicon substrate; preferably, introducing a mixed gas of SiH4 and H2 to deposit on the back of the silicon substrate to form an N-PolySi layer; then introducing PH3 gas to deposit on the back of the silicon substrate to form a PSG layer; more preferably, the flow ratio of SiH4, H2 and PH3 is 1:(1-3):(0.2-0.5); more preferably, the power for depositing the N-PolySi layer and the PSG layer is 12kW-15kW, the temperature is 400°C-500°C, and the pressure in the furnace tube is 2torr-5torr; The annealing step includes: controlling the annealing temperature to 800° C.-950° C. and the annealing time to 0.5 h-2 h; The secondary patterning step includes: retaining the PSG layer in the N-type doped area on the back of the silicon substrate and removing the PSG layer in the remaining area; The cleaning and texturing step includes: retaining the N-PolySi layer in the N-type doped area on the back of the silicon substrate, removing the N-PolySi layer in the remaining area, and removing the BSG layer and the PSG layer on the back of the silicon substrate; The passivation treatment steps include: depositing an aluminum oxide passivation layer on both sides of the silicon substrate, depositing a silicon nitride passivation layer on the back side, and sequentially depositing a silicon nitride passivation layer and a silicon oxide passivation layer on the front side.

10. A photovoltaic module, characterized in that: The invention comprises the TBC battery according to any one of claims 1 to 4 or the TBC battery prepared by the preparation method according to any one of claims 5 to 9.

Images