Identifying failure in device core

Abstract

An example system for testing a device under test (DUT) that includes a first core and a second core. The system includes parallel channels for connecting to a number of pins on the DUT. The channel is for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes time division multiplexed (TDM) data including contiguous data packets received over the channel from the DUT as part of the bitstream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. Circuitry associated with the channel is configured to compare the measurement data to expected data and determine a pass / fail state of the first core and the second core based on the comparison.

Description

TECHNICAL FIELD

[0001] This specification describes example implementations of systems and methods for identifying failures in device cores and for limiting storage of data from one or more of the device cores after a predetermined number of failures. BACKGROUND

[0002] A test system is configured to test the operation of an electronic device, referred to as a device under test (DUT). The test system can include test instruments to transmit signals including commands and data to the DUT for testing. The DUT responds with measurement data. The test system expects the measurement data to have particular values. If the measurement data has those values, the DUT passes the test. If the measurement data does not have those values, the DUT can fail the test.

[0003] The DUT can include more than one core. An example core can include a processing unit within the DUT. The test system can receive measurement data from multiple cores in the DUT and determine whether each core passes or fails the test. SUMMARY

[0004] An example system is for testing a device under test (DUT) that includes a first core and a second core. The system includes a parallel lane for connecting to a number of pins on the DUT. The lane is for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes time division multiplexed (TDM) data that includes successive data packets received from the DUT through the lane as part of a bit stream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. The data packets are sent in time slots, where each time slot corresponds to a parallel transmission of the bit stream over the number of pins. The TDM data repeats in a pattern on the lane every predetermined number of time slots. Circuitry associated with the lane is configured to compare the measurement data to expected data and determine pass / fail status of the first core and the second core based on the comparison. The system can individually or in combination include one or more of the following features.

[0005] The circuit system may be configured to determine a fail count for the first core and the second core based on the comparison, wherein the fail count indicates the number of times the first core or the second core failed the test. The circuit system may be configured to limit storage of subsequently received measurement data for the first core or the second core when the fail count exceeds a threshold number for the first core or the second core. Limiting storage may include ignoring subsequently received measurement data for the first core or the second core. Limiting storage may include not storing the subsequently received measurement data for the first core or the second core in the memory. Limiting storage may include limiting how many cycles in the first core or the second core that affect the subsequently received measurement data are stored in the memory for the number of fails for the first core or the second core. A cycle may include a time slot, and wherein a fail includes a single failure of the test.

[0006] The circuit system may be configured to output the fail count. At least some cycles of measurement data from the first core and the second core may be stored in a results log in the memory. The cycles may include time slots. The first number of bits and the second number of bits may each be different and cumulatively different from a number of pins such that portions of two different data packets are included in at least some of the time slots. The predetermined number of time slots may be greater than one time slot. The circuit system may be configured to determine a pass / fail status by accumulating pass / fail data associated with a time slot in a current data frame and previous pass / fail data for a time slot in a previous data frame. A data frame may include the predetermined number of time slots. The pass / fail data may be based on the accumulated status of the first core and the second core over multiple repeating patterns of time slots.

[0007] Determining the failure count may include individually counting the number of times the first core or the second core fails the test. Counting may include incrementing an address of a memory based on a time slot. Counting may include incrementing an address of a first memory based on a time slot, wherein the memory maps time slots to core numbers, and wherein the core number addresses a second memory.

[0008] The system may include a memory.The circuitry may be configured to store in the memory a fail count per core after a predetermined number of cycles of the measurement data.

[0009] An example system is for testing a DUT that includes a first core and a second core. The system includes a parallel lane for connecting to a number of pins on the DUT. The lane is for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes TDM data that includes successive data packets received from the DUT through the lane as part of a bitstream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. The data packets are transmitted in time slots, where each time slot corresponds to a parallel transmission of the bitstream over the number of pins. The TDM data repeats in a pattern on the lane every predetermined number of time slots. Circuitry associated with the lane is configured to compare the measurement data to expected data and determine a fail count per time slot based on the comparison. The fail count indicates a number of times the first core or the second core failed a test. The system can individually or in combination include one or more of the following features.

[0010] The circuitry can be configured to compare the measurement data to the expected data by aggregating pass / fail data associated with time slots in a current data frame and previous pass / fail data for time slots in a previous data frame. A data frame can include a predetermined number of time slots. The pass / fail data can be based on a cumulative state per time slot. The circuitry can be configured to limit storage of subsequently received measurement data for the first core or the second core when the fail count exceeds a threshold number. Limiting storage can include disregarding the subsequently received measurement data for the first core or the second core. Limiting storage can include not storing the subsequently received measurement data for the first core or the second core.

[0011] An example system is for testing a DUT that includes a first core and a second core. The system includes a parallel lane for connecting to a number of pins on the DUT. The lane is for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data. The measurement data includes TDM data that includes successive data packets received from the DUT through the lane as part of a bitstream. Each data packet includes a first number of bits from the first core and a second number of bits from the second core. The data packets are transmitted in time slots, where each time slot corresponds to a parallel transmission of the bitstream over the number of pins. The TDM data repeats in a pattern on the lane every predetermined number of time slots. Circuitry associated with the lane is configured to compare the measurement data to expected data and determine a fail count per time slot based on the comparison. The fail count indicates a number of times the first core or the second core failed a test. The system can individually or in combination include one or more of the following features.

[0012] Any two or more of the features described in this specification, including in the summary of the application part, can be combined to form specific embodiments of the application not specifically described in this specification.

[0013] At least part of the devices, systems, and methods described in this specification can be configured or controlled by executing instructions stored on one or more non-transitory machine- readable storage media on one or more processing devices. Examples of non-transitory machine- readable storage media include read-only memory, optical disk drives, memory disk drives, and random access memory. At least part of the devices, systems, and methods described in this specification can be configured or controlled using a computing system that includes one or more processing devices and memory storing instructions executable by the one or more processing devices to perform various control operations. The devices, systems, and methods described in this specification may, for example, be configured by design, construction, composition, arrangement, placement, programming, operation, activation, deactivation, and / or control.

[0014] The details of one or more implementations are set forth in the accompanying drawings and description below. Other features and advantages will be apparent from the description and drawings, and from the claims. BRIEF DESCRIPTION OF DRAWINGS

[0015] Figure 1 is a block diagram illustrating components of an example device under test (DUT) and components of an example test system on which example methods described herein can be performed.

[0016] Figure 2 is an example table illustrating how time-division multiplexed measurement data is sent over multiple pins and stored.

[0017] Figure 3 is an example version of the table of Figure 2 actual data values.

[0018] Figure 4 is an example table illustrating expected measurement data associated with a fail data.

[0019] Figure 5 is an example table illustrating pin masking / no storing of data.

[0020] Figure 6 is a flowchart illustrating an example method for not storing measurement data based on a DUT core that sent the measurement data.

[0021] Figure 7 includes two example tables showing cumulative fail counts for a first core of a DUT and a second core of the DUT.

[0022] Figure 8is an example table showing cores masked / not storing data per core.

[0023] Figure 9 Example circuitry for determining whether a core failed in any slot and for determining a fail count for a core is shown.

[0024] Figure 10 is a block diagram showing components of an example test system on which example methods described herein can be performed.

[0025] Like reference numbers in different drawings indicate like elements. DETAILED DESCRIPTION

[0026] Described herein are example implementations of a test system configured to test a device having multiple cores. Example cores include processing units, such as cores of a microprocessor, that are configured to read and execute computer program instructions. The multiple cores can concurrently and independently execute computer program instructions. A device under test (DUT) can include multiple cores that output time-division multiplexed (TDM) data. The TDM data includes measurement data based on tests performed on the cores during testing. For example, a test system can transmit test data to cores of a DUT and receive back TDM data from the cores of the DUT, the TDM data based on the DUT’s response to the test data. The TDM data can include bits output over multiple test channels, where a 1 or 0 represents a measurement based on a test performed on the DUT. The test system analyzes the TDM to identify failures in the cores.

[0027] The TDM data is stored in a capture memory on the test system or associated with the test system. The capture memory has a limited capacity. Example methods described herein can identify cores having more than a predetermined number of failures. Once those cores are identified, the methods treat the cores as failing the test. Thus, the methods can reduce the storage of TDM data from failing cores in the capture memory. This enables the capture memory to store more TDM data from cores that are not failing. Alternatively, reducing the need for storage can enable the test system to use a capture memory that is smaller in size than prior art systems.

[0028] Figure 1 is a block diagram showing an example DUT 10 having two cores 12, 13 and a test system 15 configured to test the DUT 10. The DUT 10 can be any type of electronic device, such as a microprocessor, microcontroller, etc. While the DUT 10 is shown as having two cores 12, 13, the DUT 10 can have any number of cores. The test system 15 can be any type of test system configured to test the DUT 10. Figure 1Two cores are shown, but the DUT can include more than two cores. The test system 15 interfaces with the DUT 10 through a set of four input pins 16 and four output pins 17 corresponding to four input channels and four output channels, respectively. Other DUTs can have fewer or more than four input pins and four output pins. The input pins 16 provide test data 20 from the test system 15 to the DUT 10, and the output pins 17 provide measurement data 21 from the DUT 10 to the test system 15. In this example, a communication bus 22 travels in the DUT 10 from the input pins 16 to the output pins 17 through each core 12, 13. As data is streamed on the bus 22, each core 12, 13 can receive test data 20 from the bus 22 and place measurement data 21 back on the bus 22.

[0029] Data is delivered to and received from the DUT 10 on a clock cycle basis. To this end, the test system 15 can include one or more clock circuits 23 to control timing. The test system 15 can provide test data to the DUT 10 as a burst of digital patterns. The burst of digital patterns can be measured over consecutively increasing clock cycles.

[0030] The test system 15 can test the cores 12, 13 in parallel. Generally, during testing of the DUT, the test system 15 transmits test data to the DUT in N-bit (N > 2) packets, where a first set of N-bits of each packet is associated with a first core, a next set of N-bits is associated with a second core, and so on. The test system 15 can receive measurement data from the DUT 10 according to the same timing and configuration as the test data was sent to the DUT 10. For example, during testing of the DUT, the DUT transmits measurement data to the test system in N-bit packets with the same timing as the test data, and where a first set of N-bits of each packet is associated with a first core, a next set of N-bits is associated with a second core, and so on.

[0031] Figure 2 An example is shown of how measurement data 21 about Figure 1 the five-bit packets and four pins is received from the DUT 10 at the test system 15. Measurement data 21 for different pin and packet configurations will differ from Figure 2 the measurement data shown. As Figure 2 shown, at each clock cycle 24, one bit of data from either core A 12 or core B 13 is passed from the DUT 10 to the test system 15 on each output pin.

[0032] As presented, at each clock cycle 24, Figure 1 and Figure 2In the example of DUT 10, during testing of DUT 10, DUT 10 transmits measurement data to test system 15 in five-bit packets, where the first three bits of each packet are associated with core A 12 and the last two bits are associated with core B 13. In this example, the five bits are labeled A0, A1, A2, B1, and B2, where "A" refers to bits received from core A 12 and "B" refers to bits received from core B 13. Each bit is also labeled with an index to indicate its packet number, so B1[8] indicates that it is the last bit associated with core B in packet number 8 (index).

[0033] In Figure 2 the bits associated with core A 12 are represented as horizontal lines in green shading and the bits associated with core B 13 are represented as vertical lines in blue shading. For the four pins, on the first clock period 24, only four of the five bits 25 of the data packet can be transferred. The last bit 26 of the data packet is transferred in the next clock period 28 along with three bits of a second data packet. The remaining two bits of the second packet are transferred on the third period, and so on. In Figure 2 a horizontal bar, such as bar 29, is present above the first bit of each data packet.

[0034] In this example, after five clock periods 30, the first bit 32 of the packet (A0 in this example) is again transferred on the first pin (Pinl). For this particular data packet and pin configuration, this happens every five clock periods.

[0035] This five-period period is referred to as a frame 31. Each period within the frame is referred to as a time slot 33. The time slots and periods include the same data, but time slots are counted within a frame and their count restarts with each new frame, while periods count up from zero without renumbering. In this regard, the clock periods, data frames, and time slots are numbered to show how the data is transferred over time. Data packets with different numbers of bits can have frames of different sizes.

[0036] Referring back to Figure 1, the test system 15 includes a time slot counter circuit 36 ​​that is configured to count clock cycles of the clock circuit 23 when outputting and receiving data. The time slot counter circuit 36 ​​restarts its count each time the time slot counter has counted the number of cycles within a frame. In this way, the time slot counter circuit 36 ​​maintains a time slot index for the measurement data. The time slot counter circuit 36 ​​can be configured to specify the clock cycles at which the time slot counter will start and restart. Therefore, when constructing a test pattern for testing the DUT, the test engineer can indicate the cycles at which the time slot counter will start and restart. Example implementations can instantiate a single shared time slot counter or multiple time slot counters for given test data (such as a digital pattern burst).

[0037] Because of the discrepancy between the number of pins and the number of bits per packet, each pin 17 does not pass data in the order in which the bits appear within the packet. Figure 2 In the example shown, Pin 1, for example, passes bits in the order A0, B1, B0, A2, and A1. Pin 2, for example, passes bits in the order A1, A0, B1, B0, and A2; and so on.

[0038] Figure 3 12 and DUT core B 13 received at the test system 15. Figure 1 and Figure 2 The four pins and five bit groups described are grouped as example measurements of 38 (actually 1s and 0s). Figure 3 In the example, the allocation of cycles, frames and time slots to the two cores is Figure 2 are the same.

[0039] Figure 4 The data expected to be received at the test system 15 from DUT core A 12 and DUT core B 13 is shown. Figures 1 to 3 The four pins and five-bit grouped data 40 are depicted, where "H" refers to "high" or "1" and L refers to "low" or "0". The expected data is predetermined. For example, the expected data may be the data that the DUT should provide if there are no errors in the core of the DUT (including the hardware and / or software in such core). The test system 15 includes a capture memory 29 or has access to an external memory for storing the received measurement data. The test system 15 may also include on-board memory 42 or have access to an external memory for storing the expected data. In this regard, the expected data may be received from the DUT manufacturer and pre-programmed into the test system.

[0040] In some cases, the measured data and the expected data do not match, indicating a failure or "fail" in Core A 12 and / or Core B 13 of the DUT 10. Figure 4 In the example, two examples that failed are marked as 49 and 51. For example, the measurement data 48 received from the DUT in time slot 3, frame 1 is Figure 3 is "0" (low) in Figure 4 In another example, the expected data 49 for this frame and time slot is "H". In another example, the measurement data 50 received from the DUT in time slot 1, frame 1 is Figure 3 is "1" (high) in Figure 4 The expected data 51 for that frame and time slot is "L". Such a difference between the received data and the expected data indicates a fail. The fail is shown in bold red.

[0041] The test system 15 may use the failed data (i.e., for example, Figure 2 The data that failed to pass (e.g., data sent by pins 48 and 50) is stored in capture memory 39 for subsequent failure diagnosis. Capture memory 39 is a limited resource, so not every failed cycle can be captured. Until now, test systems have limited the storage of measurement data in capture memory to a predetermined number of cycles captured by any one pin. Figure 5 The diagram of FIG. 1 shows a prior art storage in a capture memory including failed data cycles.

[0042] exist Figure 5 In the prior art example, the capture memory is limited to storing five failures per pin 47, regardless of which core the failures occur in. Accordingly, Pin 3 has reached its maximum storage of five failures 53 to 57 in the capture memory, while the other pins have not yet reached it. Therefore, failures 59 and 60 that occur on Pin 3 in cycles 11 and 18 (see Figure 4 ) is not stored in the capture memory. The fail 61 that occurs on Pin 4 in cycle 13 is stored because the fail count for that pin is only 2 during that cycle (with another fail for Pin 4 in frame 1, timeslot 3 62).

[0043] Limiting storage by the pin's cumulative miss count ensures that the pin's data does not consume all of the capture memory, but since the pin's data will be associated with multiple cores, this prior art storage scheme may hide failures on a particular core. For example, in cycle 18 ( Figure 4 ) is the only failure associated with core B in this example, but according to Figure 5 According to the prior art storage solution, the failed record is not stored in the capture memory.

[0044] The methods described herein, including method 65 and its variants, maintain a record of fails on a per-core basis. By maintaining a record of fails on a per-core basis, once a core has been deemed to fail, these methods are able to limit (e.g., eliminate) the storage of measurement data for the core, thereby increasing the memory storage capacity for data of other cores that have not been deemed to fail. Example method 65 can be performed on a test system, such as those described herein or other test systems not specifically described herein.

[0045] Reference is made to Figure 6 Example method 65 includes receiving (65a) measurement data, such as TDM data, from a plurality (e.g., two or more) of cores of a DUT. Method 65 can be performed once per cycle.

[0046] The measurement data is received at the test system from the DUT over a plurality of channels. The plurality of channels can be a plurality of pins, such as pins 17 of Figure 1 , where each pin corresponds to a channel. The measurement data includes consecutive data packets as part of a bitstream. In this example, the measurement data includes a first number of bits from one core, such as core A 12, and a second number of bits from a second core, such as core B 13; however, the measurement data can include data from three, four, five, or more cores sent in the manner described herein. As Figure 2 shown, the measurement data is sent in time slots, where each time slot corresponds to the parallel sending of a bit of the bitstream on a pin. The measurement data format (not necessarily the actual data itself, i.e., 1s and 0s) repeats on the channels in the same pattern every frame. For example, as Figure 2 shown, in frame 0 time slot 0, AO(0) is sent at Pinl, Al(0) is sent at Pinl, A2(0) is sent at Pin3, and BO(0) is sent at Pinl. Likewise, in frame 1 time slot 0, AO(4) is sent at Pinl, Al(4) is sent at Pinl, A2(4) is sent at Pin3, and BO(4) is sent at Pinl, and so on.

[0047] Method 65 compares (65b) the received measurement data to corresponding expected data to determine pass / fail information for the first core A 12 and the second core B 13. That is, the comparison of the expected data to the received measurement data identifies bits in the measurement data that correspond to a fail in a core of the DUT. Examples of such fails are described above Figure 4 . These fails can be stored in a table or other data structure in capture memory 39 (or memory 42) on the test system.

[0048] Method 65 determines (65c) a fail count for each core (core A 12 and core B 13 in this example) and stores the fail count for each core in a table or other data structure in memory on the test system. This can be done by identifying bits that indicate a failure on each pin and counting the number of times each pin fails. For example, if a fail is identified, a count associated with the current cycle of the core is incremented. Thus, the fail count for a core indicates the number of times that core failed a test by the test system.

[0049] Figure 7 An example of a per-pin, per-core cumulative fail count 68a for core A 12 and a per-core cumulative fail count 68b for core B 13 is shown. This information can be accumulated based on the comparisons (65b) described above and stored, for example, in a table or other data structure in capture memory 39 (or memory 42) on the test system.

[0050] Method 65 compares (65d) the fail count for each pin of each core to a predetermined threshold for the respective core. The threshold for each core can be set based on an acceptable number of failures for each core as deemed by the DUT manufacturer or test system operator. Different cores can have the same predetermined threshold or different predetermined thresholds. The predetermined threshold can be stored in memory 42 on the test system and retrieved by method 65 to perform the comparison.

[0051] If it is determined (65d) that the fail count is less than the predetermined threshold, the measurement data is stored (65f) in the capture memory. If it is determined (65e) that the fail count is greater than the predetermined threshold, the measurement data is not stored (65g) in the capture memory.

[0052] In some implementations, a user can specify that a core's fails should be masked. In such implementations, the measurement data need not be compared to expected data and the cycle is always considered to have passed. The fail count need not be incremented, so a predetermined threshold need not be implemented to achieve the masking. This can be useful when a core is known to cause a large number of failures and it is desired that none of these failures be recorded. In some implementations, masking includes ignoring all subsequently received measurement data for the core. The data is subsequently received from the perspective that it is not stored after the user specifies that the core's fails should be masked.

[0053] In this regard, a software routine or circuit system may provide a way to indicate that one or more cores should not participate in failure detection during a pattern burst. Masking can be achieved without modifying the pattern itself. For each channel, at each time slot index, the routine or circuit system indicates whether any failures detected on that channel will be masked. By indicating that all time slots associated with a given core of the DUT across all channels are to be masked, the test engineer can prevent failures from that area from affecting the failure results. If the test program has determined that one or more redundant DUT cores have failed, masking can remove those DUT cores from further testing. Masking all time slots associated with all but one core will limit the failure to that one DUT core, thereby enabling failure diagnosis in situations where some of the features described below are not available.

[0054] The repeating frame pattern indicated above facilitates masking of subsequently received measurement data. Knowing where data from core A appears and where data from core B appears enables masking of that data. For example, referring to Figure 2 If the data for core A is masked after frame "0" 31, the circuitry learns the pattern of core A in frame "1" 70, frame "2" 71, and so on, because the pattern repeats. Therefore, the data for those subsequent frames can be masked simply by identifying the time slots in which the data for those frames reside based on the pattern repetition, thereby reducing the amount of data stored in the capture memory.

[0055] In some implementations, the method 65 may be configured to generate a value indicating whether data for a time slot associated with a channel has not been stored based on the miss count of a core (such as core A 12 or core B 13). Data may be stored or not stored based on the value. In this regard, some time slots may have some of their data not stored in memory. For example, referring to Figure 2 , if time slot 3 of frame 3 is masked and core A 12 has exceeded its predetermined number of fails but core B 13 has not yet exceeded its predetermined number of fails, then only bits 74 and 75 of core A 12 are not stored in the capture memory during that cycle.

[0056] Figure 8 shows how to limit data storage in capture memory based on the fail count per core. Figure 8 The period indicated by H or L is stored in the capture memory. Figure 7 , in cycle 18, the failure count of Pin3 of core B is 77 ( Figure 7 ) is 1, and in cycle 11, the failure count of Pin3 of Core A is 79 ( Figure 7 ) is 6. Figure 8In the example of FIG. 7, the failure on core A at pin 3, cycle "11" 79 is not stored in the capture memory because the fail count 6 for core A has exceeded its predetermined fail threshold 5. However, the failure on pin 3, cycle "18" 77 is stored in the capture memory because it is associated with core B which has not exceeded its fail threshold 5.

[0057] The method 65 can be implemented using a test system that includes one or more processing devices and / or that includes solid state circuitry. Figure 9 An example solid state circuitry 80 that can be used to perform at least a portion of the method 65 is shown.

[0058] The circuitry 81 also includes two select values ("select") 86, 87 that can be set to configure the functionality of the circuit. The two selects 86, 87 can be configured to determine whether the circuitry 140 is "by slot" or "by core." That is, the selects 86, 87 configure the circuitry 140 to update when the core associated with the current cycle fails on a given cycle or when the slot associated with the current cycle fails on a given cycle. The circuitry 140 can be instantiated once per test channel, where Figure 9 The remaining circuitry of the circuitry 80 is common to all test channels.

[0059] The circuitry 80 includes a cycle counter 81 that receives a clock cycle, such as Figure 2 cycle 24, and increments by one on each clock cycle to produce a current cycle count. The circuitry 80 stores a preprogrammed constant frame length 82, which can be stored in a memory or register (not shown). The frame length 82 can be the number of slots in a frame, such as Figure 2 30. The cycle count and frame length are combined by logic 127 to produce a modulo slot value 84. The modulo slot value indicates the current slot of the received measurement data.

[0060] The memory 105 stores data that maps slots to cores. The modulo slot value 84 can be used to identify the core 129 in a lookup table in the memory 105 that maps to the current slot. The multiplexer 90 selects the index value 89 that corresponds to the identification of the slot (modulo 84) or the identification of the core (from the memory 105) based on the select 86. That is, if the select 86 indicates "by slot," the identification of the slot is used and if the select 86 indicates "by core," the identification of the core is used. On each clock cycle, the index value 89 that corresponds to the current slot or core can or can not change based on the selector 90 and the lookup table 105.

[0061] Memory 91 stores a lookup table or other data structure that includes pass / fail values that indicate whether at least one bit corresponding to the current time slot or the current core has passed or failed (i.e., whether the bit matches the expected data). More specifically, this data is based on previous measurements of the time slot or core from past data frames. For example, this data can be cumulative based on previous measurements of the time slot or core from past data frames, as described below.

[0062] Circuitry 80 also includes a comparison circuit 93 (such as one or more comparators) and a logic element 94 (such as an OR gate). On each clock cycle, circuitry 80 indexes memory 91 based on index value 89 to obtain an index value 100 from the memory for the current time slot or core. That is, the previous measurements of the current time slot or core based on past frames are obtained.

[0063] Additionally, on each clock cycle, comparison circuit 93 compares the measured data 95 in the current time slot and frame to the expected data 96 for that same time slot and frame to determine whether the measured data passes or fails on that clock cycle.

[0064] The comparison result 99 is combined (e.g., logically ORed) with the previous index value 100 from memory 91, and the result 101 is stored back into memory 91 as an updated (e.g., cumulative) value that indicates whether the core or time slot associated with the current cycle failed on any previous cycle associated with that core or time slot (e.g., in a previous frame). That is, the determined fail result at the current time slot or core location is ORed with the contents of the memory based on the index during each mode cycle. Thus, the memory contents reflect the cumulative fail status of all previous cycles of the time slot.

[0065] In some examples, memory 91 can have a size / capacity as deep as the maximum allowed number of time slots and as wide as the number of fail statuses collected in a single mode cycle.

[0066] Circuitry 80 outputs a Boolean status 103 that indicates the cumulative pass / fail value for the core or time slot. The cumulative pass value keeps track of whether the time slot or core has ever failed. The fail count keeps track of the number of times the time slot or core has failed. In tracking time slots, this information can be processed after a mode burst to determine which areas (e.g., which cores) of the DUT failed. That is, if a failure (repeat pattern of learn frames) is stored per time slot, the test system can identify which cores of the DUT failed based on the failures in the time slots.

[0067] Circuitry 80 also includes logic 104 and a memory 126 that stores a "fail count" indicative of the number of fails for the current bin or core. The fail count indicates the number of failures that have occurred for a given bin or core. On each cycle, an output 107 of memory 126 reflects the number of fails for the bin or core associated with the current cycle. Logic 104 is configured to use pass / fail comparison result 99 to determine whether the value 108 that will be used to update memory 126 will be equal to the current value 125 of that memory (e.g., whether there was no other fail on the bin or core) or whether that value 125 is to be incremented by one (e.g., whether there was a fail on the bin or core). If logic 104 determines based on comparison result 99 that the current cycle failed, then logic 104 increments current value 125 by one and outputs the resulting incremented value 108 to memory 126. Otherwise, the logic outputs current value 125 to memory 126. This fail count per bin or core can be used as described herein to limit the number of cycles stored in the capture memory per core or per bin.

[0068] Memory 126 can use a multiplexer 130 based on selection 87 and based on modulus bin value 85 and core identification 129 to index by "bin" or "core" in the same manner as described above with respect to multiplexer 90.

[0069] Figure 10 is a block diagram illustrating components of an example ATE 110 including test equipment / devices (also referred to as "testers") 110 and a control system 113. ATE 110 can be Figure 1 a particular implementation of test system 15 of

[0070] ATE 110 includes a test head 115 and a device interface board (DIB) 116 that is physically and electrically connected to test head 115. In this example, DIB 116 includes a circuit board that includes mechanical and electrical interfaces at locations 118. One or more DUTs 120, such as DUT 10 (of FIG. 1) Figure 1 ), are connected to each of those locations for testing by the ATE. DIB 116 can include connectors, conductive traces, conductive layers, and circuitry, etc., for routing signals between test instruments in test head 115, DUTs connected to DIB locations, and other circuitry in the ATE. Power (including voltage) can be delivered to DUTs connected to the DIB via one or more layers in the DIB.

[0071] The test head 115 includes a plurality of test instruments 121a-121n, each of which can be configured as needed to implement testing and / or other functions. While only four test instruments are shown, the ATE 110 can include any suitable number of test instruments, including one or more test instruments located outside of the test head 115. The test instruments can be hardware devices that can include one or more processing devices and / or other circuitry. The test instruments can be configured (e.g., programmed) to output commands to test a DUT held on a DIB. The commands to test the DUT can be or include instructions, signals, data, parameters, variables, test patterns, and / or any other information designed to elicit a response from the DUT.

[0072] In some implementations, the commands to test the DUT can be generated by executing or interpreting a test program received by the ATE 110 from an external system on the ATE 110. In an example, the test program can be or include a set of commands that are executed or interpreted by the ATE 110 to generate the commands used by the ATE to test the DUT.

[0073] One or more (e.g., all) of the test instruments can be configured to receive responses from the DUT to the commands transmitted to the DUT from the ATE. The responses include the measurement data described herein. The test instruments can be configured with one or more processing devices and / or Figure 1 and Figure 9 circuitry 132 to analyze the response signals to determine whether the DUT core passed or failed the test according to the method 65 and store the data in the capture memory 130 or the memory 131, and / or transmit the response signals to the control system 113 for analysis according to the method 65.

[0074] The test channels 123, including the pins 16 and 17, are configured between the test head and the DIB to enable communication between the DUT and the test instruments.

[0075] The control system 113 is configured (e.g., programmed) to communicate with the test instruments 121a-121n to direct and / or control testing of the DUTs. In some implementations, the communication 129 can be over a computer network or via a direct connection, such as a computer bus or optical media. In some implementations, the computer network can be or include a local area network (LAN) or a wide area network (WAN). The control system can be or include a computing system including one or more processing devices 124 (e.g., microprocessors) and memory 125 for storage. The control system 113 can be configured to provide test programs and / or commands to the test instruments 121a-121n in the test head, which use the test programs and / or commands to test the DUTs. The control system 113 can also be configured to receive DUT response signals (e.g., measurement data) from the test instruments and determine whether the DUT cores pass or fail the test according to the method 65 and store the data in the capture memory 151 or the memory 152.

[0076] All or portions of the test systems and methods described in this specification and their various modifications can be configured or controlled, at least in part, by one or more computers, such as the control system 113, using one or more computer programs tangibly embodied in one or more information carriers, such as one or more non-transitory machine-readable storage media. The computer programs can be written in any form of programming language, including compiled or interpreted languages, and the computer programs can be deployed in any form, including as a stand-alone program or as a module, component, subroutine, or other unit suitable for use in a computing environment. The computer programs can be deployed to be executed on one computer or on multiple computers at one site or distributed across multiple sites and interconnected by a network.

[0077] The acts associated with configuring or controlling the test systems and methods described herein can be performed by one or more programmable processors executing one or more computer programs to control or execute the operations described herein. All or part of the test systems and methods can be configured or controlled by special purpose logic circuitry, such as an FPGA (field programmable gate array) and / or an ASIC (application specific integrated circuit) or embedded microprocessors localized to instrument hardware.

[0078] Processors suitable for the execution of a computer program include, by way of example, both general and special purpose microprocessors, and any one or more processors of any kind of digital computer. Generally, a processor will receive instructions and data from a read-only memory or a random access memory or both. The elements of a computer include one or more processors for executing instructions and one or more memory devices for storing instructions and data. Generally, a computer also can include, or be operatively coupled to receive data from or transfer data to, or both, one or more machine-readable storage media, such as a mass storage device (e.g., a disk drive, a floppy disk, a magnetic tape, or a compact disk) for storing data. Non-transitory machine-readable storage media suitable for embodying computer program instructions and data include all forms of non-volatile memory, including by way of example semiconductor memory devices, such as EPROM (erasable programmable read-only memory), EEPROM (electrically erasable programmable read-only memory), and flash memory devices; magnetic disks such as internal hard disks or removable disks; magneto-optical disks; and CD-ROM (compact disk read-only memory) and DVD- ROM (digital versatile disk read-only memory).

[0079] The elements of the different implementations described can be combined to form other implementations not specifically described herein. Elements can be left out of the systems described without adversely affecting their operation or the operation of the systems. Further, various separate elements can be combined into one or more individual elements to perform the functions described in this specification.

[0080] Other implementations not specifically described herein are also within the scope of the following claims.

Claims

1. A system for testing a device under test (DUT), the DUT comprising a first core and a second core, the system comprising: parallel channels for connecting to a number of pins on the DUT, the channels for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data; wherein the measurement data comprises time division multiplexed (TDM) data, the time division multiplexed (TDM) data comprising successive data packets received from the DUT via the channel as part of a bit stream, wherein each data packet comprises a first number of bits from the first core and a second number of bits from the second core, wherein the data packets are transmitted in time slots, wherein each time slot corresponds to parallel transmission of the bit stream over the number of pins, and wherein the TDM data repeats in a pattern every predetermined number of time slots on the channel; and Circuitry is associated with the channel, the circuitry configured to compare the measured data with expected data and determine a pass / fail status for the first core and the second core based on the comparison. 2 . The system of claim 1 , wherein the circuitry is configured to determine a fail count for the first core and the second core based on the comparison, wherein the fail count indicates a number of times the first core or the second core has failed a test. 3 . The system of claim 2 , wherein the circuitry is configured to limit storage of subsequently received measurement data for the first core or the second core when the fail count exceeds a threshold number for the first core or the second core. The system of claim 3 , wherein limiting storage comprises ignoring the subsequently received measurement data of the first core or the second core. 5 . The system of claim 3 , wherein limiting storage comprises not storing the subsequently received measurement data of the first core or the second core in memory.

6. The system of claim 3 , wherein limiting storage comprises limiting a number of cycles in the first core or the second core that affect how many cycles of the subsequently received measurement data are stored in memory for a number of failures of the first core or the second core, wherein a cycle comprises a time slot, and wherein a failure comprises a single failure of the test. The method of claim 3 , wherein the circuitry is configured to output the fail count.

8. The system of claim 1 , further comprising a memory; At least some cycles of measurement data from the first core and the second core are stored in a results log in the memory, wherein a cycle includes a time slot.

9. The system of claim 1 , wherein the first number of bits and the second number of bits are each different and cumulatively different by a number of the pins such that portions of two different data packets are included in at least some of the time slots.

10. The system of claim 1, wherein the predetermined number of time slots is greater than one time slot.

11. The system of claim 1 , wherein the circuit system is configured to determine the pass / fail status by accumulating pass / fail data associated with a time slot in a current data frame and previous pass / fail data for time slots in a previous data frame, wherein a data frame includes the predetermined number of time slots.

12. The system of claim 11, wherein the pass / fail data is based on cumulative status of the first core and the second core over a plurality of repeating patterns of time slots.

13. The system of claim 2, wherein determining the fail count comprises individually counting the number of times the first core or the second core fails the test. The method of claim 13 , wherein counting comprises incrementing an address of a memory based on the time slot.

15. The method of claim 13, wherein counting comprises incrementing an address of a first memory based on a time slot, wherein the memory maps the time slot to a core number, and wherein the core number addresses a second memory.

16. The system of claim 1, further comprising a memory; Wherein the circuitry is configured to store in the memory a fail count per core after a predetermined number of cycles of the measurement data.

17. A system for testing a device under test (DUT), the DUT comprising a first core and a second core, the system comprising: parallel channels for connecting to a number of pins on the DUT, the channels for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data; wherein the measurement data comprises time division multiplexed (TDM) data, the time division multiplexed (TDM) data comprising successive data packets received from the DUT via the channel as part of a bit stream, wherein each data packet comprises a first number of bits from the first core and a second number of bits from the second core, wherein the data packets are transmitted in time slots, wherein each time slot corresponds to parallel transmission of the bit stream over the number of pins, and wherein the TDM data repeats in a pattern every predetermined number of time slots on the channel; and Circuitry is associated with the channel, the circuitry configured to compare the measured data with expected data and determine a fail count per time slot based on the comparison, wherein the fail count indicates a number of times the first core or the second core failed testing.

18. The system of claim 17 , wherein the circuit system is configured to compare the measured data with expected data by aggregating pass / fail data associated with a time slot in a current data frame and previous pass / fail data for a time slot in a previous data frame, wherein a data frame includes the predetermined number of time slots.

19. The system of claim 18, wherein the pass / fail data is based on cumulative status per time slot.

20. The system of claim 17, wherein the circuitry is configured to limit storage of subsequently received measurement data of the first core or the second core when the fail count exceeds a threshold number.

21. The system of claim 20, wherein limiting storage comprises ignoring the subsequently received measurement data of the first core or the second core.

22. The system of claim 20, wherein limiting storage comprises not storing the subsequently received measurement data of the first core or the second core.

23. A system for testing a device under test (DUT), the DUT comprising a first core and a second core, the system comprising: parallel channels for connecting to a number of pins on the DUT, the channels for transmitting test data to the DUT and for receiving measurement data from the DUT based on the test data; wherein the measurement data comprises time division multiplexed (TDM) data, the time division multiplexed (TDM) data comprising successive data packets received from the DUT via the channel as part of a bit stream, wherein each data packet comprises a first number of bits from the first core and a second number of bits from the second core, wherein the data packets are transmitted in time slots, wherein each time slot corresponds to parallel transmission of the bit stream over the number of pins, and wherein the TDM data repeats in a pattern every predetermined number of time slots on the channel; and Circuitry is associated with the channel, the circuitry configured to mask data from the first core or the second core based on user input, wherein masking includes ignoring or not storing in memory the data from the first core or the second core.

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