Current detection circuit, vehicle gauge level chip and vehicle motor drive control system

Abstract

The invention provides a current detection circuit, a chip and a control system, and relates to the technical field of power management chips, the circuit comprises a reference current generation circuit, a differential signal conversion circuit and a voltage conversion circuit; the reference current generating circuit is used for generating reference current; the differential signal conversion circuit is used for performing differential operation on the accessed first input voltage and second input voltage to obtain differential voltage and converting the differential voltage into differential current; the current acquisition module is also used for acquiring a first current based on the reference current, and the first current is the difference between the reference current and the differential current; and the voltage conversion circuit is used for converting the first current into a voltage signal to obtain an output voltage. By converting the differential voltage into the differential current, the limitation of the current detection circuit on the condition that the input signal is relatively high common-mode voltage can be overcome, and the problem that the output offset voltage is relatively high when the common-mode voltage of the input signal is relatively high is reduced, so that the output offset voltage is reduced.

Description

Technical Field

[0001] The present application relates to the technical field of power management chips, and in particular to a current detection circuit, an automotive-grade chip, and a vehicle motor drive control system. Background Art

[0002] In automotive motor (or motor) drive applications, an H-bridge is typically used to control the direction and speed of the motor. For example, the H-bridge controls the direction of the motor's current flow to achieve forward rotation, reverse rotation, or braking. The H-bridge consists of four switching tubes. The motor driver control chip controls the switching state of the four switching tubes in the H-bridge to control the direction of the motor's current flow. At the same time, the motor driver control chip also has various protection functions, such as overcurrent protection, overheating protection, and short-circuit protection, to ensure the safe operation of the motor. The bidirectional current flowing through the motor is crucial to the safety and reliability of the vehicle. By accurately measuring the current in the H-bridge through the motor driver control chip, the motor speed and torque can be precisely controlled or the position of the stepper motor can be precisely set.

[0003] See also Figure 1 , Figure 1 A schematic diagram of measuring the current in an H-bridge is provided for related technology, such as Figure 1 As shown, the H-bridge includes: a first switch tube T1, a second switch tube T2, a third switch tube T3, and a fourth switch tube T4, and the current flowing through the motor M is controlled by the H-bridge.

[0004] When measuring the current in the H-bridge, you can set the corresponding measuring resistors at different positions to achieve the current measurement, see Figure 1 Common locations for measuring current in an H-bridge include: high-side detection, phase-to-phase detection, and low-side detection. High-side detection involves setting a first measuring resistor RS1 on the high-side side (or power supply side) and detecting the voltage across the first measuring resistor RS1 to detect the current in the H-bridge. However, high-side detection can only detect current in one direction, that is, from the power supply voltage VS to the ground. Low-side detection involves setting a third measuring resistor RS3 on the low-side side (or ground side) and detecting the voltage across the third measuring resistor RS3 to detect the current in the H-bridge. However, low-side detection cannot detect current when a short circuit occurs in the H-bridge. Phase-to-phase detection involves setting a second measuring resistor RS2 on the connection path between the motor M and the H-bridge and detecting the voltage across the second measuring resistor RS2 to detect the current in the H-bridge. Phase-to-phase detection can directly detect the current flowing through the motor M and can achieve real-time current detection, with the most accurate measurement results.

[0005] The common-mode voltage across the second measuring resistor RS2 obtained by phase detection is sometimes ground GND and sometimes the power supply voltage VS, wherein the voltage of ground GND is 0V and the voltage range of the power supply voltage VS can be 8V to 60V. The voltage across the second measuring resistor RS2 obtained by phase detection is used as the input of the current detection circuit. Therefore, the current detection circuit needs to have an extremely wide range of input common mode. In addition, the current detection circuit usually needs to amplify the input signal and set the voltage gain of different gears, for example, 10V / V (i.e., 10 times amplification) or 40V / V (i.e., 40 times amplification). Summary of the Invention

[0006] The present application provides a current detection circuit, an automotive-grade chip, and a vehicle motor drive control system to reduce output offset voltage.

[0007] In a first aspect, the present application provides a current detection circuit, the current detection circuit comprising: a reference current generating circuit, a differential signal conversion circuit, and a voltage conversion circuit;

[0008] The differential signal conversion circuit is electrically connected to the reference current generating circuit and the voltage conversion circuit respectively;

[0009] The reference current generating circuit is used to generate a reference current;

[0010] The differential signal conversion circuit is configured to perform a differential operation on the first input voltage and the second input voltage to obtain a differential voltage, and convert the differential voltage into a differential current; and further configured to obtain a first current based on the reference current, wherein the first current is the difference between the reference current and the differential current;

[0011] The voltage conversion circuit is used to convert the first current into a voltage signal to obtain an output voltage.

[0012] In one possible design, the differential signal conversion circuit includes: a current mirror circuit and a differential input circuit;

[0013] The current mirror circuit is configured to replicate the reference current according to a preset ratio to obtain a second current and a third current, wherein the current value of the second current is equal to the current value of the reference current, and the current value of the third current is equal to twice the current value of the reference current;

[0014] The differential input circuit is configured to obtain the first current according to the differential current and based on the second current and the third current.

[0015] In one possible design, the reference current generating circuit includes: a first operational amplifier, a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor, and a second resistor;

[0016] The non-inverting input terminal of the first operational amplifier is used to receive a first reference voltage, the inverting input terminal of the first operational amplifier is electrically connected to the first terminal of the third transistor and the first terminal of the first resistor, and the output terminal of the first operational amplifier is electrically connected to the control terminal of the third transistor;

[0017] The second end of the first resistor is grounded;

[0018] a first end of the second resistor for connecting to a power supply voltage, a second end of the second resistor being electrically connected to the first end of the first transistor, a control end of the first transistor being electrically connected to the first end of the fourth transistor and the current mirror circuit, a second end of the first transistor being electrically connected to the control end of the fourth transistor and the first end of the second transistor, and a second end of the fourth transistor being grounded;

[0019] The second end of the second transistor is electrically connected to the control end of the second transistor, the current mirror circuit, and the second end of the third transistor respectively.

[0020] In one possible design, the current mirror circuit includes: a third resistor, a fourth resistor, a fifth transistor, a sixth transistor, a seventh transistor, and an eighth transistor;

[0021] a first end of the third resistor is electrically connected to the first end of the fourth resistor for receiving a power supply voltage, a second end of the third resistor is electrically connected to the first end of the fifth transistor, a control end of the fifth transistor is electrically connected to the control end of the first transistor and the control end of the seventh transistor, and a second end of the fifth transistor is electrically connected to the first end of the sixth transistor;

[0022] The control terminal of the sixth transistor is electrically connected to the control terminal of the second transistor and the control terminal of the eighth transistor respectively, and the second terminal of the sixth transistor is electrically connected to the differential input circuit;

[0023] The second end of the fourth resistor is electrically connected to the first end of the seventh transistor, the second end of the seventh transistor is electrically connected to the first end of the eighth transistor, and the second end of the eighth transistor is electrically connected to the differential input circuit.

[0024] In one possible design, the differential input circuit includes: a second operational amplifier, a fifth resistor, a sixth resistor, and a ninth transistor;

[0025] a non-inverting input terminal of the second operational amplifier electrically connected to the second terminal of the sixth transistor and the first terminal of the fifth resistor, respectively; an inverting input terminal of the second operational amplifier electrically connected to the first terminal of the sixth resistor and the first terminal of the ninth transistor, respectively; and an output terminal of the second operational amplifier electrically connected to the control terminal of the ninth transistor;

[0026] The second end of the ninth transistor is electrically connected to the second end of the eighth transistor and the voltage conversion circuit respectively;

[0027] The second end of the fifth resistor is used to connect to the first input voltage, and the second end of the sixth resistor is used to connect to the second input voltage.

[0028] In one possible design, the voltage conversion circuit includes: a tenth transistor, a seventh resistor, a third operational amplifier, a voltage source, and a load capacitor;

[0029] The first end of the tenth transistor is electrically connected to the second end of the ninth transistor, the control end of the tenth transistor is electrically connected to the second end of the voltage source, the first end of the voltage source is used to receive a power supply voltage, and the second end of the tenth transistor is electrically connected to the first end of the seventh resistor and the non-inverting input end of the third operational amplifier respectively;

[0030] The inverting input terminal of the third operational amplifier is used to receive the second reference voltage, and the output terminal of the third operational amplifier is electrically connected to the second end of the seventh resistor and the first end of the load capacitor, respectively, and serves as the output terminal of the current detection circuit, and is used to output the output voltage;

[0031] A second terminal of the load capacitor is grounded.

[0032] In one possible design, the current detection circuit further includes: a calibration resistor;

[0033] The first end of the calibration resistor is electrically connected to the first end of the third transistor, and the second end of the calibration resistor is electrically connected to the first end of the first resistor;

[0034] The calibration resistor is used to correct the output offset voltage of the current detection circuit.

[0035] In one possible design, the second operational amplifier includes a plurality of bipolar junction transistors.

[0036] In a second aspect, the present application provides an automotive-grade chip, comprising: a current detection circuit as described in the first aspect.

[0037] In a third aspect, the present application provides a vehicle motor drive control system, comprising: the automotive-grade chip as described in the second aspect.

[0038] Beneficial effects of the embodiments of the present application:

[0039] In an embodiment of the present application, a differential signal conversion circuit performs a differential operation on a first input voltage and a second input voltage to obtain a differential voltage, and converts the differential voltage into a differential current. This allows the differential voltage to be converted into a differential current, overcoming the current detection circuit's limitations when the input signal is a relatively high common-mode voltage. Based on a reference current generated by a reference current generation circuit, a first current is obtained, i.e., the difference between the reference current and the differential current. The first current is then converted into a voltage signal by a voltage conversion circuit to obtain an output voltage, thereby enabling detection of the current signal. By converting the differential voltage into a differential current, the current detection circuit's limitations when the input signal is a relatively high common-mode voltage are overcome, reducing the problem of a large output offset voltage caused by a high common-mode voltage of the input signal, thereby reducing the output offset voltage. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0041] Figure 1 A schematic diagram of measuring current in an H-bridge is provided for related art;

[0042] Figure 2 A structural diagram of a detection circuit provided for related technology;

[0043] Figure 3 A schematic diagram of the structure of a current detection circuit provided in an embodiment of the present application;

[0044] Figure 4 A schematic diagram of the structure of another current detection circuit provided in an embodiment of the present application. DETAILED DESCRIPTION

[0045] In this application, "at least one" refers to one or more, and "plurality" refers to two or more. "And / or" describes the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B can represent: the existence of A alone, the existence of A and B at the same time, and the existence of B alone, where A and B can be singular or plural. The character " / " generally indicates that the objects associated before and after are in an "or" relationship. "At least one of the following" or similar expressions refers to any combination of these items, including any combination of single or plural items. For example, at least one of a alone, b alone, or c alone can represent: a alone, b alone, c alone, a and b in combination, a and c in combination, b and c in combination, or a, b, and c in combination, where a, b, and c can be single or multiple. In addition, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance.

[0046] The directions or positional relationships indicated by terms such as "center", "longitudinal", "lateral", "up", "down", "left", "right", "front", and "back" are based on the directions or positional relationships shown in the accompanying drawings and are only for the convenience of describing the present application and simplifying the description. They do not indicate or imply that the device or element referred to must have a specific direction, be constructed and operated in a specific direction. Therefore, they should not be understood as limiting the present application.

[0047] The terms "connected" and "connect" should be interpreted broadly. For example, "connected" or "connected" in a circuit structure can refer not only to a physical connection, but also to an electrical connection or a signal connection. For example, it can be a direct connection, i.e., a physical connection, or an indirect connection through at least one intermediate component, as long as the circuit is interconnected. It can also refer to internal connectivity between two components. Signal connection can refer not only to signal connection through circuits but also to signal connection through media, such as radio waves. Those skilled in the art will understand the specific meanings of the above terms in this application on a case-by-case basis.

[0048] See also Figure 2 , Figure 2 A detection circuit provided in the related art is used to realize the current detection function. Figure 2As shown, the circuit includes a differential operational amplifier U and a matching resistor network. The matching resistor network includes a first matching resistor R01, a second matching resistor R02, a first gain resistor RGAIN1, and a second gain resistor RGAIN2. Typically, the resistance value of the first matching resistor R01 is set equal to the resistance value of the second matching resistor R02, and the resistance value of the first gain resistor RGAIN1 is set equal to the resistance value of the second gain resistor RGAIN2. The differential operational amplifier U amplifies the difference between the input voltages (i.e., SP and SN) to generate the output voltage Vout.

[0049] See also Figure 2 , considering the common mode rejection ratio, the output voltage Vout of this circuit is:

[0050]

[0051] In formula (1), Vcm is the common mode voltage of the input signal, CMRR total is the common-mode rejection ratio of the detection circuit, Vos is the offset voltage of the differential operational amplifier U, Rgain is the resistance value of the first gain resistor RGAIN1 or the resistance value of the second gain resistor RGAIN2, and r is the resistance value of the first matching resistor R01 or the resistance value of the second matching resistor R02.

[0052] The difference SP-SN between the input voltages (ie, SP and SN) is also called the differential mode voltage, and Vcm is the common mode voltage of the input signal, which can be expressed as (SP+SN) / 2.

[0053] Among them, the common mode rejection ratio CMRR of the detection circuit total The expression is:

[0054]

[0055] In formula (2), CMRR OPA is the common-mode rejection ratio of the differential operational amplifier U, K1 is the mismatch coefficient of the resistor, and G is the proportional coefficient of the resistor.

[0056] Common mode rejection ratio (CMRR) of the detection circuit total It is related to the common-mode rejection ratio of the differential operational amplifier U and the matching resistor network in the detection circuit.

[0057] Common-mode rejection ratio (CMRR) is a technical indicator that measures a differential operational amplifier's ability to reject common-mode signals and amplify differential-mode signals. A higher CMRR indicates greater common-mode signal rejection and better performance. CMRR is typically measured in decibels (dB).

[0058] A resistor's mismatch coefficient refers to the difference between its actual resistance and its nominal value, usually expressed as a percentage. A smaller mismatch coefficient indicates a closer resistance to its nominal value, resulting in higher precision. Resistor mismatch coefficient = (actual resistance - nominal resistance) / nominal resistance * 100%. For example, if a resistor with a nominal resistance of 100 ohms has an actual resistance of 98 ohms, the mismatch coefficient is (98-100) / 100 * 100% = -2%, indicating that the actual resistance is 2% less than the nominal value. A resistor's mismatch coefficient can be obtained by querying the resistor's relevant parameters.

[0059] Formula (2) takes into account the mismatch coefficients of each resistor in the matching resistor network. The actual resistance of a resistor may be greater or less than its nominal resistance. Assuming that the mismatch coefficients of the first matching resistor R01, the second matching resistor R02, the first gain resistor RGAIN1, and the second gain resistor RGAIN2 are all K1, if the resistance value of the first matching resistor R01 is set to R(1-K1) and the resistance value of the second matching resistor R02 is set to R(1+K1), the resistance value of the first gain resistor RGAIN1 is R(1+K1)*G, and the resistance value of the second gain resistor RGAIN2 is R(1-K1)*G, where R is the nominal resistance value of the resistor. In an example, the resistor mismatch coefficient K1 is 1%, the nominal resistance R is 100 ohms, and the resistor scale factor G is 10. Then, the resistance value of the first matching resistor R01 is 100*(1-1%), which is equal to 99 ohms. The resistance value of the second matching resistor R02 is 100*(1+1%), which is equal to 101 ohms. The resistance value of the first gain resistor RGAIN1 is 100*(1+1%)*10, which is equal to 1010 ohms. The resistance value of the second gain resistor RGAIN2 is 100*(1-1%)*10, which is equal to 990 ohms.

[0060] G is the resistor scaling factor, which is also equal to the gain of the detection circuit. It can be set according to the desired amplification factor, for example, G equals 10 or G equals 40. In actual project applications, the gain of the detection circuit is set by setting the ratio of the first gain resistor RGAIN1 to the first matching resistor R01 (or the ratio of the second gain resistor RGAIN2 to the second matching resistor R02). For example, if the first gain resistor RGAIN1 is 40K ohms and the first matching resistor R01 is 1K ohm, then G equals 40, and the gain of the detection circuit is 40.

[0061] The common-mode rejection ratio of the detection circuit in the related art is related to the common-mode rejection ratio of the differential operational amplifier U and the matching resistor network in the detection circuit. When the common-mode rejection ratio of the differential operational amplifier U is very high, if the mismatch coefficient of the resistors in the matching resistor network is very high, the common-mode rejection ratio of the detection circuit will be attenuated. When the common-mode voltage of the input signal is high, usually the common-mode voltage of the input signal can be as high as 60V. The higher common-mode voltage will cause the output voltage to deviate from the theoretical value, resulting in untimely overcurrent protection. For example, when the attenuation caused by the matching resistor network is 60dB, assuming the common-mode voltage is 30V, the output voltage error will be 30mV.

[0062] According to formula (1) and formula (2), when the common mode voltage Vcm of the input signal is the same, for different resistor proportional coefficients G, the common mode rejection ratio CMRR of the detection circuit is total The error in the output voltage Vout of the detection circuit will also be different.

[0063] In addition, in order to reduce the error of the output voltage, the related art usually needs to calibrate the output offset voltage of the detection circuit. The output offset voltage of the detection circuit in the related art is inconsistent under different common-mode voltages and different gains. The calibration scheme cannot meet the requirements of uniform calibration for different common-mode voltages and different gains, thereby reducing the accuracy within the application range.

[0064] In response to the problems in the detection circuit in the related art that the output offset voltage increases with the increase of common-mode voltage and changes with the change of gain, the output offset voltage is large when the common-mode voltage of the input signal is high, and the output offset voltage cannot be uniformly calibrated at different common-mode voltages and different gains, the embodiments of the present application provide a current detection circuit to reduce the output offset voltage.

[0065] See also Figure 3 , Figure 3 A current detection circuit is provided in an embodiment of the present application, such as Figure 3 As shown, the current detection circuit 1000 may include: a reference current generating circuit 100 , a differential signal conversion circuit 200 and a voltage conversion circuit 300 .

[0066] The differential signal conversion circuit 200 is electrically connected to the reference current generation circuit 100 and the voltage conversion circuit 300 , respectively.

[0067] The reference current generating circuit 100 is used to generate a reference current.

[0068] The differential signal conversion circuit 200 is used to perform a differential operation on the first input voltage SNSP and the second input voltage SNSN to obtain a differential voltage and convert the differential voltage into a differential current; it is also used to obtain a first current based on a reference current, wherein the first current is the difference between the reference current and the differential current.

[0069] The voltage conversion circuit 300 is configured to convert the first current into a voltage signal to obtain an output voltage VOUT.

[0070] The current detection circuit in the present application is used to detect the current size in the H-bridge, usually using phase-to-phase detection. The phase-to-phase detection can obtain a first input voltage SNSP and a second input voltage SNSN, and use them as input voltage signals of the current detection circuit.

[0071] The differential signal conversion circuit 200 performs a differential operation on the first input voltage SNSP and the second input voltage SNSN to obtain a differential voltage SNSP-SNSN, and converts the differential voltage SNSP-SNSN into a differential current Idiff.

[0072] The reference current generating circuit 100 generates a reference current I0. The differential signal converting circuit 200 can obtain a first current I1 according to the reference current I0. The first current I1 is the difference between the reference current I0 and the differential current Idiff, that is, I1 = I0 - Idiff.

[0073] The voltage conversion circuit is then used to convert the first current I1 into a voltage signal to obtain an output voltage VOUT.

[0074] In an embodiment of the present application, a differential signal conversion circuit performs a differential operation on a first input voltage and a second input voltage to obtain a differential voltage, and converts the differential voltage into a differential current. This allows the differential voltage to be converted into a differential current, overcoming the current detection circuit's limitations when the input signal is a relatively high common-mode voltage. Based on a reference current generated by a reference current generation circuit, a first current is obtained, i.e., the difference between the reference current and the differential current. The first current is then converted into a voltage signal by a voltage conversion circuit to obtain an output voltage, thereby enabling detection of the current signal. By converting the differential voltage into a differential current, the current detection circuit's limitations when the input signal is a relatively high common-mode voltage are overcome, reducing the problem of a large output offset voltage caused by a high common-mode voltage of the input signal, thereby reducing the output offset voltage.

[0075] In one possible embodiment, see Figure 3 The differential signal conversion circuit 200 may include: a current mirror circuit 201 and a differential input circuit 202 .

[0076] The current mirror circuit 201 is used to copy the reference current I0 according to a preset ratio to obtain a second current I2 and a third current I3, wherein the current value of the second current is equal to the current value of the reference current, and the current value of the third current is equal to twice the current value of the reference current.

[0077] The differential input circuit 202 is configured to obtain a first current according to the differential current, the second current, and the third current.

[0078] In the present application, a current mirror circuit is used to replicate the reference current I0 according to a preset ratio, wherein the preset ratio can be set according to design requirements. In one example, the preset ratio can be 1:2, that is, the reference current I0 is replicated at a ratio of 1:2 to obtain a second current I2 and a third current I3, wherein the current value of the second current I2 is equal to the current value of the reference current I0, and the current value of the third current I3 is equal to twice the current value of the reference current I0. In other words, the current mirror circuit can achieve a current relationship of 1:1:2 for the reference current I0: the second current I2: the third current I3.

[0079] Furthermore, the differential input circuit performs a differential operation on the connected first input voltage SNSP and the second input voltage SNSN to obtain a differential voltage SNSP-SNSN, and converts the differential voltage SNSP-SNSN into a differential current Idiff. Based on the second current I2 and the third current I3 generated by the current mirror circuit, and the relationship between the second current I2, the third current I3 and the reference current I0, the first current I1 is obtained, and the first current I1 is made to be the difference between the reference current I0 and the differential current Idiff, that is, I1=I0-Idiff.

[0080] In the embodiment of the present application, a current mirror circuit copies the reference current according to a preset ratio to obtain a second current and a third current. Based on the relationship between the second current, the third current, and the reference current, and the differential current, the first current can be obtained, thereby achieving the purpose of converting a differential voltage into a differential current.

[0081] In one possible embodiment, see Figure 3 The reference current generating circuit 100 may include: a first operational amplifier A, a first transistor Q1, a second transistor Q2, a third transistor Q3, a fourth transistor Q4, a first resistor R1, and a second resistor R2.

[0082] The non-inverting input terminal of the first operational amplifier A is used to access the first reference voltage K2*VREF, the inverting input terminal of the first operational amplifier A is electrically connected to the first end of the third transistor Q3 and the first end of the first resistor R1, and the output terminal of the first operational amplifier A is electrically connected to the control terminal of the third transistor Q3.

[0083] A second end of the first resistor R1 is grounded.

[0084] The first end of the second resistor R2 is used to connect to the power supply voltage CP_INT, the second end of the second resistor R2 is electrically connected to the first end of the first transistor Q1, the control end of the first transistor Q1 is electrically connected to the first end of the fourth transistor Q4 and the current mirror circuit 201, the second end of the first transistor Q1 is electrically connected to the control end of the fourth transistor Q4 and the first end of the second transistor Q2, and the second end of the fourth transistor Q4 is grounded.

[0085] The second end of the second transistor Q2 is electrically connected to the control end of the second transistor Q2 , the current mirror circuit 201 , and the second end of the third transistor Q3 , respectively.

[0086] In the present application, the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 may be bipolar transistors or field-effect transistors, etc. For example, when the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are bipolar transistors, their control terminals refer to the bases of the bipolar transistors, the first terminals may be the collectors or emitters of the bipolar transistors, and the corresponding second terminals may be the emitters or collectors of the bipolar transistors; when the first transistor Q1, the second transistor Q2, the third transistor Q3, and the fourth transistor Q4 are field-effect transistors, their control terminals refer to the gates of the field-effect transistors, the first terminals may be the drains or sources of the field-effect transistors, and the corresponding second terminals may be the sources or drains of the field-effect transistors.

[0087] In one possible embodiment, see Figure 3 The current mirror circuit 201 may include: a third resistor R3, a fourth resistor R4, a fifth transistor Q5, a sixth transistor Q6, a seventh transistor Q7, and an eighth transistor Q8.

[0088] A first end of the third resistor R3 is electrically connected to a first end of the fourth resistor R4 for receiving a power supply voltage CP_INT. A second end of the third resistor R3 is electrically connected to a first end of the fifth transistor Q5. A control end of the fifth transistor Q5 is electrically connected to the control end of the first transistor Q1 and the control end of the seventh transistor Q7, respectively. A second end of the fifth transistor Q5 is electrically connected to a first end of the sixth transistor Q6.

[0089] The control terminal of the sixth transistor Q6 is electrically connected to the control terminal of the second transistor Q2 and the control terminal of the eighth transistor Q8 , respectively. The second terminal of the sixth transistor Q6 is electrically connected to the differential input circuit 202 .

[0090] A second end of the fourth resistor R4 is electrically connected to a first end of the seventh transistor Q7 , a second end of the seventh transistor Q7 is electrically connected to a first end of the eighth transistor Q8 , and a second end of the eighth transistor Q8 is electrically connected to the differential input circuit 202 .

[0091] In the present application, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 may be bipolar transistors or field-effect transistors, etc. For example, when the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 are bipolar transistors, their control terminals refer to the bases of the bipolar transistors, their first terminals may be the collectors or emitters of the bipolar transistors, and their corresponding second terminals may be the emitters or collectors of the bipolar transistors; when the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, and the eighth transistor Q8 are field-effect transistors, their control terminals refer to the gates of the field-effect transistors, their first terminals may be the drains or sources of the field-effect transistors, and their corresponding second terminals may be the sources or drains of the field-effect transistors.

[0092] In one possible embodiment, see Figure 3 The differential input circuit 202 may include: a second operational amplifier B, a fifth resistor R5, a sixth resistor R6, and a ninth transistor Q9.

[0093] The non-inverting input terminal of the second operational amplifier B is electrically connected to the second end of the sixth transistor Q6 and the first end of the fifth resistor R5, respectively. The inverting input terminal of the second operational amplifier B is electrically connected to the first end of the sixth resistor R6 and the first end of the ninth transistor Q9, respectively. The output terminal of the second operational amplifier B is electrically connected to the control terminal of the ninth transistor Q9.

[0094] The second end of the ninth transistor Q9 is electrically connected to the second end of the eighth transistor Q8 and the voltage conversion circuit 300 .

[0095] A second end of the fifth resistor R5 is used to connect to the first input voltage SNSP, and a second end of the sixth resistor R6 is used to connect to the second input voltage SNSN.

[0096] The ninth transistor Q9 in the present application may be a bipolar transistor or a field-effect transistor, etc. For example, when the ninth transistor Q9 is a bipolar transistor, its control terminal refers to the base of the bipolar transistor, the first terminal may be the collector or emitter of the bipolar transistor, and the corresponding second terminal may be the emitter or collector of the bipolar transistor; when the ninth transistor Q9 is a field-effect transistor, its control terminal refers to the gate of the field-effect transistor, the first terminal may be the drain or source of the field-effect transistor, and the corresponding second terminal may be the source or drain of the field-effect transistor.

[0097] In one possible embodiment, see Figure 3 The voltage conversion circuit 300 may include: a tenth transistor Q10, a seventh resistor R7, a third operational amplifier C, a voltage source SM, and a load capacitor CL.

[0098] A first end of the tenth transistor Q10 is electrically connected to the second end of the ninth transistor Q9. The control end of the tenth transistor Q10 is electrically connected to the second end of the voltage source SM. The first end of the voltage source SM is used to receive the power supply voltage CP_INT. The second end of the tenth transistor Q10 is electrically connected to the first end of the seventh resistor R7 and the non-inverting input end of the third operational amplifier C, respectively.

[0099] The inverting input terminal of the third operational amplifier C is used to access the second reference voltage VREF. The output terminal of the third operational amplifier C is electrically connected to the second end of the seventh resistor R7 and the first end of the load capacitor CL, respectively, and serves as the output terminal of the current detection circuit 1000, for outputting the output voltage VOUT.

[0100] A second terminal of the load capacitor CL is grounded.

[0101] The tenth transistor Q10 in the present application may be a bipolar transistor or a field-effect transistor, etc. For example, when the tenth transistor Q10 is a bipolar transistor, its control terminal refers to the base of the bipolar transistor, the first terminal may be the collector or emitter of the bipolar transistor, and the corresponding second terminal may be the emitter or collector of the bipolar transistor; when the tenth transistor Q10 is a field-effect transistor, its control terminal refers to the gate of the field-effect transistor, the first terminal may be the drain or source of the field-effect transistor, and the corresponding second terminal may be the source or drain of the field-effect transistor.

[0102] See also Figure 3 In the embodiment of the present application, the tenth transistor Q10 and the voltage source SM form a switch circuit for providing a path between the differential signal conversion circuit 200 and the voltage conversion circuit 300. The voltage source SM is used to control the tenth transistor Q10 to be in a conductive state.

[0103] When the current detection circuit is a circuit module inside the motor drive control chip, see Figure 3 The power supply voltage CP_INT is the internal charge pump voltage, which is higher than the voltage of the power supply of the motor drive control chip. Generally, the voltage value of the power supply voltage CP_INT is 15V higher than the voltage of the power supply. For example, when the voltage range of the power supply of the motor drive control chip is 8V~60V, the voltage range of the power supply voltage CP_INT is 23V~75V.

[0104] See also Figure 3The operating principle of the current detection circuit in the embodiment of the present application is as follows: a reference current generating circuit generates a reference current I0. The magnitude of the reference current I0 is equal to the first reference voltage K2*VREF divided by the resistance value of the first resistor R1, that is, I0 = K2*VREF / r1, where r1 is the resistance value of the first resistor R1 and K2 is a coefficient. The value of K2 can be set according to the user's design requirements, for example, K2 = 0.5 or K2 = 0.2. VREF is the voltage value of the second reference voltage VREF.

[0105] The current mirror circuit then replicates the reference current I0 at a ratio of 1:2 to generate a second current I2 and a third current I3. The value of the second current I2 is equal to the value of the reference current I0 (i.e., I2 = I0), and the value of the third current I3 is twice the value of the reference current I0 (i.e., I3 = 2I0). The second current I2 is the current flowing through the branch formed by the third resistor R3, the fifth transistor Q5, the sixth transistor Q6, and the fifth resistor R5. The current in this branch is equal to the value of the reference current I0. The third current I3 is the current flowing through the branch formed by the fourth resistor R4, the seventh transistor Q7, and the eighth transistor Q8. The current in this branch is twice the reference current I0. The third current I3 flows into the branch formed by the voltage conversion circuit 300, the ninth transistor Q9, and the sixth resistor R6. Due to the virtual short of the second operational amplifier B, the current in the branch formed by the ninth transistor Q9 and the sixth resistor R6 is the sum of the differential current Idiff and the reference current I0 (i.e., Idiff+I0). Idiff = (SNSP-SNSN) / r5, where r5 is the resistance value of the fifth resistor R5. Generally, the resistance values ​​of the fifth resistor R5 and the sixth resistor R6 are equal. Therefore, Idiff = (SNSP-SNSN) / r6, where r6 is the resistance value of the sixth resistor R6. In actual project applications, the resistance values ​​of the third resistor R3 and the fourth resistor R4 can be set to achieve the function of replicating the reference current according to a preset ratio.

[0106] The final current flowing into the voltage conversion circuit 300 is equal to the difference between the third current I3 and the current in the branch formed by the ninth transistor Q9 and the sixth resistor R6. That is, the first current I1 is equal to the difference between the third current I3 and the current in the branch formed by the ninth transistor Q9 and the sixth resistor R6. Therefore, I1 = 2I0 - (Idiff + I0) = I0 - Idiff. Since I0 = K2 * VREF / r1, I1 = K2 * VREF / r1 - (SNSP - SNSN) / r5.

[0107] The voltage conversion circuit is configured to convert the first current I1 into a voltage signal to generate an output voltage VOUT. The reference voltage of the third operational amplifier C is the second reference voltage VREF. Therefore, the output voltage VOUT = VREF - I1 * r7, where r7 is the resistance value of the seventh resistor R7. Generally, the resistance value of the seventh resistor R7 is equal to that of the first resistor R1.

[0108] In summary, ideally, the output voltage expression of the current detection circuit is:

[0109] VOUT=(1-K2)*VREF+(SNSP-SNSN)*r7 / r5, where r7 / r5 is the gain of the current detection circuit in this application.

[0110] The above ideal situation refers to the situation where factors such as the mismatch coefficient of the resistors in the current detection circuit, the offset voltage of the operational amplifier, and the matching error of the transistors are not taken into consideration. That is, the resistors are perfectly matched, the operational amplifier is an ideal operational amplifier, and the transistors have no matching error.

[0111] Taking into account the offset voltages of the first operational amplifier A, the second operational amplifier B, and the third operational amplifier C, the matching errors of all transistors, and the mismatch coefficients of all resistors, the output voltage expression of the current detection circuit is:

[0112]

[0113] In formula (3), K is the sum of the matching error of the current mirror part and the matching error of the resistor part, wherein the matching error of the current mirror part includes: the error caused by the current replication of the first transistor Q1, the second transistor Q2, the third transistor Q3, the fourth transistor Q4, the fifth transistor Q5, the sixth transistor Q6, the seventh transistor Q7, the eighth transistor Q8 and the ninth transistor Q9; the matching error of the resistor part includes: the error caused by the mismatch coefficient of the first resistor R1, the fifth resistor R5, the sixth resistor R6 and the seventh resistor R7.

[0114] In formula (3), Vdiff represents the differential voltage SNSP-SNSN, error represents the gain error, VosA represents the offset voltage of the first operational amplifier A, VosB represents the offset voltage of the second operational amplifier B, and VosC represents the offset voltage of the third operational amplifier C.

[0115] As can be seen from formula (3), the output voltage error of the current detection circuit is independent of the common-mode voltage, and will not produce a large output offset voltage when the common-mode voltage of the input signal is high. Furthermore, the current detection circuit has a small relationship with the gain, and will not produce a large output offset voltage as the gain changes. Therefore, the current detection circuit provided in the embodiment of the present application can reduce the output offset voltage, and the output voltage error of the current detection circuit is very small under different common-mode voltages and different gains. The current detection circuit in the present application has a high common-mode rejection ratio.

[0116] Based on the above embodiments, the present application further provides an offset calibration solution for correcting the output offset voltage to further improve the accuracy of the output voltage.

[0117] In one possible embodiment, see Figure 4 , Figure 4 Another current detection circuit diagram provided in the embodiment of the present application is as follows: Figure 4 As mentioned above, the current detection circuit 1000 may further include: a calibration resistor Rtrim.

[0118] A first end of the calibration resistor Rtrim is electrically connected to the first end of the third transistor Q3 , and a second end of the calibration resistor Rtrim is electrically connected to the first end of the first resistor R1 .

[0119] The calibration resistor Rtrim is used to correct the output offset voltage of the current detection circuit.

[0120] The offset calibration solution in the embodiment of the present application is to introduce a calibration resistor Rtrim between the first end of the third transistor Q3 and the first end of the first resistor R1. The calibration voltage Vtrim introduced by the calibration resistor Rtrim can be expressed as:

[0121]

[0122] In formula (4), r1 is the resistance value of the first resistor R1, and rtrim is the resistance value of the calibration resistor Rtrim.

[0123] According to formula (4), the calibration voltage Vtrim introduced by the calibration resistor Rtrim changes with the change of the second reference voltage VREF. According to formula (3), the term K2*VREF*K, which is the largest proportion of the output voltage of the current detection circuit to the output offset voltage, changes with the change of the second reference voltage VREF.

[0124] Therefore, if you set Then K2*VREF*K=Vtrim. The calibration voltage Vtrim introduced by the calibration resistor Rtrim can offset the output offset voltage K2*VREF*K, which accounts for the largest proportion, thereby reducing the output offset voltage and making the output voltage error of the current detection circuit very small.

[0125] In an embodiment of the present application, by introducing a calibration resistor Rtrim between the first end of the third transistor Q3 and the first end of the first resistor R1, the output offset voltage can be corrected without affecting the gain of the current detection circuit, thereby achieving the purpose of uniformly calibrating different common-mode voltages and different gains.

[0126] Since the resistance values ​​of the first resistor R1 and the seventh resistor R7 are equal, the resistance values ​​of the fifth resistor R5 and the sixth resistor R6 are equal, but the resistance values ​​of the seventh resistor R7 and the fifth resistor R5 are not equal, according to formula (3), since r7 / r5 is the gain of the current detection circuit in this application, the gain value can be very large, so that the item The output offset voltage of the current detection circuit becomes larger, which can be reduced by reducing the offset voltage of the second operational amplifier B. becomes smaller, thereby reducing the output offset voltage of the current detection circuit.

[0127] In a possible embodiment, the second operational amplifier B includes a plurality of bipolar junction transistors.

[0128] Generally, an operational amplifier includes multiple MOSFETs (Metal-Oxide-Semiconductor Field-Effect Transistors). In a possible embodiment, the offset voltage of the second operational amplifier B can be reduced by replacing the MOSFETs with smaller BJTs (Bipolar Junction Transistors).

[0129] An embodiment of the present application also provides an automotive-grade chip, including: a current detection circuit as described above.

[0130] Automotive-grade chips must meet automotive standards and are used for automotive control systems. Automotive-grade chips are one of the standard levels of specifications for automotive electronic components. Compared to standard industrial-grade chips, automotive-grade chips have higher reliability requirements, such as operating temperature range, operational stability, and defect rate.

[0131] The automotive-grade chip in this application can be a motor drive control chip, which includes the above-mentioned current detection circuit. Among them, the first input voltage SNSP and the second input voltage SNSN are the voltages across the detection resistor when using the phase-to-phase detection method. The first input voltage SNSP and the second input voltage SNSN can accurately measure the current in the H-bridge. Therefore, the first input voltage SNSP and the second input voltage SNSN serve as input signals for the motor drive control chip.

[0132] An embodiment of the present application also provides a vehicle motor drive control system, including: the automotive-grade chip as described above.

[0133] The vehicle motor drive control system in this application includes but is not limited to an automobile drive system and a motor drive system.

[0134] Finally, it should be noted that the above embodiments are merely specific implementations of this application, but the scope of protection of this application is not limited thereto. Any changes or substitutions within the technical scope disclosed in this application should be included in the scope of protection of this application. Therefore, the scope of protection of this application should be based on the scope of protection of the claims.

Claims

1. A current detection circuit, characterized in that: The current detection circuit includes: a reference current generating circuit, a differential signal conversion circuit and a voltage conversion circuit; The differential signal conversion circuit is electrically connected to the reference current generating circuit and the voltage conversion circuit respectively; The reference current generating circuit is used to generate a reference current; The differential signal conversion circuit is configured to perform a differential operation on the first input voltage and the second input voltage to obtain a differential voltage, and convert the differential voltage into a differential current; and further configured to obtain a first current based on the reference current, wherein the first current is the difference between the reference current and the differential current; The voltage conversion circuit is used to convert the first current into a voltage signal to obtain an output voltage.

2. The current detection circuit according to claim 1, wherein: The differential signal conversion circuit includes: a current mirror circuit and a differential input circuit; The current mirror circuit is configured to replicate the reference current according to a preset ratio to obtain a second current and a third current, wherein the current value of the second current is equal to the current value of the reference current, and the current value of the third current is equal to twice the current value of the reference current; The differential input circuit is configured to obtain the first current according to the differential current and based on the second current and the third current.

3. The current detection circuit according to claim 1 or 2, characterized in that: The reference current generating circuit includes: a first operational amplifier, a first transistor, a second transistor, a third transistor, a fourth transistor, a first resistor and a second resistor; The non-inverting input terminal of the first operational amplifier is used to receive a first reference voltage, the inverting input terminal of the first operational amplifier is electrically connected to the first terminal of the third transistor and the first terminal of the first resistor, and the output terminal of the first operational amplifier is electrically connected to the control terminal of the third transistor; The second end of the first resistor is grounded; a first end of the second resistor for connecting to a power supply voltage, a second end of the second resistor being electrically connected to the first end of the first transistor, a control end of the first transistor being electrically connected to the first end of the fourth transistor and the current mirror circuit, a second end of the first transistor being electrically connected to the control end of the fourth transistor and the first end of the second transistor, and a second end of the fourth transistor being grounded; The second end of the second transistor is electrically connected to the control end of the second transistor, the current mirror circuit, and the second end of the third transistor respectively.

4. The current detection circuit according to claim 3, characterized in that: The current mirror circuit includes: a third resistor, a fourth resistor, a fifth transistor, a sixth transistor, a seventh transistor and an eighth transistor; a first end of the third resistor is electrically connected to the first end of the fourth resistor for receiving a power supply voltage, a second end of the third resistor is electrically connected to the first end of the fifth transistor, a control end of the fifth transistor is electrically connected to the control end of the first transistor and the control end of the seventh transistor, and a second end of the fifth transistor is electrically connected to the first end of the sixth transistor; The control terminal of the sixth transistor is electrically connected to the control terminal of the second transistor and the control terminal of the eighth transistor respectively, and the second terminal of the sixth transistor is electrically connected to the differential input circuit; The second end of the fourth resistor is electrically connected to the first end of the seventh transistor, the second end of the seventh transistor is electrically connected to the first end of the eighth transistor, and the second end of the eighth transistor is electrically connected to the differential input circuit.

5. The current detection circuit according to claim 4, characterized in that: The differential input circuit includes: a second operational amplifier, a fifth resistor, a sixth resistor, and a ninth transistor; a non-inverting input terminal of the second operational amplifier electrically connected to the second terminal of the sixth transistor and the first terminal of the fifth resistor, respectively; an inverting input terminal of the second operational amplifier electrically connected to the first terminal of the sixth resistor and the first terminal of the ninth transistor, respectively; and an output terminal of the second operational amplifier electrically connected to the control terminal of the ninth transistor; The second end of the ninth transistor is electrically connected to the second end of the eighth transistor and the voltage conversion circuit respectively; The second end of the fifth resistor is used to connect to the first input voltage, and the second end of the sixth resistor is used to connect to the second input voltage.

6. The current detection circuit according to claim 5, characterized in that: The voltage conversion circuit includes: a tenth transistor, a seventh resistor, a third operational amplifier, a voltage source and a load capacitor; The first end of the tenth transistor is electrically connected to the second end of the ninth transistor, the control end of the tenth transistor is electrically connected to the second end of the voltage source, the first end of the voltage source is used to receive a power supply voltage, and the second end of the tenth transistor is electrically connected to the first end of the seventh resistor and the non-inverting input end of the third operational amplifier respectively; The inverting input terminal of the third operational amplifier is used to receive the second reference voltage, and the output terminal of the third operational amplifier is electrically connected to the second end of the seventh resistor and the first end of the load capacitor, respectively, and serves as the output terminal of the current detection circuit, and is used to output the output voltage; A second terminal of the load capacitor is grounded.

7. The current detection circuit according to claim 6, characterized in that: The current detection circuit further includes: a calibration resistor; The first end of the calibration resistor is electrically connected to the first end of the third transistor, and the second end of the calibration resistor is electrically connected to the first end of the first resistor; The calibration resistor is used to correct the output offset voltage of the current detection circuit.

8. The current detection circuit according to claim 5, characterized in that: The second operational amplifier includes a plurality of bipolar junction transistors.

9. An automotive-grade chip, characterized in that: include: The current detection circuit according to any one of claims 1 to 8.

10. A vehicle motor drive control system, characterized in that: include: The automotive-grade chip as described in claim 9.

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