Rendering processing method and apparatus, electronic device, storage medium

Abstract

The present disclosure provides a rendering processing method and device, electronic equipment and storage medium, the method comprising: obtaining first configuration information of depth range test (DBT) of a first drawing call of a rendering object; in the case where the switch state of the depth range test is turned on, determining first driving information of the depth range test of the first drawing call according to the first configuration information, second configuration information of the depth test of the first drawing call, and second driving information of the depth range test of a second drawing call in the front sequence; the depth range test comprises early DBT and late DBT, and the first driving information comprises a first enabling flag of the early DBT, a second enabling flag of the late DBT, and a second depth interval; generating instruction information according to the first driving information and sending it to a graphics processing device, so that the graphics processing device performs the depth range test in the first drawing call based on the instruction information. According to the embodiments of the present disclosure, the rendering efficiency can be improved.

Description

TECHNICAL FIELD

[0001] The present disclosure relates to the technical field of graphics processing, and in particular, to a rendering processing method and device, an electronic device, and a computer readable storage medium. BACKGROUND

[0002] Graphics processing technology can refer to a technology of processing two-dimensional or three-dimensional vision, images, etc. by using various hardware and software devices to achieve a specific rendering effect. A graphics processing device can refer to a device for performing graphics processing related operations, such as a graphics processing unit (GPU) or other similar devices. In the rendering process of graphics processing, in order to optimize the overall performance of the graphics processing device and reduce power consumption, the key target is to reduce the expensive pixel shader (PS) call.

[0003] In various rendering architectures of related technologies, a depth test (Z-Test) is usually provided, which compares the depth values of each fragment at the same position to ensure that only the pixels at the front end (i.e., visible) are finally displayed, which not only ensures the correct visibility order, but also filters out the occluded fragments, thereby reducing unnecessary pixel shader execution. However, the filtering of fragments in related technologies is not sufficient, resulting in low rendering efficiency. SUMMARY

[0004] The present disclosure provides a rendering processing method and device, an electronic device, and a computer readable storage medium.

[0005] In a first aspect, the present disclosure provides a rendering processing method, comprising: obtaining first configuration information of a depth range test (DBT) of a first draw call of a rendering object, the first configuration information comprising a switch state of the depth range test and a first depth interval; in a case where the switch state of the depth range test is turned on, determining first driving information of the depth range test of the first draw call according to the first configuration information, second configuration information of a depth test of the first draw call, and second driving information of a depth range test of a second draw call; wherein the second draw call is a previous draw call of the rendering object; the depth range test comprises early DBT and late DBT, and the first driving information comprises a first enable flag of the early DBT, a second enable flag of the late DBT, and a second depth interval of the depth range test; generating instruction information according to the first driving information and sending the instruction information to a graphics processing device, so that the graphics processing device performs the depth range test in the first draw call based on the instruction information.

[0006] In a second aspect, the present disclosure provides a rendering processing method, comprising: obtaining first driving information of a depth range test (DBT) of a current first draw call of a rendering object, the depth range test comprising an early DBT and a late DBT, the first driving information comprising a first enabling flag of the early DBT, a second enabling flag of the late DBT, and a second depth interval of the depth range test; in response to the first draw call, performing rasterization processing on a first primitive in a tile of the rendering object to obtain a corresponding first fragment; in a case where the first enabling flag is valid, performing depth range test on the first fragment according to the second depth interval to obtain an early DBT result of the first fragment; in a case where the early DBT result of the first fragment is passed, performing early depth test and rendering processing on the first fragment, and obtaining a second fragment after rendering in a case where the early depth test is passed; in a case where the second enabling flag is valid, performing depth range test on the second fragment according to the second depth interval to obtain a late DBT result of the second fragment; in a case where the late DBT result of the second fragment is passed, performing late depth test and rendering processing on the second fragment, and obtaining first pixel data after rendering in a case where the late depth test is passed.

[0007] In a third aspect, the present disclosure provides a rendering processing apparatus, comprising: a configuration information obtaining module configured to obtain first configuration information of a depth range test (DBT) of a current first draw call of a rendering object, the first configuration information comprising a switch state of the depth range test and a first depth interval; a driving information determining module configured to, in a case where the switch state of the depth range test is on, determine first driving information of the depth range test of the first draw call according to the first configuration information, second configuration information of depth test of the first draw call, and second driving information of depth range test of a second draw call; wherein the second draw call is a previous draw call of the rendering object; the depth range test comprises an early DBT and a late DBT, the first driving information comprising a first enabling flag of the early DBT, a second enabling flag of the late DBT, and a second depth interval of the depth range test; and an instruction sending module configured to generate instruction information according to the first driving information and send the instruction information to a graphics processing device, so that the graphics processing device performs the depth range test in the first draw call based on the instruction information.

[0008] In a fourth aspect, the present disclosure provides an electronic device, comprising: at least one processor; and a memory communicatively connected to the at least one processor; wherein the memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the rendering processing method described above.

[0009] In a fifth aspect, the present disclosure provides a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the rendering processing method described above.

[0010] In a sixth aspect, the present disclosure provides a computer program product comprising computer-readable code, or a non-transitory computer-readable storage medium carrying computer-readable code, which, when run in a processor of an electronic device, causes the processor in the electronic device to perform the rendering processing method described above.

[0011] The embodiments provided by the present disclosure can combine a depth range test (DBT) with a depth test, obtain configuration information of a depth range test of a current drawing call, determine DBT driving information of the current drawing call according to DBT configuration and depth test configuration of a previous drawing call and depth test configuration of the current drawing call, and then generate corresponding instruction information and issue the same, so that a graphics processing device performs a depth range test, thereby further removing invalid fragments on the basis of a depth test, reducing unnecessary pixel shader execution, and improving rendering efficiency.

[0012] It should be understood that the content described in this section is not intended to identify key or important features of the embodiments of the present disclosure, nor is it used to limit the scope of the present disclosure. Other features of the present disclosure will become apparent through the following description. BRIEF DESCRIPTION OF DRAWINGS

[0013] The accompanying drawings are included to provide a further understanding of the present disclosure and constitute a part of the specification, which together with the embodiments of the present disclosure serve to explain the present disclosure, and do not constitute a limitation of the present disclosure. The above and other features and advantages will become more apparent from the detailed description of the exemplary embodiments described below, with reference to the drawings, in which:

[0014] Figure 1 A schematic diagram of a rendering architecture of related art.

[0015] Figure 2 A schematic diagram of a rendering architecture of related art.

[0016] Figure 3A flowchart of a rendering processing method provided for an embodiment of the present disclosure.

[0017] Figure 4 A schematic diagram of a rendering architecture provided for an embodiment of the present disclosure.

[0018] Figure 5 A schematic diagram of a switch state of a depth test provided for an embodiment of the present disclosure.

[0019] Figure 6 A schematic diagram of a processing procedure of a depth test and a depth range test provided for an embodiment of the present disclosure.

[0020] Figure 7 A schematic diagram of a processing procedure of a depth test and a depth range test provided for an embodiment of the present disclosure.

[0021] Figure 8 A schematic diagram of a switch state of a depth test and a depth range test provided for an embodiment of the present disclosure.

[0022] Figure 9 A flowchart of a rendering processing method provided for an embodiment of the present disclosure.

[0023] Figure 10 A block diagram of a rendering processing apparatus provided for an embodiment of the present disclosure.

[0024] Figure 11 A block diagram of an electronic device provided for an embodiment of the present disclosure. DETAILED DESCRIPTION

[0025] In order for those skilled in the art to better understand the technical solutions of the present disclosure, the exemplary embodiments of the present disclosure are described below in conjunction with the accompanying drawings, which include various details of the embodiments of the present disclosure to help understanding, and should be considered only as exemplary. Therefore, those skilled in the art should recognize that various changes and modifications can be made to the embodiments described herein without departing from the scope and spirit of the present disclosure. Also, for the sake of clarity and conciseness, the description below omits the description of well-known functions and structures.

[0026] The embodiments of the present disclosure and the features in the embodiments can be combined with each other without conflict. As used herein, the term “and / or” includes any and all combinations of one or more of the associated listed items.

[0027] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to be limiting of the disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises" and / or "comprising," when used in this specification, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. "Connected" or "coupled" or similar terms are not limited to a direct connection, but can include an indirect connection unless otherwise explicitly stated.

[0028] Unless otherwise defined, all terms (including technical and scientific terms) used herein have the same meaning as commonly understood by one of ordinary skill in the art. It will be further understood that terms, such as those defined in commonly used dictionaries, should be interpreted as having a meaning that is consistent with their meaning in the context of the relevant art and the present disclosure and will not be interpreted in an overly literal or overly formal sense unless expressly so defined herein.

[0029] Before embodiments of the present disclosure are described in detail, some related concepts are first explained for the sake of clarity.

[0030] A render target can refer to an object to be rendered, which can be a part of a virtual scene that needs to be rendered, or can also be a picture or a video frame, etc. that needs to be rendered.

[0031] A primitive can refer to a basic geometric shape that constitutes a figure, such as a point, a line, a triangle, etc. For example, for a figure drawn by an application, it can be represented in a computer by splicing a large number of basic geometries to represent the figure.

[0032] A rendering pipeline is a key concept in computer graphics, which is a stage in a graphics processing unit (GPU) responsible for processing and converting graphics data for rendering. The main task of the rendering pipeline is to convert the input geometric primitives (such as points, lines, triangles, etc.) into pixels visible on the screen. The goal of the rendering pipeline is to process graphics in an efficient way and generate the final image. Through parallel processing and specialized hardware support, the GPU can quickly perform these calculations to achieve real-time graphics rendering.

[0033] In the related art, in order to optimize the overall performance of the graphics processing device and reduce power consumption, reduce the call of the pixel shader (Pixel Shader, PS), ensure that the GPU can still maintain high performance and low power consumption when rendering high-resolution and complex scenes, there are various rendering processing methods.

[0034] In some embodiments, the rendering processing manner of the related art includes immediate mode rendering (IMR), the core feature of which is that the primitives are directly written into the global frame buffer after processing without block processing. The IMR can adopt standard depth test (Z-Test), also known as visibility test, or early depth test (Early-Z).

[0035] The Z-Test ensures that only the pixels in the front end (i.e., visible) are finally displayed by comparing the depth values of the pixels in the same position, which not only ensures the correct visibility order, but also filters out the pixels that are occluded, thereby reducing unnecessary pixel shader execution. The Early-Z is to advance the depth test from the pixel shader to the stage after rasterization and before the pixel shader, so that the depth comparison of the pixels is performed as early as possible after rasterization, and the pixels that are obviously invisible are quickly removed. The removal is completed before entering the PS stage with high overhead, which greatly reduces the subsequent pixel shading burden and effectively reduces unnecessary calculation resource consumption and energy consumption.

[0036] In some embodiments, other related technologies of the depth test include Coarse-Z (coarse depth test, which is usually used for calculating the depth range (minimum value / maximum value) of a larger area (such as a block composed of multiple pixels) instead of fine processing of each pixel, for quickly removing obviously occluded areas and reducing subsequent calculations), Hierarchical-Z (hierarchical depth test, which organizes the depth buffer data in a pyramid hierarchy (such as a multi-level depth map from full resolution to low resolution), quickly judges the visibility of a large area through the depth range of the high level, and then refines to the pixel level layer by layer, which is an efficient occlusion removal technology), and the like, which are not limited by the present disclosure.

[0037] Figure 1 A schematic diagram of a rendering architecture of the related art is shown, which is a schematic diagram of an IMR rendering pipeline. As shown in Figure 1 The rendering pipeline can include vertex processing 11, clipping, projection and culling 12, rasterization 13, early depth test (also known as early visibility test) 14, texture and shading 15, alpha test 16, late depth test (also known as late visibility test) 17, and alpha blending 18.

[0038] In the above, the graphics processing device can read geometry data from the system memory, obtain primitives via vertex processing 11 and processing of the clipping, projection and culling 12 stage, rasterize the primitives via rasterization 13 to obtain corresponding fragments, perform depth comparison via early depth test 14 to remove occluded fragments, perform texture and shading based on texture data read from the system memory via the texture and shading 15 stage, perform alpha test 16, perform late depth test 17 based on the depth buffer for fragments that pass the alpha test 16, perform alpha blending 18 with data in the frame buffer, and obtain the rendering result, such as pixel data to be output.

[0039] It should be understood that the above is only a schematic of the IMR rendering pipeline, and one skilled in the art can set the specific structure of various rendering pipelines according to actual conditions, and the present disclosure does not limit this.

[0040] In some embodiments, the rendering processing manner of the related art also includes tiled-based rendering (TBR). This processing manner divides the rendering object into multiple tiles, and performs depth test and other preliminary processing within each tile using a local cache. During rendering, the direct rendering target is no longer the current frame buffer and depth buffer, but a high-speed cache called tile buffer, i.e., an on-chip buffer. Thus, the read and write operations on the frame buffer and depth buffer in the IMR are changed to read and write operations on the high-speed memory in the GPU. By using the locality advantage, global memory access is reduced, bandwidth consumption and power consumption are reduced, and overdraw is effectively reduced.

[0041] In some embodiments, the rendering processing manner of the related art also includes tile-based deferred rendering (TBDR). TBDR further delays the fragment shading processing on the basis of TBR, performs hidden surface removal (HSR) through a hardware level feature, and solves the overdraw problem. The geometry data and depth information in each tile are collected first, and the deferred depth test and rejection are performed centrally, and only the expensive PS calculation is performed on the actually visible and effective fragments. The basic idea is that the pixels passing the early depth test are not immediately drawn, but only the primitives of these pixels are marked, and only the pixels marked finally passing the HSR are drawn. In this way, the system memory bandwidth requirement can be significantly reduced, thereby minimizing invalid calculation and power consumption.

[0042] Figure 2 FIG. 1 is a schematic diagram of a rendering architecture of the related art, which is a schematic diagram of a TBDR rendering pipeline. As shown in FIG. 1, the rendering pipeline can include vertex processing 21, clipping, projection and culling 22, tiling 23, rasterization 24, early depth test 25, texture and shade 26, alpha test 27, late depth test 28, and alpha blend 29. Figure 2

[0043] Among them, the graphics processing device can read the geometry data from the system memory, obtain the primitives of the rendering object through the processing of the vertex processing 21 and the clipping, projection and culling 22 stages, complete the segmentation of the rendering object and record the graphics data covering each tile, including the primitive list, vertex data, etc., to the system memory in the tiling 23 stage. For a tile, the rendering pipeline loads all the primitives (such as triangular primitives) contained therein to the fragment stage for processing, all the primitives covering the tile can be directly read from the corresponding primitive list, and when all the primitives of the tile are processed, the next tile can be processed.

[0044] ​The primitives of each tile are rasterized 24 to get corresponding fragments; the fragments are compared by early depth test 25 to remove occluded fragments. The fragments passing early depth test 25 are processed by texture and shading 26 based on texture data in system memory, and then are tested by alpha test 27. The fragments passing alpha test 27 are tested by late depth test 28 based on on-chip depth buffer, and then are alpha blended 29 with data in on-chip color buffer to get the rendering result, such as pixel data to be output. The on-chip depth buffer interacts with depth buffer in system memory, and the on-chip color buffer interacts with frame buffer in system memory.

[0045] It should be understood that the above is only a schematic of the TBDR rendering pipeline, and those skilled in the art can set the specific structure of various rendering pipelines according to actual conditions, and the present disclosure does not limit this.

[0046] In general, IMR, TBR, TBDR and other technologies are all optimized around reducing unnecessary fragment shading (i.e. PS calls), by filtering out unnecessary fragments at different stages, not only can improve rendering efficiency, but also can reduce overall energy consumption, so as to be suitable for real-time rendering requirements in high resolution and complex scenes.

[0047] However, although the related art has achieved certain results in improving performance, it still has the following deficiencies:

[0048] Redundancy of full-range depth comparison: Traditional depth test only compares the depth value of the current fragment with the corresponding position in the frame buffer, and cannot limit the depth range according to the scene requirements. For example, when it is required to render only the objects in a certain depth interval (such as near the water surface), the traditional method will process all fragments, even if they are outside the target range, resulting in unnecessary fragment shader calculation and bandwidth waste.

[0049] Multi-stage rendering overhead of complex scenes: Some effects (such as local shading, refraction) require multiple rendering of different depth layers in the same area. Developers need to implement through multiple draw calls or complex layered rendering logic, increasing the overhead of CPU-GPU communication and state switching.

[0050] Inefficient processing of transparent and mixed effects: The rendering of transparent objects usually relies on depth write disable and ordering, but traditional depth test cannot flexibly control the mixed area, which may cause over-drawing or ordering errors.

[0051] Limitations of hidden surface removal HSR: HSR technology relies on the accuracy of occlusion information, in dynamic or complex scenes, it may not be able to effectively eliminate all occluded fragments, resulting in invalid PS calls, leading to performance degradation.

[0052] According to the rendering processing method provided in the embodiments of the present disclosure, the depth range test (DBT) can be combined with the depth test (Z-test), the user layer is allowed to configure the DBT in the draw call, the configuration information of the depth range test of the current draw call is obtained at the driver layer, the DBT driving information of the current draw call is determined according to the DBT configuration and the depth test configuration of the previous draw call and the depth test configuration of the current draw call, and then the corresponding instruction information is generated and delivered, so that the depth range test is performed by the graphics processing device, thereby further removing the invalid fragments on the basis of the depth test, reducing unnecessary pixel shader execution, improving rendering efficiency, and reducing overall power consumption.

[0053] In addition, according to the rendering processing method provided in the embodiments of the present disclosure, the depth range test can be divided into early DBT (Early-DBT) and late DBT (Late-DBT), the early DBT cooperates with the early depth test (Early-Z), and the late DBT cooperates with the late depth test (Late-Z), which can reduce unnecessary calculation of the early depth test and the late depth test, and can optimize the performance and ensure the correctness of the DBT result, respectively.

[0054] The rendering processing method according to the embodiments of the present disclosure can be executed by an electronic device such as a terminal device or a server, the terminal device can be a vehicle-mounted device, a user equipment (UE), a mobile device, a user terminal, a terminal, a cellular phone, a cordless phone, a personal digital assistant (PDA), a handheld device, a computing device, a vehicle-mounted device, a wearable device, etc., and the method can be realized by a processor calling computer readable program instructions stored in a memory. Alternatively, the method can be executed by a server.

[0055] Figure 3 A flowchart of a rendering processing method provided in the embodiments of the present disclosure is provided. The method can be executed by a processing device in a terminal device, for example, a central processing unit (CPU). Referring to Figure 3 , the method comprises:

[0056] In step S31, first configuration information of a depth range test DBT of a current first draw call of a rendering object is acquired, the first configuration information including a switch state of the depth range test and a first depth interval.

[0057] In step S32, in a case where the switch state of the depth range test is on, first driving information of the depth range test of the first draw call is determined according to the first configuration information, second configuration information of a depth test of the first draw call, and second driving information of a depth range test of a second draw call.

[0058] The second draw call is a previous draw call of the rendering object; the depth range test includes early DBT and late DBT; and the first driving information includes a first enable flag of the early DBT, a second enable flag of the late DBT, and a second depth interval of the depth range test.

[0059] In step S33, instruction information is generated according to the first driving information and sent to a graphics processing device, so that the graphics processing device performs the depth range test in the first draw call based on the instruction information.

[0060] For example, the depth range test DBT technology allows only processing of a fragment whose depth value is in a specified depth range in a rendering process, thereby eliminating fragments that do not need to be calculated. The DBT can be set to be executed after a Scissor-Test and before a Z-Test. Unlike the depth test, the DBT does not depend on an interpolated calculation or a depth value output by a fragment shader, but is determined according to a depth value stored in a current depth buffer. The DBT can further finely eliminate in a depth direction (Z direction), and the DBT in combination with the depth test can maximize reduction of generation of useless fragments and shader calls in scenes such as stencil shadow volumes, volume lights, or deferred rendering, thereby improving rendering pipeline efficiency and application performance.

[0061] In some possible implementation manners, a corresponding interface can be configured in a user layer of a processing device, to allow a user to configure parameters of the depth range test in each draw call. The interface can adopt a standardized interface provided by a graphics API (Application Programming Interface) such as Direct3D (a bottom-layer graphics API optimized for a Windows platform), Vulkan (a cross-platform open-source graphics API), and OpenGL (a cross-platform graphics API standard), and the disclosure does not limit the specific type of the interface.

[0062] In some possible implementation manners, a corresponding DBT module can be set in a hardware layer of a graphics processing device (e.g., a GPU) to implement the DBT function. The depth range test includes an early DBT (Early-DBT) and a late DBT (Late-DBT), the early DBT is set before an early depth test Early-Z, and the late DBT is set before a late depth test Late-Z, so as to remove invalid fragments in advance.

[0063] In some possible implementation manners, the parameters of the depth range test can include a switch state of the depth range test and a depth interval. The switch state includes on or off, if a user wants to disable the DBT function, the switch state is set to off; if the user wants to enable the DBT function, the switch state is set to on; the depth interval can include a minimum depth value and a maximum depth value (zmin, zmax) of a floating-point type FLOAT, which are used to limit the depth range tested by the DBT. The maximum range of the depth interval can be [0.0f, 1.0f], or can be set to be less than the maximum range, for example, [0.3f, 0.7f]. The parameters of the depth range test can further include other parameters, which are not limited in the present disclosure.

[0064] In some possible implementation manners, for a current first draw call of a rendering object, a driver layer of the processing device can obtain, in step S31, first configuration information of the first draw call, including a switch state of the depth range test and a first depth interval.

[0065] In some possible implementation manners, if the switch state is on, the first driver information of the depth range test of the first draw call can be determined according to the first configuration information, second configuration information of the depth test of the first draw call, and second driver information of the depth range test of a second draw call in step S32. The second draw call is a previous draw call of the first draw call, for example, a previous draw call of the same tile; the first driver information includes a first enabling flag of the early DBT, a second enabling flag of the late DBT, and a second depth interval of the depth range test.

[0066] In some possible implementation manners, the depth test includes an early depth test and a late depth test, and the second configuration information of the depth test includes an enabling flag of the early depth test and an enabling flag of the late depth test. The second driver information of the depth range test of the second draw call can include an enabling flag of the early DBT and the late DBT, a third depth interval of the depth range test of the second draw call, and the like.

[0067] In some possible implementation manners, in step S32, data checking and conversion can be performed on the first depth interval. The data checking can include checking whether the minimum depth value zmin and the maximum depth value zmax of the first depth interval are NAN (not a number); if there is a NaN, converting the NaN to 0.0f; and checking the range of zmin and zmax, performing a clamp operation to [0.0f, 1.0f], that is, limiting the values outside the range of [0.0f, 1.0f] to the range of [0.0f, 1.0f]; and then checking whether zmin<=zmax is satisfied, and if satisfied, passing; if not satisfied, sending a warning to the runtime environment. And the subsequent steps can still be continued, and the hardware will still process zmin<=zmax, which will be determined as a failure.

[0068] In some possible implementation manners, the adjusted zmin and zmax can be mapped to corresponding integer or floating-point values according to the data format of the depth buffer (z-buffer), to obtain a second depth interval. The data format of the depth buffer can be, for example, D16_UNORM (16-bit integer), D24_UNORM (24-bit integer), D32_FLOAT (32-bit floating-point number), and the like; and the interval [0.0f, 1.0f] of the floating-point number can be converted to [0, 65535] in D16_UNORM. The specific data format of the depth buffer is not limited in the present disclosure.

[0069] In some possible implementation manners, according to the first configuration information, the second configuration information of the depth test of the first drawing call, and the second driving information of the depth range test of the second drawing call, the first Early-DBT enabled flag of the early DBT and the second Late-DBT enabled flag of the late DBT can be determined. That is, according to the configuration state of the current drawing call and the previous drawing call, the Early-DBT and / or the Late-DBT can be dynamically decided to be enabled, so that the DBT function meets the data dependency and limitation, and processing errors that can occur are avoided, and then the corresponding enabled flags are configured to generate the driving information.

[0070] In some possible implementation manners, the driving layer can perform data packaging and transmission in step S33, to generate instruction information according to the first driving information, that is, to encode the first enabled flag, the second enabled flag, and the second depth interval into a hardware instruction package. The instruction information can further include an identifier of the data format of the depth buffer, to adapt the comparison logic and the like of the hardware module of the graphics processing device, which is not limited in the present disclosure.

[0071] In some possible implementations, the generated instruction information is sent to the graphics processing device; after receiving the instruction information, the graphics processing device can perform a depth range test in the first drawing call based on the instruction information, thereby realizing the DBT function.

[0072] According to embodiments of this disclosure, depth range testing can be combined with depth testing to obtain the configuration information of the depth range test for the current drawing call; the DBT driver information for the current drawing call can be determined based on the DBT configuration and depth test configuration of the previous drawing call and the depth test configuration of the current drawing call; then, corresponding instruction information can be generated and issued to enable the graphics processing device to perform depth range testing, thereby further removing invalid fragments based on the depth test, reducing unnecessary pixel shader execution, improving rendering efficiency, and reducing overall power consumption.

[0073] The rendering processing method according to the embodiments of this disclosure will now be described in detail.

[0074] In some possible implementations, the rendering method of the rendered object includes tile-based deferred rendering (TBDR), where the rendered object is divided into multiple tiles. That is, the rendering processing method according to embodiments of this disclosure can be executed under the TBDR architecture, by adding a depth range test (DBT) module before the depth test (Z-Test) module of the graphics processing device, and directly utilizing the depth buffer (z-buffer) to quickly execute DBT.

[0075] Figure 4 This is a schematic diagram of a rendering architecture provided in an embodiment of this disclosure. Figure 4 As shown, this embodiment of the present disclosure improves upon the TBDR architecture. The rendering pipeline 40 may include vertex processing 401; clipping, projecting, and culling 402; tiling 403; rasterization 404; early-DBT 405; early visibility test 406; texture and shade 407; alpha test 408; late-DBT 409; late visibility test 410; and alpha blend 411.

[0076] Among them, the early DBT 405 and the later DBT 409 can reuse the DBT module of the graphics processing device; the early depth test 406 and the later depth test 410 can reuse the Z-Test module of the graphics processing device.

[0077] In the processing, the graphics processing device can read geometry data from the system memory, get primitives of the rendering object via the processing of the vertex processing 401 and the clipping, projection and culling 402 stage, complete the splitting of the rendering object, record the graphics data covering to each tile including the primitive list, vertex data, etc. in the tiling 403 stage, and write to the system memory. For a tile, the rendering pipeline loads all primitives (such as triangular primitives) contained therein to the fragment stage for processing, all primitives covering to the tile can be directly read from the corresponding primitive list, and when all primitives of the tile are processed, the next tile can be processed.

[0078] The primitives of each tile are rasterized 404 to get corresponding fragments, the early DBT 405 removes the fragments outside the depth interval range based on the on-chip depth buffer, and then enters the early depth test 406 for depth comparison and removes the occluded fragments. Before the early depth test 406, the hidden surface removal HSR can also be performed.

[0079] The fragments passing the early depth test 406 are subjected to texture and shadow processing based on the texture data in the system memory in the texture and shadow 407 stage, and then subjected to the alpha test 408. The fragments passing the alpha test 408 are subjected to the late DBT 409 and the late depth test 410 based on the on-chip depth buffer in sequence, the fragments passing the late depth test 410 are subjected to alpha blending 411 with the data in the on-chip buffer to get the rendering result, such as the pixel data to be output. The on-chip depth buffer and the depth buffer in the system memory perform data interaction, and the on-chip color buffer and the frame buffer in the system memory perform data interaction.

[0080] In some possible implementation manners, corresponding interfaces are configured in the user layer in the processing device (such as the CPU) corresponding to the processing in the graphics processing device in the rendering architecture, allowing the user to configure the parameters of the depth range test in each draw call, including the switch state of the depth range test and the depth interval.

[0081] The switch state includes on or off, if the user wants to disable the DBT function, the switch state is set to off; if the user wants to enable the DBT function, the switch state is set to on; the depth interval can include the minimum depth value and the maximum depth value (zmin, zmax) of the floating point type FLOAT, for limiting the depth range tested by the DBT.

[0082] In some possible implementation manners, for a first drawing call of a current rendering object, the driving layer of the processing device can acquire, in step S31, first configuration information of the first drawing call, including a switch state of the depth range test and a first depth interval; and then determine first driving information of the depth range test DBT of the first drawing call. The first driving information includes a first enabling flag of the early DBT, a second enabling flag of the late DBT, and a second depth interval of the depth range test.

[0083] In some possible implementation manners, if the switch state is off, the first enabling flag and the second enabling flag can be directly set as invalid, the second depth interval is set as [0.0f, 0.0f] or null, and instruction information generated according to the first driving information is used to instruct the graphics processing device not to perform the DBT in the first drawing call.

[0084] In some possible implementation manners, if the switch state is on, the first driving information of the depth range test of the first drawing call can be determined according to the first configuration information, second configuration information of the depth test of the first drawing call, and second driving information of the depth range test of a second drawing call in step S32. The second drawing call is a preceding drawing call of the first drawing call, for example, a previous drawing call of the same tile. The depth test includes early depth test and late depth test, and the second configuration information of the depth test includes an enabling flag of the early depth test and an enabling flag of the late depth test. The second driving information of the depth range test of the second drawing call can include a third enabling flag of the early DBT and a fourth enabling flag of the late DBT, a third depth interval of the depth range test of the second drawing call, and the like. The third depth interval is a depth interval actually used in the DBT of the second drawing call after data verification and format conversion.

[0085] That is, the driving information of the DBT in the current drawing call can be determined together by the driving information of the DBT in the preceding drawing call and the configuration information of the depth test in the current drawing call, so that the DBT function meets the data dependency and limitation, and processing errors that can occur are avoided.

[0086] In some possible implementation manners, the step of determining the first driving information of the depth range test of the first drawing call in step S32 can include: performing data checking and format conversion on the first depth interval to obtain the second depth interval; in a case where the third enabling flag and the fourth enabling flag are both invalid, determining the first enabling flag and the second enabling flag according to the second configuration information; in a case where at least one of the third enabling flag and the fourth enabling flag is valid, determining the first enabling flag and the second enabling flag according to a difference between the second depth interval and the third depth interval, the third enabling flag, the fourth enabling flag, and the second configuration information.

[0087] For example, the first depth interval set by the user can be incorrect, and the data format of the depth buffer of the graphics processing device can be different from the data format of the first depth interval, so that the first depth interval needs to be checked and converted first.

[0088] In some possible implementation manners, the step of performing data checking and format conversion on the first depth interval can include: performing data checking on a minimum depth value and a maximum depth value of the first depth interval to determine a checked minimum depth value and a checked maximum depth value; and performing numerical conversion on the checked minimum depth value and the checked maximum depth value according to the data format of the depth buffer of the graphics processing device to determine the second depth interval.

[0089] For example, the data checking can include checking whether a minimum depth value zmin and a maximum depth value zmax of the first depth interval are not a number (NAN); if there is a NaN, converting the NaN to 0.0f; and checking the range of zmin and zmax to perform a clamp operation to [0.0f, 1.0f], that is, limiting a value outside the range of [0.0f, 1.0f] to the range of [0.0f, 1.0f]; and then checking whether zmin<=zmax is satisfied, and if satisfied, passing; if not satisfied, sending a warning to a runtime. And the subsequent steps can still be continued, and the hardware will still process zmin<=zmax, but will be determined as a failure.

[0090] In some possible implementation manners, the adjusted zmin and zmax can be mapped into corresponding integer or floating-point numerical values according to a data format of a depth buffer (z-buffer), to obtain the second depth interval. The data format of the depth buffer can be, for example, D16_UNORM (16-bit integer), D24_UNORM (24-bit integer), D32_FLOAT (32-bit floating point), or the like; and the interval [0.0f, 1.0f] of the floating point can be converted into [0, 65535] in D16_UNORM. The specific data format of the depth buffer is not limited in the present disclosure.

[0091] In this way, unreasonable depth values can be corrected, and the depth values in the depth interval are matched with the depth values stored in the depth buffer of the graphics processing device, so as to be compared subsequently, thereby improving the accuracy of the depth range test.

[0092] In some possible implementation manners, if the third and fourth enabling flags are both invalid, that is, the DBT function in the previous drawing call is closed, the second configuration information of the depth test in the current drawing call is directly used to determine whether the early DBT and the late DBT in the current drawing call are enabled, and then the first and second enabling flags are set to be valid or invalid.

[0093] If at least one of the third and fourth enabling flags is valid, that is, the DBT function in the previous drawing call is enabled, the second configuration information of the depth test in the current drawing call, the third and fourth enabling flags of the DBT in the previous drawing call, and the difference between the second depth interval and the third depth interval are comprehensively used to determine whether the early DBT and the late DBT in the current drawing call are enabled, and then the first and second enabling flags are set to be valid or invalid.

[0094] In this way, the DBT function configuration of the current drawing call can be implemented on the basis of meeting the data dependency and limitation, thereby improving the correctness of the processing result and improving the rendering efficiency.

[0095] For the early depth test Early-Z and the late depth test Late-Z, the switching enabling scenarios can be divided into the following three categories:

[0096] 1) Early-Z is enabled, and Late-Z is disabled, and the z-buffer is updated in Early-Z. The use scenarios include: a standard opaque rendering scenario; a standard translucent rendering (Alpha Blend disabled) scenario, and the like.

[0097] 2) Early-Z off, Late-Z on, update z-buffer in Late-Z, its usage scenarios include: modify depth value, if the depth value is changed in the fragment shader, Early-Z cannot predict the final depth, resulting in its failure.

[0098] 3) Early-Z on (discard some occluded fragments in advance to improve performance), Late-Z on (discard all occluded fragments to ensure correct results), update z-buffer in Late-Z, its usage scenarios include: use discard / clip operation, explicitly discard fragments in the fragment shader will make Early-Z unable to determine whether the fragment should be processed in advance, and Late-Z needs to process again; enable alpha test or alpha blending, these operations need to determine the visibility of the fragment after the execution of the fragment shader, and Late-Z needs to process again.

[0099] It should be understood that the skilled in the art can set the switch state of Early-Z and Late-Z according to the actual situation, and the present disclosure does not limit this.

[0100] In some possible implementations, whether Early-Z or Late-Z, the order of submission or primitives in the same drawing call will be strictly followed for processing. In this way, when multiple fragments (such as fragments p0, p1, p2) overlap in screen space, the post-order fragment is always tested based on the z-buffer write result of the pre-order fragment, ensuring that the correct occlusion relationship can be obtained in both Early-Z and Late-Z stages. The switch enablement of Early-Z and Late-Z of the pre-order and post-order fragments has certain dependencies and limitations, which can be specifically represented as: 1. Early-Z and Late-Z of each fragment in p0, p1, p2 are executed in order. 2. Early-Z of p0, p1, p2 is executed in order. 3. Late-Z of p0, p1, p2 is executed in order.

[0101] 4. The order of Early-Z read operation of the post-order fragment and Late-Z write operation of the pre-order fragment is uncertain. For example, if the Early-Z read operation of fragment p2 is earlier than the Late-Z write operation of fragment p1, the following situation may occur: (1) if p2 opens Early-Z and closes Late-Z, it cannot be guaranteed that the depth values z read by p2 and written by p1 are consistent, so the Early-Z read operation of p2 must wait for the Late-Z write operation of p1 to complete.

[0102] (2) If p2 has Early-Z on and Late-Z on, and the depth test comparison mode of p1 and p2 is different, then the Early-Z read operation of p2 must wait for the Late-Z write of p1 to complete, otherwise p2 in Early-Z can be discarded incorrectly.

[0103] (3) If p2 has Early-Z on and Late-Z on, and the depth test comparison mode of p1 and p2 is the same, then the following situations can occur: ① If p2's Early-Z passes, then p2's Late-Z read operation must be after p1's Late-Z write, and the final result is correct.

[0104] ② If p2's Early-Z fails, then p2 is discarded in Early-Z, and the final result is correct because: I) If p1's Late-Z fails and is discarded (z-buffer is not updated), then the depth value read by p2 is correct, and p2 is definitely discarded; II) If p1's Late-Z passes and is retained (z-buffer is updated), then p1 and p2 are on both sides of p0, and even if p2 reads the updated depth value of p1, p2 is definitely discarded.

[0105] Figure 5 A schematic diagram of the switching state of the depth test provided by the embodiments of the present disclosure. Wherein, "√" represents on or synchronous waiting; "×" represents off or no need to wait for synchronization.

[0106] As shown in Figure 5 , if the Early-Z of the previous pixel is on and the Late-Z is off, then no matter how the switching state of the Early-Z and the Late-Z of the subsequent pixel is set, there is no need to wait for synchronization, and the processing result of the subsequent pixel is always correct.

[0107] As shown in Figure 5If the Early-Z of the previous fragment is on or off, and the Late-Z of the previous fragment is on, the processing result of the later fragment can be incorrect, and needs to be set according to the on-off state of the Early-Z and the Late-Z of the later fragment and the depth test comparison mode, including: the Early-Z of the later fragment is on, and the Late-Z of the later fragment is off, referring to the above case 4(1), synchronous waiting is needed to ensure that the processing result is correct; the Early-Z of the later fragment is off, and the Late-Z of the later fragment is on, then the Late-Z of the previous fragment and the Late-Z of the later fragment are executed in sequence, referring to the above case 3, no synchronous waiting is needed, and the processing result of the later fragment is always correct; the Early-Z of the later fragment is on, and the Late-Z of the later fragment is on, if the depth test comparison mode of the previous fragment and the depth test comparison mode of the later fragment are different, referring to the above case 4(2), synchronous waiting is needed to ensure that the processing result is correct; the Early-Z of the later fragment is on, and the Late-Z of the later fragment is on, if the depth test comparison mode of the previous fragment and the depth test comparison mode of the later fragment are the same, referring to the above case 4(3), no synchronous waiting is needed, and the processing result of the later fragment is always correct.

[0108] Similar to the depth test, in the depth range test DBT process, the depth value z written by the previous fragment in the z-buffer needs to be read and compared with the maximum depth value and the minimum depth value of the depth interval. If the reading is before the writing operation of the previous fragment, an incorrect depth value will be read, which may cause the DBT to fail and the fragment to be discarded incorrectly.

[0109] The depth range test DBT according to the embodiments of the present disclosure includes early DBT and late DBT, the early DBT is set before the early depth test Early-Z, and the late DBT is set before the late depth test Late-Z, so as to remove invalid fragments in advance.

[0110] The above describes the restrictions between the on-off states of the depth tests of the previous fragment and the later fragment, when the Early-Z and the Late-Z of the previous fragment and the later fragment are both on at the same time, the Late-Z of the later fragment can always correctly read the depth value z written by the previous fragment in the z-buffer, but the Early-Z may be affected. The Early-DBT and the Late-DBT are similar, therefore, in this case, the Early-DBT needs to be turned off and the Late-DBT needs to be turned on, and whether the depth intervals of the previous fragment and the later fragment are the same or different will also affect the processing result of the DBT.

[0111] The restrictions between the on-off states of the depth tests of the previous fragment and the later fragment and the DBT are described below.

[0112] 1. The case that the depth intervals of the previous fragment and the later fragment are the same.

[0113] (1) Preceding fragment, if Early-DBT on, Late-DBT off, then the following fragment can have the following cases: ① Following fragment, if Early-Z on, Late-Z off, then Early-DBT on, Late-DBT off. Because the Early-DBT read of the following fragment is after the Early-Z write of the preceding fragment.

[0114] ② Following fragment, if Early-Z off, Late-Z on, then Early-DBT off, Late-DBT on. Because the Late-DBT read of the following fragment is after the Early-Z write of the preceding fragment.

[0115] ③ Following fragment, if Early-Z on, Late-Z on, then Early-DBT on, Late-DBT on. Because the Early-DBT, Late-DBT reads of the following fragment are after the Early-Z write of the preceding fragment.

[0116] (2) Preceding fragment, if Early-DBT off, Late-DBT on, then the following fragment can have the following cases: ① Following fragment, if Early-Z on, Late-Z off, then Early-DBT on, Late-DBT off. Because the Early-DBT read of the following fragment is after the Late-Z write of the preceding fragment (Z-Test is guaranteed in the previous description).

[0117] ② Following fragment, if Early-Z off, Late-Z on, then Early-DBT off, Late-DBT on. Because the Late-DBT read of the following fragment is after the Late-Z write of the preceding fragment.

[0118] ③ Following fragment, if Early-Z on, Late-Z on, then Early-DBT on, Late-DBT on. Consider the following scenario, for three overlapping fragments p0, p1 and p2, even if p2 reads p0's depth value before p1 writes in the Early-DBT stage (at this time, both p1 and p2 are based on p0's depth value for testing), there are the following cases: if p2 passes the Early-DBT, then no matter whether p1 passes the Late-DBT and writes back a new depth, p2 can read the correct depth value updated by p1 in the Late-DBT stage.

[0119] If p2 does not pass the Early-DBT, because p1 and p2 use the same depth interval, p1 also cannot pass the following Late-DBT. That is, in this scenario, the DBT behavior of the following fragment is always correct.

[0120] (3) Preceding fragment, if open Early-DBT, open Late-DBT: ① Following fragment, if open Early-Z, close Late-Z, then open Early-DBT, close Late-DBT. Because the Early-DBT read operation of the following fragment is after the preceding fragment's Late-Z write operation (Z-Test has ensured in the preceding summary).

[0121] ② Following fragment, if close Early-Z, open Late-Z, then close Early-DBT, open Late-DBT. Because the Late-DBT read operation of the following fragment is after the preceding fragment's Late-Z write operation.

[0122] ③ Following fragment, if open Early-Z, open Late-Z, then open Early-DBT, open Late-DBT. Consider the following scenario, for three overlapping fragments p0, p1 and p2, even if p2 reads the depth value of p0 before p1 writes in the Early-DBT stage (at this time, p1 and p2 are both based on the depth value of p0 for testing), there are the following cases: if p2 passes the Early-DBT, no matter whether p1 finally passes the Late-DBT and writes back a new depth, p2 can read the correct depth value of p1 updated in the Late-DBT stage. If p2 does not pass the Early-DBT, because p1 and p2 use the same depth interval, p1 is also bound to fail the following Late-DBT. That is, in this scenario, the DBT behavior of the following fragment is always correct.

[0123] It can be seen that, in the case that the depth interval of the preceding fragment and the following fragment is the same, the DBT switch state of the following fragment is consistent with the switch state of its depth test, and is not affected by the DBT and depth test switch states of the preceding fragment.

[0124] 2. The case that the depth interval of the preceding fragment and the following fragment is different.

[0125] (1) Preceding fragment, if open Early-DBT, close Late-DBT, Early-Z write z-buffer, then the following fragment may appear the following cases: ① Following fragment, if open Early-Z, close Late-Z, then open Early-DBT, close Late-DBT. Because the Early-DBT read operation of the following fragment is after the preceding fragment's Early-Z write operation. ② Following fragment, if close Early-Z, open Late-Z, then close Early-DBT, open Late-DBT. Because the Late-DBT read operation of the following fragment is after the preceding fragment's Early-Z write operation.

[0126] ③ The following fragment, if Early-Z is on, Late-Z is on, then Early-DBT is on, Late-DBT is on. Because the Early-DBT read operation of the following fragment is after the Early-Z write operation of the preceding fragment.

[0127] (2) The preceding fragment, if Early-DBT is off, Late-DBT is on, then the following fragment can have the following cases: ① The following fragment, if Early-Z is on, Late-Z is off, then Early-DBT is on, Late-DBT is off. Because the Early-DBT read operation of the following fragment is after the Late-Z write operation of the preceding fragment (Z-Test has been guaranteed in the previous summary).

[0128] ② The following fragment, if Early-Z is off, Late-Z is on, then Early-DBT is off, Late-DBT is on. Because the Late-DBT read operation of the following fragment is after the Late-Z write operation of the preceding fragment.

[0129] ③ The following fragment, if Early-Z is on, Late-Z is on, then Early-DBT is off, Late-DBT is on. Consider the following scenario, for three overlapping fragments p0, p1 and p2, even if p2 reads p0's depth value before p1 writes it in the p2 Early-DBT stage (at this time, p1 and p2 are both based on p0's depth value for testing), there are the following cases: if p2 Early-DBT is on and does not pass, because p1 and p2 use different depth intervals, it cannot be determined whether p1's DBT passes. If p1 passes Early-DBT and updates the depth value, p2's Early-DBT can pass, but p2 has been discarded in error, as shown in Figure 6 . Therefore, p2's Early-DBT must be turned off in this scenario to ensure that the final result is correct, as shown in Figure 7 .

[0130] (3) The preceding fragment, if Early-DBT is on, Late-DBT is on, then the following fragment can have the following cases: ① The following fragment, if Early-Z is on, Late-Z is off, then Early-DBT is on, Late-DBT is off. Because the Early-DBT read operation of the following fragment is after the Late-Z write operation of the preceding fragment (Z-Test has been guaranteed in the previous summary).

[0131] ② The following fragment, if Early-Z is off, Late-Z is on, then Early-DBT is off, Late-DBT is on. Because the Late-DBT read operation of the following fragment is after the Late-Z write operation of the preceding fragment.

[0132] ③ For subsequent fragments, if Early-Z and Late-Z are enabled, then Early-DBT is disabled and Late-DBT is enabled. Consider the following scenario: for three overlapping fragments p0, p1, and p2, even if the Early-DBT stage of p2 reads the depth value of p0 before p1's write (at this time, both p1 and p2 are tested based on the depth value of p0), the following situations exist: If Early-DBT of p2 fails, because p1 and p2 use different depth ranges, it is impossible to determine whether p1's DBT passed. If p1 passes DBT and updates its depth value, Early-DBT of p2 may pass, but p2 has been incorrectly discarded, such as... Figure 6 As shown. Therefore, in this scenario, Early-DBT of p2 must be turned off to ensure the final result is correct, as... Figure 7 As shown.

[0133] Figure 6 and Figure 7 This is a schematic diagram illustrating the processing steps for depth testing and depth range testing provided in the embodiments of this disclosure. Figure 6 and Figure 7 In the z-buffer, the depth range of the preceding fragment is [0.1, 0.5], and the depth range of the following fragment is [0.5, 0.7]. The two are different. The depth value currently stored in the z-buffer is z0=0.4, the depth value of the preceding fragment is z1=0.6, and the depth value of the following fragment is z2=0.5.

[0134] like Figure 6 As shown, the preceding fragments have Early-Z and Late-Z enabled, as well as Early-DBT and Late-DBT enabled. The following fragments have Early-Z and Late-Z enabled, as well as Early-DBT and Late-DBT enabled.

[0135] For the preceding fragment, during Early-DBT processing, z0=0.4 is within the depth range [0.1, 0.5], so Early-DBT passes; during Early-Z processing, z1=0.6>0.4, so Early-Z passes, and the fragment shader is called; then, during Late-DBT processing, z0=0.4 is within the depth range [0.1, 0.5], so Late-DBT passes; during Late-Z processing, z1=0.6>0.4, so Late-Z passes, and the depth value in the depth buffer z-buffer is updated to z0=0.6.

[0136] For the post-sequenced fragment, the Early-DBT processing starts before the Late-Z updates the depth buffer z-buffer, and the read depth value z0=0.4 is out of the depth interval [0.5, 0.7], the Early-DBT does not pass, and the post-sequenced fragment is discarded; and after the depth value is updated z0=0.6, the Early-DBT should pass because the depth value is in the depth interval [0.5, 0.7]. Therefore, the post-sequenced fragment is discarded incorrectly.

[0137] As shown in FIG. 6, the pre-sequenced fragment enables Early-Z and Late-Z, and enables Early-DBT and Late-DBT, and the post-sequenced fragment enables Early-Z and Late-Z, and disables Early-DBT and enables Late-DBT. Figure 7

[0138] For the pre-sequenced fragment, the processing process is consistent with the above description, and details are not described herein again. Figure 6

[0139] For the post-sequenced fragment, the Early-DBT is not executed, and the Early-Z is directly executed, z2=0.5>0.4, the Early-Z passes, and the call of the fragment shader is executed; then the Late-DBT processing is executed, the updated depth value z0=0.6 is read, and the depth interval is [0.5, 0.7], the Late-DBT passes, and the subsequent processing is continued. Therefore, the result is correct in this case.

[0140] It can be seen that, in the case that the depth intervals of the pre-sequenced fragment and the post-sequenced fragment are different, under the condition that the pre-sequenced fragment enables Late-Z and the post-sequenced fragment enables Early-Z and Late-Z, the post-sequenced fragment needs to disable Early-DBT and enable Late-DBT; and under other conditions, the DBT switch state of the post-sequenced fragment is consistent with the switch state of the depth test of the post-sequenced fragment, and is not affected by the switch state of the depth test of the pre-sequenced fragment.

[0141] Figure 8 The depth test and the depth range test are provided for the embodiment of the present disclosure. Wherein, “√” represents enabling; and “×” represents disabling.

[0142] As shown in FIG. 6, the pre-sequenced fragment enables Early-Z and Late-Z, and enables Early-DBT and Late-DBT, and the post-sequenced fragment enables Early-Z and Late-Z, and disables Early-DBT and enables Late-DBT. Figure 8 ​​As shown, when both Early-DBT and Late-DBT of the preceding fragment are off, the on / off states of Early-Z and Late-Z of the subsequent fragment are determined based on their respective on / off states. If both Early-Z and Late-Z are off, Early-DBT can be enabled to implement the DBT function; if at least one of Early-Z and Late-Z is on, the on / off states of Early-DBT and Late-DBT can be consistent with the on / off states of Early-Z and Late-Z.

[0143] like Figure 8 As shown, if at least one of the Early-DBT and Late-DBT of the preceding segment is enabled, and if both Early-Z and Late-Z of the subsequent segment are disabled, the on / off states of the Early-DBT and Late-DBT of the subsequent segment are jointly determined based on the on / off states of the Early-DBT and Late-DBT of the preceding segment and whether the depth range is consistent. If at least one of the Early-Z and Late-Z of the subsequent segment is enabled, the on / off states of the Early-DBT and Late-DBT of the preceding segment, the on / off states of the Early-Z and Late-Z of the subsequent segment, and whether the depth range is consistent are jointly determined based on the on / off states of the Early-DBT and Late-DBT of the preceding segment, the on / off states of the Early-Z and Late-Z of the subsequent segment, and whether the depth range is consistent.

[0144] In some possible implementations, the depth test includes early depth testing and late depth testing, and the second configuration information for the depth test currently being drawn includes the fifth enable flag for early depth testing and the sixth enable flag for late depth testing.

[0145] In the case that both the third enable flag of Early-DBT and the fourth enable flag of Late-DBT in the preceding drawing call are invalid, the step of determining the first enable flag and the second enable flag according to the second configuration information includes: if both the fifth enable flag and the sixth enable flag are invalid, determining that the first enable flag is valid and the second enable flag is invalid; if at least one of the fifth enable flag and the sixth enable flag is valid, determining the first enable flag and the second enable flag according to the fifth enable flag and the sixth enable flag.

[0146] For example, on the processing device side, the preceding fragment corresponds to the preceding draw call, and the subsequent fragment corresponds to the current draw call. If both Early-DBT and Late-DBT of the preceding draw call are disabled, the determination is made by the fifth enable flag of Early-Z and the sixth enable flag of Late-Z of the current draw call.

[0147] In some possible implementation manners, if Early-Z and Late-Z of the current rendering call are both disabled, i.e., the fifth enabling flag and the sixth enabling flag are both invalid, Early-DBT of the current rendering call can be enabled to implement the DBT function. In this case, Early-DBT has removed the fragments outside the second depth interval, and Late-DBT does not need to be repeatedly enabled, and can be closed, so that the first enabling flag is valid, for example, 1, and the second enabling flag is invalid, for example, 0.

[0148] In some possible implementation manners, if Early-Z and Late-Z of the current rendering call are at least one enabled, i.e., at least one of the fifth enabling flag and the sixth enabling flag is valid, the first enabling flag and the second enabling flag are determined according to the fifth enabling flag and the sixth enabling flag. That is, the first enabling flag is consistent with the fifth enabling flag, and the second enabling flag is consistent with the sixth enabling flag, so that Early-DBT and Late-DBT are consistent with the opening and closing states of Early-Z and Late-Z, and the cooperation of the depth range test and the depth test is implemented.

[0149] In this way, the DBT function configuration of the current rendering call can be implemented on the basis of meeting the data dependency and the limitation, so that the correctness of the processing result is improved, and the rendering efficiency is improved.

[0150] In some possible implementation manners, in the case where at least one of the third enabling flag and the fourth enabling flag is valid, the first enabling flag and the second enabling flag are determined according to the difference between the second depth interval and the third depth interval, the third enabling flag, the fourth enabling flag, and the second configuration information, including: in the case where the fifth enabling flag and the sixth enabling flag are both invalid, the first enabling flag and the second enabling flag are determined by the following manner: if the third enabling flag is valid and the fourth enabling flag is invalid, it is determined that the first enabling flag is valid and the second enabling flag is invalid;

[0151] if the fourth enabling flag is valid and the second depth interval is consistent with the third depth interval, it is determined that the first enabling flag is valid and the second enabling flag is valid;

[0152] if the fourth enabling flag is valid and the second depth interval is inconsistent with the third depth interval, it is determined that the first enabling flag is invalid and the second enabling flag is valid.

[0153] For example, on the processing device side, if at least one of the Early-DBT and the Late-DBT of the previous drawing call is enabled, that is, at least one of the third and fourth enable flags is valid; and if neither the Early-Z nor the Late-Z of the current drawing call is enabled, that is, neither the fifth nor the sixth enable flag is valid, then the difference between the second and third depth intervals, the third and fourth enable flags are used for judgment.

[0154] In some possible implementations, if the third enable flag of the Early-DBT of the previous drawing call is valid and the fourth enable flag of the Late-DBT is invalid, the Late-DBT is closed, and the depth interval has no effect on the DBT result, then the Early-DBT of the current drawing call can be enabled to implement the DBT function. In this case, the Early-DBT has removed the fragments outside the second depth interval, and the Late-DBT does not need to be repeatedly enabled, and can be closed, so that the first enable flag is valid and the second enable flag is invalid.

[0155] In some possible implementations, if the fourth enable flag of the Late-DBT of the previous drawing call is valid, that is, the Late-DBT of the previous fragment is enabled, and the Early-Z and the Late-Z of the subsequent fragment are both disabled, then the Late-DBT of the subsequent fragment is enabled, and whether the Early-DBT is enabled is determined according to whether the depth intervals of the previous and subsequent fragments are consistent. If the second and third depth intervals are consistent, the Early-DBT result will not be wrong, and can be enabled; if the second and third depth intervals are inconsistent, the Early-DBT result can be wrong, and cannot be enabled.

[0156] That is, in the case where the fourth enable flag is valid and the second and third depth intervals are consistent, the first enable flag is set to valid and the second enable flag is set to valid; in the case where the fourth enable flag is valid and the second and third depth intervals are inconsistent, the first enable flag is set to invalid and the second enable flag is set to valid. The second and third depth intervals being consistent corresponds to the maximum and minimum depth values of the second and third depth intervals being the same.

[0157] In this way, the DBT function configuration of the current drawing call can be implemented on the basis of meeting the data dependency and the limitation, the correct depth value is read in the processing, the processing result is correct, the correctness of the processing result is improved, unnecessary pixel shader execution is reduced, the rendering efficiency is improved, and the overall power consumption is reduced.

[0158] In some possible implementation manners, when at least one of the third enabling flag and the fourth enabling flag is valid, the determining of the first enabling flag and the second enabling flag according to the difference between the second depth interval and the third depth interval, the third enabling flag, the fourth enabling flag, and the second configuration information comprises: when at least one of the fifth enabling flag and the sixth enabling flag is valid, the first enabling flag and the second enabling flag are determined in the following manner: if a preset condition of the enabling flag is met and the second depth interval is consistent with the third depth interval, it is determined that the first enabling flag is valid and the second enabling flag is valid; if the preset condition is met and the second depth interval is inconsistent with the third depth interval, it is determined that the first enabling flag is invalid and the second enabling flag is valid; if the preset condition is not met, the first enabling flag and the second enabling flag are determined according to the fifth enabling flag and the sixth enabling flag, wherein the preset condition comprises that the fourth enabling flag, the fifth enabling flag, and the sixth enabling flag are all valid.

[0159] For example, on the processing device side, if at least one of Early-DBT and Late-DBT of the previous draw call is enabled, that is, at least one of the third enabling flag and the fourth enabling flag is valid; and at least one of Early-Z and Late-Z of the current draw call is enabled, that is, at least one of the fifth enabling flag and the sixth enabling flag is valid, the second depth interval and the third depth interval are combined to determine the third enabling flag and the fourth enabling flag of the previous draw call and the fifth enabling flag and the sixth enabling flag of the current draw call.

[0160] In some possible implementation manners, if Late-DBT of the previous draw call is enabled, that is, the fourth enabling flag is valid; and Early-Z and Late-Z of the current draw call are both enabled, that is, the fifth enabling flag and the sixth enabling flag are both valid, the previous analysis and Figure 8 If the second depth interval is consistent with the third depth interval, the Early-DBT result is correct and can be enabled; if the second depth interval is inconsistent with the third depth interval, the Early-DBT result is incorrect and cannot be enabled.

[0161] In this case, the preset condition of the enabling flag includes that the fourth enabling flag, the fifth enabling flag and the sixth enabling flag are all valid; if the preset condition is met and the second depth interval is consistent with the third depth interval, the first enabling flag is set to be valid and the second enabling flag is set to be valid, that is, Early-DBT and Late-DBT are both enabled; if the preset condition is met and the second depth interval is inconsistent with the third depth interval, the first enabling flag is set to be invalid and the second enabling flag is set to be valid, that is, Early-DBT is disabled and Late-DBT is enabled.

[0162] In some possible implementation manners, if the preset condition is not met, that is, the fourth enabling flag, the fifth enabling flag and the sixth enabling flag are not valid at the same time, and the foregoing analysis and Figure 8 , whether the depth intervals are consistent does not affect the result of Early-DBT. In this case, the first enabling flag and the second enabling flag can be determined according to the fifth enabling flag and the sixth enabling flag, that is, the first enabling flag is consistent with the fifth enabling flag and the second enabling flag is consistent with the sixth enabling flag, so as to keep the opening and closing states of Early-DBT and Late-DBT consistent with those of Early-Z and Late-Z.

[0163] In this way, the depth range test and the depth test can be cooperated while the correctness of the DBT processing result is ensured, invalid fragments are removed in advance before the depth test, unnecessary pixel shader execution is reduced, rendering efficiency is improved, and overall power consumption is reduced.

[0164] In some possible implementation manners, after the first enabling flag, the second enabling flag and the second depth interval are determined, that is, the first driving information of the current first drawing call is obtained, the driving layer can perform data packaging and transmission in step S33, and instruction information is generated according to the first driving information, that is, the first enabling flag, the second enabling flag and the second depth interval are encoded into a hardware instruction package. The instruction information can also include an identifier of a data format of a depth buffer, to adapt a comparison logic of a hardware module of a graphics processing device, and the present disclosure does not limit this.

[0165] In some possible implementation manners, the generated instruction information is sent to the graphics processing device; after the graphics processing device receives the instruction information, the graphics processing device can perform the depth range test in the first drawing call based on the instruction information, so as to implement the DBT function.

[0166] Figure 9 A flowchart of a rendering processing method provided by an embodiment of the present disclosure. The method can be performed by a graphics processing device in a terminal device, for example, a GPU. Referring to Figure 9 , the method includes:

[0167] In step S91, first driving information of a depth range test DBT of a current first drawing call of a rendering object is acquired, the depth range test including early DBT and late DBT, the first driving information including a first enabling flag of the early DBT, a second enabling flag of the late DBT, and a second depth interval of the depth range test.

[0168] In step S92, in response to the first drawing call, a first primitive in a tile of the rendering object is rasterized to obtain a corresponding first fragment.

[0169] In step S93, in a case where the first enabling flag is valid, the first fragment is subjected to depth range test according to the second depth interval to obtain an early DBT result of the first fragment.

[0170] In step S94, in a case where the early DBT result of the first fragment is passed, the first fragment is subjected to early depth test and rendering processing, and a second fragment after rendering is obtained in a case where the early depth test is passed.

[0171] In step S95, in a case where the second enabling flag is valid, the second fragment is subjected to depth range test according to the second depth interval to obtain a late DBT result of the second fragment.

[0172] In step S96, in a case where the late DBT result of the second fragment is passed, the second fragment is subjected to late depth test and rendering processing, and first pixel data after rendering is obtained in a case where the late depth test is passed.

[0173] For example, after receiving the instruction information sent by the processing device, the graphics processing device can determine the first driving information of the DBT of the current first drawing call of the rendering object in step S91, including the first enabling flag of the early DBT, the second enabling flag of the late DBT, and the second depth interval of the DBT.

[0174] In some possible implementation manners, the rendering manner of the rendering object includes tile-based deferred rendering TBDR, wherein the rendering object is divided into a plurality of tiles, and the rendering object includes a plurality of primitives, each tile in the plurality of tiles being covered by at least one primitive of the rendering object, and the first primitive is any one of the plurality of primitives.

[0175] In some possible implementation manners, in response to the current first drawing call, the rendering processing can be performed in combination with the rendering architecture shown in Figure 4 As shown in FIG. 1, the rendering architecture includes a processing device 10 and a graphics processing device 20. Figure 4As shown, the graphics processing device reads geometric data from the system memory, and through the processing of the vertex processing 401 and the clipping, projection, and culling 402 stages, primitive elements of the rendering object are obtained; in the tiling 403 stage, the rendering object is segmented, and the graphic data covering each tile, including the primitive element list, vertex data, etc., is recorded and written into the system memory.

[0176] In some possible implementation manners, for any primitive element in any tile of the rendering object, which is referred to as the first primitive element, rasterization processing may be performed on the first primitive element in step S92 to obtain the corresponding first fragment.

[0177] In the Early-Z execution stage of the first fragment, it is judged whether the first enable flag of Early-DBT is valid; if the first enable flag is valid, then in step S93, Early-DBT is performed on the first fragment according to the second depth interval, that is, depth range testing is performed through the DBT module.

[0178] In some possible implementation manners, step S93 may include: reading the depth value corresponding to the position information from the on-chip depth cache of the graphics processing device according to the position information of the first fragment; when the depth value is within the second depth interval, determining that the early DBT result of the first fragment passes. Among them, the position information may include the position coordinates of the pixel point corresponding to the first fragment on the screen.

[0179] For example, according to this position information, as Figure 4 shown, the DBT module may read the depth value z-buffer corresponding to this position information from the on-chip depth cache of the graphics processing device; and compare this depth value with the second depth interval. If this depth value is within the second depth interval, that is, zmin ≤ z-buffer ≤ zmax, then the early DBT result of the first fragment passes, and the subsequent Early-Z processing is continued.

[0180] On the contrary, if this depth value is outside the second depth interval, that is, z-buffer < zmin or z-buffer > zmax, then the early DBT result of the first fragment fails, and it is directly discarded, and the subsequent Early-Z processing and other processing steps are skipped.

[0181] By performing Early-DBT before Early-Z, fragments outside the preset depth interval can be culled at the earliest stage, significantly reducing the ineffective execution of subsequent depth testing and pixel shaders, thereby improving the overall rendering performance.

[0182] In some possible implementation manners, the rendering processing method according to the embodiments of the present disclosure further includes: in a case where the first enabling flag is invalid, determining that the early DBT result of the first patch is passed. That is, if the first enabling flag is invalid, the early DBT processing procedure can be skipped, it is considered that the early DBT result of the first patch is passed, and the subsequent Early-Z processing and other processing are directly performed. In this way, it can be determined whether to perform DBT according to the enabling flag, and the processing efficiency and flexibility of processing are improved.

[0183] In some possible implementation manners, in a case where the early DBT result of the first patch is passed, the first patch can be subjected to early depth testing (Early-Z) and rendering processing in step S94. If the enabling flag of Early-Z is invalid, Early-Z is skipped, and the rendering of the patch is directly performed; if the enabling flag of Early-Z is valid, Early-Z is performed, and the rendering of the patch is performed after Early-Z is passed. As shown in FIG. 4B, the rendering processing can include texture and shadow 407 and alpha test 408, and after the processing, the rendered second patch is obtained. Figure 4

[0184] In some possible implementation manners, in the Late-Z execution stage, it can be judged whether the second enabling flag of Late-DBT is valid; if the second enabling flag is valid, the second patch is subjected to Late-DBT according to the second depth interval in step S95, that is, subjected to depth range testing by the DBT module.

[0185] Similarly, according to the position information of the second patch, the DBT module can read the current depth value corresponding to the position information from the on-chip depth buffer of the graphics processing device; and compare the depth value with the second depth interval. If the depth value is within the second depth interval, the late DBT result of the second patch is passed, and the subsequent Late-Z processing is continued.

[0186] Conversely, if the depth value is outside the second depth interval, the late DBT result of the second patch is not passed, and the subsequent Late-Z processing and other processing steps are directly skipped.

[0187] By performing Late-DBT before Late-Z, the residual patch whose depth exceeds the depth interval can be subjected to secondary culling, further reducing the memory bandwidth pressure and power consumption overhead caused by patch processing, and optimizing the utilization rate of hardware resources.

[0188] ​In some possible implementations, the rendering processing method according to embodiments of this disclosure further includes: if the second enable flag is invalid, determining that the post-DBT result of the second fragment is passed. That is, if the second enable flag is invalid, the post-DBT processing can be skipped, the post-DBT result of the second fragment is considered passed, and subsequent Late-Z processing and other processing can be directly executed. In this way, it is possible to determine whether to perform DBT based on the enable flag, improving processing efficiency and flexibility.

[0189] In some possible implementations, if the late-stage depth testing (DBT) result of the first fragment is passed, the second fragment can undergo late-stage depth testing (Late-Z) and rendering in step S964. Specifically, if the Late-Z enable flag is invalid, Late-Z is skipped, and fragment rendering proceeds directly; if the Late-Z enable flag is valid, Late-Z is executed, and fragment rendering proceeds after Late-Z passes.

[0190] like Figure 4 As shown, the rendering process may include α blending 411 and other processing, after which the rendered first pixel data is obtained. This completes the entire rendering process for the first primitive.

[0191] According to the rendering processing method of this disclosure, the Depth Range Test (DBT) is combined with the Z-test, allowing the DBT to be configured during the drawing call. The processing device obtains the configuration information of the depth range test for the current drawing call. Based on the DBT configuration and depth test configuration of the previous drawing call and the depth test configuration of the current drawing call, the DBT driver information for the current drawing call is determined. Then, corresponding instruction information is generated and issued, causing the graphics processing device to perform the depth range test, thereby further removing invalid fragments based on the depth test, reducing unnecessary pixel shader execution, improving rendering efficiency, and reducing overall power consumption.

[0192] According to the rendering processing method of this disclosure, the depth range test is divided into early DBT (Early-DBT) and late DBT (Late-DBT); and early DBT works in conjunction with early depth test (Early-Z), and late DBT works in conjunction with late depth test (Late-Z), which can reduce unnecessary calculations for early depth test and late depth test, optimize performance and ensure the correctness of DBT results respectively.

[0193] According to the rendering processing method provided in the embodiments of the present disclosure, the DBT hardware module is arranged in the graphic processing device, and the depth range test can be respectively implemented before Early-Z and before Late-Z. In this way, by performing Early-DBT before Early-Z, the pixels outside the preset depth interval can be removed at the earliest stage, and the invalid execution of the subsequent depth test and pixel shader can be significantly reduced, thereby improving the overall rendering performance; by performing Late-DBT before Late-Z, the residual pixels whose depth exceeds the depth interval can be removed again, and the memory bandwidth pressure and power consumption overhead caused by the pixel processing can be further reduced, thereby optimizing the utilization rate of hardware resources.

[0194] In addition, by segmenting rendering for different depth intervals, special visual effects based on depth can be realized, such as depth contouring, layered volume fog, depth of field blur, perspective deformation, and the like, thereby giving the rendering system more flexibility and scalability.

[0195] It can be understood that the above-mentioned various method embodiments of the present disclosure can be combined with each other to form combined embodiments without deviating from the principle logic. Limited by the length of the present disclosure, the present disclosure will not be described again. Those skilled in the art can understand that in the above-mentioned method of the specific embodiment, the specific execution order of each step should be determined according to its function and possible internal logic.

[0196] In addition, the present disclosure also provides a rendering processing apparatus, an electronic device, and a computer readable storage medium, all of which can be used to implement any one of the rendering processing methods provided by the present disclosure. The corresponding technical solutions and descriptions are described in the method part and will not be described again.

[0197] Figure 10 A block diagram of a rendering processing apparatus provided in the embodiments of the present disclosure is shown in FIG. 8.

[0198] Referring to Figure 10 The embodiments of the present disclosure provide a rendering processing apparatus, which comprises: a configuration information acquisition module 81 configured to acquire first configuration information of a depth range test DBT of a current first drawing call of a rendering object, wherein the first configuration information comprises a switch state of the depth range test and a first depth interval.

[0199] The driving information determination module 82 is configured to, when the switch state of the depth range test is turned on, determine, according to the first configuration information, second configuration information of the depth test of the first drawing call, and second driving information of the depth range test of the second drawing call, first driving information of the depth range test of the first drawing call. The second drawing call is a previous drawing call of the rendering object; the depth range test includes early DBT and late DBT, and the first driving information includes a first enabling flag of the early DBT, a second enabling flag of the late DBT, and a second depth interval of the depth range test.

[0200] The instruction sending module 83 is configured to generate instruction information according to the first driving information and send the instruction information to a graphics processing device, so that the graphics processing device performs the depth range test in the first drawing call based on the instruction information.

[0201] In some possible implementation manners, the second driving information includes a third enabling flag of the early DBT, a fourth enabling flag of the late DBT, and a third depth interval of the depth range test, and the driving information determination module 82 is configured to: perform data verification and format conversion on the first depth interval to obtain the second depth interval; when the third enabling flag and the fourth enabling flag are both invalid, determine the first enabling flag and the second enabling flag according to the second configuration information; and when at least one of the third enabling flag and the fourth enabling flag is valid, determine the first enabling flag and the second enabling flag according to a difference between the second depth interval and the third depth interval, the third enabling flag, the fourth enabling flag, and the second configuration information.

[0202] In some possible implementation manners, the depth test includes early depth test and late depth test, and the second configuration information includes a fifth enabling flag of the early depth test and a sixth enabling flag of the late depth test; and the driving information determination module 82 is configured to: when the fifth enabling flag and the sixth enabling flag are both invalid, determine that the first enabling flag is valid and the second enabling flag is invalid; and when at least one of the fifth enabling flag and the sixth enabling flag is valid, determine the first enabling flag and the second enabling flag according to the fifth enabling flag and the sixth enabling flag.

[0203] In some possible implementation manners, the driving information determination module 82 is configured to:

[0204] In a case where the fifth enabling flag and the sixth enabling flag are both invalid, the first enabling flag and the second enabling flag are determined by: if the third enabling flag is valid and the fourth enabling flag is invalid, determining that the first enabling flag is valid and the second enabling flag is invalid; if the fourth enabling flag is valid and the second depth interval is consistent with the third depth interval, determining that the first enabling flag is valid and the second enabling flag is valid; and if the fourth enabling flag is valid and the second depth interval is inconsistent with the third depth interval, determining that the first enabling flag is invalid and the second enabling flag is valid.

[0205] In some possible implementation manners, the driving information determination module 82 is configured to: in a case where at least one of the fifth enabling flag and the sixth enabling flag is valid, determine the first enabling flag and the second enabling flag by: if a preset condition of an enabling flag is met and the second depth interval is consistent with the third depth interval, determining that the first enabling flag is valid and the second enabling flag is valid; if the preset condition is met and the second depth interval is inconsistent with the third depth interval, determining that the first enabling flag is invalid and the second enabling flag is valid; and if the preset condition is not met, determining the first enabling flag and the second enabling flag according to the fifth enabling flag and the sixth enabling flag, wherein the preset condition comprises that the fourth enabling flag, the fifth enabling flag, and the sixth enabling flag are all valid.

[0206] In some possible implementation manners, the driving information determination module 82 is configured to: perform data verification on minimum and maximum depth values of the first depth interval, and determine verified minimum and maximum depth values; and perform numerical conversion on the verified minimum and maximum depth values according to a data format of a depth buffer of the graphics processing device, and determine the second depth interval.

[0207] According to an embodiment of the present disclosure, a rendering processing apparatus is also provided, which comprises: a driving information obtaining module, configured to obtain first driving information of a depth range test (DBT) of a first drawing call of a rendering object, the depth range test comprising an early DBT and a late DBT, and the first driving information comprising a first enabling flag of the early DBT, a second enabling flag of the late DBT, and a second depth interval of the depth range test; a rasterization processing module, configured to perform rasterization processing on a first primitive in a tile of the rendering object to obtain a corresponding first fragment in response to the first drawing call; a first DBT module, configured to perform a depth range test on the first fragment according to the second depth interval to obtain an early DBT result of the first fragment in a case where the first enabling flag is valid; a first depth test and rendering module, configured to perform early depth test and rendering processing on the first fragment, and obtain a second fragment after rendering in a case where the early DBT result of the first fragment is passed; a second DBT module, configured to perform a depth range test on the second fragment according to the second depth interval to obtain a late DBT result of the second fragment in a case where the second enabling flag is valid; and a second depth test and rendering module, configured to perform late depth test and rendering processing on the second fragment, and obtain first pixel data after rendering in a case where the late DBT result of the second fragment is passed.

[0208] In some possible implementation ways, the first DBT module is further configured to determine that the early DBT result of the first fragment is passed in a case where the first enabling flag is invalid, or the second DBT module is further configured to determine that the late DBT result of the second fragment is passed in a case where the second enabling flag is invalid.

[0209] In some possible implementation ways, the first DBT module is configured to read a depth value corresponding to position information of the first fragment from a depth cache on a chip of a graphics processing device according to the position information, and determine that the early DBT result of the first fragment is passed in a case where the depth value is in the second depth interval.

[0210] In some possible implementation ways, the rendering manner of the rendering object comprises tile-based deferred rendering (TBDR), wherein the rendering object is divided into a plurality of tiles, and the rendering object comprises a plurality of primitives, each of the plurality of tiles is covered by at least one primitive of the rendering object, and the first primitive is any one of the plurality of primitives.

[0211] Figure 11 A block diagram of an electronic device according to an embodiment of the present disclosure is provided.

[0212] Referring to Figure 11 The electronic device provided by the embodiments of the present disclosure includes: at least one processor 701; at least one memory 702, and one or more I / O interfaces 703 connected between the processor 701 and the memory 702; wherein the memory 702 stores one or more computer programs executable by the at least one processor 701, and the one or more computer programs are executed by the at least one processor 701 to enable the at least one processor 701 to perform the rendering processing method described above.

[0213] The embodiments of the present disclosure also provide a computer-readable storage medium having a computer program stored thereon, wherein the computer program, when executed by a processor, implements the rendering processing method described above. The computer-readable storage medium can be a volatile or non-volatile computer-readable storage medium.

[0214] The embodiments of the present disclosure also provide a computer program product including computer-readable code, or a non-volatile computer-readable storage medium carrying computer-readable code, when the computer-readable code is run in the processor of the electronic device, the processor in the electronic device performs the rendering processing method described above.

[0215] Those skilled in the art can understand that all or some steps in the method disclosed above, the functions of the modules / units in the system and the device can be implemented as software, firmware, hardware and their appropriate combinations. In the hardware implementation, the division between the functional modules / units mentioned in the above description does not necessarily correspond to the division of physical components; for example, one physical component can have multiple functions, or one function or step can be performed by several physical components in cooperation. Some or all physical components can be implemented as software executed by a processor, such as a central processing unit, a digital signal processor or a microprocessor, or as hardware, or as an integrated circuit, such as an application-specific integrated circuit. Such software can be distributed on a computer-readable storage medium, which can include computer storage media (or non-transitory media) and communication media (or transitory media).

[0216] As those skilled in the art will appreciate, the term computer storage media includes volatile and non-volatile, removable and non-removable media implemented in any method or technology for storage of information such as computer readable program instructions, data structures, program modules or other data. Computer storage media include, but are not limited to, random access memory (RAM), read only memory (ROM), erasable programmable read only memory (EPROM), electrically erasable programmable read only memory (EEPROM), static random access memory (SRAM), flash memory or other memory technology, portable compact disc read only memory (CD-ROM), digital versatile disk (DVD) or other optical disk storage, magnetic cassettes, magnetic tape, magnetic disk storage or other magnetic storage devices, or any other medium which can be used to store the desired information and which can be accessed by a computer. Further, as those skilled in the art will appreciate, communication media typically embodies computer readable program instructions, data structures, program modules or other data in a modulated data signal such as a carrier wave or other transport mechanism and includes any information delivery media. The term "modulated data signal" means a signal that has one or more of its characteristics changed or set in a manner so as to encode information in the signal. By way of example, and not limitation, communication media includes wired media such as a wired network or direct-wired connection, and wireless media such as wireless networks, cellular telephone networks, code division multiple access (CDMA) networks, and other terrestrial and satellite radio frequency communication networks. Thus the computer readable program instructions and / or other program modules can be embodied in a computer readable storage medium, which can be any device or article that is enab!ed to store and / or carry computer readable program instructions and / or data structures. The computer readable storage medium can also be distributed over networked computer systems so that the computer readable program instructions and / or other program modules are stored and executed in a distributed fashion.

[0217] Computer readable program instructions described herein can be downloaded to respective computing / processing devices from a computer readable storage medium or to an external computer or external storage device via a network, for example, the Internet, a local area network, a wide area network and / or a wireless network. The network can comprise copper transmission cables, optical transmission fibers, wireless transmission, routers, firewalls, switches, gateway computers and / or edge servers. A network adapter card or network interface in each computing / processing device receives computer readable program instructions from the network and forwards the computer readable program instructions for storage in a computer readable storage medium within the respective computing / processing device.

[0218] Computer readable program instructions for carrying out operations of the present disclosure can be assembly instructions, instruction set architecture (ISA) instructions, machine instructions, machine dependent instructions, microcode, firmware instructions, state setting data, or any combination of one or more of the above in any combination, written in any combination of one or more programming languages, including object oriented programming languages such as Smalltalk, C++ or the like, and conventional procedural programming languages, such as the "C" programming language or similar programming languages. The computer readable program instructions can execute entirely on the user's computer, partly on the user's computer, as a stand-alone software package, partly on the user's computer and partly on a remote computer or entirely on the remote computer or server. In the latter scenario, the remote computer can be connected to the user's computer through any type of network, including a local area network (LAN) or a wide area network (WAN), or the connection can be made to an external computer (for example, through the Internet using an Internet Service Provider). In some embodiments, electronic circuitry including, for example, programmable logic circuitry, field-programmable gate array (FPGA), or programmable logic array (PLA) can execute the computer readable program instructions by utilizing state information of the computer readable program instructions to personalize the electronic circuitry, in order to perform aspects of the present disclosure.

[0219] The computer program product described herein can be embodied in a specific manner by hardware, software, or a combination thereof. In an optional embodiment, the computer program product is embodied as a computer storage medium. In another optional embodiment, the computer program product is embodied as a software product, such as a software development kit (SDK), and the like.

[0220] The various aspects of the present disclosure are described herein with reference to flow diagrams and / or block diagrams of methods, apparatus (systems) and computer program products according to embodiments of the present disclosure. It will be understood that each block of the flow diagrams and / or block diagrams, and combinations of blocks in the flow diagrams and / or block diagrams, can be implemented by computer readable program instructions.

[0221] These computer readable program instructions can be provided to a processor of a general purpose computer, special purpose computer, or other programmable data processing apparatus to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing apparatus, create means for implementing the functions / acts specified in the flowchart and / or block diagram block or blocks. These computer readable program instructions can also be stored in a computer readable storage medium that can include a non-transitory computer readable storage medium that can be a computer- readable storage medium having no data storage viruses or other code or instructions implementing a functionally equivalent process, such that the instructions, defining functions described by the flowchart and / or block diagram block or blocks are stored in the computer readable storage medium.

[0222] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0223] The computer readable program instructions can also be loaded onto a computer, other programmable data processing apparatus, or other device to cause a series of operational steps to be performed on the computer, other programmable apparatus or other device to produce a computer implemented process, such that the instructions which execute on the computer, other programmable data processing apparatus, or other device implement the functions / acts specified in the flowchart and / or block diagram block or blocks.

[0224] Example embodiments have been disclosed herein and, although specific terms are employed, they are used in a generic and descriptive sense only and not for purposes of limitation. In some instances, it will be apparent to those skilled in the art that features, characteristics or elements described with reference to one particular embodiment can be used, combined or modified for use with other embodiments, unless specifically noted otherwise. Accordingly, it will be understood by those skilled in the art that various changes in form and details can be made without departing from the scope of the disclosure as set forth in the appended claims.

Claims

1. A rendering processing method characterized by, The method comprises: obtaining first configuration information of a current depth range test (DBT) of a first draw call of a rendering object, the first configuration information comprising a switch state of the depth range test and a first depth interval; in a case where the switch state of the depth range test is on, determining first driving information of the depth range test of the first draw call according to the first configuration information, second configuration information of a depth test of the first draw call, and second driving information of a depth range test of a second draw call; wherein the second draw call is a previous draw call of the rendering object; the depth range test comprises early DBT and late DBT; and the first driving information comprises a first enable flag of the early DBT, a second enable flag of the late DBT, and a second depth interval of the depth range test; generating instruction information according to the first driving information and sending the instruction information to a graphics processing device, so that the graphics processing device performs the depth range test in the first draw call based on the instruction information; the second driving information comprises a third enable flag of the early DBT, a fourth enable flag of the late DBT, and a third depth interval of the depth range test, wherein the determining the first driving information of the depth range test of the first draw call comprises: performing data verification and format conversion on the first depth interval to obtain the second depth interval; in a case where the third enable flag and the fourth enable flag are both invalid, determining the first enable flag and the second enable flag according to the second configuration information; in a case where at least one of the third enable flag and the fourth enable flag is valid, determining the first enable flag and the second enable flag according to a difference between the second depth interval and the third depth interval, the third enable flag, the fourth enable flag, and the second configuration information.

2. The method of claim 1, wherein, the depth test comprises early depth test and late depth test, and the second configuration information comprises a fifth enable flag of the early depth test and a sixth enable flag of the late depth test; wherein the determining the first enable flag and the second enable flag according to the second configuration information in a case where the third enable flag and the fourth enable flag are both invalid comprises: in a case where the fifth enable flag and the sixth enable flag are both invalid, determining that the first enable flag is valid and the second enable flag is invalid; in a case where at least one of the fifth enable flag and the sixth enable flag is valid, determining the first enable flag and the second enable flag according to the fifth enable flag and the sixth enable flag.

3. The method of claim 1, wherein, the depth test comprises early depth test and late depth test, and the second configuration information comprises a fifth enable flag of the early depth test and a sixth enable flag of the late depth test; The first enabling flag and the second enabling flag are determined according to the difference between the second depth interval and the third depth interval, the third enabling flag, the fourth enabling flag and the second configuration information when at least one of the third enabling flag and the fourth enabling flag is valid, including: The first enabling flag and the second enabling flag are determined by the following way when the fifth enabling flag and the sixth enabling flag are both invalid: If the third enabling flag is valid and the fourth enabling flag is invalid, it is determined that the first enabling flag is valid and the second enabling flag is invalid; If the fourth enabling flag is valid and the second depth interval is consistent with the third depth interval, it is determined that the first enabling flag is valid and the second enabling flag is valid; If the fourth enabling flag is valid and the second depth interval is inconsistent with the third depth interval, it is determined that the first enabling flag is invalid and the second enabling flag is valid.

4. The method of claim 1, wherein, The depth test includes an early depth test and a late depth test, and the second configuration information includes a fifth enabling flag of the early depth test and a sixth enabling flag of the late depth test; The first enabling flag and the second enabling flag are determined according to the difference between the second depth interval and the third depth interval, the third enabling flag, the fourth enabling flag and the second configuration information when at least one of the third enabling flag and the fourth enabling flag is valid, including: The first enabling flag and the second enabling flag are determined by the following way when at least one of the fifth enabling flag and the sixth enabling flag is valid: If the preset condition of the enabling flag is met and the second depth interval is consistent with the third depth interval, it is determined that the first enabling flag is valid and the second enabling flag is valid; If the preset condition is met and the second depth interval is inconsistent with the third depth interval, it is determined that the first enabling flag is invalid and the second enabling flag is valid; If the preset condition is not met, the first enabling flag and the second enabling flag are determined according to the fifth enabling flag and the sixth enabling flag, The preset condition includes that the fourth enabling flag, the fifth enabling flag and the sixth enabling flag are all valid.

5. The method of claim 1, wherein, The data verification and format conversion on the first depth interval to obtain the second depth interval include: Data verification is performed on the minimum depth value and the maximum depth value of the first depth interval to determine the verified minimum depth value and the verified maximum depth value; Numerical conversion is performed on the verified minimum depth value and the verified maximum depth value according to the data format of the depth buffer of the graphic processing device to determine the second depth interval.

6. A rendering processing method characterized by, including: obtain first driving information of a depth range test DBT of a current first drawing call of a rendering object, the depth range test including early DBT and late DBT, the first driving information including a first enabling flag of the early DBT, a second enabling flag of the late DBT, and a second depth interval of the depth range test; in response to the first drawing call, perform rasterization processing on a first primitive in a tile of the rendering object to obtain a corresponding first fragment; in a case where the first enabling flag is valid, perform depth range test on the first fragment according to the second depth interval to obtain an early DBT result of the first fragment; in a case where the early DBT result of the first fragment is passed, perform early depth test and rendering processing on the first fragment, and obtain a second fragment after rendering in a case where the early depth test is passed; in a case where the second enabling flag is valid, perform depth range test on the second fragment according to the second depth interval to obtain a late DBT result of the second fragment; in a case where the late DBT result of the second fragment is passed, perform late depth test and rendering processing on the second fragment, and obtain first pixel data after rendering in a case where the late depth test is passed.

7. The method of claim 6, wherein, The method further includes: in a case where the first enabling flag is invalid, determining that the early DBT result of the first fragment is passed; or in a case where the second enabling flag is invalid, determining that the late DBT result of the second fragment is passed.

8. The method of claim 6, wherein, performing depth range test on the first fragment according to the second depth interval to obtain an early DBT result of the first fragment includes: reading a depth value corresponding to position information of the first fragment from an on-chip depth cache of a graphics processing device according to the position information of the first fragment; in a case where the depth value is in the second depth interval, determining that the early DBT result of the first fragment is passed.

9. The method of claim 6, wherein, The rendering manner of the rendering object includes tile-based deferred rendering TBDR, wherein the rendering object is divided into a plurality of tiles, and the rendering object includes a plurality of primitives, each tile in the plurality of tiles is covered by at least one primitive of the rendering object, and the first primitive is any one of the plurality of primitives.

10. A rendering processing apparatus characterized by comprising: It includes: a configuration information obtaining module configured to obtain first configuration information of a depth range test DBT of a current first drawing call of a rendering object, the first configuration information including a switch state of the depth range test and a first depth interval; a driving information determining module configured to, in a case where the switch state of the depth range test is on, determine first driving information of the depth range test of the first drawing call according to the first configuration information, second configuration information of depth test of the first drawing call, and second driving information of depth range test of a second drawing call. The second drawing call is a pre-drawing call of the rendering object; the depth range test comprises an early DBT and a late DBT, the first driving information comprises a first enabling flag of the early DBT, a second enabling flag of the late DBT, and a second depth interval of the depth range test; The instruction sending module is configured to generate instruction information according to the first driving information and send the instruction information to the graphic processing device, so that the graphic processing device performs the depth range test in the first drawing call based on the instruction information, The second driving information comprises a third enabling flag of the early DBT, a fourth enabling flag of the late DBT, and a third depth interval of the depth range test, wherein the driving information determination module is configured to: perform data verification and format conversion on the first depth interval to obtain the second depth interval; in a case where the third enabling flag and the fourth enabling flag are both invalid, determine the first enabling flag and the second enabling flag according to the second configuration information; in a case where at least one of the third enabling flag and the fourth enabling flag is valid, determine the first enabling flag and the second enabling flag according to a difference between the second depth interval and the third depth interval, the third enabling flag, the fourth enabling flag, and the second configuration information.

11. An electronic device, comprising: comprise: at least one processor; and a memory connected with the at least one processor in communication; wherein the memory stores one or more computer programs executable by the at least one processor, and the one or more computer programs are executed by the at least one processor to enable the at least one processor to perform the rendering processing method according to any one of claims 1-9.

12. A computer readable storage medium having stored thereon a computer program, characterized in that, The computer program, when executed by the processor, implements the rendering processing method according to any one of claims 1-9.

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