Display device

Abstract

Provided is a display device capable of reducing power consumption. The display device includes: a first transistor, a switch of which is controlled with a first control signal, and which is connected between an image data signal line to which a data voltage is supplied and a first node; a third transistor which controls a switch with a first control signal and is connected between the first node and the second node; a second transistor having a gate electrode connected to a second node, and connected between a power supply line to which a constant voltage is supplied and a third node; a fourth transistor that controls a switch with the first control signal and is connected between a reference voltage power supply line to which a reference voltage is supplied and the second node; and a fifth transistor that controls the switch with a second control signal different from the first control signal and is connected between an initialization voltage power supply line to which an initialization voltage is supplied and the third node.

Description

Technical Field

[0001] One embodiment of the present invention relates to a display device. Background Art

[0002] In recent years, self-luminous display devices have been installed in televisions, smartphones, digital signage (electronic signboards, electronic advertising boards, etc.), and have become increasingly popular. For example, a self-luminous display device includes a plurality of pixels and a control circuit for driving the plurality of pixels. For example, the plurality of pixels each include a plurality of transistors, capacitors, and light-emitting elements. A light-emitting element is an element that emits light in a self-luminous manner, such as a light-emitting diode (LED), a tiny light-emitting diode (microLED), or an organic electroluminescence (EL) element. In a self-luminous display device, a voltage is supplied to each of the plurality of pixels through a control circuit, so that a current corresponding to the supplied voltage value flows to the light-emitting elements included in each of the plurality of pixels. The light-emitting elements each emit light at a brightness corresponding to the current flowing to the light-emitting elements, and the pixel including the light-emitting element can display an image at a grayscale corresponding to the brightness.

[0003] For example, Patent Document 1 discloses an EL display device that takes increasing the brightness of the EL element during the lighting period as a technical issue, focuses on the distortion of the pulse waveform to address the problem of increased power and circuit scale, and enables appropriate threshold correction action to be implemented by reducing the drain current of the driving transistor.

[0004] Patent Document 1: Japanese Patent Application Laid-Open No. 2011-164133 Summary of the Invention

[0005] As exemplified in Patent Document 1, self-luminous display devices that include an EL display device have the problem of increased power consumption and circuit size. Therefore, for example, a technical challenge in self-luminous display devices is to reduce power consumption. Another technical challenge in self-luminous display devices is to reduce circuit size.

[0006] In view of such technical problems, one embodiment of the present invention has as one object to provide a display device capable of reducing power consumption. Another embodiment of the present invention has as one object to provide a display device capable of reducing circuit scale.

[0007] A display device according to one embodiment of the present invention includes: a first transistor, the switching of which is controlled by a first control signal, the first transistor being electrically connected between an image data signal line and a first node, the image data signal line being supplied with a data voltage; a third transistor, the switching of which is controlled by the first control signal, the third transistor being electrically connected between the first node and a second node; a second transistor having a gate electrode electrically connected to the second node, the second transistor being electrically connected between a power supply line and a third node, the power supply line being supplied with a constant voltage; a fourth transistor, the switching of which is controlled by the first control signal, the fourth transistor being electrically connected between a reference voltage power supply line and the second node, the reference voltage power supply line being supplied with a reference voltage; a fifth transistor, the switching of which is controlled by a second control signal different from the first control signal, the fifth transistor being electrically connected between an initialization voltage power supply line and the third node, the initialization voltage power supply line being supplied with an initialization voltage; a light-emitting element being electrically connected to the third node; and a capacitor element being electrically connected between the first node and the third node.

[0008] A display device according to one embodiment of the present invention includes: a first transistor, the switching of which is controlled by a first control signal, and the first transistor is electrically connected between an image data signal line and a first node, the image data signal line being supplied with a data voltage; a third transistor, the switching of which is controlled by the first control signal, and the transistor being electrically connected between the first node and a third node; a second transistor, the transistor having a gate electrode electrically connected to the second node, the transistor being electrically connected between the third node and a fourth node; and a fourth transistor, the switching of which is controlled by the first control signal, the transistor being electrically connected between a third control signal line and the third node, the transistor being supplied with a first initialization voltage. and a second initialization voltage, which is different from the first initialization voltage; a fifth transistor, which uses a second control signal different from the first control signal to control the switch of the fifth transistor, and the fifth transistor is electrically connected between a third control signal line and the fourth node; a sixth transistor, which uses the first control signal to control the switch of the sixth transistor, and the sixth transistor is electrically connected between the second node and the fourth node; a seventh transistor, which uses the first control signal to control the switch of the seventh transistor, and the seventh transistor is electrically connected between a power line and the fourth node, and the power line is supplied with a constant voltage; a light-emitting element, which is electrically connected to the third node; and a capacitor element, which is electrically connected between the first node and the second node. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figure 1 This is a schematic diagram showing the structure of a self-luminous display device according to the first embodiment of the present invention.

[0010] Figure 2 Schematic diagram showing input signals to the pixel circuit according to the first embodiment of the present invention.

[0011] Figure 3 This is a circuit diagram showing the configuration of a pixel circuit according to the first embodiment of the present invention.

[0012] Figure 4 This is a timing chart of the self-luminous display device according to the first embodiment of the present invention.

[0013] Figure 5 This is a timing chart of the self-luminous display device according to the first embodiment of the present invention.

[0014] Figure 6 This is a timing chart of the self-luminous display device according to the first embodiment of the present invention.

[0015] Figure 7 This is a timing chart of the self-luminous display device according to the first embodiment of the present invention.

[0016] Figure 8 A timing chart of the self-luminous display device according to the first embodiment of the present invention.

[0017] Figure 9 It is a layout diagram of pixels according to the first embodiment of the present invention.

[0018] Figure 10 It is shown along Figure 9 This is a cross-sectional view of a section taken along line A1 - A2 in the illustrated layout.

[0019] Figure 11 This is a timing chart showing a method for manufacturing the self-luminous display device according to the first embodiment of the present invention.

[0020] Figure 12 It is a layout diagram of pixels according to the first embodiment of the present invention.

[0021] Figure 13 It is a layout diagram of pixels according to the first embodiment of the present invention.

[0022] Figure 14 It is a layout diagram of pixels according to the first embodiment of the present invention.

[0023] Figure 15Schematic diagram showing input signals to a pixel circuit according to the second embodiment of the present invention.

[0024] Figure 16 This is a circuit diagram showing the configuration of a pixel circuit according to the second embodiment of the present invention.

[0025] Figure 17 This is a timing chart of the self-luminous display device according to the second embodiment of the present invention.

[0026] Figure 18 This is a timing chart of the self-luminous display device according to the second embodiment of the present invention.

[0027] Figure 19 This is a timing chart of the self-luminous display device according to the second embodiment of the present invention.

[0028] Figure 20 This is a timing chart of the self-luminous display device according to the second embodiment of the present invention.

[0029] Figure 21 This is a diagram for explaining the setting of input signals according to the second embodiment of the present invention.

[0030] Figure 22 Schematic diagram showing input signals to a pixel circuit according to the third embodiment of the present invention.

[0031] Figure 23 This is a circuit diagram showing the configuration of a pixel circuit according to the third embodiment of the present invention.

[0032] Figure 24 This is a timing chart of the self-luminous display device according to the third embodiment of the present invention.

[0033] Figure 25 This is a timing chart of the self-luminous display device according to the third embodiment of the present invention.

[0034] Figure 26 This is a timing chart of the self-luminous display device according to the third embodiment of the present invention.

[0035] Figure 27 This is a timing chart of the self-luminous display device according to the third embodiment of the present invention.

[0036] Figure 28 This is a diagram for explaining the setting of input signals according to the third embodiment of the present invention.

[0037] Figure 29 Schematic diagram showing input signals to a pixel circuit according to a fourth embodiment of the present invention.

[0038] Figure 30 This is a circuit diagram showing the configuration of a pixel circuit according to a fourth embodiment of the present invention.

[0039] Figure 31 This is a timing chart of the self-luminous display device according to the fourth embodiment of the present invention.

[0040] Figure 32 It is shown in Figure 31 The timing shown Figure 30 Schematic diagram of the operating state of the pixel circuit shown.

[0041] Figure 33 It is shown in Figure 31 The timing shown Figure 30 Schematic diagram of the operating state of the pixel circuit shown.

[0042] Figure 34 This is a timing chart of the self-luminous display device according to the fourth embodiment of the present invention.

[0043] Figure 35 It is shown in Figure 34 The timing shown Figure 30 Schematic diagram of the operating state of the pixel circuit shown.

[0044] Figure 36 This is a timing chart of the self-luminous display device according to the fourth embodiment of the present invention.

[0045] Figure 37 This is a timing chart of the self-luminous display device according to the fourth embodiment of the present invention.

[0046] Figure 38 Schematic diagram showing input signals to a pixel circuit according to a fifth embodiment of the present invention.

[0047] Figure 39 This is a circuit diagram showing the configuration of a pixel circuit according to a fifth embodiment of the present invention.

[0048] Figure 40 This is a timing chart of the self-luminous display device according to the fifth embodiment of the present invention.

[0049] Figure 41 It is shown in Figure 40 The timing shown Figure 39 Schematic diagram of the operating state of the pixel circuit shown.

[0050] Figure 42 It is shown in Figure 40 The timing shown Figure 39 Schematic diagram of the operating state of the pixel circuit shown.

[0051] Figure 43 This is a timing chart of the self-luminous display device according to the fifth embodiment of the present invention.

[0052] Figure 44 It is shown in Figure 43 The timing shown Figure 39 Schematic diagram of the operating state of the pixel circuit shown.

[0053] Figure 45 This is a timing chart of the self-luminous display device according to the fifth embodiment of the present invention.

[0054] Figure 46 This is a timing chart of the self-luminous display device according to the fifth embodiment of the present invention.

[0055] Figure 47 Schematic diagram showing input signals to a pixel circuit according to the sixth embodiment of the present invention.

[0056] Figure 48 This is a circuit diagram showing the configuration of a pixel circuit according to a sixth embodiment of the present invention.

[0057] Figure 49 This is a timing chart of the self-luminous display device according to the sixth embodiment of the present invention.

[0058] Figure 50 This is a timing chart of the self-luminous display device according to the sixth embodiment of the present invention.

[0059] Figure 51 This is a timing chart of the self-luminous display device according to the sixth embodiment of the present invention.

[0060] Figure 52 This is a timing chart of the self-luminous display device according to the sixth embodiment of the present invention.

[0061] Figure 53 Schematic diagram showing input signals to a pixel circuit according to the seventh embodiment of the present invention.

[0062] Figure 54 This is a circuit diagram showing the configuration of a pixel circuit according to the seventh embodiment of the present invention.

[0063] Figure 55 This is a timing chart of the self-luminous display device according to the seventh embodiment of the present invention.

[0064] Figure 56 This is a timing chart of the self-luminous display device according to the seventh embodiment of the present invention.

[0065] Figure 57This is a timing chart of the self-luminous display device according to the seventh embodiment of the present invention.

[0066] Figure 58 This is a timing chart of the self-luminous display device according to the seventh embodiment of the present invention.

[0067] Description of Reference Numerals

[0068] 10: Self-luminous display device, 22: Display area, 24: Peripheral area, 26: Terminal area, 100: Array substrate, 101: Substrate, 101A: First surface, 101B: Second surface, 110: IC chip, 111: Shift register, 112: Shift register, 113: Shift register, 120: First scan driver, 121: Base layer, 122: Semiconductor layer, 122A: Semiconductor layer, 122B: Semiconductor layer, 122C: Semiconductor layer, 123: Channel region, 124A: Impurity region, 125: Gate insulating layer, 126: Conductive layer, 127A: Gate wiring, 127B: Gate wiring, 127C: Gate wiring, 127D: Gate wiring, 12 8: Insulating layer, 130: Second scan driver, 131: Insulating layer, 132: Conductive layer, 132A: First wiring, 132B: First wiring, 132C: First wiring, 132D: First wiring, 132E: First wiring, 132F: First wiring, 132G: First wiring, 132H: First wiring, 135: First contact hole opening, 135A: First contact hole opening, 135B: First contact hole opening, 135C: First contact hole opening, 135D: First contact hole opening, 135E: First contact hole opening, 135F: First contact hole opening, 135G: First contact hole opening, 135H: First contact hole opening, 135J: First contact hole opening, 135K: first contact hole opening, 136: insulating layer, 137: insulating layer, 138: second contact hole opening, 138A: organic insulating film opening, 138B: second contact hole opening, 138C: second contact hole opening, 138D: second contact hole opening, 138E: second contact hole opening, 138F: second contact hole opening, 138G: second contact hole opening, 139: conductive layer, 140A: second wiring, 140B: second wiring, 140C: third wiring, 140D: fourth wiring, 141: insulating layer, 143: anode electrode, 144: first layer, 145: second layer, 146: third layer, 147: contact hole opening, 148: conductive layer, 149: second wiring, 150: third wiring, 151: fourth wiring, 152: third wiring, 153: fourth wiring, 154: fourth wiring, 155: fourth wiring, 156: fourth wiring, 157: fourth wiring, 158: fifth wiring, 159: fifth wiring, 160: fifth wiring, 161: fifth wiring, 162: fifth wiring, 163: sixth wiring, 164: fifth wiring, 165: sixth wiring, 166: seventh wiring, 167: seventh wiring, 168: seventh wiring, 169: eighth wiring, 170: eighth wiring, 171: eighth wiring, 172: eighth wiring, 173: eighth wiring, 174: eighth wiring, 175: eighth wiring, 176: eighth wiring, 177: eighth wiring, 178: eighth wiring, 179: eighth wiring, 180: eighth wiring, 181: eighth wiring, 182: eighth wiring, 183: eighth wiring, 184: eighth wiring, 185 8: Functional layer, 149: Common electrode, 150: Terminal portion, 152: First inorganic insulating layer, 154: Organic insulating layer, 156: Second inorganic insulating layer, 158: Cover film, 160: Flexible printed circuit substrate, 161: Shift register, 162: Shift register, 163: Shift register, 165: Sealing film, 170: Array portion, 180: Pixel, 180A: Pixel, 180B: Pixel, 180C: Pixel, 180D: Pixel, 180E: Pixel, 180F: Pixel, 181: Pixel circuit, 181A: Pixel circuit, 181B: Pixel circuit, 181C: Pixel circuit, 181D: Pixel circuit, 181E: Pixel circuit, 181F: Pixel circuit,321: Image data signal line, 322: Image data signal line, 323: Image data signal line, 329: First scanning signal line, 330: First scanning signal line, 330A: First scanning signal line, 330B: First scanning signal line, 331: First scanning signal line, 332: First scanning signal line, 334: Second scanning signal line, 335: Second scanning signal line, 336: Second scanning signal line, 341: Connection wiring, 342: Connection wiring, 612: Gate electrode, 614: First electrode, 616: Second electrode, 622: Gate electrode, 624: First electrode, 626: Second electrode, 632: Gate electrode, 634: First electrode, 636: Second electrode, 642: Gate electrode, 644: First electrode, 646: Second electrode, 652: Gate electrode , 654: first electrode, 656: second electrode, 682: first electrode, 684: second electrode, 692: first electrode, 694: second electrode, 712: gate electrode, 714: first electrode, 716: second electrode, 722: gate electrode, 724: first electrode, 726: second electrode, 732: gate electrode, 734: first electrode, 736: second electrode, 742: gate electrode, 744: first electrode, 746: second electrode, 752: gate electrode, 754: first electrode, 756: second electrode, 762: gate electrode, 764: first electrode, 766: second electrode, 772: gate electrode, 774: first electrode, 776: second electrode, 782: first electrode, 784: second electrode, 792: first electrode, 794: second electrode. , DETAILED DESCRIPTION

[0069] Hereinafter, with reference to the accompanying drawings, etc., an example of a display device capable of achieving a reduction in power consumption according to various embodiments of the present invention will be described. The present invention can be implemented in a plurality of different ways, and is not limited to the description of the following exemplary embodiments for explanation. In addition, in order to make the explanation clearer, the accompanying drawings sometimes schematically represent the width, thickness, shape, structure, etc. of each part compared to the actual method, but this is ultimately an example and does not limit the explanation of the present invention. It should be noted that the words marked as "first" and "second" for each element are convenient identifiers used to distinguish between the elements, and unless otherwise specified, they have no meaning beyond this.

[0070] In this specification, unless otherwise specified, expressions such as "α includes A, B, or C," "α includes any one of A, B, and C," and "α includes one selected from the group consisting of A, B, and C" do not exclude the case where α includes multiple combinations of A to C. Furthermore, these expressions do not exclude the case where α includes other elements.

[0071] For example, a display device according to one embodiment of the present invention uses an EL element as a self-luminous light-emitting element. For example, a display device using an EL element is sometimes referred to as a self-luminous display device, an EL display device, or the like. For example, in an embodiment of the present invention, a display device using an EL element is referred to as a self-luminous display device.

[0072] <1. First embodiment>

[0073] <1-1. Overview of Self-Luminous Display Device 10 >

[0074] Reference Figure 1 , an overview of the self-luminous display device 10 according to the first embodiment will be described. Figure 1 Schematic diagram showing the structure of the self-luminous display device 10 . Figure 1 The structure of the self-luminous display device 10 shown is an example, and the structure of the self-luminous display device 10 is not limited to Figure 1 The structure shown.

[0075] The self-luminous display device 1 includes an array substrate 100 , a flexible printed circuit board 160 (FPC 160 ), and an IC chip 110 . The self-luminous display device 10 includes a display area 22 provided on the array substrate 100 , a peripheral area 24 surrounding the display area 22 , and a terminal area 26 .

[0076] In the display area 22, a plurality of pixels 180 are arranged in a matrix along a first direction D1 (column direction) and a second direction D2 (row direction) intersecting the first direction D1. A pixel 180 is the smallest unit that constitutes a portion of an image displayed in the display area 22. For example, each of the plurality of pixels 180 may correspond to a sub-pixel R, a sub-pixel G, and a sub-pixel B. Alternatively, a single pixel may be formed from three sub-pixels. The arrangement of the pixels 180 is not limited, and the plurality of pixels 180 may be arranged in a stripe, for example. The self-luminous display device 10 may also be arranged in a delta arrangement, a pentile arrangement, or other arrangements.

[0077] Subpixels R, G, and B are configured to display images of different colors. For example, each of subpixels R, G, and B can include a light-emitting element including a light-emitting layer that emits the three primary colors of red, green, and blue. By supplying an arbitrary voltage or current to each of the three subpixels, the self-luminous display device 10 can display an image.

[0078] The peripheral area 24 includes an IC chip 110, a first scan driver 120, and a second scan driver 130. The IC chip 110 is connected to the terminal portion 150 using a connection wiring 341. The first scan driver 120 and the second scan driver 130 are each connected to the IC chip 110 using a connection wiring 342. The peripheral area 24 is sometimes referred to as a picture frame area. Connection wiring 341 is sometimes referred to as connection wiring 341 alone, or a bundle of multiple connection wirings 341 is sometimes referred to as connection wiring 341. Similarly to connection wiring 341, connection wiring 342 is sometimes referred to as connection wiring 342 alone, or a bundle of multiple connection wirings 342 is sometimes referred to as connection wiring 342.

[0079] The terminal region 26 includes a terminal portion 150 and an FPC 160 electrically connected to the terminal portion 150. The terminal region 26 is a region on the opposite side of the peripheral region 24 where the display region 22 is provided in the first direction D1.

[0080] The FPC 160 is connected to an external device (not shown) outside the self-luminous display device 10. Thus, the self-luminous display device 10 is connected to the external device via the FPC 160 and the terminal portion 150 connected to the FPC. Control signals and voltages are transmitted from the external device to the self-luminous display device 10 via the FPC 160 and the terminal portion 150 connected to the FPC. The self-luminous display device 10 uses the control signals and voltages received from the external device to drive each pixel 180 provided in the self-luminous display device 10. As a result, the self-luminous display device 10 can display an image on the display area 22.

[0081] The IC chip 110 supplies signals, voltages, and the like for driving each pixel 180 to the first scanning driver 120 , the second scanning driver 130 , and each pixel 180 (pixel circuit 181 ) via the FPC 160 , the terminal portion 150 , and the connection wiring 341 .

[0082] In this specification and the accompanying drawings, the IC chip 110, the first scan driver 120, the second scan driver 130 and the IC chip 110 may each be individually referred to as a control circuit, or a circuit group including the IC chip 110, the first scan driver 120, the second scan driver 130 and part or all of the IC chip 110 may be referred to as a control circuit.

[0083] <1-2. Structure of IC Chip 110 >

[0084] Reference Figure 1The IC chip 110 is briefly described. The IC chip 110 is provided adjacent to the display area 22 in the first direction D1. Image data signal lines 321, 322, and 323 extend from the IC chip 110 in the first direction D1 and are connected to a plurality of pixels 180 arranged in the first direction D1.

[0085] For example, IC chip 110 includes multiple selection circuits (not shown). Each of the multiple selection circuits is, for example, a switch controlled by an on signal and an off signal supplied to the selection signal line. A selection circuit is selected in response to the on signal supplied to the selection signal line, and supplies image data signal SL(m) including data signal VDATA to image data signal line 321 and pixels 180 electrically connected to image data signal line 321. The selection signal and image data signal SL(m) are transmitted from an external device to IC chip 110 via FPC 160 and terminal 150 connected to the FPC.

[0086] For example, an on-signal is a signal including a voltage that turns on a selection circuit (switch), and an off-signal is a signal including a voltage that turns off a selection circuit (switch). In the present invention, the on-signal can be a high-level voltage (potential) (High, High, HI) and the off-signal can be a low-level voltage (potential) (Low, Low, LO), or the on-signal can be a low-level voltage (potential) (Low, Low, LO) and the off-signal can be a high-level voltage (potential) (High, High, HI). A high-level voltage is greater (higher) than a low-level voltage. It should be noted that, in the self-luminous display device according to the embodiments of this specification, as an example, the on-signal is a high-level voltage and the off-signal is a low-level voltage.

[0087] <1-3. Structure of First Scan Driver 120 >

[0088] Reference Figure 1 , the first scan driver 120 is briefly described. The first scan driver 120 is located adjacent to the display area 22 in the second direction D2. First scan signal lines 330, 331, and 332 extend from the first scan driver 120 in the second direction D2 and are connected to a plurality of pixels 180 arranged in the second direction D2. For example, the first scan driver 120 is a so-called gate driver.

[0089] The first scan driver 120 includes multiple shift registers (e.g., shift registers 111, 112, and 113). For example, shift registers 111, 112, and 113 sequentially supply first scan signals (e.g., first scan signal SC1(n), first scan signal SC1(n+1), first scan signal SC1(n+2), etc.) with different timings to the first scan signal lines 330, 331, and 332, respectively, based on control signals such as a clock signal and a start pulse supplied from the IC chip 110. This drives each pixel 180 (pixel circuit 181) electrically connected to the first scan signal line. The first scan signal SC1(n) is sometimes referred to as a first control signal. For example, the first scan signal and the first scan signal line are referred to as a scan signal and a scan signal line.

[0090] For example, shift register 111 is electrically connected to shift register 112, and shift register 112 is electrically connected to shift register 113. Shift register 111 is electrically connected to first scanning signal line 330 and, for example, supplies first scanning signal SC1(n) to first scanning signal line 330. Similarly to shift register 111, shift register 112 is electrically connected to first scanning signal line 331 and, for example, supplies first scanning signal SC1(n+1) to first scanning signal line 331. Shift register 113 is electrically connected to first scanning signal line 332 and, for example, supplies first scanning signal SC1(n+2) to first scanning signal line 332. First scanning signal SC1(n+1) has the same pulse width as first scanning signal SC1(n) and is a shifted signal of first scanning signal SC1(n). Similar to the first scanning signal SC1 (n+1), the first scanning signal SC1 (n+2) has the same pulse width as the first scanning signal SC1 (n+1), and is a signal obtained by shifting the first scanning signal SC1 (n+1).

[0091] <1-4. Configuration of Second Scan Driver 130 >

[0092] Reference Figure 1 The second scan driver 130 is now described in its entirety. The second scan driver 130 is adjacent to the display area 22 in the second direction D2 and is located on the opposite side of the display area 22 from the location where the first scan driver 120 is located. Second scan signal lines 334, 335, and 336 extend from the second scan driver 130 in the second direction D2 and are connected to a plurality of pixels 180 (pixel circuits 181) arranged in the second direction D2.

[0093] Like the first scan driver 120, the second scan driver 130 includes multiple shift registers (e.g., shift registers 161, 162, and 163). For example, shift registers 161, 162, and 163 sequentially supply second scan signals (e.g., second scan signal SC2(n), second scan signal SC2(n+1), and second scan signal SC2(n+2)) with different timings to the second scan signal lines 334, 335, and 336 based on control signals such as a clock signal and a start pulse supplied from the IC chip 110, thereby driving each pixel 180 (pixel circuit 181) electrically connected to the second scan signal line. The second scan signal SC2(n) is sometimes referred to as the second control signal.

[0094] For example, shift register 161 is electrically connected to shift register 162, and shift register 162 is electrically connected to shift register 163. Shift register 161 is electrically connected to second scanning signal line 334 and, for example, supplies second scanning signal SC2(n) to second scanning signal line 334. Similarly to shift register 161, shift register 162 is electrically connected to second scanning signal line 335 and, for example, supplies second scanning signal SC2(n+1) to second scanning signal line 335. Shift register 163 is electrically connected to second scanning signal line 336 and, for example, supplies second scanning signal SC2(n+2) to second scanning signal line 336. The pulse width of second scanning signal SC2(n+1) is the same as that of second scanning signal SC2(n), and second scanning signal SC2(n+1) is a shifted signal of second scanning signal SC2(n). Likewise, the pulse width of the second scanning signal SC2 (n+2) is the same as that of the second scanning signal SC2 (n+1), and the second scanning signal SC2 (n+2) is a signal obtained by shifting the second scanning signal SC2 (n+1).

[0095] <1-5. Structure of Pixel 180>

[0096] Reference Figures 1 to 3 , an overview of the pixel 180 and the pixel circuit 181 is described. Figure 2 1 is a schematic diagram illustrating input signals to the pixel circuit 181 included in the pixel 180 . Figure 3 is a circuit diagram showing the structure of the pixel circuit 181. Figure 2 as well as Figure 3 Show Figure 1 The structure of the pixel circuit 181 of the pixel 180 shown is an example. The structure of the pixel 180 and the pixel circuit 181 is not limited to Figures 1 to 3 The structure shown. Figure 1 The same or similar structures will be explained as needed.

[0097] Pixel circuit 181 is a circuit for driving pixel 180. The pixel circuits for sub-pixels R, G, and B included in pixel 180 are identical to pixel circuit 181, but the light-emitting elements OLED emit different colors. The following description uses a red light-emitting element OLED as an example.

[0098] like Figure 2 As shown, pixel circuit 181 is supplied with a first scanning signal SC1(n), an image data signal SL(m), a second scanning signal SC2(n), a reference voltage VREF, and an initialization voltage VINI. Furthermore, as power sources for driving pixel 180, a driving voltage VDDEL and a reference voltage VSSEL are supplied to pixel circuit 181. For example, reference voltage VREF, initialization voltage VINI, driving voltage VDDEL, and reference voltage VSSEL may be constant voltages or variable voltages that vary according to the timing of each signal.

[0099] The reference voltage VREF is supplied to the reference voltage power line SVR, the initialization voltage VINI is supplied to the initialization voltage power line SVI, the driving voltage VDDEL is supplied to the driving power line PVDD, and the reference voltage VSSEL is supplied to the reference voltage line PVSS. For example, the reference voltage power line SVR, the initialization voltage power line SVI, the driving power line PVDD, and the reference voltage line PVSS are each electrically connected to a different connection wiring 342. Alternatively, for example, the reference voltage power line SVR, the initialization voltage power line SVI, the driving power line PVDD, and the reference voltage line PVSS may each be a different connection wiring 342.

[0100] For example, the reference voltage VREF, the initialization voltage VINI, the driving voltage VDDEL, and the reference voltage VSSEL are supplied from an external device to the IC chip 110 via the FPC 160, the terminal portion 150, and the connection wiring 341. Furthermore, for example, the reference voltage VREF, the initialization voltage VINI, the driving voltage VDDEL, and the reference voltage VSSEL are supplied from the IC chip 110 to the plurality of pixels 180 (pixel circuit 181) via the connection wiring 342, the reference voltage power line SVR, the initialization voltage power line SVI, the driving power line PVDD, and the reference voltage line PVSS. It should be noted that, although not shown in the figure, the reference voltage VREF, the initialization voltage VINI, the driving voltage VDDEL, and the reference voltage VSSEL can be supplied to the plurality of pixels 180 (pixel circuit 181) by connecting to the reference voltage power line SVR, the initialization voltage power line SVI, the driving power line PVDD, and the reference voltage line PVSS from an external device through the FPC 160, the terminal portion 150, and the connection wiring 341, without passing through the IC chip 110 and the connection wiring 342. For example, the reference voltage VREF, the initialization voltage VINI, and the reference voltage VSSEL can be lower than the driving voltage VDDEL.

[0101] like Figure 3 As shown, pixel circuit 181 includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a capacitor CS, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (source and drain) consisting of a first electrode and a second electrode. The capacitor CS and the light-emitting element OLED each have a pair of electrodes consisting of a first electrode and a second electrode.

[0102] For example, the first transistor T1 is a selection transistor and has a function of supplying an image data signal SL(m) to the first node N1.

[0103] For example, the second transistor T2 is a driving transistor. The threshold voltage VTH of the second transistor T2 is corrected based on the reference voltage VREF and the initialization voltage VINI. Furthermore, the second transistor T2 controls the connection and disconnection between the driving power line PVDD and the light-emitting element OLED based on the corrected threshold voltage VTH and the input image data signal SL(m). Specifically, the second transistor T2 has the function of supplying the driving voltage VDDEL to the light-emitting element OLED and causing current to flow, thereby causing the light-emitting element OLED to emit light.

[0104] The third transistor T3 has a function of conducting electricity between the first node N1 and the second node N2 and supplying the image data signal SL(m) to the second node N2 .

[0105] The fourth transistor T4 has the following functions: conducting electricity between the second node N2 and the reference voltage power supply line SVR, supplying the reference voltage VREF to the second node N2, and initializing the second node N2.

[0106] The fifth transistor T5 has the following functions: conducting the third node N3 with the initialization voltage supply line SVI, supplying the initialization voltage VINI to the third node N3, and initializing the third node N3.

[0107] For example, the capacitor element CS has the following functions: holding a charge (e.g., a first charge) corresponding to the initialization voltage VINI supplied to the third node N3 and a data voltage (e.g., a voltage VSIGL (see FIG. 1 )) included in the image data signal SL(m) supplied to the first node N1. Figure 6 ) and the voltage VSIGH (refer to Figure 6 ) has the function of maintaining a charge (for example, a second charge) equivalent to a voltage below ) .

[0108] The light emitting element OLED has diode characteristics, and has a function of emitting light based on a current flowing into the light emitting element OLED (ie, a drain current Ion of the second transistor T2 ).

[0109] The first transistor T1 includes a gate electrode 612, a first electrode 614, and a second electrode 616. The gate electrode 612 is electrically connected to the first scanning signal line 330. The first electrode 614 is electrically connected to the image data signal line 321. The second electrode 616 is electrically connected to the first node N1, the first electrode 634 of the third transistor T3, and the second electrode 694 of the capacitor CS. A first scanning signal SC1(n) is supplied to the first scanning signal line 330. The first scanning signal SC1(n) controls the switching of the first transistor T1. In other words, the first transistor T1 is controlled to switch between a conductive state (on state) and a non-conductive state (off state) by the first scanning signal SC1(n). When the signal supplied to the first scanning signal SC1(n) is low, the first transistor T1 is in a non-conductive state. When the signal supplied to the first scanning signal SC1(n+1) is high, the first transistor T1 is in a conductive state.

[0110] The first scan signal line 330 is electrically connected to the gate electrode 632 of the third transistor T3 and the gate electrode 642 of the fourth transistor T4 in addition to the gate electrode 612 of the first transistor T1 .

[0111] The second transistor T2 includes a gate electrode 622, a first electrode 624, and a second electrode 626. The gate electrode 622 is electrically connected to the second electrode 636 of the third transistor T3 and the second electrode 646 of the fourth transistor T4. The first electrode 624 is electrically connected to the third node N3, the second electrode 656 of the fifth transistor T5, the first electrode 692 of the capacitor CS, and the second electrode 684 of the light-emitting element OLED. The second electrode 626 is electrically connected to the driving power line PVDD. The driving power line PVDD is supplied with a driving voltage VDDEL. The threshold voltage of the second transistor T2 is the threshold voltage VTH. The second transistor T2 is controlled to be in a conducting state (on state) or a non-conducting state (off state) based on the potential difference between the voltage supplied to the second node N2 and the voltage of the first electrode 624, the potential difference between the second electrode 626 and the first electrode 624, and the threshold voltage VTH. For example, when the potential difference between the voltage supplied to the second node N2 and the voltage of the first electrode 624 is less than the threshold voltage VTH, and the potential difference between the second electrode 626 and the first electrode 624 is less than 0 V, the second transistor T2 is in a non-conductive state. For example, when the potential difference between the voltage supplied to the second node N2 and the voltage of the first electrode 624 is greater than the threshold voltage VTH, and the potential difference between the second electrode 626 and the first electrode 624 is greater than 0 V, the second transistor T2 is in a conductive state.

[0112] The third transistor T3 includes a gate electrode 632, a first electrode 634, and a second electrode 636. The switching of the third transistor T3 is controlled by the first scan signal SC1(n). The third transistor T3 is controlled to switch between a conductive state (on state) and a non-conductive state (off state) by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is low, the third transistor T3 is in a conductive state. When the signal supplied to the first scan signal SC1(n) is high, the third transistor T3 is in a non-conductive state.

[0113] The fourth transistor T4 includes a gate electrode 642, a first electrode 644, and a second electrode 646. The first electrode 644 is electrically connected to a reference voltage power line SVR. A reference voltage VREF is supplied to the reference voltage power line SVR. The switching of the fourth transistor T4 is controlled by the first scanning signal line 330. In other words, the fourth transistor T4 is controlled to be in a conducting state (on state) or a non-conducting state (off state) by the first scanning signal line 330. When the signal supplied to the first scanning signal line 330 is LOW, the fourth transistor T4 is in a non-conducting state. When the signal supplied to the first scanning signal line 330 is HI, the fourth transistor T4 is in a conducting state.

[0114] The fifth transistor T5 includes a gate electrode 652, a first electrode 654, and a second electrode 656. The gate electrode 652 is electrically connected to the second scan signal line 334. The first electrode 654 is electrically connected to the initialization voltage power line SVI. An initialization voltage VINI is supplied to the initialization voltage power line SVI. A second scan signal SC2(n) is supplied to the second scan signal line 334. The switching of the fifth transistor T5 is controlled by the second scan signal SC2(n). In other words, the fifth transistor T5 is controlled to be in a conducting state (on state) or a non-conducting state (off state) by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is low, the fifth transistor T5 is in a non-conducting state. When the signal supplied to the second scan signal SC2(n) is high, the fifth transistor T5 is in a conducting state.

[0115] The first electrode 682 of the light emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, the reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 682 of the light emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light emitting element OLED is, for example, an anode electrode.

[0116] For example, the conductive state of a transistor in the self-luminous display device 10 indicates that the source electrode and drain electrode of the transistor are conductive, and the transistor is in the ON state. The non-conductive state of a transistor in the self-luminous display device 10 indicates that the source electrode and drain electrode of the transistor are non-conductive, and the transistor is in the OFF state. It should be noted that in some transistors, the source electrode and drain electrode may be interchanged depending on the voltage or potential supplied to each electrode. Furthermore, those skilled in the art will readily understand that even when a transistor is in the OFF state, a small current, such as leakage current, may flow.

[0117] Figure 3Each transistor shown can include a Group 14 element such as silicon or germanium, or an oxide exhibiting semiconductor properties, in its channel region. For example, a metal oxide exhibiting semiconductor properties can be used as the oxide exhibiting semiconductor properties. As an example, the metal oxide exhibiting semiconductor properties uses an oxide semiconductor containing two or more metals, including indium (In). In addition to indium, other metal oxides exhibiting semiconductor properties can include gallium (Ga), zinc (Zn), aluminum (Al), hafnium (Hf), yttrium (Y), zirconium (Zr), and lanthanides. Furthermore, the metal oxide exhibiting semiconductor properties can be amorphous, crystalline, or a mixture of amorphous and crystalline. It should be noted that when the self-luminous display device 10 includes both a transistor including a Group 14 element in its channel region and a transistor including an oxide exhibiting semiconductor properties in its channel region, the method for manufacturing the self-luminous display device 10 includes forming a semiconductor layer including a Group 14 element and forming a semiconductor layer including an oxide exhibiting semiconductor properties.

[0118] For example, transistors using metal oxides with semiconductor properties have extremely low leakage current. Therefore, when using transistors using metal oxides with semiconductor properties, charge equivalent to the voltage (potential) written to the capacitor is less likely to escape from the capacitor. Consequently, by using transistors using metal oxides with semiconductor properties, the charge written to the capacitor can be retained for a long period of time. Furthermore, under the same conditions of gate-source voltage (the potential difference between the gate and source electrodes (Vgs)) and source-drain voltage (for example, the potential difference between the source and drain electrodes (Vds)), the drain current of a transistor using metal oxides with semiconductor properties may be greater than the drain current of a transistor using low-temperature polysilicon (LTPS). Consequently, under the same conditions of drain current, the gate-source voltage and source-drain voltage of a transistor using metal oxides with semiconductor properties can be set lower than those of a transistor using LTPS. Therefore, by using transistors using metal oxides with semiconductor properties, the power consumption of the self-luminous display device 10 can be suppressed.

[0119] For example, the channel region of the first transistor T1 or the channel region of the fourth transistor T4 may be formed using a metal oxide having semiconductor properties. Alternatively, the channel region of the second transistor T2 or the channel region of the fifth transistor T5 may be formed using a metal oxide having semiconductor properties. For example, if the channel region of the first transistor T1 is formed using a metal oxide, the charge (e.g., the second charge) corresponding to the voltage included in the data signal VDATA held at the first node N1 and the second electrode 694 of the capacitor CS is less likely to be discharged, and the first node N1 and the second electrode 694 of the capacitor CS can retain this charge for a long period of time.

[0120] For example, the channel region of each transistor may also include crystalline silicon. For example, the crystalline silicon may be low-temperature polysilicon (LTPS) or single-crystal silicon. For example, each transistor in the self-luminous display device 10 is formed using a thin-film transistor (TFT). In addition, the channel region of each transistor may also be formed using single-crystal silicon such as a silicon wafer or an SOI substrate. Each transistor may also include either an n-channel field-effect transistor or a p-channel field-effect transistor. The self-luminous display device 10 may also appropriately match the transistor structure, storage capacitor connection, power supply voltage, etc., depending on the application and specifications.

[0121] In the first embodiment, the first transistor T1 , the second transistor T2 , the fourth transistor T4 , and the fifth transistor T5 are n-channel field effect transistors, and the third transistor T3 is a p-channel field effect transistor.

[0122] <1-6. Driving Method of Self-Luminous Display Device 10 >

[0123] Reference Figures 4 to 8 , a driving method of the self-luminous display device 10 is described. Figures 4 to 8 Schematic diagram showing a timing chart of the self-luminous display device 10. Figures 4 to 8 The driving method shown is an example, and the driving method of the self-luminous display device 10 is not limited to Figures 4 to 8 The driving method shown in Figures 1 to 3 The same or similar structures will be described as needed. It should be noted that the horizontal axis of the timing diagram is time (TIME).

[0124] For example, the frequency of driving the self-luminous display device 10 is 60 Hz, and one frame (1 FRAME) is driven at 60 Hz. Figure 4 The current frame (KthFRAME), part of the frame before the current frame (K-1stFRAME), and part of the frame after the current frame (K+1stFRAME) are shown.

[0125] like Figure 4 As shown, the driving method of the self-luminous display device 10 includes at least an initialization and writing period PIW (period PIW) and a threshold acquisition and holding period PVH (period PVH) within a single frame. In the pixels 180 (pixel circuits 181) included in the self-luminous display device 10, the period PVH is executed after the period PIW. Furthermore, the period PIW and the period PVH of the current frame are executed after the light-emission period PEM of the previous frame, and the period PIW and the period PVH of the subsequent frame are executed after the light-emission period PEM of the current frame.

[0126] Period PIW is the period during which the data signal VDATA is written to the pixel 180 (pixel circuit 181) and the second node N2 and third node N3 of the pixel 180 (pixel circuit 181) are initialized. Furthermore, during period PVH, an operation is applied such that the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage, thereby acquiring the threshold voltage of the second transistor T2 and retaining a charge corresponding to the threshold voltage at the second node N2 (gate electrode 622 of the second transistor T2). Furthermore, during period PEM, the pixel 180 emits light based on the written (supplied) data signal VDATA and the acquired threshold voltage (corrected threshold voltage) of the second transistor T2.

[0127] Figures 5 to 8 These are diagrams of the period PIW and the period PVH for explaining a method of driving the pixel 180 (pixel circuit 181 ) of the self-luminous display device 10 . Figures 5 to 8 The light emitting period PEM of the frame before this frame (K-1stFRAME), the period PIW and the period PVH of this frame (KthFRAME) are shown. Figures 5 to 8 One horizontal period (horizontal period HRP) for one pixel 180 (pixel circuit 181 ) is shown.

[0128] In the driving method of the self-luminous display device 10, a horizontal period includes a period PIW and a period PVH. During a horizontal period, a pixel 180 (pixel circuit 181) receives inputs including a first scanning signal SC1(n), a second scanning signal SC2(n), an image data signal SL(m) including a data signal VDATA, an initialization voltage VINI, and a reference voltage VREF. For example, the first scanning signal SC1(n) and the second scanning signal SC2(n) are shifted, and a pixel 180 (pixel circuit 181) corresponding to the shifted signals is selected. The image data signal SL(m), the initialization voltage VINI, and the reference voltage VREF are then input to the selected pixel 180 (pixel circuit 181). The same operation is performed for all pixels 180 (pixel circuit 181). Based on the image data signal SL(m) input to all pixels 180 (pixel circuit 181), an image corresponding to one frame, equivalent to one frame, is displayed in the display area 22 of the self-luminous display device 10.

[0129] For example, supplied to Figures 4 to 8 Tables 1 and 2 show the voltages (potentials) of the signals and nodes in the respective periods of the frames in the timing chart shown.

[0130]

[0131]

[0132] <1-6-1. First Example of a Method for Driving the Self-Luminous Display Device 10>

[0133] Reference Figure 5 A first example of a driving method for the self-luminous display device 10 will be described. The driving method illustrated in this first example involves causing pixel 180 (pixel circuit 181) to display a white image based on voltage VSIGH included in data signal VDATA in the frame (K-1st FRAME) preceding the current frame (KthFRAME). Subsequently, pixel 180 (pixel circuit 181) displays a black image based on voltage VSIGL included in data signal VDATA in the KthFRAME. In other words, the driving method illustrated in this first example involves displaying images of different colors in consecutive frames.

[0134] According to each horizontal period, the image data signal SL (m) including the data signal VDATA is input to each pixel 180 (pixel circuit 181). The data signal VDATA is analog data including a voltage greater than the voltage VSIGL and less than the voltage VSIGH. For example, in each horizontal period, a selection signal (not shown) is used to select a voltage greater than the voltage VSIGL and less than the voltage VSIGH, and the voltage is supplied to the image data signal SL (m). For example, during a period in which the selection signal is not used to select data, the data signal VDATA is maintained at a voltage greater than the voltage VSIGL and less than the voltage VSIGH. As shown in Table 2, for example, when the voltage VSIGL is -0.5V, the pixel 180 supplied with the voltage VSIGL does not emit light and becomes black. In addition, for example, when the voltage VSIGH is 3.5V, the pixel 180 supplied with the voltage VSIGH emits light and emits each color. In addition, in Figure 5 For example, voltage VH is 10V, voltage VM is 5V, and voltage VN is -5V.

[0135] The light emission period PEM of the K-1st FRAME is the period during which pixel 180 (pixel circuit 181) emits light in response to the potential difference Vgs (voltage V(N2) - voltage V(N3) = voltage Vna - voltage Vnb) of second transistor T2. For example, pixel 180 (pixel circuit 181) emits red light, and three pixels (pixel 180 emitting red, blue, and green) emit white light.

[0136] For example, during the light-emission period PEM of the K-1st FRAME, no select signal is used to select data. The data signal VDATA is maintained at a voltage above the voltage VSIGL and below the voltage VSIGH, and the first scan signal SC1(n) and the second scan signal SC2(n) are supplied at LO. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are in the off state. Furthermore, the voltage Vna supplied to the first node N1 and the second node N2 is 7V, and the voltage Vnb supplied to the third node N3 is 2.5V. Furthermore, the potential difference Vgs is 4.5V, and the third transistor T3 is in the on state. Therefore, the second transistor T2 can flow a current Ion based on the potential difference Vgs and the potential difference Vds corresponding to the voltage VSIGH input during the horizontal period HRP of the K-1st FRAME. Since the second transistor T2 is in the on state, the current Ion flows from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light. As shown in Table 2, for example, LO is -3.5V and HI is 10V.

[0137] At the beginning of a horizontal period HRP of the KthFRAME following the K-1stFRAME light-emission period PEM, pixel 180 (pixel circuit 181) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGL corresponding to black, indicating no light emission. The first scan signal SC1(n) transitions from being supplied at LOW to being supplied at HI. The second scan signal SC2(n) transitions from being supplied at LOW. Consequently, the first transistor T1 and the fourth transistor T4 transition from being OFF to being ON, the third transistor T3 transitions from being ON to being OFF, and the fifth transistor T5 remains OFF. As a result, the voltage supplied to the first node N1 gradually decreases from voltage Vna to voltage VSIGL (voltage Vnd), and the voltage supplied to the second node N2 gradually decreases from voltage Vna to reference voltage VREF. Furthermore, in response to the decrease in the voltage supplied to the second node N2, the second transistor T2 transitions from being ON to being OFF. For example, as shown in Table 2, the reference voltage VREF is 0 V, and the voltage VSIGL (voltage Vnd) is −0.5 V. At this time, the voltage supplied to the third node N3 is maintained at Vnb.

[0138] As described above, the period PIW in one horizontal period HRP of KthFRAME is a period for writing the data signal VDATA to the pixel 180 (pixel circuit 181 ) and for initializing the second node N2 and the third node N3 of the pixel 180 (pixel circuit 181 ).

[0139] During period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL, and the first scanning signal SC1(n) maintains the state of being supplied with the HI state. Furthermore, the second scanning signal SC1(n) changes from being supplied with the LO state to being supplied with the HI state. Consequently, the fifth transistor T5 changes from being OFF to being ON, the first transistor T1 and the fourth transistor T4 remain ON, and the third transistor remains OFF.

[0140] As a result, the voltage supplied to the first node N1 gradually decreases from voltage Vna to voltage VSIGL (voltage Vnd, -0.5V), reaching voltage Vnd (-0.5V). The voltage supplied to the second node N2 gradually decreases from voltage Vna to reference voltage VREF, reaching reference voltage VREF (0V). Furthermore, the voltage supplied to the third node N3 gradually decreases from voltage Vnb to initialization voltage VINI (voltage Vnc), reaching voltage Vnc. For example, as shown in Table 2, initialization voltage VINI (voltage Vnc) is -1.5V. That is, the voltage supplied to the second node N2 (0 V) is greater than the voltage supplied to the first node N1 (-0.5 V), and the voltage supplied to the first node N1 (-0.5 V) is greater than the voltage supplied to the third node N3 (-1.5 V). The potential difference Vgs becomes 1.5 V (0 V - (-1.5 V)), and the potential difference Vds becomes 9.5 V (8 V - (-1.5 V)).

[0141] As described above, the data signal VDATA including the voltage VSIGL is supplied to (written into) the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-1.5V). For example, the period during which the second node N2 is initialized is the same as the period during which the data signal VDATA is supplied to the first node, while the period during which the third node N3 is initialized is different from and shorter than the period during which the second node N2 is initialized.

[0142] As described above, the period PVH after the period PIW in a horizontal period HRP of KthFRAME is a period in which an operation is applied to make the potential difference Vgs of the second transistor T2 the same as the threshold voltage, the threshold voltage of the second transistor T2 is obtained, and a charge corresponding to the threshold voltage is maintained at the second node N2 (gate electrode 622 of the second transistor T2).

[0143] During period PVH, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL, and the first scanning signal SC1(n) maintains the state of being supplied with the HI state. Furthermore, the second scanning signal SC1(n) changes from being supplied with the HI state to being supplied with the LO state. Consequently, the fifth transistor T5 changes from being supplied with the ON state to being supplied with the OFF state, the first transistor T1 and the fourth transistor T4 remain supplied with the ON state, and the third transistor remains supplied with the OFF state.

[0144] Immediately after the start of period PVH, the potential difference Vgs is 1.5V, and the potential difference Vds is 9.5V. These potential differences Vgs and Vds are greater than the threshold voltage VTH (1V), turning the second transistor T2 on. Consequently, a drain current Ion flows from the second electrode 626 of the second transistor T2 to the first electrode 624.

[0145] When the potential difference Vgs reaches the threshold voltage VTH, the second transistor T2 switches from the on state to the off state, and the drain current Ion stops flowing. At this point, the voltage supplied to the third node N3 rises from voltage Vnc to voltage Vne, and the potential difference Vgs becomes reference voltage VREF minus voltage Vne. In other words, reference voltage VREF (0V) minus voltage Vne becomes threshold voltage VTH (1V), and voltage Vne becomes -1V.

[0146] As described above, during the period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby obtaining the threshold voltage VTH of the second transistor T2. In addition, charge corresponding to the threshold voltage VTH is retained at the second node N2 (gate electrode 622 of the second transistor T2).

[0147] During the KthFRAME light emission period PEM following the KthFRAME horizontal period HRP, the pixel 180 emits light based on the voltage VSIGL supplied to the first node N1 and the potential difference Vsg between the voltage supplied to the second node N2 and the voltage supplied to the third node.

[0148] For example, during the light-emission period PEM of KthFRAME, no select signal is used to select data, and the data signal VDATA is maintained at a voltage above VSIGL and below VSIGH. Furthermore, the first scan signal SC1(n) changes from being HI to being LO, while the second scan signal SC2(n) remains LO.

[0149] As a result, the first transistor T1 and the fourth transistor T4 go from on to off, and the third transistor T3 goes from off to on. Furthermore, the fifth transistor T5 remains off. As the third transistor T3 turns on, the first node N1 and the second node N2 become conductive, and the potential difference Vgs becomes VSIGL (-0.5V) - (reference voltage VREF (0V) - threshold voltage VTH (1V)) = Vnd (-0.5V) - Vne (-1V). In other words, the potential difference Vgs becomes 0.5V, which is lower than the threshold voltage VTH. Consequently, the second transistor T2 turns off, and current stops flowing from the drive power line PVDD to the reference voltage line PVSS. Consequently, the light-emitting element OLED does not emit light. As a result, for example, the pixel 180 (pixel circuit 181), which normally emits red light, turns black. In addition, similar to the red-emitting pixel 180 , the blue-emitting pixel 180 and the green-emitting pixel 180 do not emit light, so that the three pixels of the red-emitting pixel 180 , the blue-emitting pixel 180 , and the green-emitting pixel 180 become black.

[0150] The self-luminous display device 10 includes a first node N1 to which a data signal VDATA, which is a voltage greater than or equal to VSIGL and less than or equal to VSIGH, is supplied (written); a second node N2 (the gate electrode 622 of the second transistor T2) to which a reference voltage VREF is supplied; and a third node N3 (including the first electrode 624 of the second transistor T2) to which an initialization voltage VINI is supplied. Specifically, the self-luminous display device 10 can independently control: the first node N1 to which data is written; the second node N2 and the third node N3, which participate in initializing the second transistor T2 for flowing current into the light-emitting element OLED. As a result, as described in the driving method of the self-luminous display device 10, the driving method of the self-luminous display device 10 can include executing the processing (driving) performed during the writing period and the processing (driving) performed during the initialization period at the same timing. In other words, the driving method of the self-luminous display device 10 does not require the processing (driving) performed during the initialization period to be performed after the processing (driving) performed during the writing period.

[0151] For example, in a display device including a pixel circuit where the first node N1 and the second node N2 are identical (without the third transistor T3), the processing (driving) performed during the write period and the processing (driving) performed during the initialization period cannot be performed at the same timing. Therefore, the write period and the initialization period are independent. Consequently, in a display device including a pixel circuit where the first node N1 and the second node N2 are identical (without the third transistor T3), the time required for one horizontal period becomes longer.

[0152] On the other hand, as described above, the self-luminous display device 10 includes a structure for independently controlling the first node N1, the second node N2, and the third node N3, and can execute the processing (driving) performed during the writing period and the processing (driving) performed during the initialization period at the same timing.

[0153] As a result, the self-luminous display device 10 can shorten the time required for a horizontal period. Furthermore, by shortening the time required for a horizontal period, the self-luminous display device 10 can reduce power consumption by an amount equivalent to the shortened time. Therefore, the self-luminous display device 10 is a display device capable of achieving low power consumption.

[0154] Furthermore, by shortening the time required for one horizontal period, the self-luminous display device 10 can increase the number of pixels that can be written within the shortened time. Therefore, the self-luminous display device 10 is a display device capable of achieving high definition.

[0155] <1-6-2. Second Example of the Driving Method of the Self-Luminous Display Device 10>

[0156] Reference Figure 6 , a second example of the driving method of the self-luminous display device 10 is described. The driving method shown in the second example includes: after the pixel 180 (pixel circuit 181) displays a white image based on the voltage VSIGH included in the data signal VDATA in the previous frame (K-1stFRAME) of the current frame (KthFRAME), the pixel 180 (pixel circuit 181) also displays a white image based on the voltage VSIGH included in the data signal VDATA in KthFRAME. In other words, the driving method shown in the second example displays images of the same color (white) in consecutive frames. Figures 1 to 5 The same or similar structures will be explained as needed.

[0157] The configurations of the K-1st FRAME light-emission period PEM, one horizontal period HRP of the Kth FRAME, and the image data signal SL(m), first scanning signal SC1(n), and second scanning signal SC2(n) within the light-emission period PEM are the same as those in the first example. Furthermore, the voltages (potentials) of the first node N1, second node N2, and third node N3 within the K-1st FRAME light-emission period PEM, as well as the operation of each transistor, are the same as those in the first example. Therefore, the configurations similar to those in the first example will be described as needed.

[0158] During the start of a horizontal period HRP of KthFRAME, pixel 180 (pixel circuit 181) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGH corresponding to white. The voltage supplied to first node N1 gradually decreases from voltage Vna to voltage VSIGH (voltage Vnf), while the voltage supplied to second node N2 gradually decreases from voltage Vna to reference voltage VREF. Furthermore, in response to the decrease in voltage supplied to second node N2, second transistor T2 transitions from an on state to an off state. For example, as shown in Table 2, reference voltage VREF is 0V and voltage VSIGH (voltage Vnf) is 3.5V.

[0159] During period PIW, the voltage supplied to the first node N1 gradually decreases from voltage Vna to voltage VSIGH (voltage Vnf, 3.5V), reaching voltage Vnf (3.5V). The voltage supplied to the second node N2 gradually decreases from voltage Vna to reference voltage VREF, reaching reference voltage VREF (0V). Furthermore, the voltage supplied to the third node N3 gradually decreases from voltage Vnb to initialization voltage VINI (voltage Vnc), reaching voltage Vnc. For example, as shown in Table 2, initialization voltage VINI (voltage Vnc) is -1.5V. At this time, potential difference Vgs is 1.5V (0V - (-1.5V)), and potential difference Vds is 9.5V (8V - (-1.5V)).

[0160] As described above, similarly to the first example, during period PIW, the data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1 , the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (−1.5V).

[0161] During the period PVH following the period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGH. Immediately after the start of the period PVH, similar to the first example, the second transistor T2 is turned on, and the drain current Ion flows from the second electrode 626 of the second transistor T2 to the first electrode 624.

[0162] During period PVH, the first node N1 is maintained at voltage Vnf, and the second node N2 is maintained at reference voltage VREF (0V). Also, during period PVH, similarly to the first example, when potential difference Vgs reaches threshold voltage VTH, the second transistor T2 transitions from on to off, and drain current Ion ceases to flow. Similarly to the first example, the voltage supplied to the third node N3 rises from voltage Vnc to voltage Vne, and reference voltage VREF minus voltage Vne becomes threshold voltage VTH, resulting in voltage Vne being -1V.

[0163] As described above, similarly to the first example, during the period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby obtaining the threshold voltage VTH of the second transistor T2. Furthermore, a charge corresponding to the threshold voltage VTH is retained at the second node N2 (the gate electrode 622 of the second transistor T2).

[0164] During the KthFRAME light-emission period PEM following the KthFRAME horizontal period HRP, as the third transistor T3 turns on, the first node N1 and the second node N2 are conductively connected, causing the voltages at the first node N1 and the second node N2 to gradually rise. As a result, the second transistor T2 turns on, causing drain current Ion to flow from the drive power line PVDD to the reference voltage line PVSS. Consequently, the voltage at the third node N3 rises, tracking the rise in the voltages at the first node N1 and the second node N2.

[0165] For example, the voltages at the first node N1 and the second node N2 rise to voltage Vna, and the voltage at the third node N3 rises to voltage Vnb. As a result, the potential difference Vgs becomes voltage Vna (7V) minus voltage Vnb (-2.5V). In other words, the potential difference Vgs becomes 4.5V, which is greater than the threshold voltage VTH (1V). Consequently, the second transistor T2 turns on, and drain current Ion flows from the drive power line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. In other words, the flow of drain current Ion causes the voltage at the third node N3 to rise to 2.5V, exceeding the threshold voltage VTHEL (0.7V, see Table 2) of the light-emitting element OLED, causing the light-emitting element OLED to emit light. As a result, for example, pixel 180 (pixel circuit 181) turns red, while the three pixels—pixel 180 emitting blue and pixel 180 emitting green—emit white light.

[0166] <1-6-3. Third Example of the Driving Method of the Self-Luminous Display Device 10>

[0167] Reference Figure 7, a third example of the driving method of the self-luminous display device 10 is described. The driving method shown in the third example includes: after the pixel 180 (pixel circuit 181) displays a black image based on the voltage VSIGL included in the data signal VDATA in the previous frame (K-1stFRAME) of the current frame (KthFRAME), the pixel 180 (pixel circuit 181) also displays a black image based on the voltage VSIGH included in the data signal VDATA in KthFRAME. In other words, the driving method shown in the third example includes displaying images of the same color (black) in consecutive frames. Figures 1 to 6 The same or similar structures will be explained as needed.

[0168] The configurations of the light-emission period PEM of K-1stFRAME, one horizontal period HRP of KthFRAME, and the image data signal SL(m), first scanning signal SC1(n), and second scanning signal SC2(n) within the light-emission period PEM are the same as those in the first example. Configurations similar to those in the first and second examples will be described as needed.

[0169] The light emission period PEM of the K-1stFRAME is the period during which the pixel 180 (pixel circuit 181) emits light in response to the potential difference Vgs (voltage V(N2) - voltage V(N3) = Vnd (-0.5V) - voltage Vne (-1V). For example, the potential difference Vgs is 0.5V, which is lower than the threshold voltage VTH (1V, see Table 2) of the second transistor T2. Therefore, the second transistor T2 is in the off state, and current does not flow from the drive power line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light. As a result, for example, the pixel 180 (pixel circuit 181) becomes black.

[0170] At the start of a horizontal period HRP of the KthFRAME following the K-1stFRAME light-emission period PEM, pixel 180 (pixel circuit 181) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGL (-0.5V) corresponding to black, which indicates no light. The voltage supplied to first node N1 remains at voltage Vnd (-0.5V), maintaining the -0.5V supply voltage. The voltage supplied to second node N2 gradually increases from voltage Vnd (-0.5V) toward reference voltage VREF (0V).

[0171] During period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL. The voltage supplied to the first node N1 remains at -0.5V, and the voltage supplied to the first node N1 remains at -0.5V. The voltage supplied to the second node N2 gradually increases from the voltage Vnd toward the reference voltage VREF, reaching the reference voltage VREF (0V). Furthermore, the voltage supplied to the third node N3 gradually decreases from the voltage Vne (-1V) toward the initialization voltage VINI (voltage Vnc, -1.5V), reaching the voltage Vnc (-1.5V).

[0172] As described above, similarly to the first example, during period PIW, the data signal VDATA including the voltage VSIGL (-0.5V) is supplied (written) to the first node N1, the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (-1.5V).

[0173] In the period PVH following the period PIW, the image data signal SL(m) maintains a state in which the data signal VDATA including the voltage VSIGL is supplied.

[0174] Immediately after the start of period PVH, the potential difference Vgs is 1.5V (reference voltage VREF (0V) minus voltage Vnc (-1.5V)), and the potential difference Vds is 9.5V. These potential differences Vgs and Vds are greater than the threshold voltage VTH (1V), turning on the second transistor T2. Consequently, a drain current Ion flows from the second electrode 626 of the second transistor T2 to the first electrode 624. Even when the drain current Ion flows into the second transistor T2, the voltage at the third node N3 is -1.5V, which is lower than the threshold voltage VTHEL of the light-emitting element OLED. Therefore, the light-emitting element OLED does not emit light momentarily between frames that are continuously displayed black.

[0175] During period PVH, when the potential difference Vgs reaches the threshold voltage VTH (1V), the second transistor T2 switches from the on state to the off state, and the drain current Ion stops flowing. At this time, the voltage supplied to the third node N3 rises from Vnc (-1.5V) to Vne (-1V), and the potential difference Vgs reaches the threshold voltage VTH (1V) (reference voltage VREF (0V) - Vne (-1V)).

[0176] As described above, similarly to the first example, during the period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby obtaining the threshold voltage VTH of the second transistor T2. Furthermore, a charge corresponding to the threshold voltage VTH is retained at the second node N2 (the gate electrode 622 of the second transistor T2).

[0177] During the KthFRAME light emission period PEM following the KthFRAME horizontal period HRP, as in the first example, the third transistor T3 turns on, connecting the first node N1 to the second node N2, and the potential difference Vgs reaches 0.5V. As a result, as in the first example, the second transistor T2 turns off, preventing current from flowing from the drive power line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light. For example, pixel 180 (pixel circuit 181) appears black. Furthermore, similar to the red pixel 180, the blue pixel 180 and the green pixel 180 also do not emit light, resulting in the three pixels (red pixel 180, blue pixel 180, and green pixel 180) appearing black.

[0178] For example, in a display device including a pixel circuit where the first node N1 and the second node N2 are identical (without the third transistor T3), the processing (driving) performed during the write period and the processing (driving) performed during the initialization period cannot be performed at the same timing. Therefore, the write period and the initialization period are independent. As a result, even when displaying images of the same color (black) in consecutive frames, a display device including a pixel circuit where the first node N1 and the second node N2 are identical performs processing during both the write period and the initialization period within consecutive frames. Consequently, in a display device including a pixel circuit where the first node N1 and the second node N2 are identical, there is a risk of significant fluctuations in the voltages of each node.

[0179] On the other hand, as described above, the self-luminous display device 10 includes a structure for independently controlling the first node N1, the second node N2, and the third node N3, and can execute the processing (driving) performed during the writing period and the processing (driving) performed during the initialization period at the same timing.

[0180] As a result, the self-luminous display device 10 can suppress significant fluctuations in the voltages of various nodes when displaying images of the same color (black) across consecutive frames. For example, as described above, the voltage fluctuation at the first node N1 is 0, while the voltage fluctuations at the second node N2 and the third node N3 are each 0.5V. Furthermore, in the self-luminous display device 10, the voltage fluctuations at various nodes when displaying images of the same color (black) across consecutive frames are minimal, thereby reducing power consumption caused by fluctuations in the voltages of various nodes. Consequently, the self-luminous display device 10 is capable of achieving low power consumption.

[0181] <1-6-4. Fourth Example of the Driving Method of the Self-Luminous Display Device 10>

[0182] Reference Figure 8 , a fourth example of a driving method for the self-luminous display device 10 is described. The driving method shown in the fourth example includes: after the pixel 180 (pixel circuit 181) displays a black image based on the voltage VSIGL included in the data signal VDATA in the previous frame (K-1stFRAME) of the current frame (KthFRAME), the pixel 180 (pixel circuit 181) displays a white image based on the voltage VSIGH included in the data signal VDATA in KthFRAME. In other words, the driving method shown in the fourth example includes displaying images of different colors in consecutive frames. Figures 1 to 5 The same or similar structures will be explained as needed.

[0183] The configurations of the K-1st FRAME light-emission period PEM, one horizontal period HRP of the Kth FRAME, and the image data signal SL(m), first scanning signal SC1(n), and second scanning signal SC2(n) within the light-emission period PEM are the same as those of the first example. Furthermore, the voltages (potentials) of the first node N1, second node N2, and third node N3 within the K-1st FRAME light-emission period PEM, as well as the operation of each transistor, are the same as those of the third example. The configurations and other features common to the first through third examples will be described as needed.

[0184] During the start of a horizontal period HRP of KthFRAME, pixel 180 (pixel circuit 181) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGH corresponding to white. The voltage supplied to first node N1 gradually increases from voltage Vnd (-0.5V) to voltage VSIGH (voltage Vnf, 3.5V), while the voltage supplied to second node N2 gradually increases from voltage Vnd to reference voltage VREF (0V).

[0185] During period PIW, the voltage supplied to the first node N1 gradually increases from voltage Vnd (-0.5V) to voltage VSIGH (voltage Vnf, 3.5V), and the first node N1 is supplied with voltage Vnf (3.5V). The voltage supplied to the second node N2 gradually increases from voltage Vnd to reference voltage VREF (0V), and the second node N2 is supplied with voltage VREF (0V). Furthermore, the voltage supplied to the third node N3 gradually decreases from voltage Vne (-1V) to initialization voltage VINI (voltage Vnc, -1.5V), and the third node N3 is supplied with voltage Vnc (-1.5V). At this time, the potential difference Vgs is 1.5V (0V - (-1.5V)), and the potential difference Vds is 9.5V (8V - (-1.5V)).

[0186] As described above, similarly to the second example, during period PIW, the data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1 , the second node N2 is initialized by the reference voltage VREF (0V), and the third node N3 is initialized by the initialization voltage VINI (−1.5V).

[0187] During the period PVH following the period PIW, similar to the second example, the first node N1 is maintained at the state of being supplied with the voltage Vnf, the second node N2 is maintained at the state of being supplied with the reference voltage VREF (0 V), and the voltage supplied to the third node N3 increases from the voltage Vnc to the voltage Vne, so that the third node N3 is supplied with the voltage Vne (-1 V).

[0188] As described above, similarly to the second example, during the period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby obtaining the threshold voltage VTH of the second transistor T2. Furthermore, a charge corresponding to the threshold voltage VTH is retained at the second node N2 (the gate electrode 622 of the second transistor T2).

[0189] During the KthFRAME light-emission period PEM following the KthFRAME horizontal period HRP, similar to the second example, the voltages at the first and second nodes N1 and N2 rise to voltages Vna and Vnb, respectively, resulting in a potential difference Vgs of 4.5V (voltage Vna (7V) minus voltage Vnb (-2.5V)). This potential difference Vgs exceeds the threshold voltage VTH (1V), turning on the second transistor T2 and allowing drain current Ion to flow from the drive power line PVDD to the reference voltage line PVSS. As a result, the light-emitting element OLED emits light. For example, pixel 180 emits red light, while three pixels, namely pixel 180 emitting blue and pixel 180 emitting green, emit white light.

[0190] <1-7. Cross-sectional Structure of Pixel 180 Along Line A1-A2>

[0191] Reference Figure 3 、 Figure 9 as well as Figure 10 , the cross-sectional structure of the pixel 180 along the A1-A2 line is described. Figure 9 This is a planar layout diagram of pixel 180. Figure 10 It is shown along Figure 9 The cross-sectional view is a cross-sectional view of a cross section taken along line A1 - A2 in the planar layout of the pixel 180 shown. Figure 9 The planar layout of the pixel 180 shown and Figure 10 The cross section of the pixel 180 shown is an example, and the planar layout and cross section of the pixel 180 are not limited to Figure 9 as well as Figure 10 For example, Figures 1 to 8 The same or similar structures will be explained as needed.

[0192] It should be noted that Figure 10 The cross-section of the pixel 180 shown is an example of a cross-section of the pixel 180, and is a cross-section along the driving power line PVDD, the contact hole opening 147 for the anode electrode, the first electrode 692 and the second electrode 694 of the capacitor element CS, the gate electrode 622 of the second transistor T2, the channel region 123 of the semiconductor layer 122, the organic insulating film opening 138A for the capacitor element CS, the second contact hole opening 138B, the first wiring 132B, the first wiring 132D, the first contact hole opening 135, the impurity region 124A, the second scanning signal line 334, the reference voltage power line SVR and the initialization voltage power line SVI.

[0193] The substrate 101 includes a first surface 101A and a second surface 101B opposite the first surface 101A. The semiconductor layer 122 is provided on the first surface 101A of the substrate 101 via the base layer 121. The semiconductor layer 122 includes a semiconductor layer 122A, which includes a channel region 123 and an impurity region 124A. For example, an impurity region is referred to as a source region or a drain region. Furthermore, for example, the second transistor T2 and the fifth transistor T5 include the semiconductor layer 122A, and the first electrode 624 and the second electrode 656 include the impurity region 124A. In other words, the semiconductor layer 122A includes the channel region of the second transistor T2 and the channel region of the fifth transistor T5.

[0194] A gate insulating layer 125, a conductive layer 126, an insulating layer 128, and a conductive layer 132 are sequentially arranged on the semiconductor layer 122. The conductive layer 126 includes a gate wiring 127A (gate electrode 622), a gate wiring 127B (second scanning signal line 334), a gate wiring 127C (reference voltage supply line SVR), and a gate wiring 127D (initialization voltage supply line SVI). The conductive layer 132 includes a first wiring 132A (drive power line PVDD), a first wiring 132B, a first wiring 132C (second electrode 694), and a first wiring 132D. It should be noted that the region where the conductive layer 126 overlaps with the semiconductor layer 122 is the channel region. In other words, the region where the gate electrode of each transistor overlaps with the semiconductor layer is the channel region.

[0195] Each transistor of the pixel 180 is formed using the semiconductor layer 122 (the channel region 123 and the impurity region 124A), the gate insulating layer 125 , and the conductive layer 126 (for example, the gate wiring 127A).

[0196] First contact hole opening 135, which reaches semiconductor layer 122, is provided in gate insulating layer 125 and insulating layer 128. First contact hole opening 135 exposes semiconductor layer 122 (e.g., impurity region 124A). Conductive layer 132 is electrically connected to semiconductor layer 122 (e.g., impurity region 124A) via first contact hole opening 135. Alternatively, an opening (not shown) reaching conductive layer 126 (e.g., gate wiring 127A) may be provided in insulating layer 128.

[0197] The insulating layer 131 is provided so as to cover the conductive layer 132. The insulating layer 136 is provided so as to cover the insulating layer 131.

[0198] Second contact hole opening 138B is provided in insulating layer 131 and insulating layer 136. Second contact hole opening 138B is provided in insulating layer 136. Conductive layer 139 is provided on insulating layer 136, in organic insulating film opening 138A and second contact hole opening 138B for capacitor element CS. Conductive layer 139 includes second wiring 140A (first electrode 692), second wiring 140B, and third wiring 140C. Second contact hole opening 138B exposes conductive layer 132 (for example, first wiring 132D). For example, second contact hole opening 138B electrically connects first electrode 692 to first wiring 132D. For example, capacitor element CS is formed using insulating layer 131 as a dielectric, first wiring 132C (second electrode 694), and second wiring 140A (first electrode 692). For example, second wiring 140A also functions as a pixel electrode. Although not shown, for example, second contact hole opening 138 partially exposes a plurality of terminals (not shown) included in terminal section 150. The exposed terminals are electrically connected to FPC 160 using a conductive film such as an anisotropic conductive film (not shown).

[0199] Insulating layer 141 is provided to cover conductive layer 139 .

[0200] Base layer 121 , semiconductor layer 122 , gate insulating layer 125 , conductive layer 126 , insulating layer 128 , conductive layer 132 , insulating layer 131 , insulating layer 136 , conductive layer 139 , and insulating layer 137 are collectively referred to as array portion 170 .

[0201] Next, the layers above the insulating layer 141 will be described. Anode contact hole openings 147 are provided in the insulating layer 141. Anode contact hole openings 147 expose the conductive layer 139 (for example, the second wiring 140A).

[0202] Anode electrode 143 is provided to cover the exposed conductive layer 139, the anode contact hole opening 147, and the insulating layer 141. A functional layer 148 is provided above anode electrode 143, and a common electrode 149 is provided on top of functional layer 148, covering it. Common electrode 149 is electrically connected to the cathode electrode (the first electrode 682 of the light-emitting element OLED). The light-emitting element OLED comprises anode electrode 143, functional layer 148, and common electrode 149 (cathode).

[0203] The structure of the functional layer 148 can be selected appropriately. For example, the functional layer 148 can be composed of a combination of a carrier injection layer, a carrier transport layer, a light emitting layer, a carrier blocking layer, an exciton blocking layer, and the like. Figure 10The functional layer 148 shown includes a first layer 144, a second layer 145, and a third layer 146. For example, the first layer 144 is a carrier (hole) injection and transport layer, the second layer 145 is a light-emitting layer, and the third layer 146 is a carrier (electron) injection and transport layer.

[0204] The sealing film 165 is disposed on the common electrode 149. For example, the sealing film 165 includes a first inorganic insulating layer 152, an organic insulating layer 154, and a second inorganic insulating layer 156. It should be noted that the first inorganic insulating layer 152 and the second inorganic insulating layer 156 are formed to cover at least the display area 22. The cover film 158 is disposed on the second inorganic insulating layer 156.

[0205] For example, the first layer 144, the second layer 145 (light-emitting layer), the third layer 146, and the common electrode 149 included in the functional layer 148 are not disposed on the IC chip 110, the first scan driver 120, and the second scan driver 130. A sealing film 165 and a cover film 158 are disposed on the IC chip 110, the first scan driver 120, and the second scan driver 130. The sealing film 165 and the cover film 158 prevent impurities (such as water and oxygen) from entering the light-emitting element OLED and the transistors from outside the self-luminous display device 10.

[0206] Common metal materials can be used for the conductive layer 126, the conductive layer 132, the conductive layer 139, and the common electrode 149. For example, common metal materials include aluminum (Al), titanium (Ti), chromium (Cr), cobalt (Co), nickel (Ni), molybdenum (Mo), hafnium (Hf), tantalum (Ta), tungsten (W), bismuth (Bi), silver (Ag), copper (Cu), and alloys or compounds thereof.

[0207] For example, the semiconductor layer 122 may include LTPS or metal oxide.

[0208] For example, a general insulating material can be used as a material for forming the base layer 121, the gate insulating layer 125, the insulating layer 131, the first inorganic insulating layer 152, and the second inorganic insulating layer 156. For example, silicon oxide (SiO x ), silicon oxynitride (SiO x N y ), silicon nitride (SiN x ), silicon oxynitride (SiN x O y ) and other inorganic insulating layers.

[0209] The insulating layer 128, the insulating layer 136, the insulating layer 141, and the organic insulating layer 154 can be formed using, for example, an organic compound material having excellent surface flatness. The insulating layer 128, the insulating layer 136, and the insulating layer 141 are sometimes referred to as an organic insulating layer.

[0210] <1-8. Method for Manufacturing Self-Luminous Display Device 10 >

[0211] Reference Figure 3 、 Figures 9 to 14 , a method for manufacturing the self-luminous display device 10 (pixel 180 ) will be described. Figure 11 It is a timing chart showing a method for manufacturing the self-luminous display device 10 . Figures 12 to 14 This is a layout diagram of pixel 180. Figures 1 to 10 The same or similar structures will be explained as needed.

[0212] like Figure 10 As shown, when the production of the self-luminous display device 10 (pixel 180 ) starts, the base layer 121 is formed on the first surface 101A of the substrate 101 .

[0213] like Figure 10 or Figure 12 As shown, the semiconductor layer 122 is formed on the base layer 121 ( Figure 11 Step 10 (S10) of the embodiment of the present invention. Semiconductor layer 122 includes semiconductor layers 122A, 122B, and 122C. Semiconductor layer 122A serves as the semiconductor layer for both the second transistor T2 and the fifth transistor T5. Semiconductor layer 122B serves as the semiconductor layer for both the first transistor T1 and the third transistor T3. Semiconductor layer 122C serves as the semiconductor layer for the fourth transistor T4. In other words, semiconductor layer 122B includes the channel region for both the first transistor T1 and the third transistor T3, while semiconductor layer 122C includes the channel region for the fourth transistor T4. In other words, pixel 180 includes a semiconductor layer that serves as both two transistors and a semiconductor layer that serves as one transistor.

[0214] Impurities are injected into the semiconductor layer 122 ( Figure 11 Step 11 (S11)). By S11, the impurity region 124A is formed. For example, if referring to Figure 12 , the first electrode 614, the second electrode 616, the first electrode 624, the second electrode 626, the first electrode 614, the second electrode 616, the first electrode 644, the second electrode 646, the first electrode 654, and the second electrode 656 include impurity regions into which impurities such as phosphorus (P) are implanted. Figure 12 , the first electrode 634 and the second electrode 636 include impurity regions into which impurities such as boron (B) are implanted.

[0215] Gate insulating layer 125 ( Figure 10 ) is formed on the semiconductor layer 122 and on the base layer 121 where the semiconductor layer 122 is not formed ( Figure 11 Step 12 (S12)).

[0216] Conductive layer 126 ( Figure 10 ) is formed on the gate insulating layer 125 ( Figure 11 Step 13 (S13). Figure 10 or Figure 12 As shown, the conductive layer 126 includes a gate wiring 127A (gate electrode 622), a gate wiring 127B (second scan signal line 334), a gate wiring 127C (reference voltage supply line SVR), a gate wiring 127D (initialization voltage supply line SVI), a first scan signal line 330A, and a first scan signal line 330B. The gate wiring 127B (second scan signal line 334) includes a gate electrode 652. The first scan signal line 330A includes a gate electrode 612, and the first scan signal line 330B includes a gate electrode 632 and a gate electrode 642. For example, the first scan signal line 330A and the first scan signal line 330B are electrically connected at the periphery of the display area 22 or in the peripheral area 24, and are supplied with the same first scan signal.

[0217] The area where the gate electrode 622 of the second transistor T2 overlaps with the semiconductor layer 122A is the channel area 123, and the channel area 123 is equivalent to the channel length of the second transistor T2. Similarly, the area where the gate electrode 612 of the first transistor T1 overlaps with the semiconductor layer 122B is the channel area of ​​the first transistor T1, and is equivalent to the channel length. Figure 12 As shown, when viewed from above, the channel region 123 of the second transistor T2 is larger (longer) than the channel region of the first transistor T1, the channel region of the third transistor T3, the channel region of the fourth transistor T4, and the channel region of the fifth transistor T5. In other words, the channel length of the second transistor T2 is longer than the channel length of the first transistor T1, the channel length of the third transistor T3, the channel length of the fourth transistor T4, and the channel length of the fifth transistor T5. The second transistor T2 operates in the saturation region, so the second transistor T2 needs to have a higher resistance to hot carriers than the other transistors in the pixel 180. As a result, the channel length of the second transistor T2 is longer than the channel length of the other transistors in the pixel 180.

[0218] Insulation layer 128 ( Figure 10 ) is formed on the conductive layer 126 and on the gate insulating layer 125 where the conductive layer 126 is not formed ( Figure 11 Step 14 (S14)).

[0219] like Figure 10 or Figure 12 As shown, first contact hole openings 135, 135A, 135B, 135C, 135D, 135E, 135F, 135G, 135H, 135J, and 135K are opened (step 15 (S15)). Each opening opens gate insulating layer 125 and insulating layer 128, exposing the corresponding wiring, semiconductor layer, or electrode. For example, first contact hole opening 135 exposes semiconductor layer 122A (e.g., impurity region 124A), and first contact hole opening 135A exposes gate wiring 127D. The other openings also expose the corresponding wiring, semiconductor layer, or electrode.

[0220] Conductive layer 132 ( Figure 10 ) is formed on the insulating layer 128 (step 16 (S16)). Figure 10 or Figure 13 As shown, the conductive layer 132 includes a first wiring 132A (driving power line PVDD), a first wiring 132B, a first wiring 132C (a second electrode 694 ), a first wiring 132D, a first wiring 132E, a first wiring 132F, a first wiring 132G, a first wiring 132H, and an image data signal line 321 .

[0221] like Figure 13 As shown, in a plan view, the first wiring 132A is electrically connected to the second electrode 626 via the first contact hole opening portion 135D, the first wiring 132B is electrically connected to the first electrode 644 via the first contact hole opening portion 135J, the second electrode 694 is electrically connected to the first electrode 644 via the first contact hole opening portion 135J, and the first wiring 132D is electrically connected to the second electrode 656 via the first contact hole opening portion 135. Figure 13 As shown, when viewed from above, the first wiring 132E is electrically connected to the initialization voltage power line SVI via the first contact hole opening portion 135A, and is electrically connected to the first electrode 654 via the first contact hole opening portion 135C, the first wiring 132F is electrically connected to the second electrode 646 via the first contact hole opening portion 135K, the first wiring 132G is electrically connected to the second electrode 636 via the first contact hole opening portion 135F, and is electrically connected to the gate electrode 622 via the first contact hole opening portion 135E, the first wiring 132H is electrically connected to the reference voltage power line SVR via the first contact hole opening portion 135B, and the image data signal line 321 is electrically connected to the first electrode 614 via the first contact hole opening portion 135H.

[0222] In addition, if Figure 13As shown, the second electrode 694 , the gate electrode 622 , and the semiconductor layer 122A (channel region 123 ) overlap. That is, the second transistor T2 (the channel region and the gate electrode 622 ) overlaps the second electrode 694 of the capacitor CS.

[0223] Insulation layer 131 ( Figure 10 ) is formed on the conductive layer 132 and on the insulating layer 128 where the conductive layer 132 is not formed ( Figure 11 Step 17 (S17)).

[0224] like Figure 10 or Figure 14 As shown, second contact hole openings 138B, 138C, 138D, 138E, 138F, and 138G are opened (step 18 (S18)). Each opening opens insulating layer 131, exposing the corresponding wiring, semiconductor layer, or electrode. For example, second contact hole opening 138B exposes first wiring 132D, and second contact hole opening 138G exposes first wiring 132G. The remaining openings also expose the corresponding wiring, semiconductor layer, or electrode.

[0225] Insulating layer 136 (organic insulating layer) ( Figure 10 ) is formed on the insulating layer 131 ( Figure 11 Step 19 (S19)).

[0226] like Figure 10 or Figure 14 As shown, the insulating layer 136 (organic insulating layer) is opened (step 20 (S20)). In the opening in S20, the organic insulating film opening 138A for the capacitor element CS is opened. Also, in the opening in S20, similar to the opening in S18, second contact hole openings 138B, 138C, 138D, 138E, 138F, and 138G are opened. In other words, the second contact hole openings 138B, 138C, 138D, 138E, 138F, and 138G are opened twice. Each opening opens the insulating layer 136, exposing the wiring, semiconductor layer, or electrode corresponding to each opening. For example, in the organic insulating film opening 138A for the capacitor element CS, only the insulating layer 136 above the second electrode 694 is removed, exposing the insulating layer 131. Meanwhile, the second contact hole opening 138G removes the insulating layers 136 and 131 on the first wiring 132G to expose the first wiring 132G. The other openings also expose the corresponding wiring, semiconductor layer, or electrode.

[0227] Conductive layer 139 ( Figure 10) is formed on the insulating layer 136 and on the insulating layer 131 exposed through the organic insulating film opening 138A for the capacitor element CS (step 21 (S21)). Figure 9 or Figure 10 As shown, the conductive layer 139 includes a second wiring 140A (first electrode 692 ), a second wiring 140B, a third wiring 140C, and a fourth wiring 140D.

[0228] like Figure 9 As shown, in a plan view, the first electrode 692 is electrically connected to the first wiring 132D and the second electrode 656 via the second contact hole opening 138B and the first contact hole opening 135. The second wiring 140B is electrically connected to the first wiring 132H and the reference voltage supply line SVR via the second contact hole opening 138D and the first contact hole opening 135B. The third wiring 140C is electrically connected to the first wiring 132E and the initialization voltage supply line SVI via the second contact hole opening 138C and the first contact hole opening 135A. The fourth wiring 140D is electrically connected to the first wiring 132G, the gate electrode 622 and the second electrode 636 via the second contact hole opening portion 138G, the first contact hole opening portion 135F and the first contact hole opening portion 135E, and is electrically connected to the first wiring 132F and the second electrode 646 via the second contact hole opening portion 138F and the first contact hole opening portion 135K.

[0229] Second wiring 140B overlaps with reference voltage power line SVR and extends parallel to the second direction D2. Therefore, reference voltage power line SVR is formed using two layers of metal wiring, resulting in lower wiring resistance than voltage lines formed using a single layer of metal wiring. As a result, reference voltage power line SVR has a high current supply capability and can supply a stable voltage to each transistor. Similar to reference voltage power line SVR, third wiring 140C overlaps with initialization voltage power line SVI and extends parallel to the second direction D2. Therefore, similar to reference voltage power line SVR, initialization voltage power line SVI is formed using two layers of metal wiring, resulting in lower wiring resistance than voltage lines formed using a single layer of metal wiring. As a result, initialization voltage power line SVI has a high current supply capability and can supply a stable voltage to each transistor.

[0230] Second wiring 140A (first electrode 692) included in the same conductive layer 139 is in contact with insulating layer 131 and conductive layer 132 (first wiring 132D), and second wiring 140B included in the same conductive layer 139 is in contact with insulating layer 136. In other words, different wirings included in the same conductive layer 139 are in contact with different layers below the same conductive layer 139.

[0231] In addition, if Figure 9 As shown, the first electrode 692 , the second electrode 694 , the gate electrode 622 , and the semiconductor layer 122A (channel region 123 ) overlap. That is, the second transistor T2 overlaps the capacitor CS.

[0232] Furthermore, the first wiring 132C (second electrode 694) is formed on the insulating layer 128, which is formed on the gate wiring 127A (gate electrode 622) having an area larger than the surface area of ​​the second electrode 694. Since the insulating layer 128 reduces the unevenness of the underlying layer, the second electrode 694 is formed on the large gate electrode 622 and on the flat insulating layer 128. In addition, for example, Figure 13 As shown, in a plan view, the area of ​​the second electrode 694 is larger than the area of ​​the electrode of the same conductive layer 132. In other words, the surface of the second electrode 694 is flat, and the area of ​​the second electrode 694 is large. Furthermore, the thickness of the insulating layer 131 formed on the second electrode 694 is thinner than the thickness of the insulating layer 136. Therefore, the method for manufacturing the self-luminous display device 10 (pixel 180) includes forming the first electrode 692 on the gate electrode 622 with a large area, and on the second electrode 694 with a gentle unevenness, and on the thin insulating layer 131.

[0233] Insulating layer 141 (organic insulating layer) ( Figure 10 ) is formed on the conductive layer 139 and on the insulating layer 136 where the conductive layer 139 is not formed ( Figure 11 Step 22 (S22)).

[0234] like Figure 9 or Figure 10 As shown, a hole is opened in insulating layer 141 (organic insulating layer) (step 23 (S23)). During the opening in S23, a contact hole opening 147 for the anode electrode is opened. Anode contact hole opening 147 removes insulating layer 141 above second wiring 140A, exposing second wiring 140A. Anode contact hole opening 147 is sometimes referred to as an organic insulating layer opening.

[0235] Anode electrode 143 is provided on exposed second wiring 140A, anode contact hole opening 147, and insulating layer 141. Functional layer 148 is provided on anode electrode 143. Common electrode 149 is provided on functional layer 148 (step 24 (S24)).

[0236] After S24 , the sealing film 165 and the cover film 158 are sequentially disposed on the common electrode 149 .

[0237] like Figure 10As shown above, the manufacture of the self-luminous display device 10 (pixel 180 ) is completed.

[0238] <1-9. Speeding up p-channel field-effect transistors>

[0239] For example, Figure 3 As shown, the third transistor T3 is a p-channel field effect transistor that controls the connection and disconnection between the first node N1 and the second node N2. In order to speed up the operation of the pixel 180, the third transistor T3 needs to quickly transmit the data signal VDATA supplied to the first node N1 to the second node N2.

[0240] On the other hand, for example, it is known that in the on-state of each of a p-channel field-effect transistor and an n-channel field-effect transistor, carriers are trapped in trap levels, thereby increasing the threshold voltage (for example, Japanese Patent Application Laid-Open No. 2008-028191). Furthermore, it is known that due to the increased threshold voltage, the transition from the on-state to the non-conducting state of each transistor becomes slower than the transition of the transistor in a state where carriers are not trapped in trap levels (for example, Japanese Patent Application Laid-Open No. 2008-028191).

[0241] For example, this phenomenon is caused by the fact that, among both holes and electrons, the density of trap levels (density of states) that trigger hole traps is higher than the density of trap levels (density of states) that trigger electron traps. This phenomenon is known to occur more significantly in p-channel field-effect transistors (e.g., Japanese Patent Application Laid-Open No. 2012-019146). For example, the density of trap levels that trigger hole traps is from -0.4 eV to the Fermi level Ei, while the density of states that trigger electron traps is from the Fermi level Ei to 0.4 eV. Furthermore, for example, the range from -0.4 eV to the Fermi level Ei is referred to as a deep level.

[0242] In order to suppress such a phenomenon, the method for manufacturing the self-luminous display device 10 may further include setting the state density of the deep level of the third transistor T3 to 1×10 17 eV -1 cm -3For example, when the third transistor T3 includes LTPS, the method for manufacturing the self-luminous display device 10 includes increasing the purity of monosilane (SiH4) gas to form the semiconductor layer 122. The impurity concentration in the LTPS formed by increasing the purity of the gas is reduced, so the method for manufacturing the self-luminous display device 10 can reduce the state density of the deep energy level of the third transistor T3. Furthermore, for example, the method for manufacturing the self-luminous display device 10 includes increasing the size of the LTPS grains according to the energy of the laser irradiation when forming the LTPS. By increasing the size of the LTPS grains, the number of grain boundaries is reduced, so the method for manufacturing the self-luminous display device 10 can reduce the state density of the deep energy level of the third transistor T3. As a result, high-speed operation of the third transistor T3 can be achieved.

[0243] <2. Second embodiment>

[0244] Reference Figure 1 、 Figure 4 、 Figures 15 to 21 , an overview of the self-luminous display device 10 according to the second embodiment will be described. Figure 15 This is a schematic diagram illustrating input signals to the pixel 180A (pixel circuit 181A) according to the second embodiment of the present invention. Figure 16 is a circuit diagram showing the structure of the pixel circuit 181A. Figures 17 to 20 This is a timing chart of the self-luminous display device 10 according to the second embodiment of the present invention. Figure 21 This is a diagram for explaining the setting of input signals according to the second embodiment of the present invention.

[0245] The self-luminous display device according to the second embodiment has a structure and function obtained by replacing the pixel 180 and the pixel circuit 181 of the self-luminous display device 10 according to the first embodiment with the pixel 180A and the pixel circuit 181A. The structure and function other than this are the same as those of the self-luminous display device 10 according to the first embodiment. When describing the structure and function of the second embodiment, the structure and function similar to those of the self-luminous display device 10 according to the first embodiment will be described as needed. Figures 1 to 14 The same or similar structures will be explained as needed.

[0246] <2-1. Structure of Pixel 180A>

[0247] Reference Figure 15 as well as Figure 16 , an overview of the pixel 180A and the pixel circuit 181A is described.

[0248] Pixel circuit 181A is connected to a scanning voltage power line SVIR. This scanning voltage power line SVIR serves as a signal line that also supplies the reference voltage power line SVR and the initialization voltage power line SVI to pixel circuit 181. In other words, the reference voltage power line SVR and the initialization voltage power line SVI supplied to pixel circuit 181 are a common signal line. While the scanning voltage power line SVIR functions as a power supply, it is considered a signal line here because it is used to change the potential. Specifically, pixel circuit 181A has a structure and function obtained by replacing the reference voltage power line SVR and the initialization voltage power line SVI connected to pixel circuit 181 with the scanning voltage power line SVIR that shares the reference voltage power line SVR and the initialization voltage power line SVI. Furthermore, pixel circuit 181A has a structure and function obtained by replacing the reference voltage VREF and the initialization voltage VINI supplied to pixel circuit 181 with the scanning voltage power line SIR(n). The scanning voltage supply line SVIR (a signal line that also serves as the reference voltage supply line SVR and the initialization voltage supply line SVI) is sometimes referred to as a third control signal line. The scanning voltage supply SIR(n) is sometimes referred to as a third control signal line.

[0249] The scanning voltage power supply SIR(n) is supplied to the scanning voltage power supply line SVIR. In the pixel circuit 181A, the first electrode 644 of the fourth transistor T4 and the first electrode 654 of the fifth transistor T5 are electrically connected to the scanning voltage power supply line SVIR.

[0250] For example, the scanning voltage power supply line SVIR is electrically connected to the connection wiring 342 ( Figure 1 、 Figure 15 ) in the embodiment of the present invention, a connection wiring 342 different from the driving power supply line PVDD and the reference voltage line PVSS. In addition, for example, the scanning voltage power supply line SVIR may also be one of the connection wirings 342.

[0251] For example, the scanning voltage SIR(n) can be supplied from an external device to the IC chip 110 ( Figure 1 ) can also be supplied from IC chip 110 via connection wiring 342 and scanning voltage supply line SVIR to the plurality of pixels 180A (pixel circuit 181A). It should be noted that, although not shown in the figure, scanning voltage supply SIR(n), like initialization voltage VINI, can be supplied to the plurality of pixels 180A (pixel circuit 181A) by being connected to scanning voltage supply line SVIR from an external device through FPC 160, terminal portion 150, and connection wiring 341 without passing through IC chip 110 and connection wiring 342.

[0252] The fourth transistor T4 has the following function: conducting the second node N2 with the scan voltage supply line SVIR, supplying the initialization voltage VINI1 or VINI2 to the second node N2, and initializing the second node N2. For example, the initialization voltages VINI1 and VINI2 are constant voltages.

[0253] The fifth transistor T5 has the following functions: conducting the third node N3 and the scan voltage supply line SVIR, supplying the initialization voltage VINI1 to the third node N3, and initializing the third node N3.

[0254] The configuration and functions of the pixel circuit 181A other than those described in “2-1. Configuration of pixel 180A” are the same as those of the pixel circuit 181. Description of the configuration and functions that are the same as those of the pixel circuit 181 will be omitted here.

[0255] <2-2. Driving Method of Pixel Circuit 181A>

[0256] Reference Figures 17 to 20 , a driving method of the self-luminous display device 10 according to the second embodiment will be described. Figures 1 to 16 The same or similar structures will be described as needed. It should be noted that, similar to the first embodiment, the horizontal axis of the timing chart represents time (TIME).

[0257] The driving method of the self-luminous display device 10 according to the second embodiment has a structure and function that replaces the operations associated with the reference voltage supply line SVR and the initialization voltage supply line SVI (reference voltage VREF and initialization voltage VINI) in the driving method of the self-luminous display device 10 according to the first embodiment with operations associated with the scanning voltage supply SIR(n). The structure and functions other than the operations associated with the scanning voltage supply SIR(n) are the same as those of the driving method of the self-luminous display device 10 according to the first embodiment. The description of the structures and functions that are the same as those of the driving method of the self-luminous display device 10 according to the first embodiment will be omitted here.

[0258] The driving method of the self-luminous display device 10 according to the second embodiment includes the following steps: Figure 4 The driving method of the self-luminous display device 10 shown is the same as that of the embodiment.

[0259] Figures 17 to 20 These are diagrams of the period PIW and the period PVH for explaining a method of driving the pixel 180A (pixel circuit 181A). Figures 17 to 20 The light emitting period PEM of the frame before this frame (K-1stFRAME), the period PIW and the period PVH of this frame (KthFRAME) are shown. Figures 17 to 20 One horizontal period (horizontal period HRP) for one pixel 180A (pixel circuit 181A) is shown.

[0260] During one horizontal period in the driving method of the self-luminous display device 10 according to the second embodiment, a first scanning signal SC1(n), a second scanning signal SC2(n), an image data signal SL(m) including a data signal VDATA, and a scanning voltage supply SIR(n) are input to a pixel 180A (pixel circuit 181A). For example, the first scanning signal SC1(n), the second scanning signal SC2(n), and the scanning voltage supply SIR(n) are shifted, and a pixel 180A (pixel circuit 181A) corresponding to the shifted signals is selected. The image data signal SL(m), the initialization voltage VINI, and the reference voltage VREF are input to the selected pixel 180A (pixel circuit 181A). The same operation is performed for all pixels 180A (pixel circuit 181A). Based on the image data signal SL(m) input to all pixels 180A (pixel circuit 181A), an image corresponding to one frame, equivalent to one frame, is displayed in the display area 22 of the self-luminous display device 10.

[0261] For example, supplied to Figures 17 to 20 Tables 3 and 4 show the signals and voltages (potentials) of the nodes in each frame in the timing chart shown.

[0262]

[0263]

[0264] <2-2-1. First Example of a Method for Driving Pixel Circuit 181A>

[0265] Reference Figure 17 Next, a first example of a method for driving the pixel circuit 181A is described. The first example of the method for driving the pixel circuit 181A, like the first example of the method for driving the self-luminous display device 10 according to the first embodiment, includes displaying images of different colors in consecutive frames.

[0266] The configurations of the image data signal SL(m), the first scanning signal SC1(n), and the second scanning signal SC2(n) during the light-emission period PEM of the K-1st frame, one horizontal period HRP of the Kth frame, and the light-emission period PEM are similar to those of the first example of the method for driving the self-luminous display device 10 according to the first embodiment. Furthermore, the voltages (potentials) of the first node N1, the second node N2, and the third node N3 during the light-emission period PEM of the K-1st frame, as well as the operation of each transistor, are similar to those described in "1-6-1. First Example of the Method for Driving the Self-luminous Display Device 10." Details similar to those described in "1-6-1. First Example of the Method for Driving the Self-luminous Display Device 10" will be described as needed.

[0267] It should be noted that the scanning voltage power supply SIR(n) supplies the initialization voltage VINI2 during the light emission period PEM of K-1stFRAME, supplies the initialization voltage VINI1 during the start period of one horizontal period HRP of KFRAME and during the period PIW, and supplies the initialization voltage VINI2 during the period PVH and the light emission period PEM of KFRAME.

[0268] For example, as shown in Table 4, initialization voltage VINI2 is 0 V, and initialization voltage VINI1 is -1.5 V. Initialization voltage VINI2 is the same as reference voltage VREF, and initialization voltage VINI1 is the same as initialization voltage VINI. For example, similar to the first example of the driving method of the self-luminous display device 10 according to the first embodiment, voltage VH is 10 V, voltage VM is 5 V, and voltage VN is -5 V.

[0269] At the beginning of a horizontal period HRP of KthFRAME following the light-emission period PEM of K-1stFRAME, the scan voltage source SIR(n) switches from being supplied with the initialization voltage VINI2 to being supplied with the initialization voltage VINI1. When the scan voltage source SIR(n) switches from being supplied with the initialization voltage VINI1, the first scan signal SC1(n) switches from being supplied with the LOW state to being supplied with the HI state. Furthermore, the second scan signal SC2(n) switches from being supplied with the LOW state. Consequently, the first transistor T1 and the fourth transistor T4 switch from being OFF to being ON, the third transistor T3 switches from being ON to being OFF, and the fifth transistor T5 remains OFF. As a result, the voltage supplied to the first node N1 gradually decreases from voltage Vna to voltage VSIGL (voltage Vnd, -0.5V), and the voltage supplied to the second node N2 gradually decreases from voltage Vna to initialization voltage VINI1 (-1.5V). Furthermore, in response to the decrease in the voltage supplied to the second node N2, the second transistor T2 switches from being ON to being OFF.

[0270] During period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL, the first scan signal SC1(n) maintains the state of being supplied with the HI, and the scan voltage source SIR(n) maintains the state of being supplied with the initialization voltage VINI1. Furthermore, the second scan signal SC1(n) changes from being supplied with the LO to being supplied with the HI. Consequently, the fifth transistor T5 changes from being supplied with the OFF state to being supplied with the ON state, the first transistor T1 and the fourth transistor T4 remain in the ON state, and the third transistor remains in the OFF state. Furthermore, during the end of period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL, the first scan signal SC1(n) maintains the state of being supplied with the HI, and the scan voltage source SIR(n) maintains the state of being supplied with the initialization voltage VINI1. Furthermore, the second scan signal SC1(n) changes from being supplied with the HI to being supplied with the LO. Consequently, the fifth transistor T5 changes from being supplied with the OFF state to being supplied with the OFF state, the first transistor T1 and the fourth transistor T4 remain in the ON state, and the third transistor remains in the OFF state.

[0271] As a result, the voltage supplied to the first node N1 gradually decreases from voltage Vna to voltage VSIGL (voltage Vnd, -0.5V), reaching voltage Vnd (-0.5V). The voltage supplied to the second node N2 gradually decreases from voltage Vna to initialization voltage VINI1 (-1.5V), reaching initialization voltage VINI1 (-1.5V). Furthermore, the voltage supplied to the third node N3 gradually decreases from voltage Vnb to initialization voltage VINI1 (voltage Vnc, -1.5V), reaching voltage Vnc (-1.5V). That is, the voltage supplied to the second node N2 (-1.5 V) is the same as the voltage supplied to the third node N3 (-1.5 V), the voltage supplied to the first node N1 (0 V) is greater than the voltage supplied to the second node N2 (-1.5 V) and the voltage supplied to the third node N3 (-1.5 V), the potential difference Vgs becomes 0 V (-1.5 V - (-1.5 V)), and the potential difference Vds becomes 9.5 V (8 V - (-1.5 V)).

[0272] As described above, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1 , and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (−1.5 V).

[0273] During period PVH, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL, the first scan signal SC1(n) maintains the state of being supplied with the HI state, and the second scan signal SC1(n) maintains the state of being supplied with the LO state. It should be noted that after the second scan signal SC1(n) is supplied with the LO state during period PIW, the scan voltage supply SIR(n) changes from being supplied with the initialization voltage VINI1 to being supplied with the initialization voltage VINI2. While the scan voltage supply SIR(n) is supplied with the initialization voltage VINI1, the first scan signal SC2(n) changes from being supplied with the HI state to being supplied with the LO state. Consequently, the fifth transistor T5 changes from being in the ON state to being in the OFF state, the first transistor T1 and the fourth transistor T4 remain in the ON state, and the third transistor remains in the OFF state.

[0274] Immediately after the start of the period PVH, the potential difference Vgs is 0 V and the potential difference Vds is 9.5 V. Since the potential difference Vgs is lower than the threshold voltage VTH (1 V), the second transistor T2 is in the off state. Consequently, the drain current Ion does not flow from the second electrode 626 of the second transistor T2 to the first electrode 624.

[0275] During period PVH, the fourth transistor T4 remains on. Therefore, when the voltage supplied to the scan voltage source SIR(n) changes from initialization voltage VINI1 to initialization voltage VINI2, the voltage supplied to the second node N2 gradually increases from voltage Vnc (-1.5V) to initialization voltage VINI2 (0V), reaching initialization voltage VINI2 (0V). At this time, the fifth transistor T5 is off, and the Vgs of the second transistor T2 approaches 1.5V (0V (node ​​N2) - (-1.5V) (node ​​N3), which is greater than the threshold voltage VTH (1V). Therefore, the drain current Ion of the second transistor T2 begins to flow, and the voltage supplied to the third node N3 gradually increases from voltage Vnc (-1.5V). As a result, the voltage supplied to the third node N3 reaches voltage Vne (-1V), and the potential difference Vgs becomes 1V (0V - (-1V)). Since the potential difference Vgs is equal to the threshold voltage VTH (1V), the second transistor T2 is off. Therefore, the drain current Ion does not flow from the second electrode 626 of the second transistor T2 to the first electrode 624 .

[0276] As described above, during the period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby obtaining the threshold voltage VTH of the second transistor T2. In addition, charge corresponding to the threshold voltage VTH is retained at the second node N2 (gate electrode 622 of the second transistor T2).

[0277] During the KthFRAME light emission period PEM following the KthFRAME horizontal period HRP, no data is selected using a selection signal, and the data signal VDATA is maintained at a voltage above the voltage VSIGL and below the voltage VSIGH. Furthermore, the first scan signal SC1(n) transitions from being HI to being LO, while the second scan signal SC2(n) remains LO. The scan voltage supply SIR(n) remains supplied with the initialization voltage VINI2 (0V).

[0278] As a result, the first transistor T1 and the fourth transistor T4 go from an on state to an off state, and the third transistor T3 goes from an off state to an on state. Furthermore, the fifth transistor T5 remains in an off state. As the third transistor T3 turns on, the first node N1 and the second node N2 become conductive, and the potential difference Vgs becomes 0.5V. The potential difference Vgs is smaller than the threshold voltage VTH. Consequently, the second transistor T2 turns off, and current does not flow from the drive power line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to not emit light. As a result, for example, pixel 180A (pixel circuit 181A) emitting red, pixel 180A emitting blue, and pixel 180A emitting green do not emit light, causing the three pixels (pixel 180A, blue, and green) to appear black.

[0279] As described above, the driving method of the self-luminous display device 10 according to the second embodiment (the driving method of the pixel circuit 181A) includes, similar to the driving method of the self-luminous display device 10 according to the first embodiment, executing the processing (driving) performed during the writing period and the processing (driving) performed during the initialization period at the same timing. Therefore, the driving method of the pixel circuit 181A has the same operational effects as the driving method of the self-luminous display device 10 according to the first embodiment.

[0280] Pixel circuit 181A is also connected to a scanning voltage power line SVIR, which also serves as a reference voltage power line SVR and an initialization voltage power line SVI supplied to pixel circuit 181. Therefore, pixel circuit 181A has a structure that can reduce the number of signal lines, allowing a self-luminous display device including pixel circuit 181A to reduce pixel size. Consequently, a self-luminous display device including pixel circuit 181A can achieve an increase in the number of pixels and achieve higher resolution.

[0281] <2-2-2. Second Example of the Driving Method of the Pixel Circuit 181A>

[0282] Reference Figure 18 , a second example of the driving method of the pixel circuit 181A is described. The driving method shown in the second example of the pixel circuit 181A includes displaying images of the same color (white) in consecutive frames, similarly to the second example of the driving method of the self-luminous display device 10 according to the first embodiment. Figures 1 to 17 The same or similar structures will be explained as needed.

[0283] The configuration of the K-1st FRAME light-emission period PEM, one horizontal period HRP of the Kth FRAME, the image data signal SL(m), the scanning voltage supply SIR(n), the first scanning signal SC1(n), and the second scanning signal SC2(n) within the light-emission period PEM, as well as the conductive and non-conductive states of each transistor, are similar to those described in "2-2-1. First Example of Driving Method for Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, second node N2, and third node N3 within the K-1st FRAME light-emission period PEM, as well as the operation of each transistor, are similar to those described in "2-2-1. First Example of Driving Method for Pixel Circuit 181A." Configurations similar to those described in "2-2-1. First Example of Driving Method for Pixel Circuit 181A" will be described as needed. Configurations similar to those described in "1-6-2. Second Example of Driving Method for Self-Luminous Display Device 10" will be described as needed.

[0284] At the beginning of a horizontal period HRP of KthFRAME, pixel 180A (pixel circuit 181A) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGH corresponding to white. The voltage supplied to first node N1 gradually decreases from voltage Vna to voltage VSIGH (voltage Vnf, 3.5V). The voltage supplied to second node N2 and third node N3 are the same as those described in "2-2-1."

[0285] During period PIW, the voltage supplied to the first node N1 gradually decreases from voltage Vna to voltage Vnf, reaching voltage Vnf (3.5 V). The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "2-2-1."

[0286] As described above, in the period PIW, the data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1 , and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (−1.5 V).

[0287] During the period PVH following the period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGH. The first node N1 maintains the state of being supplied with the voltage Vnf. The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "2-2-1. First Example of Driving Method of Pixel Circuit 181A."

[0288] As described above, similar to the description in "2-2-1," during period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby obtaining the threshold voltage VTH of the second transistor T2. Furthermore, a charge corresponding to the threshold voltage VTH is retained at the second node N2 (gate electrode 622 of the second transistor T2).

[0289] During the light-emitting period PEM of KthFRAME following a horizontal period HRP of KthFRAME, similarly to the driving method of the self-luminous display device 10 according to the first embodiment, the first node N1 and the second node N2 are turned on, and the voltage of the first node N1 and the voltage of the second node N2 gradually increase, the second transistor T2 becomes turned on, the drain current Ion flows from the driving power line PVDD to the reference voltage line PVSS, and the voltage of the third node N3 increases in a manner following the increase in the voltage of the first node N1 and the voltage of the second node N2.

[0290] As a result, similar to the driving method of the self-luminous display device 10 according to the first embodiment, the potential difference Vgs reaches 4.5V, which is greater than the threshold voltage VTH. Consequently, the second transistor T2 is turned on, and the drain current Ion flows from the drive power line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, pixel 180A (pixel circuit 181A) turns red, while the three pixels—pixel 180A emitting blue and pixel 180A emitting green—emit white light.

[0291] <2-2-3. Third Example of the Driving Method of the Pixel Circuit 181A>

[0292] Reference Figure 19 , a third example of the driving method of the pixel circuit 181A is described. The driving method shown in the third example of the driving method of the pixel circuit 181A includes, similarly to the third example of the driving method of the self-luminous display device 10 according to the first embodiment, displaying an image of the same color (black) in consecutive frames. Figures 1 to 18 The same or similar structures will be explained as needed.

[0293] The configuration of the image data signal SL(m), the scanning voltage supply SIR(n), the first scanning signal SC1(n), and the second scanning signal SC2(n) during the light-emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the conductive and non-conductive states of each transistor within the light-emission period PEM are similar to those described in "2-2-1. First Example of the Driving Method of the Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, second node N2, and third node N3 during the light-emission period PEM of the K-1st FRAME, as well as the operation of each transistor, are similar to those described in the third example of the driving method of the self-luminous display device 10 according to the first embodiment. Configurations similar to those described in "2-2-1. First Example of the Driving Method of the Pixel Circuit 181A" and "2-2-2. Second Example of the Driving Method of the Pixel Circuit 181A" will be described as needed. Furthermore, as needed, the same configuration as in “1-6-3. Third example of the driving method of the self-luminous display device 10 ” will be described.

[0294] During the K-1st FRAME light emission period PEM, for example, the potential difference Vgs reaches 0.5V, which is lower than the threshold voltage VTH of the second transistor T2. Since the second transistor T2 is in the off state, no current flows from the drive power line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to not emit light. As a result, for example, pixel 180A (pixel circuit 181A) appears black.

[0295] At the start of a horizontal period HRP of the KthFRAME following the K-1stFRAME light-emission period PEM, pixel 180A (pixel circuit 181A) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGL (-0.5V) corresponding to black, which indicates no light. The voltage supplied to first node N1 remains at voltage Vnd (-0.5V), maintaining the -0.5V supply voltage. The voltage supplied to second node N2 gradually decreases from voltage Vnd (-0.5V) to voltage Vnc (-1.5V).

[0296] During period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL. The voltage supplied to the first node N1 remains at -0.5V, and the voltage supplied to the first node N1 remains at -0.5V. The voltage supplied to the second node N2 gradually decreases from the voltage Vnd to the voltage Vnc, reaching the voltage Vnc (-1.5V). Furthermore, the voltage supplied to the third node N3 gradually decreases from the voltage Vne (-1V) to the initialization voltage VINI1 (voltage Vnc, -1.5V), reaching the voltage Vnc (-1.5V).

[0297] As described above, in the period PIW, the data signal VDATA including the voltage VSIGL (−0.5V) is supplied to (written into) the first node N1 , and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (−1.5V).

[0298] During the period PVH following the period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL. The voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "2-2-1. First Example of Driving Method of Pixel Circuit 181A."

[0299] As described above, similar to the description in "2-2-1. First Example of Driving Method of Pixel Circuit 181A," during period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby obtaining the threshold voltage VTH of the second transistor T2. Furthermore, a charge corresponding to the threshold voltage VTH is retained at the second node N2 (gate electrode 622 of the second transistor T2).

[0300] During the light emission period PEM of KthFRAME following the one horizontal period HRP of KthFRAME, the voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "2-2-1. First Example of the Driving Method of the Pixel Circuit 181A." Furthermore, similarly to the description in "2-2-1. First Example of the Driving Method of the Pixel Circuit 181A," during the light emission period PEM of KthFRAME following the one horizontal period HRP of KthFRAME, the red-emitting pixel 180A does not emit light, so that the three pixels, namely, the red-emitting pixel 180A, the blue-emitting pixel 180A, and the green-emitting pixel 180A, are black.

[0301] As described above, the third example of the driving method for the self-luminous display device 10 according to the second embodiment (the method for driving the pixel circuit 181A) is similar to the third example of the driving method for the self-luminous display device 10 according to the first embodiment. When displaying images of the same color (black) in consecutive frames, the voltage fluctuations at each node are minimal. This reduces power consumption caused by fluctuations in the voltages at each node. Consequently, the self-luminous display device 10 is a display device capable of achieving low power consumption.

[0302] <2-2-4. Fourth Example of the Driving Method of the Pixel Circuit 181A>

[0303] Reference Figure 20 , a fourth example of a driving method for the pixel circuit 181A is described. The driving method shown in the fourth example of the driving method for the pixel circuit 181A includes displaying images of different colors in consecutive frames, similarly to the fourth example of the driving method for the self-luminous display device 10 according to the first embodiment. Figures 1 to 19 The same or similar structures will be explained as needed.

[0304] The configuration of the K-1st FRAME light-emission period PEM, one horizontal period HRP of the Kth FRAME, the image data signal SL(m), the scanning voltage supply SIR(n), the first scanning signal SC1(n), and the second scanning signal SC2(n) within the light-emission period PEM, as well as the conductive and non-conductive states of each transistor, are similar to those described in "2-2-1. First Example of the Driving Method of Pixel Circuit 181A." Furthermore, the voltages (potentials) of the first node N1, second node N2, and third node N3 within the K-1st FRAME light-emission period PEM, as well as the operation of each transistor, are similar to those described in "2-2-3. Third Example of the Driving Method of Pixel Circuit 181A." The configuration similar to that described in "2-2-1. First Example of the Driving Method of Pixel Circuit 181A" through "2-2-3. Third Example of the Driving Method of Pixel Circuit 181A" will be described as needed. Furthermore, as needed, the same configuration as in “1-6-4. Fourth example of the method for driving the self-luminous display device 10 ” will be described.

[0305] During the start of a horizontal period HRP of KthFRAME, pixel 180A (pixel circuit 181A) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGH corresponding to white. The voltage supplied to first node N1 gradually increases from voltage Vnd (-0.5V) to voltage VSIGH (voltage Vnf, 3.5V), while the voltage supplied to second node N2 gradually decreases from voltage Vne (-1V) to voltage Vnc (-1.5V).

[0306] During period PIW, the voltage supplied to the first node N1 gradually increases from voltage Vnd (-0.5V) to voltage VSIGH (voltage Vnf, 3.5V), and the first node N1 is supplied with voltage Vnf (3.5V). The voltage supplied to the second node N2 gradually decreases from voltage Vne (-1V) to voltage Vnc (-1.5V), and the second node N2 is supplied with voltage Vnc (-1.5V). Furthermore, the voltage supplied to the third node N3 gradually decreases from voltage Vne (-1V) to initialization voltage VINI1 (voltage Vnc, -1.5V), and the third node N3 is supplied with voltage Vnc (-1.5V). At this time, the potential difference Vgs reaches 0V (-1.5V - (-1.5V)), and the potential difference Vds reaches 9.5V (8V - (-1.5V)).

[0307] As described above, in the period PIW, the data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1 , and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (−1.5 V).

[0308] During the period PVH following the period PIW, similarly to the contents described in "2-2-2", the first node N1 is maintained in a state of being supplied with the voltage Vnf, the second node N2 is maintained in a state of being supplied with the initialization voltage VINI2 (0 V), and the voltage supplied to the third node N3 rises from the voltage Vnc to the voltage Vne, and the third node N3 becomes supplied with the voltage Vne (-1 V).

[0309] As described above, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. In addition, a charge corresponding to the threshold voltage VTH is held at the second node N2 (gate electrode 622 of the second transistor T2).

[0310] During the KthFRAME light emission period PEM following the KthFRAME horizontal period HRP, the potential difference Vgs reaches 4.5V, similar to the description in "2-2-2. Second Example of Driving Method for Pixel Circuit 181A." The potential difference Vgs is greater than the threshold voltage VTH, turning on the second transistor T2 and causing the drain current Ion to flow from the drive power line PVDD to the reference voltage line PVSS. As a result, the light-emitting element OLED emits light. For example, pixel 180A emits red light, while three pixels—pixel 180A emitting blue and pixel 180A emitting green—emit white light.

[0311] <2-3. Setting Values ​​of Initialization Voltages VINI1 and VINI2>

[0312] Reference Figure 21 , the setting values ​​of the initialization voltages VINI1 and VINI2 are described. Figure 21 1 is a diagram for explaining the setting values ​​of the initialization voltages VINI1 and VINI2 of the scanning voltage power supply line SVIR of the attacked scanning voltage power supply SIR(n). Figures 1 to 20 The same or similar structures will be explained as needed.

[0313] For example, Figure 21 As shown, between the periods PIW and PVH, the scan voltage source SIR(n) changes from being supplied with the initialization voltage VINI1 to being supplied with the initialization voltage VINI2 according to the timing of the first scan signal SC1(n) and the second scan signal SC2(n).

[0314] During period PIW, in pixel circuit 181A, scan voltage supply SIR(n) (initialization voltage VINI2) is supplied from scan voltage supply line SVIR to second node N2 and third node N3, initializing second node N2 and third node N3. Pixel 180A, including pixel circuit 181A, does not emit light during period PIW. The condition for the light-emitting element OLED to not emit light is that the initialization voltage VINI1 supplied to third node N3 is lower than the threshold voltage VTHEL of the light-emitting element OLED. In other words, initialization voltage VINI1 < threshold voltage VTHEL.

[0315] Furthermore, pixel circuit 181A corrects threshold voltage VTH during period PVH and holds a charge equivalent to threshold voltage VTH. Pixel 180A, including pixel circuit 181A, does not emit light during period PVH. The condition for light-emitting element OLED to not emit light is that voltage Vne supplied to third node N3 is lower than threshold voltage VTHEL of light-emitting element OLED. In other words, voltage Vne < threshold voltage VTHEL.

[0316] For example, in pixel circuit 181A, when emitting light based on voltage VSIGH (initialization voltage VINI2) corresponding to white, initialization voltage VINI2 is supplied to second node N2, and voltage Vne is supplied to third node N3. In this case, potential difference Vgs is the difference between the voltage supplied to second node N2 and the voltage supplied to third node N3: potential difference Vgs = initialization voltage VINI2 - voltage Vne. Furthermore, since charge equivalent to threshold voltage VTH is retained in potential difference Vgs, initialization voltage VINI2 - voltage Vne = threshold voltage VTH.

[0317] The conditions for the initialization voltage VINI2 calculated using the above formula are as follows: Figure 21 As shown, the initialization voltage VINI2 is less than the threshold voltage VTHEL and the threshold voltage VTH. In addition, the condition of the initialization voltage VINI1 is that the initialization voltage VINI1 is less than the threshold voltage VTHEL.

[0318] <3. Third embodiment>

[0319] Reference Figure 1 、 Figure 4 、 Figures 22 to 28 , an overview of a self-luminous display device 10 according to a third embodiment will be described. Figure 22 This is a schematic diagram showing input signals to the pixel 180B (pixel circuit 181B) according to the third embodiment of the present invention. Figure 23 is a circuit diagram showing the structure of the pixel circuit 181B. Figures 24 to 27 This is a timing chart of the self-luminous display device 10 according to the third embodiment of the present invention. Figure 28 This is a diagram for explaining the setting of input signals according to the third embodiment of the present invention.

[0320] The self-luminous display device according to the third embodiment has a structure and functions obtained by replacing the pixel 180A and pixel circuit 181A of the self-luminous display device 10 according to the second embodiment with a pixel 180B and pixel circuit 181B. The structure and functions otherwise are the same as those of the self-luminous display device 10 according to the second embodiment. Therefore, when describing the structure and functions of the third embodiment, the structure and functions that are the same as those of the self-luminous display device 10 according to the second embodiment will be described as needed.

[0321] <3-1. Structure of Pixel 180B>

[0322] Reference Figure 22 as well as Figure 23 , an overview of the pixel 180B and the pixel circuit 181B is described.

[0323] like Figure 22 as well as Figure 23 As shown, the pixel circuit 181B includes a structure and function obtained by replacing the scanning voltage power line SVIR of the pixel circuit 181A with the scanning voltage power line SVIRB. Figure 23 As shown, the structures of the second transistor T2 and the light-emitting element OLED of the pixel circuit 181B are different from those of the pixel circuit 181A.

[0324] Specifically, if Figure 22 As shown, pixel circuit 181B is connected to a scanning voltage supply line SVIRB, which supplies a scanning voltage supply SIRB(n). Scanning voltage supply line SVIRB, like scanning voltage supply line SVIR, is a signal line that also serves as a reference voltage supply line SVR and an initialization voltage supply line SVI. Scanning voltage supply SIRB(n) is a signal obtained by inverting the polarity of scanning voltage supply SIR(n) supplied to pixel circuit 181A. Similarly to scanning voltage supply SIRB(n), the polarity of signals other than scanning voltage supply SIRB(n) supplied to pixel circuit 181B is also an inverted signal of the polarity of signals other than scanning voltage supply SIR(n) supplied to pixel circuit 181A. Scanning voltage supply line SVIRB (a signal line that also serves as a reference voltage supply line SVR and an initialization voltage supply line SVI) is sometimes referred to as a third control signal line. Scanning voltage supply SIRB(n) is sometimes referred to as a third control signal.

[0325] In addition, specifically, Figure 23 As shown, pixel circuit 181B includes a second transistor T2, which is a p-channel field-effect transistor. Furthermore, in pixel circuit 181B, a second electrode 684 of the light-emitting element OLED is electrically connected to a reference voltage line PVSS, and a first electrode 682 of the light-emitting element OLED is electrically connected to a first electrode 624 of the second transistor T2, a third node N3, a second electrode 656 of the fifth transistor T5, and a first electrode 692 of the capacitor CS. The first electrode 682 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light-emitting element OLED is, for example, an anode electrode.

[0326] The fourth transistor T4 has the following functions: conducting the second node N2 with the scan voltage supply line SVIRB, supplying the initialization voltage VINI1 or VINI2 to the second node N2, and initializing the second node N2.

[0327] The fifth transistor T5 has the following functions: conducting the third node N3 and the scan voltage supply line SVIRB, supplying the initialization voltage VINI2 to the third node N3, and initializing the third node N3.

[0328] The configuration and function of the pixel circuit 181B other than the configuration and function described in “3-1” are the same as those of the pixel circuit 181 or the pixel circuit 181A.

[0329] <3-2. Driving Method of Pixel Circuit 181B>

[0330] Reference Figures 24 to 27 , a driving method of the self-luminous display device 10 according to the third embodiment will be described. Figures 1 to 23 The same or similar structures will be described as needed. It should be noted that, similar to the first and second embodiments, the horizontal axis of the timing chart represents time (TIME).

[0331] For example, the driving method of the self-luminous display device 10 according to the third embodiment is a driving method in which the polarity of each signal in the driving method of the self-luminous display device 10 according to the second embodiment is reversed. This is a driving method in which the polarity of the voltage (potential) supplied to each node in the driving method of the self-luminous display device 10 according to the second embodiment is reversed. Other structures and functions are the same as those of the driving method of the self-luminous display device 10 according to the first embodiment and the driving method of the self-luminous display device 10 according to the second embodiment. Therefore, the description of the structures and functions that are the same as those of the driving method of the self-luminous display device 10 according to the second embodiment will be omitted here.

[0332] The driving method of the self-luminous display device 10 according to the third embodiment includes the following steps: Figure 4 The driving method of the self-luminous display device 10 shown is the same as that of the embodiment.

[0333] Figures 24 to 27 These are diagrams of the period PIW and the period PVH for explaining a method of driving the pixel 180B (pixel circuit 181B). Figures 24 to 27 The light emitting period PEM of the frame before this frame (K-1stFRAME), the period PIW and the period PVH of this frame (KthFRAME) are shown. Figures 24 to 27 One horizontal period (horizontal period HRP) for one pixel 180B (pixel circuit 181B) is shown.

[0334] During one horizontal period in the driving method of the self-luminous display device 10 according to the third embodiment, a pixel 180B (pixel circuit 181B) receives inputs including a first scanning signal SC1(n), a second scanning signal SC2(n), an image data signal SL(m) including a data signal VDATA, and a scanning voltage supply SIRB(n). For example, the first scanning signal SC1(n), the second scanning signal SC2(n), and the scanning voltage supply SIR(n) are shifted, and a pixel 180B (pixel circuit 181B) corresponding to the shifted signals is selected. The image data signal SL(m), the initialization voltage VINI, and the reference voltage VREF are then input to the selected pixel 180B (pixel circuit 181B). The same operation is performed for all pixels 180B (pixel circuit 181B), and based on the image data signal SL(m) input to all pixels 180B (pixel circuit 181B), an image corresponding to one frame, equivalent to one frame, is displayed in the display area 22 of the self-luminous display device 10.

[0335] For example, supplied to Figures 24 to 27 Tables 5 and 6 show the signals and voltages (potentials) of the nodes in each frame in the timing chart shown.

[0336]

[0337]

[0338] As described above, the signal supplied to the pixel circuit 181B is a signal obtained by inverting the polarity of the signal supplied to the pixel circuit 181A. For example, as shown in Table 5, Table 6, Figures 24 to 27 As shown, the voltage VSIGL included in the data signal VDATA is -3.5V, and the pixel 180B supplied with the voltage VSIGL emits light. For example, one pixel emits red, one pixel emits green, and one pixel emits blue, resulting in three pixels emitting white. Alternatively, for example, the voltage VSIGH included in the data signal VDATA is 0.5V, and the pixel 180B supplied with the voltage VSIGH does not emit light, appearing black. Alternatively, for example, the voltage VL(LO) is -10V, the voltage VNN is 5V, the voltage VMN is -5V, the initialization voltage VINI1 is 1.5V, and the initialization voltage VINI2 is 0V. For example, the voltage VH (HI), the voltage VL (LO), the voltage VNN, the voltage VMN, the initialization voltage VINI1, and the initialization voltage VINI2 supplied to the pixel circuit 181B correspond to voltages (potentials) obtained by inverting the polarity of the voltage VL (LO), the voltage VH (HI), the voltage VN, the voltage VM, the initialization voltage VINI2, and the initialization voltage VINI1 supplied to the pixel circuit 181A.

[0339] <3-2-1. First Example of a Method for Driving the Pixel Circuit 181B>

[0340] Reference Figure 24 A first example of a method for driving pixel circuit 181B will be described. This first example of the method for driving pixel circuit 181B includes: after pixel 180B displays a white image based on voltage VSIGL (-3.5V) included in data signal VDATA in the frame (K-1st FRAME) preceding the current frame (KthFRAME), pixel 180B then displays a black image based on voltage VSIGH (0.5V) included in data signal VDATA in the KthFRAME. In other words, the first example of the method for driving the self-luminous display device 10 according to the third embodiment includes displaying images of different colors in consecutive frames.

[0341] As described above, the structure and function of the image data signal SL(m), first scanning signal SC1(n), and second scanning signal SC2(n) within the light-emission period PEM of the K-1st FRAME, the horizontal period HRP of the Kth FRAME, and the light-emission period PEM are similar to those obtained by inverting the polarity of the voltages (potentials) of these signals in the method for driving the self-luminous display device 10 according to the second embodiment. For example, the voltages (potentials) at the first node N1, second node N2, and third node N3 within the light-emission period PEM of the K-1st FRAME, the horizontal period HRP of the Kth FRAME, and the light-emission period PEM are similar to those obtained by inverting the polarity of the voltages (potentials) of these nodes in the method for driving the self-luminous display device 10 according to the second embodiment. The conduction and non-conduction of the transistors within the light-emission period PEM of the K-1st FRAME, the horizontal period HRP of the Kth FRAME, and the light-emission period PEM are also similar to those described in "2-2-1. First Example of the Method for Driving the Self-luminous Display Device 10."

[0342] For example, voltages Vnan, Vnbn, Vncn, Vndn, Vnen, and Vnfn are voltages (potentials) obtained by inverting the polarity of voltages Vna, Vnb, Vnc, Vnd, Vne, and Vnf. Referring to the voltages (potentials) in the driving method according to the second embodiment, voltage Vnan is -7 V, voltage Vnbn is -2.5 V, voltage Vncn is 1.5 V, voltage Vndn is 0.5 V, voltage Vnen is 1 V, and voltage Vnfn is -3.5 V.

[0343] Referring to the first example of the driving method according to the second embodiment, the conduction state and the non-conduction state of each transistor of the PEM during the light emission period of K-1stFRAME and Figure 24 During the light-emission period PEM of K-1stFRAME, pixel 180B emits light based on the potential difference Vgs (voltage V(N2) - voltage V(N3) = voltage Vnan - voltage Vnbn) of second transistor T2. With a potential difference Vgs of -4.5V, pixel 180B emits red light, and the three pixels (pixel 180B emitting red, pixel 180B emitting blue, and pixel 180B emitting green) emit white light.

[0344] During the start of a horizontal period HRP of KthFRAME after the light-emitting period PEM of K-1stFRAME, the scanning voltage power supply SIRB (n) changes from the state of being supplied with the initialization voltage VINI2 (0V) to the state of being supplied with the initialization voltage VINI1 (1.5V). If the scanning voltage power supply SIRB (n) changes to the state of being supplied with the initialization voltage VINI1, the first scanning signal SC1 (n) changes from the state of being supplied with LO to the state of being supplied with HI. In addition, the second scanning signal SC2 (n) is in the state of being supplied with LO. Referring to the first example of the driving method involved in the second embodiment, the conductive state and the non-conductive state of each transistor during the start of a horizontal period HRP of KthFRAME and Figure 24 The voltage supplied to the first node N1 gradually increases from voltage Vnan to voltage VSIGH (voltage Vndn), and the voltage supplied to the second node N2 gradually increases from voltage Vnan to initialization voltage VINI1 (voltage Vncn). Furthermore, in response to the increase in the voltage supplied to the second node N2, the second transistor T2 switches from an on state to an off state.

[0345] During period PIW, the image data signal SL(m) maintains the state in which the data signal VDATA including the voltage VSIGH is supplied. Furthermore, during period PIW, the first scan signal SC1(n) maintains the state in which the data signal VDATA including the voltage VSIGH is supplied, the scan voltage supply SIRB(n) maintains the state in which the initialization voltage VINI1 is supplied, and the second scan signal SC1(n) transitions from the state in which the data signal VDATA including the voltage VSIGL is supplied. Furthermore, during the end of period PIW, the image data signal SL(m) maintains the state in which the data signal VDATA including the voltage VSIGL is supplied, the first scan signal SC1(n) maintains the state in which the data signal VDATA including the voltage VSIGL is supplied, and the scan voltage supply SIR(n) maintains the state in which the initialization voltage VINI1 is supplied. Furthermore, the second scan signal SC1(n) transitions from the state in which the data signal VDATA including the voltage VSIGL is supplied.

[0346] Referring to the first example of the driving method according to the second embodiment, the conduction state and the non-conduction state of each transistor during the period PIW and Figure 24 , the voltage supplied to the first node N1 gradually increases from voltage Vnan to voltage VSIGH, reaching voltage Vndn (0.5V). The voltage supplied to the second node N2 gradually increases from voltage Vnan to initialization voltage VINI1 (voltage Vncn), reaching voltage Vncn (1.5V). Furthermore, the voltage supplied to the third node N3 gradually increases from voltage Vnbn to initialization voltage VINI1 (voltage Vnc), reaching voltage Vnc (1.5V). The potential difference Vgs becomes 0V, and the potential difference Vds becomes -9.5V (-8V - (1.5V)).

[0347] As described above, in the period PIW, the data signal VDATA including the voltage VSIGH is supplied to (written into) the first node N1 , and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (1.5 V).

[0348] During period PVH, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGH. Furthermore, the first scan signal SC1(n) maintains the state of being supplied with the HI signal, and the second scan signal SC1(n) maintains the state of being supplied with the LO signal. It should be noted that after the second scan signal SC1(n) is supplied with the LO signal during period PIW, the scan voltage supply SIRB(n) switches from being supplied with the initialization voltage VINI1 to being supplied with the initialization voltage VINI2. When the scan voltage supply SIR(n) switches from being supplied with the initialization voltage VINI2, the first scan signal SC1(n) switches from being supplied with the HI signal to being supplied with the LO signal.

[0349] Immediately after the start of period PVH, the potential difference Vgs is 0V and the potential difference Vds is -9.5V. This potential difference Vgs is greater than the threshold voltage VTHP (-1V, see Table 6) of the second transistor T2, turning off the second transistor T2. Consequently, the drain current Ion does not flow from the first electrode 624 to the second electrode 626 of the second transistor T2.

[0350] In the period PVH, referring to the first example of the driving method according to the second embodiment, the conduction state and the non-conduction state of each transistor in the period PVH and Figure 24Since the fourth transistor T4 remains on, if the voltage supplied to the scan voltage source SIRB(n) changes from initialization voltage VINI1 to initialization voltage VINI2, the voltage supplied to the second node N2 gradually decreases from voltage Vncn (1.5V) to initialization voltage VINI2 (0V), reaching initialization voltage VINI2 (0V). At this time, the fifth transistor T5 is off, and the Vgs of the second transistor T2 approaches -1.5V (0V (node ​​N2) - (1.5V) (node ​​3)), which is greater than the threshold voltage VTH (-1V). Therefore, the drain current Ion of the second transistor T2 begins to flow, and the voltage supplied to the third node N3 gradually decreases from voltage Vncn (1.5V) to voltage Vne (1V). As a result, the voltage supplied to the third node N3 reaches voltage Vnen (1V), and the potential difference Vgs becomes -1V (0V - (1V)). The potential difference Vgs is equal to the threshold voltage VTHP (−1 V), so the second transistor T2 is in the off state. Therefore, the drain current Ion does not flow from the second electrode 626 of the second transistor T2 to the first electrode 624 .

[0351] As described above, during the period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTHP, thereby obtaining the threshold voltage VTHP of the second transistor T2. In addition, a charge corresponding to the threshold voltage VTHP is retained at the second node N2 (the gate electrode 622 of the second transistor T2).

[0352] During the KthFRAME light emission period PEM following the KthFRAME horizontal period HRP, no select signal is used to select data, and the data signal VDATA is maintained at a voltage above the voltage VSIGL and below the voltage VSIGH. Furthermore, the first scan signal SC1(n) transitions from being HI to being LO, while the second scan signal SC2(n) remains LO. The scan voltage supply SIRB(n) remains supplied with the initialization voltage VINI2 (0V).

[0353] As a result, the first transistor T1 and the fourth transistor T4 go from an on state to an off state, and the third transistor T3 goes from an off state to an on state. Furthermore, the fifth transistor T5 remains in an off state. As the third transistor T3 turns on, the first node N1 and the second node N2 become conductive, and the potential difference Vgs reaches -0.5V. The potential difference Vgs is smaller than the threshold voltage VTHP. Consequently, the second transistor T2 turns off, and current does not flow from the drive power line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to not emit light. As a result, for example, pixel 180B (pixel circuit 181B) emitting red, pixel 180B emitting blue, and pixel 180B emitting green do not emit light, causing the three pixels (pixel 180B, blue, and green) to appear black.

[0354] As described above, the driving method of the self-luminous display device 10 according to the third embodiment (the driving method of the pixel circuit 181B) includes, similar to the driving method of the self-luminous display device 10 according to the second embodiment, executing the processing (driving) performed during the writing period and the processing (driving) performed during the initialization period at the same timing. Furthermore, like the pixel circuit 181A, the pixel circuit 181B has a structure that can reduce the number of signal lines. Therefore, the self-luminous display device including the pixel circuit 181B can reduce the pixel size. Therefore, the self-luminous display device 10 and the driving method of the self-luminous display device 10 according to the third embodiment have the same operational advantages as the self-luminous display device 10 and the driving method of the self-luminous display device 10 according to the second embodiment.

[0355] <3-2-2. Second Example of the Driving Method of the Pixel Circuit 181B>

[0356] Reference Figure 25 , a second example of the driving method of the pixel circuit 181B is described. The driving method shown in the second example of the pixel circuit 181B includes: after the pixel 180B displays a white image based on the voltage VSIGL (-3.5V) included in the data signal VDATA in the previous frame (K-1stFRAME) of the current frame (KthFRAME), the pixel 180B also displays a white image based on the voltage VSIGL (-3.5V) included in the data signal VDATA in KthFRAME. In other words, the second example of the driving method of the self-luminous display device 10 involved in the third embodiment includes displaying images of the same color (white) in consecutive frames. For Figures 1 to 24 The same or similar structures will be explained as needed.

[0357] The configuration of the K-1st FRAME light-emission period PEM, one horizontal period HRP of the Kth FRAME, the image data signal SL(m), the scanning voltage supply SIRB(n), the first scanning signal SC1(n), and the second scanning signal SC2(n) within the light-emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "3-2-1." Furthermore, the voltages (potentials) of the first node N1, second node N2, and third node N3 within the K-1st FRAME light-emission period PEM, as well as the operation of each transistor, are the same as those described in "3-2-1. First Example of Driving Method for Pixel Circuit 181B." Configurations similar to those described in "3-2-1. First Example of Driving Method for Pixel Circuit 181B" will be described as needed. Configurations similar to those described in "2-2-2. Second Example of Driving Method for Pixel Circuit 181A" will be described as needed.

[0358] During the start of a horizontal period HRP of KthFRAME, pixel 180B (pixel circuit 181B) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGL corresponding to white. The voltage supplied to first node N1 gradually increases from voltage Vnan to voltage VSIGL (voltage Vnfn, -3.5V). The voltage supplied to second node N2 and third node N3 are the same as those described in "3-2-1. First Example of Driving Method of Pixel Circuit 181B."

[0359] During period PIW, the voltage supplied to the first node N1 gradually increases from voltage Vnan to voltage Vnfn, reaching voltage Vnfn (-3.5 V). The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "3-2-1. First Example of Driving Method of Pixel Circuit 181B."

[0360] As described above, in the period PIW, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1 , and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (1.5 V).

[0361] During the period PVH following the period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL. The first node N1 maintains the state of being supplied with the voltage Vnfn. The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "3-2-1. First Example of Driving Method of Pixel Circuit 181B."

[0362] As described above, similar to the description in "3-2-1," during period PVH, the threshold voltage VTHP of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTHP. Furthermore, a charge corresponding to the threshold voltage VTHP is retained at the second node N2 (gate electrode 622 of the second transistor T2).

[0363] In the light emitting period PEM of KthFRAME after one horizontal period HRP of KthFRAME, referring to the conduction state and non-conduction state of each transistor in the light emitting period PEM of KthFRAME of the second example of the driving method involved in the second embodiment and Figure 24 , the first node N1 and the second node N2 are turned on, and the voltage of the first node N1 and the voltage of the second node N2 gradually decrease. The second transistor T2 becomes turned on, and the drain current Ion flows from the reference voltage line PVSS to the drive power line PVDD. The voltage of the third node N3 decreases in a manner that follows the decrease of the voltage of the first node N1 and the voltage of the second node N2.

[0364] As a result, the potential difference Vgs (voltage Vnan (-7V) - voltage Vnbn (-2.5V)) becomes -4.5V, which is lower than the threshold voltage VTHP (-1V). Consequently, the second transistor T2 is turned on, and the drain current Ion flows from the reference voltage line PVSS to the drive power line PVDD, causing the light-emitting element OLED to emit light. For example, pixel 180B (pixel circuit 181B) turns red, while the three pixels—pixel 180B emitting blue and pixel 180B emitting green—emit white light.

[0365] <3-2-3. Third Example of the Driving Method of the Pixel Circuit 181B>

[0366] Reference Figure 26, a third example of the driving method of the pixel circuit 181B is described. The driving method shown in the third example of the driving method of the pixel circuit 181B includes: after the pixel 180B displays a black image based on the voltage VSIGL included in the data signal VDATA in the previous frame (KthFRAME) of the current frame (KthFRAME), the pixel 180B also displays a black image based on the voltage VSIGH included in the data signal VDATA in KthFRAME. In other words, it includes displaying images of the same color (black) in consecutive frames. Figures 1 to 25 The same or similar structures will be explained as needed.

[0367] The structure of the light-emitting period PEM of K-1stFRAME, one horizontal period HRP of KthFRAME, the image data signal SL(m), the scanning voltage power supply SIRB(n), the first scanning signal SC1(n) and the second scanning signal SC2(n) in the light-emitting period PEM, and the conduction state and non-conduction state of each transistor are the same as the structure described in "3-2-1. First example of the driving method of the pixel circuit 181B".

[0368] Referring to the third example of the driving method according to the second embodiment, the conduction state and the non-conduction state of each transistor of the PEM during the light emission period of K-1stFRAME and Figure 26 During the K-1st FRAME light emission period PEM, pixel 180B emits light based on the potential difference Vgs (voltage V(N2) - voltage V(N3) = voltage Vnen - voltage Vnen) across second transistor T2. Potential difference Vgs is 0V, which is greater than the threshold voltage VTHP (-1V) of second transistor T2. Since second transistor T2 is off, no current flows from reference voltage line PVSS to drive power line PVDD, causing the light-emitting element OLED to not emit light. As a result, for example, pixel 180B (pixel circuit 181B) appears black.

[0369] During the start of the horizontal period HRP of KthFRAME following the light-emission period PEM of K-1stFRAME, the pixel 180B (pixel circuit 181B) receives the image data signal SL(m) including the data signal VDATA including the voltage VSIGH (0.5V) corresponding to black, which indicates no light emission. Referring to the conduction state and the non-conduction state of each transistor during the start of the horizontal period HRP of KthFRAME in the third example of the driving method according to the second embodiment, Figure 26, the voltage supplied to the first node N1 remains at the voltage Vndn (0.5 V), and the first node N1 maintains the state of being supplied with 0.5 V. The voltage supplied to the second node N2 gradually increases from the voltage Vndn (0.5 V) to the initialization voltage VINI1 (voltage Vncn, 1.5 V).

[0370] During period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGH. The first node N1 maintains the state of being supplied with 0.5V. The voltage supplied to the second node N2 gradually increases from the voltage Vndn to the voltage Vncn, reaching the voltage Vncn (1.5V). Furthermore, the voltage supplied to the third node N3 gradually increases from the voltage Vnen (1V) to the initialization voltage VINI1 (voltage Vncn, 1.5V), reaching the voltage Vncn (1.5V).

[0371] As described above, in the period PIW, the data signal VDATA including the voltage VSIGH (0.5V) is supplied to (written into) the first node N1 , and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (1.5V).

[0372] During the period PVH following the period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGH. The voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "3-2-1. First Example of Driving Method of Pixel Circuit 181B."

[0373] As described above, similar to the description in "3-2-1. First Example of Driving Method of Pixel Circuit 181B," during period PVH, the threshold voltage VTHP of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTHP. Furthermore, a charge corresponding to the threshold voltage VTHP is retained at the second node N2 (gate electrode 622 of the second transistor T2).

[0374] During the KthFRAME light emission period PEM following the KthFRAME horizontal period HRP, the voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "3-2-1. First Example of Driving Method of Pixel Circuit 181B." As in "3-2-1. First Example of Driving Method of Pixel Circuit 181B," the red-emitting pixel 180B does not emit light, and the three pixels, namely, the red-emitting pixel 180B, the blue-emitting pixel 180B, and the green-emitting pixel 180B, are black.

[0375] As described above, the third example of the driving method for the self-luminous display device 10 according to the third embodiment (the method for driving the pixel circuit 181B) is similar to the third example of the driving method for the self-luminous display device 10 according to the second embodiment. When displaying images of the same color (black) in consecutive frames, the voltage fluctuations at each node are minimal. This reduces power consumption caused by the voltage fluctuations at each node. Consequently, the self-luminous display device 10 is a display device capable of achieving low power consumption.

[0376] <3-2-4. Fourth Example of the Driving Method of the Pixel Circuit 181B>

[0377] Reference Figure 27 , a fourth example of the driving method of the pixel circuit 181B is described. The driving method shown in the fourth example of the driving method of the pixel circuit 181B includes: after the pixel 180B (pixel circuit 181B) displays a black image based on the voltage VSIGH included in the data signal VDATA in the previous frame (K-1stFRAME) of the current frame (KthFRAME), the pixel 180B (pixel circuit 181B) displays a white image based on the voltage VSIGL included in the data signal VDATA in KthFRAME. In other words, it includes displaying images of different colors in consecutive frames. Figures 1 to 26 The same or similar structures will be explained as needed.

[0378] The configuration of the K-1st FRAME light-emission period PEM, one horizontal period HRP of the Kth FRAME, the image data signal SL(m), the scanning voltage supply SIRB(n), the first scanning signal SC1(n), and the second scanning signal SC2(n) within the light-emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "3-2-1." Furthermore, the voltages (potentials) of the first node N1, second node N2, and third node N3 within the K-1st FRAME light-emission period PEM, as well as the operation of each transistor, are the same as those described in "3-2-3. Third Example of the Driving Method for Pixel Circuit 181B." The configuration and other details similar to those described in "3-2-1. First Example of the Driving Method for Pixel Circuit 181B" to "3-2-3. Third Example of the Driving Method for Pixel Circuit 181B" will be described as needed.

[0379] During the start of a horizontal period HRP of KthFRAME, pixel 180B (pixel circuit 181B) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGL corresponding to white. The voltage supplied to first node N1 gradually decreases from voltage Vndn (0.5V) to voltage VSIGL (voltage Vnfn, −3.5V), while the voltage supplied to second node N2 gradually increases from voltage Vnen (1V) to voltage Vncn (1.5V).

[0380] During period PIW, the voltage supplied to the first node N1 gradually decreases from voltage Vndn (0.5V) to voltage VSIGL (voltage Vnfn, -3.5V), and the first node N1 is supplied with voltage Vnfn (-3.5V). The voltage supplied to the second node N2 gradually increases from voltage Vnen (0.5V) to voltage Vncn (1.5V), and the second node N2 is supplied with voltage Vncn (1.5V). Furthermore, the voltage supplied to the third node N3 gradually increases from voltage Vnen (1V) to initialization voltage VINI1 (voltage Vncn, 1.5V), and the third node N3 is supplied with voltage Vncn (1.5V). At this time, the potential difference Vgs reaches 0V (1.5V - (1.5V)), and the potential difference Vds reaches -9.5V (-8V - (1.5V)).

[0381] As described above, in the period PIW, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1 , and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (1.5 V).

[0382] During the period PVH following the period PIW, similar to the description in "3-2-2," the first node N1 is maintained at the voltage Vnfn, the second node N2 is maintained at the initialization voltage VINI2 (0V), and the voltage supplied to the third node N3 decreases from the voltage Vncn to the voltage Vnen, with the third node N3 being supplied with the voltage Vnen (1V). At this time, Vgs is -1V (0V-1V), which is the same as the threshold voltage VTHP (-1V).

[0383] As described above, during the period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTHP, thereby obtaining the threshold voltage VTHP of the second transistor T2. Furthermore, a charge corresponding to the threshold voltage VTHP is retained at the second node N2 (the gate electrode 622 of the second transistor T2).

[0384] During the KthFRAME light-emission period PEM following the KthFRAME horizontal period HRP, the potential difference Vgs reaches -4.5V, as described in "3-2-2." The potential difference Vgs is smaller than the threshold voltage VTHP, turning on the second transistor T2. The drain current Ion flows from the reference voltage line PVSS to the drive power line PVDD. As a result, the light-emitting element OLED emits light. For example, pixel 180B emits red light, while three pixels—pixel 180B emitting blue and pixel 180B emitting green—emit white light.

[0385] <3-3. Setting Values ​​of Initialization Voltages VINI1 and VINI2>

[0386] Reference Figure 28 , the setting values ​​of the initialization voltages VINI1 and VINI2 are described. Figure 28 1 is a diagram for explaining the setting values ​​of the initialization voltages VINI1 and VINI2 of the scanning voltage power supply line SVIRB to which the scanning voltage power supply SIRB(n) is supplied. Figures 1 to 27 The same or similar structures will be explained as needed.

[0387] For example, Figure 28 As shown, between the periods PIW and PVH, the scan voltage source SIRB(n) changes from being supplied with the initialization voltage VINI1 to being supplied with the initialization voltage VINI2 according to the timing of the first scan signal SC1(n) and the second scan signal SC2(n).

[0388] During period PIW, in pixel circuit 181B, scan voltage supply SIRB(n) (initialization voltage VINI1) is supplied from scan voltage supply line SVIRB to second node N2 and third node N3, initializing second node N2 and third node N3. Pixel 180B, including pixel circuit 181B, does not emit light during period PIW. The condition for the light-emitting element OLED to not emit light is that the initialization voltage VINI1 supplied to third node N3 is greater than the threshold voltage VTHEL of the light-emitting element OLED. In other words, initialization voltage VINI1 > threshold voltage VTHEL.

[0389] Furthermore, pixel circuit 181B corrects threshold voltage VTHP during period PVH and holds a charge equivalent to threshold voltage VTHP. Pixel 180B, including pixel circuit 181B, does not emit light during period PVH. The condition for light-emitting element OLED to not emit light is that voltage Vnen supplied to third node N3 is greater than threshold voltage VTHEL of light-emitting element OLED. In other words, voltage Vnen > threshold voltage VTHEL.

[0390] For example, when pixel circuit 181B emits light based on voltage VSIGL corresponding to white, initialization voltage VINI2 is supplied to second node N2, and voltage Vnen is supplied to third node N3. In this case, potential difference Vgs is the difference between the voltage supplied to second node N2 and the voltage supplied to third node N3, where potential difference Vgs = initialization voltage VINI2 - voltage Vnen. Furthermore, since charge equivalent to threshold voltage VTHP is retained in potential difference Vgs, initialization voltage VINI2 - voltage Vnen = threshold voltage VTHP.

[0391] The conditions for the initialization voltage VINI2 calculated using the above formula are as follows: Figure 28 As shown, the initialization voltage VINI2 is greater than the threshold voltage VTHEL and the threshold voltage VTHP. In addition, the condition of the initialization voltage VINI1 is that the initialization voltage VINI1 is greater than the threshold voltage VTHEL.

[0392] <4. Fourth embodiment>

[0393] Reference Figure 1 、 Figure 4 、 Figures 29 to 37 , an overview of a self-luminous display device 10 according to a fourth embodiment will be described. Figure 29 This is a schematic diagram illustrating input signals to the pixel 180C (pixel circuit 181C) according to the fourth embodiment of the present invention. Figure 30 is a circuit diagram showing the structure of the pixel circuit 181C. Figure 31 、 Figure 34 、 Figure 36、 Figure 37 This is a timing chart of the self-luminous display device 10 according to the fourth embodiment of the present invention. Figure 32 as well as Figure 33 It is shown in Figure 31 Schematic diagram of the operating state of the pixel circuit 181C at the timing shown. Figure 35 It is shown in Figure 34 Schematic diagram of the operating state of the pixel circuit 181C at the timing shown.

[0394] The self-luminous display device according to the fourth embodiment has a structure and function obtained by replacing the pixel 180A and the pixel circuit 181A of the self-luminous display device 10 according to the second embodiment with the pixel 180C and the pixel circuit 181C. The structure and function other than this are the same as those of the self-luminous display device 10 according to the second embodiment. Therefore, when describing the structure and function of the fourth embodiment, the structure and function similar to those of the self-luminous display device 10 according to the second embodiment will be described as needed. Figures 1 to 28 The same or similar structures will be explained as needed.

[0395] <4-1. Structure of Pixel 180C>

[0396] Reference Figure 29 as well as Figure 30 , an overview of the pixel 180C and the pixel circuit 181C is described.

[0397] The pixel circuit 181C is connected to the second scanning signal line 334. The second scanning signal line 334 according to the fourth embodiment serves as both the second scanning signal line 334 supplied to the pixel circuit 181A and the scanning voltage supply line SVIR. In other words, the second scanning signal line 334 according to the fourth embodiment is a signal line that combines the second scanning signal line 334 supplied to the pixel circuit 181A and the scanning voltage supply line SVIR. The scanning voltage supply SIR2(n), obtained by combining the second scanning signal and the scanning voltage supply SIR(n) supplied to the pixel circuit 181A, is supplied to the second scanning signal line 334 according to the fourth embodiment. The second scanning signal line 334 according to the fourth embodiment (which serves as both the second scanning signal line 334 and the scanning voltage supply line SVIR) is sometimes referred to as a third control signal line. The scanning voltage supply SIR2(n) is sometimes referred to as a third control signal.

[0398] In the pixel circuit 181C, the first electrode 644 of the fourth transistor T4, the first electrode 654, and the gate electrode 652 of the fifth transistor T5 are electrically connected to the second scanning signal line 334. The fourth transistor T4 has the following functions: conducts electricity between the second node N2 and the second scanning signal line 334, supplies the initialization voltage VINI1 or VINI2 to the second node N2, and initializes the second node N2.

[0399] The pixel circuit 181C also includes a p-channel field effect transistor (FET) fifth transistor T5 , which connects the third node N3 to the second scanning signal line 334 and supplies the initialization voltage VINI1 to the third node N3 to initialize the third node N3 .

[0400] The configuration and function of the pixel circuit 181C other than the configuration and function described in “4-1” are the same as those of the pixel circuit 181A.

[0401] <4-2. Driving Method of Pixel Circuit 181C>

[0402] Reference Figures 29 to 37 , a driving method of the self-luminous display device 10 according to the fourth embodiment will be described. Figures 1 to 30 The same or similar structures will be described as needed. It should be noted that, similar to the first embodiment, the horizontal axis of the timing chart represents time (TIME).

[0403] The driving method of the self-luminous display device 10 according to the fourth embodiment has a structure and function obtained by replacing the operations associated with the second scanning signal SC2(n) and the scanning voltage source SIR(n) in the driving method of the self-luminous display device 10 according to the second embodiment with operations associated with the scanning voltage source SIR2(n). The structure and function other than the operations associated with the scanning voltage source SIR2(n) are the same as those of the driving method of the self-luminous display device 10 according to the second embodiment. The description of the structure and function that are the same as those of the driving method of the self-luminous display device 10 according to the second embodiment will be omitted here.

[0404] The driving method of the self-luminous display device 10 according to the fourth embodiment includes the following steps: Figure 4 The driving method of the self-luminous display device 10 shown is the same as that of the embodiment.

[0405] Figure 31 、 Figure 34 、 Figure 36 、 Figure 37 These are diagrams of the period PIW and the period PVH for explaining a method of driving the pixel 180C (pixel circuit 181C). Figures 31 to 34The light emitting period PEM of the frame before this frame (K-1stFRAME), the period PIW and the period PVH of this frame (KthFRAME) are shown. Figure 31 、 Figure 34 、 Figure 36 、 Figure 37 One horizontal period (horizontal period HRP) for one pixel 180C (pixel circuit 181C) is shown.

[0406] In the driving method of the self-luminous display device 10 according to the fourth embodiment, during one horizontal period, a scanning signal SC(n), a scanning voltage supply SIR2(n), and an image data signal SL(m) including a data signal VDATA are input to a pixel 180C (pixel circuit 181C). For example, the scanning signal SC(n) and the scanning voltage supply SIR2(n) are shifted, and a pixel 180C (pixel circuit 181C) corresponding to the shifted signal is selected. The image data signal SL(m), the initialization voltage VINI, and the reference voltage VREF are input to the selected pixel 180C (pixel circuit 181C). The same operation is performed for all pixels 180C (pixel circuit 181C). Based on the image data signal SL(m) input to all pixels 180C (pixel circuit 181C), an image corresponding to one frame, equivalent to one frame, is displayed in the display area 22 of the self-luminous display device 10.

[0407] For example, supplied to Figure 31 、 Figure 34 、 Figure 36 、 Figure 37 Tables 7 and 8 show the signals and voltages (potentials) of the nodes in each frame in the timing chart shown.

[0408]

[0409]

[0410] The driving method of the self-luminous display device 10 according to the fourth embodiment is shown in Table 7, Table 8, Figures 31 to 34As shown, the voltage VSIGL included in the data signal VDATA is -0.5V. Pixel 180C supplied with the voltage VSIGL does not emit light, turning black. The voltage VSIGH included in the data signal VDATA is 3.5V. Pixel 180C supplied with the voltage VSIGH emits light. For example, one pixel emits red, one pixel emits green, and one pixel emits blue, for a total of three pixels emitting white. Furthermore, for example, the voltage VL(LO) is -3.5V, the voltage VH(HI) is 10V, the voltage VN is -5V, the voltage VM is 5V, the initialization voltage VINI1 is -3.5V, the initialization voltage VINI2 is 0V, the threshold voltage VTH of the second transistor T2 is 1V, the threshold voltage VTHPT5 of the fifth transistor T5 is -1V, and the threshold voltage VTHEL of the light-emitting element OLED is 0.7V.

[0411] <4-2-1. First Example of a Driving Method for Pixel Circuit 181C>

[0412] Reference Figure 31 Figure 33 Next, a first example of a method for driving the pixel circuit 181C will be described. The first example of a method for driving the pixel circuit 181C is similar to "2-2-1. First example of a method for driving the pixel circuit 181A," and includes displaying images of different colors in consecutive frames.

[0413] The structure and function of the light-emitting period PEM of K-1stFRAME, the horizontal period HRP of KthFRAME, and the image data signal SL(m) within the light-emitting period PEM are the same as those in "2-2-1. First example of the driving method of the pixel circuit 181A", and the structure and function of the scanning signal SC(n) are the same as the first scanning signal SC1(n) in the self-luminous display device 10 involved in the second embodiment.

[0414] During the light-emission period PEM of the K-1st FRAME, pixel 180C emits light based on the potential difference Vgs (voltage V(N2) - voltage V(N3) = voltage Vna - voltage Vnb) across the second transistor T2. For example, the scan signal SC(n) and the scan voltage source SIR2(n) are supplied at LO. The first transistor T1, the fourth transistor T4, and the fifth transistor T5 are turned off, and the third transistor T3 is turned on. Furthermore, the voltage Vna supplied to the first node N1 and the second node N2 is 7V, and the voltage Vnb supplied to the third node N3 is 2.5V. Therefore, the potential difference Vgs is 4.5V, and the second transistor T2 can flow a current Ion based on the potential difference Vgs and the potential difference corresponding to the voltage VSIGH input during the K-1st FRAME horizontal period HRP. Furthermore, when the second transistor T2 is in the on state, current Ion flows from the drive power line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, the pixel 180C emits red light, and three pixels, namely, the pixel 180C emitting red light, the pixel 180C emitting blue light, and the pixel 180C emitting green light, emit white light.

[0415] For example, Figure 31 as well as Figure 32 As shown, at the start of a horizontal period HRP of KthFRAME following the light-emission period PEM of K-1stFRAME, the scan voltage source SIR2(n) switches from being supplied with the HI state to being supplied with the initialization voltage VINI1 (voltage Vnh, -3.5V). When the scan voltage source SIR2(n) switches from being supplied with the initialization voltage VINI1, the scan signal SC(n) switches from being supplied with the LO state to being supplied with the HI state. Consequently, the first transistor T1, the fourth transistor T4, and the fifth transistor T5 switch from being OFF to being ON, and the third transistor T3 switches from being ON to being OFF. As a result, for example, the voltage supplied to the third node N3 gradually decreases from voltage Vnb. Furthermore, the voltage supplied to the first node N1 gradually decreases from voltage Vna to voltage VSIGL (voltage Vnd, -0.5V), and the voltage supplied to the second node N2 gradually decreases from voltage Vna to initialization voltage VINI1 (voltage Vnh, -3.5V).

[0416] During period PIW, image data signal SL(m) maintains the state of being supplied with data signal VDATA including voltage VSIGL, scan signal SC(n) maintains the state of being supplied with HI, and scan voltage source SIR2(n) maintains the state of being supplied with initialization voltage VINI1 (voltage Vnh, −3.5V). Therefore, first transistor T1, fourth transistor T4, and fifth transistor T5 remain in the on state, and the third transistor remains in the off state.

[0417] As a result, the voltage supplied to the third node N3 gradually decreases from voltage Vnb. When the potential difference between initialization voltage VINI1 (-3.5V) supplied to the gate electrode 652 and the voltage supplied to the second electrode 656 (the voltage supplied to the third node N3) becomes equal to the threshold voltage VTHPT5 (-1V) of the fifth transistor T5, the fifth transistor T5 switches from an on state to an off state. Specifically, when the voltage supplied to the second electrode 656 (the voltage supplied to the third node N3) reaches voltage Vng (-2.5V), the fifth transistor T5 switches from an on state to an off state. Furthermore, the voltage supplied to the first node N1 gradually decreases from voltage Vna to voltage VSIGL (voltage Vnd, -0.5V), reaching voltage Vnd (-0.5V). The voltage supplied to the second node N2 gradually decreases from voltage Vna to initialization voltage VINI1 (voltage Vnh, -3.5V), reaching initialization voltage VINI1 (-3.5V). When the voltage supplied to the second node N2 (-3.5 V) becomes lower than the voltage of the third node N3 (-2.5 V), the second transistor T2 switches from the on state to the off state. The potential difference Vds when the second transistor T2 is in the off state is 10.5 V (8 V - (-2.5 V)).

[0418] As described above, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1 , the second node N2 is initialized by the initialization voltage VINI1 (−3.5V), and the third node N3 is initialized to the voltage Vng (−2.5V) by the initialization voltage VINI1 (voltage Vnh, −3.5V).

[0419] For example, Figure 31 as well as Figure 33As shown, during period PVH, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL, and the scan signal SC(n) maintains the state of being supplied with the HI state. The scan voltage source SIR2(n) changes from being supplied with the initialization voltage VINI1 (voltage Vnh, -3.5V) to being supplied with the initialization voltage VINI2 (0V). Consequently, the fifth transistor T5 changes from being off to being on, the first transistor T1 and the fourth transistor T4 remain on, and the third transistor remains off.

[0420] Immediately after the start of the period PVH, the potential difference Vgs is -1 V and the potential difference Vds is 9.5 V. Since the potential difference Vgs is lower than the threshold voltage VTH (1 V), the second transistor T2 is in the off state. Consequently, the drain current Ion does not flow from the second electrode 626 of the second transistor T2 to the first electrode 624.

[0421] As a result, the voltage supplied to the first node N1 remains at voltage Vnd (-0.5V), while the voltage supplied to the second node N2 gradually increases from voltage Vnh (-3.5V) to initialization voltage VINI2 (0V), reaching initialization voltage VINI2 (0V). Furthermore, the voltage supplied to the third node N3 gradually increases from voltage Vng (-2.5V). When the potential difference between initialization voltage VINI2 (0V) supplied to the gate electrode 652 and the voltage supplied to the second electrode 656 (the voltage supplied to the third node N3) becomes equal to the threshold voltage VTH (1V) of the second transistor T2, the second transistor T2 switches from the on state to the off state. Specifically, when the voltage supplied to the second electrode 656 (the voltage supplied to the third node N3) changes from voltage Vng (-2.5V) to voltage Vne (-1V), the second transistor T2 switches from the on state to the off state. Consequently, the potential difference Vgs becomes 1V (0V - (-1V)). Since the potential difference Vgs is equal to the threshold voltage VTH (1V), the second transistor T2 is in the off state. Therefore, the drain current Ion does not flow from the second electrode 626 of the second transistor T2 to the first electrode 624 .

[0422] As described above, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. In addition, a charge corresponding to the threshold voltage VTH is held at the second node N2 (gate electrode 622 of the second transistor T2).

[0423] During the KthFRAME light-emission period PEM following the KthFRAME horizontal period HRP, no select signal is used to select data, and the data signal VDATA is maintained at a voltage above the voltage VSIGL and below the voltage VSIGH. Furthermore, the scan signal SC(n) transitions from being HIGH to being LO. When the scan signal SC(n) transitions to LO, the scan voltage supply SIR2(n) transitions from being supplied with the initialization voltage VINI2 (0V) to being supplied with the HI (10V) state.

[0424] Therefore, the first transistor T1 and the fourth transistor T4 are turned off from the on state, and the third transistor T3 is turned on from the off state. Furthermore, the fifth transistor T5 remains in the off state. By turning on the third transistor T3, the first node N1 and the second node N2 are electrically connected, and the potential difference Vgs becomes 0.5V (-0.5V - (-1V)). The potential difference Vgs is smaller than the threshold voltage VTH. Therefore, the second transistor T2 is turned off, and current does not flow from the drive power line PVDD to the reference voltage line PVSS, so the light-emitting element OLED does not emit light. As a result, for example, the pixel 180C that emits red, the pixel 180C that emits blue, and the pixel 180C that emits green do not emit light, so the three pixels using the pixel 180C that emits red, the pixel 180C that emits blue, and the pixel 180C that emits green are turned black.

[0425] As described above, the driving method of the self-luminous display device 10 according to the fourth embodiment (the driving method of the pixel circuit 181C) includes, similarly to the driving method of the self-luminous display device 10 according to the second embodiment, executing the processing (driving) performed during the writing period and the processing (driving) performed during the initialization period at the same timing. Therefore, the driving method of the pixel circuit 181C has the same operational advantages as the driving method of the self-luminous display device 10 according to the second embodiment.

[0426] Pixel circuit 181C is also connected to a second scanning signal line 334, which is a common, integrated combination of the second scanning signal line SC2(n) supplied to pixel circuit 181A and the scanning voltage supply line SVIR. Consequently, pixel circuit 181C has a structure that reduces the number of signal lines, allowing a self-luminous display device including pixel circuit 181C to reduce pixel size. Consequently, a self-luminous display device including pixel circuit 181C can achieve an increased number of pixels and higher resolution.

[0427] <4-2-2. Second Example of the Driving Method of the Pixel Circuit 181C>

[0428] Reference Figure 34 as well as Figure 35 , a second example of the driving method of the pixel circuit 181C is described. The driving method shown in the second example of the pixel circuit 181C includes displaying images of the same color (white) in consecutive frames, similar to "2-2-2. Second example of the driving method of the pixel circuit 181B". Figures 1 to 31 The same or similar structures will be explained as needed.

[0429] The configuration of the image data signal SL(m), scanning voltage source SIR2(n), and scanning signal SC(n) during the light-emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the conductive and non-conductive states of each transistor within the light-emission period PEM are the same as those described in "4-2-1." Furthermore, the voltages (potentials) of the first node N1, second node N2, and third node N3 within the light-emission period PEM of the K-1st FRAME, as well as the operation of each transistor, are the same as those described in "4-2-1. First Example of Driving Method for Pixel Circuit 181C." Configurations similar to those described in "4-2-1. First Example of Driving Method for Pixel Circuit 181C" will be described as needed. Configurations similar to those described in "2-2-2. Second Example of Driving Method for Pixel Circuit 181A" will be described as needed.

[0430] At the beginning of a horizontal period HRP of KthFRAME, pixel 180C (pixel circuit 181C) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGH corresponding to white. The voltage supplied to first node N1 gradually decreases from voltage Vna to voltage VSIGH (voltage Vnf, 3.5V). The voltages supplied to second node N2 and third node N3 are the same as those described in "4-2-1" and are therefore omitted here.

[0431] During period PIW, the voltage supplied to the first node N1 gradually decreases from voltage Vna to voltage Vnf, reaching voltage Vnf (3.5 V). The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "4-2-1" and are therefore omitted here.

[0432] As described above, during period PIW, the data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1, the second node N2 is initialized by the initialization voltage VINI1 (-3.5V), and the third node N3 is initialized by the initialization voltage VINI1 (voltage Vnh, -3.5V) and the voltage Vng (-2.5V).

[0433] During the period PVH following the period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGH. The first node N1 maintains the state of being supplied with the voltage Vnf. The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "4-2-1. First Example of Driving Method of Pixel Circuit 181C" and are therefore omitted here.

[0434] As described above, similar to the description in "4-2-1. First Example of Driving Method of Pixel Circuit 181C," during period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. Furthermore, a charge corresponding to the threshold voltage VTH is retained at the second node N2 (gate electrode 622 of the second transistor T2).

[0435] In the light emitting period PEM of KthFRAME following the horizontal period HRP of KthFRAME, similarly to the driving method of the self-luminous display device 10 according to the second embodiment, for example, Figure 35 As shown, the first node N1 and the second node N2 are turned on, and the voltage of the first node N1 and the voltage of the second node N2 gradually increase, the second transistor T2 becomes turned on, the drain current Ion flows from the driving power line PVDD to the reference voltage line PVSS, and the voltage of the third node N3 increases in a manner following the increase of the voltage of the first node N1 and the voltage of the second node N2.

[0436] As a result, similar to the driving method of the self-luminous display device 10 according to the first embodiment, the potential difference Vgs reaches 4.5V, exceeding the threshold voltage VTH. Consequently, the second transistor T2 is turned on, and the drain current Ion flows from the drive power line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, pixel 180C (pixel circuit 181C) turns red, while the three pixels—pixel 180C emitting blue and pixel 180C emitting green—emit white light.

[0437] <4-2-3. Third Example of the Driving Method of the Pixel Circuit 181C>

[0438] Reference Figure 36 , a third example of the driving method of the pixel circuit 181C is described. The driving method shown in the third example of the driving method of the pixel circuit 181C is similar to the third example of the driving method of the self-luminous display device 10 according to the second embodiment, and includes displaying images of the same color (black) in consecutive frames. Figures 1 to 35 The same or similar structures will be explained as needed.

[0439] The light-emission period PEM of K-1stFRAME, one horizontal period HRP of KthFRAME, the image data signal SL(m), the scanning voltage supply SIR2(n), the scanning signal SC(n), and the conductive and non-conductive states of each transistor within the light-emission period PEM are the same as those described in "4-2-1." As needed, structures similar to those described in "4-2-1. First Example of Driving Method for Pixel Circuit 181C" will be described. Furthermore, structures similar to those in "2-2-3. Third Example of Driving Method for Pixel Circuit 181A" will be described as needed.

[0440] During the K-1st FRAME light emission period PEM, for example, the potential difference Vgs reaches 0.5V, which is lower than the threshold voltage VTH (1V, see Table 8) of the second transistor T2. Since the second transistor T2 is in the off state, no current flows from the drive power line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to not emit light. As a result, for example, pixel 180C (pixel circuit 181C) appears black.

[0441] At the start of a horizontal period HRP of the KthFRAME following the K-1stFRAME light-emission period PEM, the scan voltage source SIR2(n) switches from being supplied with the HI state to being supplied with the initialization voltage VINI1 (voltage Vnh, -3.5V). When the scan voltage source SIR2(n) switches to being supplied with the initialization voltage VINI1, the scan signal SC(n) switches from being supplied with the LO state to being supplied with the HI state. Pixel 180C (pixel circuit 181C) receives the image data signal SL(m) including the data signal VDATA, which includes the voltage VSIGL (-0.5V) corresponding to black, which indicates no light emission. The voltage supplied to the first node N1 remains at voltage Vnd (-0.5V), maintaining the -0.5V state. The voltage supplied to the third node N3 gradually decreases from voltage Vnd (-0.5V) to voltage Vng (-2.5V). The voltage supplied to the second node N2 gradually decreases from the voltage Vnd (−0.5 V) to the voltage Vnh (−3.5 V).

[0442] During period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL. The voltage supplied to the first node N1 remains at -0.5V, and the voltage supplied to the first node N1 remains at -0.5V. The voltage supplied to the second node N2 gradually decreases from the voltage Vnd to the voltage Vnh, reaching the voltage Vnh (-3.5V). Furthermore, the voltage supplied to the third node N3 gradually decreases from the voltage Vne (-1V) to the voltage Vng (-2.5V), reaching the voltage Vng (-2.5V).

[0443] As described above, during period PIW, the data signal VDATA including the voltage VSIGL (-0.5V) is supplied to (written into) the first node N1, the second node N2 is initialized by the initialization voltage VINI1 (-3.5V), and the third node N3 is initialized to the voltage Vng (-2.5V) by the initialization voltage VINI1 (voltage Vnh, -3.5V).

[0444] During the period PVH following the period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL. The voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "4-2-1. First Example of Driving Method of Pixel Circuit 181C."

[0445] As described above, similar to the description in "4-2-1. First Example of Driving Method of Pixel Circuit 181C," during period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby obtaining the threshold voltage VTH of the second transistor T2. Furthermore, a charge corresponding to the threshold voltage VTH is retained at the second node N2 (gate electrode 622 of the second transistor T2).

[0446] During the light emission period PEM of KthFRAME following the one horizontal period HRP of KthFRAME, the voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "4-2-1. First Example of the Driving Method of the Pixel Circuit 181C." Furthermore, similarly to the description in "4-2-1. First Example of the Driving Method of the Pixel Circuit 181C," during the light emission period PEM of KthFRAME following the one horizontal period HRP of KthFRAME, the red-emitting pixel 180C does not emit light, so that the three pixels—the red-emitting pixel 180C, the blue-emitting pixel 180C, and the green-emitting pixel 180C—are black.

[0447] As described above, the third example of the driving method for the self-luminous display device 10 according to the fourth embodiment (the method for driving the pixel circuit 181C) is similar to the third example of the driving method for the self-luminous display device 10 according to the first embodiment. When displaying images of the same color (black) in consecutive frames, the voltage fluctuations at each node are minimal. This reduces power consumption caused by the voltage fluctuations at each node. Consequently, the self-luminous display device 10 is a display device capable of achieving low power consumption.

[0448] <4-2-4. Fourth Example of the Driving Method of the Pixel Circuit 181C>

[0449] Reference Figure 37 , a fourth example of a driving method for the pixel circuit 181C will be described. The driving method shown in the fourth example of the driving method for the pixel circuit 181C is similar to the fourth example of the driving method for the self-luminous display device 10 according to the second embodiment, and includes displaying images of different colors in consecutive frames. Figures 1 to 36 The same or similar structures will be explained as needed.

[0450] The configuration of the image data signal SL(m), scanning voltage supply SIR2(n), and scanning signal SC(n) during the light-emission period PEM of the K-1st FRAME, the horizontal period HRP of the Kth FRAME, and the conductive and non-conductive states of each transistor are the same as those described in "4-2-1." Furthermore, the voltages (potentials) of the first node N1, second node N2, and third node N3 during the light-emission period PEM of the K-1st FRAME, as well as the operation of each transistor, are the same as those described in "4-2-3. Third Example of the Driving Method for Pixel Circuit 181C." Configurations similar to those described in "4-2-1. First Example of the Driving Method for Pixel Circuit 181C" through "4-2-3. Third Example of the Driving Method for Pixel Circuit 181C" will be described as needed. Configurations similar to those in "3-2-3. Fourth Example of the Driving Method for Pixel Circuit 181C" will be described as needed.

[0451] At the beginning of a horizontal period HRP of KthFRAME, pixel 180C (pixel circuit 181C) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGH corresponding to white. Furthermore, as described in "4-2-3," scan voltage supply SIR2(n) transitions from being supplied with the HI state to being supplied with the initialization voltage VINI1 (voltage Vnh, -3.5V). When scan voltage supply SIR2(n) transitions to being supplied with the initialization voltage VINI1, scan signal SC(n) transitions from being supplied with the LO state to being supplied with the HI state. The voltage supplied to the first node N1 gradually increases from the voltage Vnd (-0.5 V) to the voltage VSIGH (voltage Vnf, 3.5 V), the voltage supplied to the second node N2 gradually decreases from the voltage Vnd (-0.5 V) to the voltage Vng (-3.5 V), and the voltage supplied to the third node N3 gradually decreases from the voltage Vne (-1 V) to the voltage Vnh (-2.5 V).

[0452] During period PIW, the voltage supplied to the first node N1 gradually increases from voltage Vnd (-0.5V) to voltage VSIGH (voltage Vnf, 3.5V), and the first node N1 is supplied with voltage Vnf (3.5V). The voltage supplied to the second node N2 gradually decreases from voltage Vne (-1V) to voltage Vng (-3.5V), and the second node N2 is supplied with voltage Vnd (-3.5V). Furthermore, the voltage supplied to the third node N3 gradually decreases from voltage Vne (-1V) to voltage Vnh (-2.5V), and the third node N3 is supplied with voltage Vnh (-2.5V). At this time, the potential difference Vgs is -1V (-3.5V - (-3.5V)), and the potential difference Vds is 10.5V (8V - (-2.5V)).

[0453] As described above, during period PIW, the data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1, the second node N2 is initialized by the initialization voltage VINI1 (-3.5V), and the third node N3 is initialized to the voltage Vng (-2.5V) by the initialization voltage VINI1 (voltage Vnh, -3.5V).

[0454] During the period PVH following the period PIW, similarly to the contents described in “4-2-2. Second Example of the Driving Method of the Pixel Circuit 181C”, the first node N1 maintains the state of being supplied with the voltage Vnf, the second node N2 rises to the initialization voltage VINI2 (0 V), the voltage supplied to the third node N3 rises from the voltage Vnc to the voltage Vne, and the third node N3 becomes the state of being supplied with the voltage Vne (-1 V).

[0455] As described above, during the period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby obtaining the threshold voltage VTH of the second transistor T2. In addition, charge corresponding to the threshold voltage VTH is retained at the second node N2 (gate electrode 622 of the second transistor T2).

[0456] During the KthFRAME light emission period PEM following the KthFRAME horizontal period HRP, the potential difference Vgs reaches 4.5V, similar to the description in "4-2-2. Second Example of Driving Method for Pixel Circuit 181C." The potential difference Vgs is greater than the threshold voltage VTH, turning on the second transistor T2 and causing the drain current Ion to flow from the drive power line PVDD to the reference voltage line PVSS. As a result, the light-emitting element OLED emits light. For example, pixel 180C emits red light, while three pixels—pixel 180C emitting blue and pixel 180C emitting green—emit white light.

[0457] <5. Fifth embodiment>

[0458] Reference Figure 1 、 Figure 4 、 Figures 38 to 46 , an overview of a self-luminous display device 10 according to a fifth embodiment will be described. Figure 38 This is a schematic diagram showing input signals to the pixel 180D (pixel circuit 181D) according to the fifth embodiment of the present invention. Figure 39 is a circuit diagram showing the structure of the pixel circuit 181D. Figure 40 、 Figure 43 、 45 、 Figure 46 This is a timing chart of the self-luminous display device 10 according to the fifth embodiment of the present invention. Figure 41 as well as Figure 42 It is shown in Figure 40 Schematic diagram of the operating state of the pixel circuit 181D at the timing shown. Figure 44 It is shown in Figure 43 Schematic diagram of the operating state of the pixel circuit 181D at the timing shown.

[0459] The self-luminous display device 10 according to the fifth embodiment has a structure and functions obtained by replacing the pixel 180B and pixel circuit 181B of the self-luminous display device 10 according to the third embodiment with a pixel 180D and pixel circuit 181D. The structure and functions otherwise are the same as those of the self-luminous display device 10 according to the third embodiment. Therefore, when describing the structure and functions of the fifth embodiment, the structure and functions that are the same as those of the self-luminous display device 10 according to the third embodiment will be described as needed.

[0460] 5-1. Structure of the Pixel 180D

[0461] Reference Figure 38 as well as Figure 39 , an overview of the pixel 180D and the pixel circuit 181D is described.

[0462] like Figure 38 as well as Figure 39 As shown, the pixel circuit 181D includes a structure and function obtained by replacing the second scanning signal SC2(n) and the scanning voltage power supply SIRB(n) supplied to the pixel circuit 181B with a scanning voltage power supply SIR3(n) that is a common second scanning signal SC2(n) and the scanning voltage power supply SIRB(n). Figure 39 As shown, the structures of the second transistor T2 and the light-emitting element OLED of the pixel circuit 181D are different from those of the pixel circuit 181B.

[0463] Specifically, if Figure 38 As shown, pixel circuit 181D is connected to a second scanning signal line 334 supplied with a scanning voltage supply SIR3(n). The second scanning signal line 334 according to the fifth embodiment serves as both the second scanning signal line 334 supplied to pixel circuit 181B and the scanning voltage supply line SVIRB. In other words, the second scanning signal line 334 according to the fifth embodiment is a signal line obtained by integrating and sharing the second scanning signal line 334 supplied to pixel circuit 181B and the scanning voltage supply line SVIRB. Furthermore, scanning voltage supply SIR3(n) is a signal obtained by inverting the polarity of scanning voltage supply SIR2(n) supplied to pixel circuit 181C. Similarly to scanning voltage supply SIR3(n), the polarity of signals supplied to pixel circuit 181D other than scanning voltage supply SIR3(n) is also an inverted polarity of signals other than scanning voltage supply SIR2(n) supplied to pixel circuit 181C. The second scanning signal line 334 (a signal line serving both as the second scanning signal line 334 and the scanning voltage supply line SVIRB) according to the fifth embodiment is sometimes referred to as a third control signal line. The scanning voltage supply SIR3(n) is sometimes referred to as a third control signal.

[0464] In addition, specifically, Figure 39 As shown, pixel circuit 181D includes a second transistor T2, which is a p-channel field-effect transistor. Furthermore, in pixel circuit 181D, a second electrode 684 of the light-emitting element OLED is electrically connected to a reference voltage line PVSS, and a first electrode 682 of the light-emitting element OLED is electrically connected to a first electrode 624 of the second transistor T2, a third node N3, a second electrode 656 of the fifth transistor T5, and a first electrode 692 of the capacitor CS. The first electrode 682 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 684 of the light-emitting element OLED is, for example, an anode electrode.

[0465] The fourth transistor T4 has the following functions: conducting the second node N2 with the second scan signal line 334 , supplying the scan voltage SIR3 (n) (initialization voltage VINI1 or VINI2 ) to the second node N2 , and initializing the second node N2 .

[0466] The fifth transistor T5 has the function of conducting the third node N3 and the second scanning signal line 334 , supplying the scanning voltage SIR3 (n) (initialization voltage VINI2 ) to the third node N3 , and initializing the third node N3 .

[0467] The configuration and function of the pixel circuit 181D other than the configuration and function described in “5-1. Configuration of Pixel 180D” are the same as those of the pixel circuit 181B.

[0468] <5-2. Driving Method of Pixel Circuit 181D>

[0469] Reference Figures 40 to 46 , a driving method of the self-luminous display device 10 according to the fifth embodiment will be described. Figures 1 to 39 The same or similar structures will be described as needed. It should be noted that, similar to the first and second embodiments, the horizontal axis of the timing chart represents time (TIME).

[0470] For example, the driving method of the self-luminous display device 10 according to the fifth embodiment has a structure and function obtained by replacing the operations associated with the second scanning signal SC2(n) and the scanning voltage supply SIRB(n) in the driving method of the self-luminous display device 10 according to the third embodiment with operations associated with the scanning voltage supply SIR3(n) obtained by commonizing the second scanning signal SC2(n) and the scanning voltage supply SIRB(n). The description of the structure and functions that are the same as those of the driving method of the self-luminous display device 10 according to the third embodiment is omitted here.

[0471] For example, the driving method of the self-luminous display device 10 according to the fifth embodiment is a driving method that inverts the polarity of each signal in the driving method of the self-luminous display device 10 (pixel circuit 181C) according to the fourth embodiment. This method inverts the polarity of the voltage (potential) supplied to each node in the driving method of the self-luminous display device 10 according to the fourth embodiment. Note that the scan voltage supply SIR3(n) is a signal obtained by inverting the polarity of the scan voltage supply SIR2(n) according to the fourth embodiment. The description of the same structures and functions as those in the driving method of the self-luminous display device 10 according to the fourth embodiment is omitted here.

[0472] The driving method of the self-luminous display device 10 according to the fifth embodiment includes the following steps: Figure 4 The driving method of the self-luminous display device 10 shown is the same as that of the embodiment.

[0473] Figure 40 、 Figure 43 、 Figure 45 、 Figure 46 These are diagrams of the period PIW and the period PVH for explaining a method of driving the pixel 180D (pixel circuit 181D). Figure 40 、 Figure 43 、 Figure 45、 Figure 46 The light emitting period PEM of the frame before this frame (K-1stFRAME), the period PIW and the period PVH of this frame (KthFRAME) are shown. Figure 40 、 Figure 43 、 Figure 45 、 Figure 46 One horizontal period (horizontal period HRP) for one pixel 180D (pixel circuit 181D) is shown.

[0474] In the driving method of the self-luminous display device 10 according to the fifth embodiment, during one horizontal period, a scanning signal SC(n) and a scanning voltage supply SIR3(n) are input to each pixel 180D (pixel circuit 181D). For example, the scanning signal SC(n) and the scanning voltage supply SIR3(n) are shifted, and a pixel 180D (pixel circuit 181D) corresponding to the shifted signal is selected. An image data signal SL(m), an initialization voltage VINI, and a reference voltage VREF are input to the selected pixel 180D (pixel circuit 181D). The same operation is performed for all pixels 180D (pixel circuit 181D). Based on the image data signal SL(m) input to all pixels 180D (pixel circuit 181D), an image corresponding to one frame is displayed in the display area 22 of the self-luminous display device 10.

[0475] For example, Figure 40 、 Figure 43 、 Figure 45 、 Figure 46 Tables 9 and 10 show the signals in each frame in the timing chart and the voltage (potential) supplied to each node.

[0476]

[0477]

[0478] As described above, the polarity of the signal supplied to the pixel circuit 181D is a signal obtained by inverting the polarity of the signal supplied to the pixel circuit 181C. For example, as shown in Table 9, Table 10, Figure 40 、 Figure 43 、 Figure 45 、 Figure 46As shown, the voltage VSIGL included in the data signal VDATA is -3.5V, and the pixel 180D supplied with the voltage VSIGL emits light. For example, one pixel emits red, one pixel emits green, and one pixel emits blue, for a total of three pixels emitting white. Alternatively, for example, the voltage VSIGH included in the data signal VDATA is 0.5V, and the pixel 180 supplied with the voltage VSIGH does not emit light, appearing black. Alternatively, for example, the voltage VL(LO) is -10V, the voltage VNN is 5V, and the voltage VMN is -5V, the initialization voltage VINI1 is 3.5V, and the initialization voltage VINI2 is 0V. For example, the voltage VH (HI), the voltage VL (LO), the voltage VNN, the voltage VMN, the initialization voltage VINI1, and the initialization voltage VINI2 supplied to the pixel circuit 181D correspond to voltages (potentials) obtained by inverting the polarity of the voltage VL (LO), the voltage VH (HI), the voltage VN, the voltage VM, the initialization voltage VINI2, and the initialization voltage VINI1 supplied to the pixel circuit 181C.

[0479] <5-2-1. First Example of the Driving Method of the Pixel Circuit 181D>

[0480] Reference Figures 40 to 42 A first example of a method for driving pixel circuit 181D will be described. This first example of the method for driving pixel circuit 181D includes: after pixel 180D displays a white image based on voltage VSIGL (-3.5V) included in data signal VDATA in the frame (KthFRAME) preceding the current frame (KthFRAME), pixel 180D then displays a black image based on voltage VSIGH (0.5V) included in data signal VDATA in the KthFRAME. In other words, the first example of the method for driving the self-luminous display device 10 according to the fifth embodiment includes displaying images of different colors in consecutive frames.

[0481] As described above, the structures and functions of the signals within the K-1st FRAME light-emission period PEM, the Kth FRAME horizontal period HRP, and the light-emission period PEM are similar to those obtained by inverting the polarity of the voltages (potentials) of the signals in the method for driving the self-luminous display device 10 according to the fourth embodiment. For example, the voltages (potentials) at the first node N1, the second node N2, and the third node N3 within the K-1st FRAME light-emission period PEM, the Kth FRAME horizontal period HRP, and the light-emission period PEM are similar to those obtained by inverting the polarity of the voltages (potentials) at the nodes in the method for driving the self-luminous display device 10 according to the fourth embodiment. The conduction and non-conduction states of the transistors within the K-1st FRAME light-emission period PEM, the Kth FRAME horizontal period HRP, and the light-emission period PEM are also similar to those described in "4-2-1. First Example of Driving Method for Pixel Circuit 181C."

[0482] For example, voltages Vnan, Vnbn, Vncn, Vndn, Vnen, and Vnfn are voltages (potentials) obtained by inverting the polarity of voltages Vna, Vnb, Vnc, Vnd, Vne, and Vnf. Referring to the voltages (potentials) in the driving method according to the fourth embodiment, voltage Vnan is -7 V, voltage Vnbn is -2.5 V, voltage Vncn is 1.5 V, voltage Vndn is 0.5 V, voltage Vnen is 1 V, voltage Vnfn is -3.5 V, voltage Vngn is 2.5 V, and voltage Vnhn is 3.5 V.

[0483] Referring to the first example of the driving method according to the fourth embodiment, the conduction state and the non-conduction state of each transistor of the PEM during the light emission period of K-1stFRAME and Figure 40 During the light-emission period PEM of K-1stFRAME, pixel 180D emits light based on the potential difference Vgs (voltage V(N2) - voltage V(N3) = voltage Vnan - voltage Vnbn) of second transistor T2. With a potential difference Vgs of -4.5V, pixel 180B emits red light, and the three pixels (pixel 180 emitting red, pixel 180 emitting blue, and pixel 180 emitting green) emit white light.

[0484] For example, during the start of a horizontal period HRP of KthFRAME following the light-emitting period PEM of K-1stFRAME, the scanning voltage power supply SIR3(n) changes from being supplied with LO to being supplied with the initialization voltage VINI1 (3.5V). When the scanning voltage power supply SIR3(n) changes from being supplied with the initialization voltage VINI1, the scanning signal SC(n) changes from being supplied with LO to being supplied with HI. Referring to the conductive state and the non-conductive state during the start of a horizontal period HRP of KthFRAME in the first example of the driving method according to the fourth embodiment, Figure 40 , the voltage supplied to the first node N1 gradually increases from the voltage Vnan to the voltage VSIGH (voltage Vndn), and the voltage supplied to the second node N2 gradually increases from the voltage Vnan to the initialization voltage VINI1 (voltage Vnhn).

[0485] For example, Figure 40 as well as Figure 41 As shown, during the period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGH, the scanning signal SC(n) maintains the state of being supplied with HI, and the scanning voltage source SIR3(n) maintains the state of being supplied with the initialization voltage VINI1. Referring to the conductive state and the non-conductive state of each transistor during the period PIW of the first example of the driving method according to the fourth embodiment, Figure 40 , the voltage supplied to the third node N3 gradually rises from voltage Vnbn. When the potential difference between the initialization voltage VINI1 (3.5V) supplied to the gate electrode 652 and the voltage supplied to the second electrode 656 (the voltage supplied to the third node N3) becomes equal to the threshold voltage VTHT5 (1V) of the fifth transistor T5, the fifth transistor T5 switches from the on state to the off state. Specifically, when the voltage supplied to the second electrode 656 (the voltage supplied to the third node N3) reaches voltage Vngn (2.5V), the fifth transistor T5 switches from the on state to the off state. Furthermore, the voltage supplied to the first node N1 gradually rises from voltage Vnan to voltage VSIGH (voltage Vndn, 0.5V), reaching voltage Vndn (0.5V). The voltage supplied to the second node N2 gradually rises from voltage Vnan to initialization voltage VINI1 (voltage Vnhn, 3.5V), reaching initialization voltage VINI1 (3.5V). When the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3 becomes equal to the threshold voltage VTHT5 (1V), the fifth transistor T5 switches from the on state to the off state. The potential difference Vds when the fifth transistor T5 is in the off state is -10.5V (-8V - (2.5V)).

[0486] As described above, during period PIW, the data signal VDATA including the voltage VSIGH is supplied (written) to the first node N1, the second node N2 is initialized by the initialization voltage VINI1 (3.5V), and the third node N3 is initialized to the voltage Vngn (2.5V) by the initialization voltage VINI1 (voltage Vnhn, 3.5V).

[0487] During period PVH, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGH. Furthermore, the scanning signal SC(n) maintains the state of being supplied with HI, and the scanning voltage source SIR3(n) changes from being supplied with the initialization voltage VINI1 to being supplied with the initialization voltage VINI2.

[0488] Immediately after the start of period PVH, the potential difference Vgs is 1V, and the potential difference Vds is -10.5V. This potential difference Vgs is higher than the threshold voltage VTHP (-1V, see Table 10) of the second transistor T2, so the second transistor T2 is in the off state. Consequently, the drain current Ion does not flow from the first electrode 624 to the second electrode 626 of the second transistor T2.

[0489] In the period PVH, referring to the first example of the driving method according to the fourth embodiment, the conduction state and the non-conduction state of each transistor in the period PVH and Figure 40 , the fourth transistor T4 is kept on, so when the voltage supplied to the scanning voltage power supply SIR3(n) changes from the initialization voltage VINI1 to the initialization voltage VINI2, the voltage supplied to the second node N2 gradually decreases from the voltage Vnhn (3.5V) to the initialization voltage VINI2 (0V), and becomes the initialization voltage VINI2 (0V) (for example, Figure 40 as well as Figure 42 ). In this case, for example, Figure 40 as well as Figure 42As shown, although the fifth transistor T5 is in the off state, the Vgs of the second transistor T2 reaches -2.5V (0V (node ​​N2) - (2.5V) (node ​​N3)), which is lower than the threshold voltage VTHP (-1V). This causes the drain current Ion of the second transistor T2 to flow, and the voltage supplied to the third node N3 gradually decreases from the voltage Vngn (2.5V) to the voltage Vnen (1V). As a result, the voltage supplied to the third node N3 reaches the voltage Vnen (1V), and the voltage supplied to the second node N2 reaches the initialization voltage VINI2 (0V), causing the potential difference Vgs to reach -1V (0V - (1V)). Since the potential difference Vgs is equal to the threshold voltage VTHP (-1V), the second transistor T2 is in the off state. Consequently, the drain current Ion does not flow from the second electrode 626 of the second transistor T2 to the first electrode 624.

[0490] As described above, during the period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTHP, thereby obtaining the threshold voltage VTHP of the second transistor T2. In addition, a charge corresponding to the threshold voltage VTHP is retained at the second node N2 (the gate electrode 622 of the second transistor T2).

[0491] During the KthFRAME light-emission period PEM following the KthFRAME horizontal period HRP, no select signal is used to select data, and the data signal VDATA is maintained at a voltage above the voltage VSIGL and below the voltage VSIGH. Furthermore, the scan signal SC(n) transitions from being HI to being LO. When the scan signal SC(n) transitions to being LO, the scan voltage supply SIR3(n) transitions from being supplied with the initialization voltage VINI2 (0V) to being supplied with LO (-10V).

[0492] Therefore, referring to the first example of the driving method according to the fourth embodiment, the conduction state and the non-conduction state of each transistor of PVH during KthFRAME and Figure 40 , the first node N1 and the second node N2 are conductive, and the potential difference Vgs reaches -0.5V. This potential difference Vgs is greater than the threshold voltage VTHP. Consequently, the second transistor T2 is turned off, and no current flows from the drive power line PVDD to the reference voltage line PVSS. Therefore, the light-emitting element OLED does not emit light. As a result, for example, pixel 180D (pixel circuit 181D) that emits red, pixel 180D that emits blue, and pixel 180D that emits green do not emit light. Therefore, the three pixels (pixel 180D, blue, and green) that emit red, blue, and green appear black.

[0493] As described above, the driving method of the self-luminous display device 10 according to the fifth embodiment (the driving method of the pixel circuit 181D) includes, similar to the driving method of the self-luminous display device 10 according to the fourth embodiment, executing the processing (driving) performed during the writing period and the processing (driving) performed during the initialization period at the same timing. Furthermore, like the pixel circuit 181B, the pixel circuit 181D has a structure that can reduce the number of signal lines. Therefore, the self-luminous display device including the pixel circuit 181D can reduce the pixel size. Therefore, the self-luminous display device 10 and the driving method of the self-luminous display device 10 according to the fifth embodiment have the same operational advantages as the self-luminous display device 10 and the driving method of the self-luminous display device 10 according to the third embodiment.

[0494] <5-2-2. Second Example of the Driving Method of the Pixel Circuit 181D>

[0495] Reference Figure 43 as well as Figure 44 , a second example of the driving method of the pixel circuit 181D is described. The driving method shown in the second example of the pixel circuit 181D includes: after the pixel 180D displays a white image based on the voltage VSIGL (-3.5V) included in the data signal VDATA in the previous frame (KthFRAME) (K-1stFRAME) of the current frame (KthFRAME), the pixel 180D also displays a white image based on the voltage VSIGL (-3.5V) included in the data signal VDATA in KthFRAME. In other words, the second example of the driving method of the self-luminous display device 10 involved in the fifth embodiment includes displaying images of the same color (white) in consecutive frames. For Figures 1 to 40 The same or similar structures will be explained as needed.

[0496] The structure of the K-1st FRAME light-emission period PEM, one horizontal period HRP of the Kth FRAME, the image data signal SL(m), the scanning voltage supply SIR(n), and the scanning signal SC(n) within the light-emission period PEM, as well as the conductive and non-conductive states of each transistor, are the same as those described in "5-2-1." Furthermore, the voltages (potentials) of the first node N1, second node N2, and third node N3 within the K-1st FRAME light-emission period PEM, as well as the operation of each transistor, are the same as those described in "5-2-1." Details similar to those described in "5-2-1" will be described as needed.

[0497] During the start of a horizontal period HRP of KthFRAME, pixel 180D (pixel circuit 181D) receives an input image data signal SL(m) including a data signal VDATA including a voltage VSIGL corresponding to white. The voltage supplied to first node N1 gradually increases from voltage Vnan to voltage VSIGL (voltage Vnfn, -3.5V). The voltage supplied to second node N2 and third node N3 is the same as that described in "5-2-1. First Example of Driving Method of Pixel Circuit 181D," and therefore, their description is omitted here.

[0498] During period PIW, the voltage supplied to the first node N1 gradually increases from voltage Vnan to voltage Vnfn, reaching voltage Vnfn (-3.5 V). The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "5-2-1. First Example of Driving Method of Pixel Circuit 181D."

[0499] As described above, during period PIW, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1, the second node N2 is initialized by the initialization voltage VINI1 (voltage Vnhn, -3.5V), and the third node N3 is initialized to the voltage Vngn (-2.5V) by the initialization voltage VINI1 (voltage Vnhn, -3.5V).

[0500] During the period PVH following the period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL. The first node N1 maintains the state of being supplied with the voltage Vnfn. The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "5-2-1. First Example of Driving Method of Pixel Circuit 181D."

[0501] As described above, similar to the description in "5-2-1. First Example of Driving Method of Pixel Circuit 181D," during period PVH, the threshold voltage VTHP of the second transistor T2 is corrected so that the potential difference Vgs of the second transistor T2 becomes equal to the threshold voltage VTHP. Furthermore, a charge corresponding to the threshold voltage VTHP is retained at the second node N2 (gate electrode 622 of the second transistor T2).

[0502] In the light emitting period PEM of KthFRAME after one horizontal period HRP of KthFRAME, similarly to the contents described in "4-2-1", for example, Figure 44As shown, the first node N1 and the second node N2 are turned on, and the voltage of the first node N1 and the voltage of the second node N2 gradually decrease, the second transistor T2 becomes turned on, the drain current Ion flows from the reference voltage line PVSS to the drive power line PVDD, and the voltage of the third node N3 decreases in a manner following the decrease in the voltage of the first node N1 and the voltage of the second node N2.

[0503] As a result, the potential difference Vgs (voltage Vnan (-7V) - voltage Vnbn (-2.5V)) becomes -4.5V, which is lower than the threshold voltage VTHP (-1V). Consequently, the second transistor T2 is turned on, and the drain current Ion flows from the reference voltage line PVSS to the drive power line PVDD, causing the light-emitting element OLED to emit light. For example, pixel 180D (pixel circuit 181D) turns red, while the three pixels—pixel 180D emitting blue and pixel 180D emitting green—emit white light.

[0504] <5-2-3. Third Example of the Driving Method of the Pixel Circuit 181D>

[0505] Reference Figure 45 , a third example of the driving method of the pixel circuit 181D is described. The driving method shown in the third example of the driving method of the pixel circuit 181D includes: after the pixel 180D displays a black image based on the voltage VSIGL included in the data signal VDATA in the previous frame (KthFRAME) of the current frame (KthFRAME), the pixel 180D also displays a black image based on the voltage VSIGH included in the data signal VDATA in KthFRAME. In other words, it includes displaying images of the same color (black) in consecutive frames. Figures 1 to 44 The same or similar structures will be explained as needed.

[0506] The structure of the light-emitting period PEM of K-1stFRAME, the horizontal period HRP of KthFRAME, the image data signal SL(m), the scanning voltage power supply SIR3(n) and the scanning signal SC(n) within the light-emitting period PEM, and the conduction state and non-conduction state of each transistor are the same as the structure described in "5-2-1. First example of the driving method of the pixel circuit 181D".

[0507] Referring to the first example of the driving method of the pixel circuit 181D in the structure described in "5-2-1. The first example of the driving method of the pixel circuit 181D", the conductive state and the non-conductive state of each transistor of the PEM during the light emission period of K-1stFRAME are Figure 45During the K-1stFRAME light-emission period PEM, pixel 180D emits light based on the potential difference Vgs (voltage V(N2) - voltage V(N3) = voltage VINI2 - voltage Vnen) across second transistor T2. This potential difference Vgs is -0.5V, which is greater than the threshold voltage VTHP (-1V) of second transistor T2. Consequently, second transistor T2 is turned off, preventing current from flowing from reference voltage line PVSS to drive power line PVDD. Consequently, the light-emitting element OLED does not emit light. As a result, for example, pixel 180D (pixel circuit 181D) appears black.

[0508] During the start of the horizontal period HRP of KthFRAME following the light-emission period PEM of K-1stFRAME, the pixel 180D (pixel circuit 181D) receives the image data signal SL(m) including the data signal VDATA including the voltage VSIGH (0.5V) corresponding to black, which indicates no light emission. Referring to the conduction state and the non-conduction state of each transistor during the start of the horizontal period HRP of KthFRAME in the configuration described in "5-2-1. First Example of the Driving Method of the Pixel Circuit 181D," Figure 45 , the voltage supplied to the first node N1 remains at the voltage Vndn (0.5 V), and the first node N1 maintains the state of being supplied with 0.5 V. The voltage supplied to the second node N2 gradually increases from the voltage Vndn (0.5 V) to the initialization voltage VINI1 (voltage Vnhn, 3.5 V).

[0509] In the period PIW, referring to the conduction state and non-conduction state of each transistor during the start of one horizontal period HRP of KthFRAME in the structure described in "5-2-1. First example of the driving method of the pixel circuit 181D", Figure 45 , the image data signal SL(m) continues to be supplied with the data signal VDATA including the voltage VSIGH, the first node N1 continues to be supplied with 0.5V, and the voltage supplied to the second node N2 gradually rises to the voltage Vnhn (3.5V). Furthermore, the voltage supplied to the third node N3 reaches the voltage Vngn (2.5V).

[0510] As described above, in the period PIW, the data signal VDATA including the voltage VSIGH (0.5V) is supplied to (written into) the first node N1 , and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (3.5V).

[0511] During the period PVH following the period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGH. The voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "5-2-1. First Example of Driving Method of Pixel Circuit 181D," and therefore their description is omitted here.

[0512] As described above, similar to the description in "5-2-1. First Example of Driving Method of Pixel Circuit 181D," during period PVH, the threshold voltage VTHP of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTHP. Furthermore, a charge corresponding to the threshold voltage VTHP is retained at the second node N2 (gate electrode 622 of the second transistor T2).

[0513] During the light-emission period PEM of KthFRAME following the one horizontal period HRP of KthFRAME, the voltage supplied to the first node N1, the voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "3-2-3. Third Example of the Driving Method of Pixel Circuit 181B," and thus their description is omitted here. Similarly to the description in "3-2-3. Third Example of the Driving Method of Pixel Circuit 181B," during the light-emission period PEM of KthFRAME following the one horizontal period HRP of KthFRAME, the red-emitting pixel 180D, the blue-emitting pixel 180D, and the green-emitting pixel 180D do not emit light, so the three pixels (the red-emitting pixel 180D, the blue-emitting pixel 180D, and the green-emitting pixel 180D) are black.

[0514] As described above, the third example of the driving method for the self-luminous display device 10 according to the fifth embodiment (the method for driving the pixel circuit 181D) is similar to the third example of the driving method for the self-luminous display device 10 according to the second embodiment. When displaying images of the same color (black) in consecutive frames, the voltage fluctuations at each node are minimal. This reduces power consumption caused by the voltage fluctuations at each node. Consequently, the self-luminous display device 10 is a display device capable of achieving low power consumption.

[0515] <5-2-4. Fourth Example of the Driving Method of the Pixel Circuit 181D>

[0516] Reference Figure 46, a fourth example of the driving method of the pixel circuit 181D is described. The driving method shown in the fourth example of the driving method of the pixel circuit 181D includes: after the pixel 180D (pixel circuit 181D) displays a black image based on the voltage VSIGH included in the data signal VDATA in the previous frame (K-1stFRAME) of the current frame (KthFRAME), the pixel 180 (pixel circuit 181) displays a white image based on the voltage VSIGL included in the data signal VDATA in KthFRAME. In other words, it includes displaying images of different colors in consecutive frames. Figures 1 to 45 The same or similar structures will be explained as needed.

[0517] The structure of the light-emitting period PEM of K-1stFRAME, the horizontal period HRP of KthFRAME, the image data signal SL(m), the scanning voltage power supply SIR3(n) and the scanning signal SC(n) within the light-emitting period PEM, and the conduction state and non-conduction state of each transistor are the same as the structure described in "5-2-1. First example of the driving method of the pixel circuit 181D".

[0518] During the K-1st FRAME light-emission period, the voltages (potentials) at the first, second, and third nodes N1, N2, and N3 within the PEM, as well as the operation of each transistor, are identical to those described in "5-2-3. Third Example of Driving Method for Pixel Circuit 181D." Specifically, pixel 180D (pixel circuit 181D) does not emit light and appears black.

[0519] At the beginning of a horizontal period HRP of KthFRAME, pixel 180D (pixel circuit 181D) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGL corresponding to white. The voltage supplied to first node N1 gradually decreases from voltage Vndn (0.5V) to voltage VSIGL (voltage Vnfn, −3.5V), while the voltage supplied to second node N2 gradually increases from voltage Vnen (1V) to voltage Vngn (2.5V).

[0520] During period PIW, the first node N1 is supplied with voltage Vnfn (-3.5V), and the second node N2 is supplied with voltage Vnhn (3.5V). Furthermore, the third node N3 is supplied with voltage Vngn (2.5V). At this time, the potential difference Vgs is 1V (3.5V - (2.5V)), and the potential difference Vds is -10.5V (-8V - (2.5V)).

[0521] As described above, in the period PIW, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1 , and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 (3.5 V).

[0522] During the period PVH following the period PIW and the luminous period PEM following the period PVH, the conductive state and the non-conductive state of each transistor are the same as those in the structure described in “5-2-2. Second example of the driving method of the pixel circuit 181D”, and the voltage supplied to the first node N1, the voltage supplied to the second node N2, and the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those in the state described in “5-2-2. Second example of the driving method of the pixel circuit 181D”.

[0523] Similar to the state described in "5-2-2. Second Example of the Driving Method for Pixel Circuit 181D," during period PVH in the third example of the driving method for pixel circuit 181D, the threshold voltage VTHP of second transistor T2 is obtained by making the potential difference Vgs of second transistor T2 equal to the threshold voltage VTHP. Furthermore, a charge corresponding to the threshold voltage VTHP is retained at the second node N2 (gate electrode 622 of second transistor T2).

[0524] In addition, similar to the state described in "5-2-2. Second example of the driving method of pixel circuit 181D", during the light emission period PEM of KthFRAME in the third example of the driving method of pixel circuit 181D, similar to the content described in "3-3-2", pixel 180D emits red light, and three pixels of pixel 180D emitting blue light and pixel 180D emitting green light emit white light.

[0525] <6. Sixth embodiment>

[0526] Reference Figure 1 、 Figure 4 、 Figures 47 to 52 , an overview of a self-luminous display device 10 according to a sixth embodiment will be described. Figure 47 This is a schematic diagram illustrating input signals to the pixel 180E (pixel circuit 181E) according to the sixth embodiment of the present invention. Figure 48 181E is a circuit diagram showing the structure of the pixel circuit 181E. Figures 49 to 52 This is a timing chart of the self-luminous display device 10 according to the sixth embodiment of the present invention.

[0527] The self-luminous display device 10 involved in the sixth embodiment includes a pixel 180E and a pixel circuit 181E. The structure of the pixel 180E and the pixel circuit 181E is different from the structure of the pixel 180 and the pixel circuit 181 of the self-luminous display device 10 involved in the first embodiment. Specifically, the circuit structure of the pixel circuit 181E is different from the circuit structure of the pixel circuit 181. In addition, in the pixel circuit 181E, the scanning voltage power supply SIR (n) supplied to the pixel circuit 181 has a structure and function obtained by replacing it with the scanning voltage power supply SIR4 (n). The structure and function other than this are the same as those of the self-luminous display device 10 involved in the first embodiment. When explaining the structure and function of the sixth embodiment, the structure and function that are the same as those of the self-luminous display device 10 involved in the first embodiment will be explained as needed. In addition, for the structure and function that are the same as those of the self-luminous display device 10 involved in the first embodiment, Figures 1 to 46 The same or similar structures will be explained as needed.

[0528] 6-1. Structure of Pixel 180E

[0529] Reference Figure 47 as well as Figure 48 , an overview of the pixel 180E and the pixel circuit 181E is described.

[0530] like Figure 47 As shown, pixel circuit 181E is connected to a scanning voltage supply line SVIR that supplies a scanning voltage supply SIR4(n). For example, scanning voltage supply line SVIR, driving voltage VDDEL, and reference voltage VSSEL are each electrically connected to a separate connection wiring 342. Alternatively, scanning voltage supply line SVIR, driving voltage VDDEL, and reference voltage VSSEL may each be a separate connection wiring 342.

[0531] like Figure 48 As shown, pixel circuit 181E includes a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, a capacitor CS, and a light-emitting element OLED. Each of these transistors includes a gate electrode and a pair of electrodes (source and drain) consisting of a first electrode and a second electrode. The capacitor CS and the light-emitting element OLED each have a pair of electrodes consisting of a first electrode and a second electrode.

[0532] For example, the first transistor T1 is a selection transistor and has a function of supplying an image data signal SL(m) to the first node N1.

[0533] For example, the second transistor T2 is a driving transistor. The threshold voltage VTH of the second transistor T2 is corrected based on the initialization voltages VINI1 and VINI2. Furthermore, the second transistor T2 controls the connection and disconnection between the third node N3 (the first electrode 724, the second electrode 736, the second electrode 746, and the second electrode 784) and the fourth node N4 (the second electrode 726, the second electrode 756, the second electrode 766, and the first electrode 774) based on the corrected threshold voltage VTH and the input image data signal SL(m).

[0534] The third transistor T3 has a function of conducting electricity between the first node N1 and the third node N3 .

[0535] The fourth transistor T4 has the following function: conducts electricity between the third node N3 (the first electrode 724, the second electrode 736, the second electrode 746, and the second electrode 784) and the scan voltage power line SVIR (the first electrode 744 and the first electrode 754), supplies the scan voltage power SIR4(n) to the third node N3, and initializes the third node N3.

[0536] The fifth transistor T5 has the following functions: conducting the fourth node N4 (the second electrode 726, the second electrode 756, the second electrode 766, and the first electrode 774) with the scanning voltage power line SVIR, supplying the scanning voltage power SIR4(n) to the fourth node N4 (the second electrode 726, the second electrode 756, the second electrode 766, and the first electrode 774), and initializing the fourth node N4 (the second electrode 726, the second electrode 756, the second electrode 766, and the first electrode 774).

[0537] The sixth transistor T6 has a function of conducting electricity between the second node N2 (gate electrode 722 , first electrode 792 , first electrode 774 ) and the fourth node N4 (second electrode 726 , second electrode 756 , second electrode 766 , first electrode 774 ).

[0538] The seventh transistor T7 has a function of conducting the driving power line PVDD (the second electrode 776 ) and the fourth node N4 (the second electrode 726 , the second electrode 756 , the second electrode 766 , and the first electrode 774 ).

[0539] For example, the capacitor element CS has the function of holding charges corresponding to the voltage supplied to the second node N2 and the function of holding charges corresponding to the data voltage included in the image data signal SL(m) supplied to the first node N1 .

[0540] The light emitting element OLED has diode characteristics, and has a function of emitting light based on a current flowing into the light emitting element OLED (ie, a drain current Ion of the second transistor T2 ).

[0541] The first transistor T1 includes a gate electrode 712, a first electrode 714, and a second electrode 716. The gate electrode 712 is electrically connected to the first scan signal line 330. The first electrode 714 is electrically connected to the image data signal line 321. The second electrode 716 is electrically connected to the first node N1, the first electrode 734 of the third transistor T3, and the second electrode 794 of the capacitor CS. The first transistor T1 is switched by the first scan signal SC1(n). In other words, the first transistor T1 is controlled to be conductive or non-conductive by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is low, the first transistor T1 is non-conductive. When the signal supplied to the first scan signal SC1(n) is high, the first transistor T1 is conductive.

[0542] The first scan signal line 330 is electrically connected to the gate electrode 712 of the first transistor T1 , the gate electrode 732 of the third transistor T3 , the gate electrode 742 of the fourth transistor T4 , the gate electrode 762 of the sixth transistor T6 , and the gate electrode 772 of the seventh transistor T7 .

[0543] The second transistor T2 includes a gate electrode 722, a first electrode 724, and a second electrode 726. The gate electrode 722 is electrically connected to the second node N2, the first electrode 764 of the sixth transistor T6, and the first electrode 792 of the capacitor CS. The first electrode 724 is electrically connected to the third node N3, the second electrode 736 of the third transistor T3, the second electrode 746 of the fourth transistor T4, and the second electrode 784 of the light-emitting element OLED. The second electrode 726 is electrically connected to the second electrode 756 of the fifth transistor T5, the second electrode 766 of the sixth transistor T6, and the first electrode 774 of the seventh transistor T7. The threshold voltage of the second transistor T2 is the threshold voltage VTH. The second transistor T2 is controlled to be in a conducting state or a non-conducting state based on the potential difference Vgs between the voltage supplied to the second node N2 and the voltage supplied to the third node N3, the potential difference Vds between the second electrode 726 and the first electrode 724, and the threshold voltage VTH.

[0544] The third transistor T3 includes a gate electrode 732, a first electrode 734, and a second electrode 736. The third transistor T3 is switched on and off by the first scan signal SC1(n). In other words, the third transistor T3 is controlled to be conductive or non-conductive by the first scan signal SC1(n). When the signal supplied to the first scan signal SC1(n) is low, the third transistor T3 is conductive. When the signal supplied to the first scan signal SC1(n) is high, the third transistor T3 is non-conductive.

[0545] The fourth transistor T4 includes a gate electrode 742, a first electrode 744, and a second electrode 746. The first electrode 744 is electrically connected to the scan voltage supply line SVIR. The fourth transistor T4 is switched on and off by the first scan signal SC1(n). In other words, the fourth transistor T4 is controlled to switch between a conductive state and a non-conductive state by the first scan signal SC1(n). When the first scan signal SC1(n) is low, the fourth transistor T4 is in a non-conductive state. When the first scan signal SC1(n) is high, the fourth transistor T4 is in a conductive state.

[0546] The fifth transistor T5 includes a gate electrode 752, a first electrode 754, and a second electrode 756. The gate electrode 752 is electrically connected to the second scan signal line 334. The first electrode 754 is electrically connected to the scan voltage supply line SVIR. The fifth transistor T5 is switched on and off by the second scan signal SC2(n). In other words, the fifth transistor T5 is controlled to be conductive or non-conductive by the second scan signal SC2(n). When the signal supplied to the second scan signal SC2(n) is low, the fifth transistor T5 is non-conductive. When the signal supplied to the second scan signal SC2(n) is high, the fifth transistor T5 is conductive.

[0547] The sixth transistor T6 includes a gate electrode 762, a first electrode 764, and a second electrode 766. The gate electrode 762 is electrically connected to the first scan signal line 330. The sixth transistor T6 is switched on and off by the first scan signal SC1(n). In other words, the first scan signal SC1(n) controls the sixth transistor T6 between a conductive state and a non-conductive state. When the signal supplied to the first scan signal SC1(n) is low, the sixth transistor T6 is non-conductive. When the signal supplied to the first scan signal SC1(n) is high, the sixth transistor T6 is conductive.

[0548] The seventh transistor T7 includes a gate electrode 772, a first electrode 774, and a second electrode 776. The gate electrode 772 is electrically connected to the first scan signal line 330. The second electrode 776 is electrically connected to the drive power line PVDD. The seventh transistor T7 is switched on and off by the first scan signal SC1(n). In other words, the first scan signal SC1(n) controls the seventh transistor T7 between a conductive state and a non-conductive state. When the signal supplied to the first scan signal SC1(n) is low, the seventh transistor T7 is conductive. When the signal supplied to the first scan signal SC1(n) is high, the seventh transistor T7 is non-conductive.

[0549] The first electrode 782 of the light-emitting element OLED is electrically connected to the reference voltage line PVSS. As described above, the reference voltage VSSEL is supplied to the reference voltage line PVSS. The first electrode 782 of the light-emitting element OLED is, for example, a cathode electrode, and the second electrode 784 of the light-emitting element OLED is, for example, an anode electrode.

[0550] Each transistor included in the pixel circuit 181E may have the same structure as each transistor included in the pixel circuit 181. For example, the channel region of each transistor may include low-temperature polysilicon (LTPS), and n-channel transistors may be formed using a metal oxide having semiconductor properties.

[0551] In the sixth embodiment, the first transistor T1 , the second transistor T2 , the fourth transistor T4 , the fifth transistor T5 , and the sixth transistor T6 are n-channel field effect transistors, and the third transistor T3 and the seventh transistor T7 are p-channel field effect transistors.

[0552] <6-2. Driving Method of Pixel Circuit 181E>

[0553] Reference Figures 48 to 52 , a driving method of the self-luminous display device 10 according to the sixth embodiment will be described. Figures 1 to 48 The same or similar structures will be described as needed. It should be noted that, similar to the first embodiment, the horizontal axis of the timing chart represents time (TIME).

[0554] The driving method of the self-luminous display device 10 according to the sixth embodiment includes the following steps: Figure 4 The driving method of the self-luminous display device 10 shown is the same as that of the embodiment.

[0555] Figures 49 to 52 These are diagrams of the period PIW and the period PVH for explaining a method of driving the pixel 180E (pixel circuit 181E). Figures 49 to 52The light emitting period PEM of the frame before this frame (K-1stFRAME), the period PIW and the period PVH of this frame (KthFRAME) are shown. Figures 49 to 52 One horizontal period (horizontal period HRP) for one pixel 180E (pixel circuit 181E) is shown.

[0556] In the driving method of the self-luminous display device 10 according to the sixth embodiment, during one horizontal period, a pixel 180E (pixel circuit 181E) receives inputs including a first scanning signal SC1(n), a second scanning signal SC2(n), an image data signal SL(m) including a data signal VDATA, and a scanning voltage supply SIR4(n). For example, the first scanning signal SC1(n), the second scanning signal SC2(n), and the scanning voltage supply SIR4(n) are shifted, and a pixel 180E (pixel circuit 181E) corresponding to the shifted signals is selected. The image data signal SL(m), the driving voltage VDDEL, and the reference voltage VSSEL are then input to the selected pixel 180E (pixel circuit 181E). The same operation is performed for all pixels 180E (pixel circuit 181E), and based on the image data signal SL(m) input to all pixels 180E (pixel circuit 181E), an image corresponding to one frame is displayed in the display area 22 of the self-luminous display device 10.

[0557] For example, supplied to Figures 49 to 52 Tables 11 and 12 show the signals and voltages (potentials) of the nodes in each frame in the timing chart shown.

[0558]

[0559]

[0560] <6-2-1. First Example of a Method for Driving the Pixel Circuit 181E>

[0561] Reference Figure 49 Next, a first example of a method for driving the pixel circuit 181E will be described. The first example of the method for driving the pixel circuit 181E, like the first example of the method for driving the self-luminous display device 10 according to the first embodiment, includes displaying images of different colors in consecutive frames.

[0562] The timing at which the light-emission period PEM of K-1stFRAME, one horizontal period HRP of KthFRAME, and the image data signal SL(m), the first scanning signal SC1(n), and the second scanning signal SC2(n) within the light-emission period PEM are supplied to the pixel circuit 181E is the same as the first example of the driving method of the self-luminous display device 10 according to the first embodiment.

[0563] As shown in Tables 11 and 12, the image data signal SL(m) including the data signal VDATA supplied to the pixel circuit 181E during each horizontal period is between -4.5V and -0.5V. For example, if the voltage VSIGL is -4.5V, the pixel 180E supplied with the voltage VSIGL emits light and displays various colors. Alternatively, if the voltage VSIGH is -0.5V, the pixel 180E supplied with the voltage VSIGH does not emit light and displays black. Alternatively, for example, the initialization voltage VINI2 is -1V, the initialization voltage VINI1 is 0.5V, the voltage VH is 10V, the voltage VL is -6.5V, the voltage VM is 5V, and the voltage VN is -5V.

[0564] Scan voltage power supply SIR4(n) is supplied with initialization voltage VINI1 during the light-emission period PEM of K-1stFRAME, the start of one horizontal period HRP of KFRAME, and period PIW. Initialization voltage VINI2 is supplied during period PVH of KFRAME. Scan voltage power supply SIR4(n) is supplied with initialization voltage VINI1 during the start of the light-emission period PEM. When the first scan signal SC1(n) changes from being HI to being LO, scan voltage power supply SIR4(n) changes from being supplied with initialization voltage VINI1 to being supplied with initialization voltage VINI2.

[0565] During the light-emission period PEM of the K-1st FRAME, the first scan signal SC1(n) and the second scan signal SC2(n) are supplied LO. The first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 are non-conducting, while the third transistor T3 and the seventh transistor T7 are conducting. For example, if the voltage Vna supplied to the second node N2 is 7V, the voltage Vnb supplied to the first node N1 and the third node N3 is 2.5V, and the potential difference Vgs is 4.5V, the second transistor T2 is conducting. Therefore, the second transistor T2 can flow a current Ion based on the potential difference Vgs and the potential difference Vds corresponding to the voltage VSIGH input during the horizontal period HRP of the K-1st FRAME. The seventh transistor T7 is conducting, and the current Ion flows from the driving power line PVDD to the light-emitting element OLED and the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, the pixel 180E (pixel circuit 181E) emits red light, and three pixels, namely, the pixel 180E emitting red light, the pixel 180E emitting blue light, and the pixel 180E emitting green light, emit white light.

[0566] During the start of a horizontal period HRP of the KthFRAME following the K-1stFRAME light-emission period PEM, pixel 180E (pixel circuit 181E) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGH (-0.5V) corresponding to black, which indicates no light emission. The second scan signal SC2(n) remains in the LOW state. When the first scan signal SC1(n) changes from the LOW state to the HI state, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 change from the non-conductive state to the conductive state, the third transistor T3 and the seventh transistor T7 change from the conductive state to the non-conductive state, and the fifth transistor T5 remains in the non-conductive state. As a result, the voltage supplied to the first node N1 and the voltage supplied to the third node N3 decrease from voltage Vnb.

[0567] During period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGH, the first scan signal SC1(n) maintains the state of being supplied with the HI, and the scan voltage source SIR4(n) maintains the state of being supplied with the initialization voltage VINI1. Furthermore, the second scan signal SC1(n) changes from being supplied with the LO state to being supplied with the HI state. Consequently, the fifth transistor T5 changes from being non-conductive to being conductive, the first transistor T1, the fourth transistor T4, the fifth transistor T5, and the sixth transistor T6 remain conductive, and the third transistor T3 and the seventh transistor T7 remain non-conductive.

[0568] During the end of period PIW, image data signal SL(m) maintains the state of being supplied with data signal VDATA including voltage VSIGL, first scan signal SC1(n) maintains the state of being supplied with HI, and scan voltage source SIR4(n) maintains the state of being supplied with initialization voltage VINI1. Furthermore, second scan signal SC1(n) changes from being supplied with HI to being supplied with LO. Consequently, fifth transistor T5 changes from being conductive to being non-conductive. First transistor T1, fourth transistor T4, and sixth transistor T6 remain conductive, while third transistor T3 and seventh transistor T7 remain non-conductive. Fifth transistor T5 changes to being non-conductive at the final timing.

[0569] As a result, the voltage supplied to the first node N1 gradually decreases from voltage Vnb to voltage VSIGL (voltage Vnd, -0.5V), reaching voltage Vnd (-0.5V). The voltage supplied to the second node N2 gradually decreases from voltage Vna to initialization voltage VINI1 (voltage Vni, 0.5V), reaching voltage Vni (0.5V). Furthermore, the voltage supplied to the third node N3 gradually decreases from voltage Vnb to initialization voltage VINI1 (voltage Vni, 0.5V), reaching voltage Vni (0.5V). Consequently, the potential difference Vgs and the potential difference Vds become 0V (0.5-(0.5V)). As a result, the potential difference Vgs becomes smaller than the threshold voltage VTH (1V), rendering the second transistor T2 non-conductive. Consequently, drain current Ion does not flow from the second electrode 726 of the second transistor T2 to the first electrode 724.

[0570] As described above, the data signal VDATA including the voltage VSIGL is supplied to (written into) the first node N1 , and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 .

[0571] During period PVH, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL, the first scan signal SC1(n) maintains the state of being supplied with the HI, and the second scan signal SC1(n) changes to the LO. The scan voltage source SIR4(n) changes from being supplied with the initialization voltage VINI1 to being supplied with the initialization voltage VINI2. Consequently, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 remain in the on state, while the third transistor T3, the fifth transistor T5, and the seventh transistor T7 remain in the off state.

[0572] Furthermore, at the end of period PVH, if the first scan signal SC1(n) changes from being supplied HI to being supplied LO, the scan voltage source SIR4(n) changes from being supplied with initialization voltage VINI2 to being supplied with initialization voltage VINI1. Consequently, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 change from being conductive to being non-conductive, the third transistor T3 and the seventh transistor T7 change from being non-conductive to being conductive, and the fifth transistor T5 remains non-conductive.

[0573] Therefore, during period PVH, the voltage supplied to the first node N1 remains at voltage Vnd (-0.5V). Since the fourth transistor T4 remains in the on state, the voltage supplied to the third node N3 gradually decreases from voltage Vni (0.5V) to initialization voltage VINI2 (-1V), reaching initialization voltage VINI2 (-1V). At this time, although the fifth transistor T5 is in the non-conducting state, the Vgs of the second transistor T2 approaches 1.5V (0.5V (node ​​N2) - (-1V (node ​​N3)), which is greater than the threshold voltage VTH (1V). Therefore, drain current Ion of the second transistor T2 begins to flow, and the voltage supplied to the second node N2 gradually decreases from voltage Vni (0.5V). Since initialization voltage VINI2 (voltage Vne, -1V) is continuously supplied to the third node N3, when the voltage supplied to the second node N2 reaches 0V, the potential difference Vgs reaches threshold voltage VTH. As a result, the second transistor T2 becomes non-conducting. Therefore, the drain current Ion does not flow from the second electrode 726 of the second transistor T2 to the first electrode 724 .

[0574] As described above, during the period PVH, the threshold voltage VTH of the second transistor T2 is obtained by making the potential difference Vgs of the second transistor T2 equal to the threshold voltage VTH. In addition, a charge corresponding to the threshold voltage VTH is held at the second node N2 (the gate electrode 722 of the second transistor T2).

[0575] During the KthFRAME light emission period PEM following the KthFRAME horizontal period HRP, no select signal is used to select data, and the data signal VDATA is maintained at a voltage above the voltage VSIGL and below the voltage VSIGH. Furthermore, the first scan signal SC1(n) transitions from being HI to being LO, while the second scan signal SC2(n) remains LO. The scan voltage supply SIR4(n) remains supplied with the initialization voltage VINI1 (0.5V).

[0576] As a result, the first transistor T1, the fourth transistor T4, and the sixth transistor T6 go from a conducting state to a non-conducting state, and the third transistor T3 and the seventh transistor T7 go from a non-conducting state to a conducting state. Furthermore, the fifth transistor T5 remains in a non-conducting state. As the third transistor T3 becomes conductive, the first node N1 and the third node N3 become conductive, and the voltage supplied to the first node N1 becomes voltage Vne (-1V). Due to the conductive state between the first node N1 and the third node N3, the voltage supplied to the first node N1 gradually decreases toward -1V. Consequently, due to capacitive coupling between the second node N2 (the gate electrode 722 of the second transistor T2, the first electrode 724 of the capacitor CS) and the third node N3, the voltage supplied to the second node N2 gradually decreases from voltage Vni (0V). For example, the voltage supplied to the second node N2 becomes voltage Vnd (-0.5V).

[0577] Therefore, during the light-emission period PEM of KthFRAME, the potential difference Vgs reaches -0.5V. This potential difference Vgs is smaller than the threshold voltage VTH. Consequently, the second transistor T2 is non-conductive, and current does not flow from the drive power line PVDD to the reference voltage line PVSS. Consequently, the light-emitting element OLED does not emit light. As a result, for example, pixel 180E (pixel circuit 181E) emitting red, pixel 180E emitting blue, and pixel 180E emitting green do not emit light. Consequently, the three pixels (pixel 180E, blue, and green) emitting red, blue, and green appear black.

[0578] <6-2-2. Second Example of the Driving Method of the Pixel Circuit 181E>

[0579] Reference Figure 50 , a second example of the driving method of the pixel circuit 181E is described. The driving method shown in the second example of the pixel circuit 181E is similar to the second example of the driving method of the self-luminous display device 10 according to the first embodiment, and includes displaying images of the same color (white) in consecutive frames. Figures 1 to 49 The same or similar structures will be explained as needed.

[0580] The timing of supplying the image data signal SL(m), the scanning voltage supply SIR4(n), the first scanning signal SC1(n), and the second scanning signal SC2(n) to the pixel circuit 181E during the light-emission period PEM of the K-1st FRAME, the horizontal period HRP of the Kth FRAME, and the period PEM is the same as that described in "6-2-1. First Example of the Driving Method of the Pixel Circuit 181E." Furthermore, the voltage (potential) of the first node N1 during the light-emission period PEM of the K-1st FRAME, the voltages (potentials) of the second node N2 and the third node N3 during the light-emission period PEM of the K-1st FRAME and the horizontal period HRP of the Kth FRAME, and the operation of each transistor are the same as those described in "6-2-1. First Example of the Driving Method of the Pixel Circuit 181E." Details similar to those described in "6-2-1. First Example of the Driving Method of the Pixel Circuit 181E" will be described as needed.

[0581] During the start of a horizontal period HRP of KthFRAME, pixel 180E (pixel circuit 181E) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGL (−4.5V) corresponding to white. The voltage supplied to first node N1 gradually decreases from voltage Vnb to voltage VSIGL (voltage Vnj, −4.5V).

[0582] During period PIW, the voltage supplied to the first node N1 gradually decreases from voltage Vnb to voltage Vnj, reaching voltage Vnj (-4.5 V). The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "6-2-1. First Example of Driving Method of Pixel Circuit 181E."

[0583] As described above, similarly to the content described in "6-2-1. First Example of Driving Method of Pixel Circuit 181E", during period PIW, the data signal VDATA including the voltage VSIGL is supplied (written) to the first node N1, and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1.

[0584] During the period PVH following the period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGL. The first node N1 maintains the state of being supplied with the voltage Vnj. The voltage supplied to the second node N2, the voltage supplied to the third node N3, the potential difference Vgs, and the potential difference Vds are the same as those described in "6-2-1. First Example of Driving Method of Pixel Circuit 181E."

[0585] As described above, similar to the description in "6-2-1. First Example of Driving Method of Pixel Circuit 181E," during period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby obtaining the threshold voltage VTH of the second transistor T2. Furthermore, a charge corresponding to the threshold voltage VTH is retained at the second node N2 (gate electrode 722 of the second transistor T2).

[0586] During the KthFRAME light emission period PEM following the KthFRAME horizontal period HRP, similar to the description in "6-2-1. First Example of Driving Method for Pixel Circuit 181E," the first node N1 and the third node N3 are conductive. While the fourth transistor T4 and the sixth transistor T6 are non-conductive, the voltage at the third node N3 gradually rises. Therefore, through capacitive coupling between the second node N2 (the gate electrode 722 of the second transistor T2 and the first electrode 724 of the capacitor CS) and the third node N3, the voltage supplied to the second node N2 gradually rises from voltage Vni (0V). The voltage at the second node N2 gradually rises from voltage Vni (0V). When the potential difference Vgs exceeds the threshold voltage VTH, the second transistor T2 transitions from a non-conductive state to a conductive state. The seventh transistor T7 is in the on state. Therefore, when the second transistor T2 is turned on, the drain current Ion flows from the driving power supply line PVDD to the reference voltage line PVSS, and the voltage supplied to the first node N1 increases in a manner that follows the increase in the voltage supplied to the first node N1 and the voltage supplied to the second node N2. During this period, the potential difference between the first electrode 792 and the second electrode 794 in PVH is 4.5V (the potential difference between the voltage supplied to the second node N2 and the voltage supplied to the third node N3), and the capacitor element CS holds a charge equivalent to 4.5V. For example, the capacitor element CS holds a charge equivalent to 4.5V, so as Figure 50 As shown, when the voltage supplied to the first node N1 and the voltage supplied to the third node N3 rise to the voltage Vnb (2.5V), the voltage supplied to the second node N2 rises to the voltage Vna (7V).

[0587] The potential difference Vgs (4.5V) is greater than the threshold voltage VTH and the threshold voltage VTHEL of the light-emitting element OLED. Therefore, the second transistor T2 is turned on, and the drain current Ion flows from the drive power line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit light. For example, pixel 180E (pixel circuit 181E) turns red, while the three pixels (pixel 180E emitting blue and pixel 180E emitting green) emit white.

[0588] <6-2-3. Third Example of the Driving Method of the Pixel Circuit 181E>

[0589] Reference Figure 51 , a third example of the driving method of the pixel circuit 181E is described. The driving method shown in the third example of the driving method of the pixel circuit 181E is similar to the third example of the driving method of the self-luminous display device 10 involved in the first embodiment, including displaying images of the same color (black) in consecutive frames. Figures 1 to 50 The same or similar structures will be explained as needed.

[0590] The timing at which the image data signal SL(m), the scanning voltage supply SIR4(n), the first scanning signal SC1(n), and the second scanning signal SC2(n) are supplied to the pixel circuit 181E during the light-emission period PEM of the K-1st FRAME, one horizontal period HRP of the Kth FRAME, and the conduction and non-conduction states of each transistor within the light-emission period PEM are the same as those described in "6-2-1. First Example of the Driving Method of the Pixel Circuit 181E." The same structures as those described in "6-2-1. First Example of the Driving Method of the Pixel Circuit 181E" and "6-2-2. Second Example of the Driving Method of the Pixel Circuit 181E" will be described as needed.

[0591] During the K-1st FRAME light-emission period PEM, for example, the potential difference Vgs reaches 0.5V, which is lower than the threshold voltage VTH (1V, see Table 12) of the second transistor T2. Since the second transistor T2 is in a non-conductive state, no current flows from the drive power supply line PVDD to the reference voltage line PVSS, causing the light-emitting element OLED to emit no light. As a result, similar to pixel 180E (pixel circuit 181E) described in the Kth FRAME light-emission period PEM in "6-2-1. First Example of Driving Method of Pixel Circuit 181E," the three pixels—pixel 180E emitting red, pixel 180E emitting blue, and pixel 180E emitting green—are black.

[0592] During the start of a horizontal period HRP of the KthFRAME following the K-1stFRAME light-emission period PEM, the pixel 180E (pixel circuit 181E) receives an image data signal SL(m) including a data signal VDATA including a voltage VSIGLH (-0.5V) corresponding to black, which indicates no light emission. The voltage supplied to the first node N1 gradually increases from Vne (-1V) to Vnd (-0.5V), the voltage supplied to the second node N2 gradually increases from Vnd (-0.5V) to Vni (0.5V), and the voltage supplied to the third node N3 gradually increases from Vne (-1V) to Vni (0.5V).

[0593] During period PIW, the image data signal SL(m) maintains the state of being supplied with the data signal VDATA including the voltage VSIGH. The first node N1 is supplied with -0.5V, and the second node N2 and the third node N3 are supplied with the voltage Vni (0.5V).

[0594] As described above, in the period PIW, the data signal VDATA including the voltage VSIGL (−0.5V) is supplied to (written into) the first node N1 , and the second node N2 and the third node N3 are initialized by the initialization voltage VINI1 .

[0595] During the period PVH following the period PIW, similarly to the description in "6-2-1. First Example of Driving Method of Pixel Circuit 181E," during the period PVH, the potential difference Vgs of the second transistor T2 is made equal to the threshold voltage VTH, thereby obtaining the threshold voltage VTH of the second transistor T2. Furthermore, a charge corresponding to the threshold voltage VTH is retained at the second node N2 (the gate electrode 722 of the sec...

Claims

1. A display device comprising: a first transistor, the switching of which is controlled by a first control signal, the first transistor being electrically connected between an image data signal line and a first node, the image data signal line being supplied with a data voltage; a third transistor, using the first control signal to control switching of the third transistor, the third transistor being electrically connected between the first node and the second node; a second transistor having a gate electrode electrically connected to the second node, the second transistor being electrically connected between a power supply line supplied with a constant voltage and a third node; a fourth transistor, the first control signal being used to control switching of the fourth transistor, the fourth transistor being electrically connected between a reference voltage power line and the second node, the reference voltage power line being supplied with a reference voltage; a fifth transistor, the switching of the fifth transistor being controlled by a second control signal different from the first control signal, the fifth transistor being electrically connected between an initialization voltage power line and the third node, the initialization voltage power line being supplied with an initialization voltage; a light emitting element electrically connected to the third node; as well as The capacitor is electrically connected between the first node and the third node.

2. The display device according to claim 1, wherein The display device includes a third control signal line, The third control signal line also serves as the reference voltage power line and the initialization voltage power line.

3. The display device according to claim 1, wherein The display device includes a third control signal line, The third control signal line also serves as a second control signal line, the reference voltage power supply line, and the initialization voltage power supply line, and the second control signal is supplied to the second control signal line.

4. The display device according to claim 1, further comprising: a first control circuit, outputting the first control signal; as well as The second control circuit outputs the second control signal.

5. The display device according to claim 4, wherein The first control circuit supplies a high-level voltage to the first control signal to turn on the first transistor and the fourth transistor. The second control circuit supplies a high-level voltage to the second control signal to turn on the fifth transistor. The first control circuit and the second control circuit are controlled in the following manner: The control is performed in such a manner that the period during which the first transistor supplies the data voltage to the first node and the period during which the fourth transistor supplies the reference voltage to the second node are the same, and the control is performed in such a manner that the period during which the first transistor supplies the data voltage to the first node is shorter than the period during which the fifth transistor supplies the initialization voltage to the third node. The display device according to claim 1 , wherein: The first transistor, the second transistor, and the fourth transistor are n-channel field effect transistors. The third transistor is a p-channel field effect transistor.

7. The display device according to claim 1, wherein The first transistor, the fourth transistor, and the fifth transistor are n-channel field effect transistors. The second transistor and the third transistor are p-channel field effect transistors.

8. The display device according to claim 6 or 7, wherein: The deep energy level of the channel region of the third transistor has a value of 1×10 17 eV -1 cm -3 The following density of states.

9. The display device according to claim 6 or 7, wherein: The display device includes a first semiconductor layer, a second semiconductor layer and a third semiconductor layer. The first semiconductor layer includes a channel region of the second transistor and a channel region of the fifth transistor, The second semiconductor layer includes a channel region of the first transistor and a channel region of the third transistor, The third semiconductor layer includes a channel region of the fourth transistor.

10. The display device according to claim 1, wherein A channel length of the second transistor is longer than a channel length of the first transistor, a channel length of the third transistor, a channel length of the fourth transistor, and a channel length of the fifth transistor.

11. The display device according to claim 1, wherein The channel region of each of the second transistor, the third transistor, the fourth transistor, and the fifth transistor comprises crystalline silicon. The first transistor and the fourth transistor each have an oxide semiconductor in their channel regions.

12. The display device according to claim 1, wherein The display device includes a first conductive layer and a second conductive layer different from the first conductive layer. The reference voltage power line and the initialization voltage power line each include a first conductive layer and a second conductive layer that are different from each other. In a plan view, the first conductive layer and the second conductive layer included in the reference voltage power line overlap, and the first conductive layer and the second conductive layer included in the initialization voltage power line overlap.

13. The display device according to claim 1, wherein The gate electrode overlaps with the capacitor in a plan view.

14. A display device comprising: a first transistor, the switching of which is controlled by a first control signal, the first transistor being electrically connected between an image data signal line and a first node, the image data signal line being supplied with a data voltage; a third transistor, using the first control signal to control switching of the third transistor, the third transistor being electrically connected between the first node and a third node; a second transistor having a gate electrode electrically connected to the second node, the second transistor being electrically connected between the third node and a fourth node; a fourth transistor, switching the fourth transistor is controlled by the first control signal, the fourth transistor being electrically connected between a third control signal line and the third node, the third control signal line being supplied with a first initialization voltage and a second initialization voltage, the second initialization voltage being different from the first initialization voltage; a fifth transistor, using a second control signal different from the first control signal to control switching of the fifth transistor, the fifth transistor being electrically connected between a third control signal line and the fourth node; a sixth transistor, using the first control signal to control switching of the sixth transistor, the sixth transistor being electrically connected between the second node and the fourth node; a seventh transistor, switching of the seventh transistor is controlled by the first control signal, the seventh transistor being electrically connected between a power line and the fourth node, the power line being supplied with a constant voltage; a light emitting element electrically connected to the third node; as well as A capacitor element is electrically connected between the first node and the second node.

15. The display device according to claim 14, further comprising: a first control circuit, outputting the first control signal; as well as The second control circuit outputs the second control signal.

16. The display device according to claim 15, wherein The first control circuit supplies a high-level voltage to the first control signal to turn on the first transistor, the fourth transistor, and the sixth transistor. The second control circuit supplies a high-level voltage to the second control signal to turn on the fifth transistor. The first control circuit controls so that the period during which the first transistor supplies the data voltage to the first node, the period during which the fourth transistor supplies the first initialization voltage to the third node, and the period during which the sixth transistor supplies the first initialization voltage and the second initialization voltage to the second node are the same.

17. The display device according to claim 14, wherein: The first transistor, the second transistor, the fourth transistor, the fifth transistor, and the sixth transistor are n-channel field effect transistors. The third transistor and the seventh transistor are p-channel field effect transistors.

18. The display device according to claim 14, wherein The first transistor, the fourth transistor, the fifth transistor, and the sixth transistor are n-channel field effect transistors. The second transistor, the third transistor, and the seventh transistor are p-channel field effect transistors.

19. The display device according to claim 18, wherein The deep energy level of the channel region of the third transistor has a value of 1×10 17 eV -1 cm -3 The following density of states.

20. The display device according to claim 14, wherein The channel regions of the first transistor, the second transistor, the third transistor, the fourth transistor, the fifth transistor, and the seventh transistor each include crystalline silicon. A channel region of the sixth transistor includes an oxide semiconductor.

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