Display panel and display device thereof

Abstract

The invention provides a display panel and a display device thereof. The display panel comprises a plurality of pixel units, each pixel unit comprises a light-emitting device and a pixel driving circuit, and each pixel driving circuit comprises a driving transistor and a first reset transistor; wherein one end of the first reset transistor is used for accessing a first reset signal, the other end is connected to a light-emitting loop formed by connecting the driving transistor and the light-emitting device in series, and the control end is used for accessing a first grid control signal. In a first time period after a data writing time period of a display frame of the display panel, the first gate control signal is in an effective level, and the first reset transistor is conducted, so that the driving transistor is conducted according to a data signal written in the data writing time period; therefore, the first reset signal is transmitted to the first electrode and the second electrode of the driving transistor so as to reset the first electrode and the second electrode of the driving transistor.

Description

Technical Field

[0001] The present application relates to the field of display technology, and in particular to a display panel and a display device thereof. Background Art

[0002] In display technology, pixel units do not have the on-state bias stress (OBS) function, making it difficult to reset the circuit nodes on both sides of the driving transistor contained in the pixel unit, which in turn leads to poor frequency switching effects. This, to a certain extent, limits the further improvement of display panel performance and cannot meet the market demand for high-quality display effects and more stable performance. Summary of the Invention

[0003] The embodiments of the present application provide a display panel and a display device thereof, so that a pixel unit has an OBS function to improve the frequency switching effect.

[0004] An embodiment of the present application provides a display panel, comprising: a plurality of pixel units arranged in an array, the pixel units comprising a light-emitting device and a pixel driving circuit; the pixel driving circuit comprising a driving transistor and a first reset transistor; the driving transistor and the light-emitting device are connected in series in a light-emitting circuit between a first power line and a second power line; a first electrode of the first reset transistor is used to access a first reset signal, a second electrode of the first reset transistor is connected to the light-emitting circuit, and a control electrode of the first reset transistor is used to access a first gate control signal; wherein, in a first time period after a data writing period of a display frame of the display panel, when the first gate control signal is at an effective level, the first reset transistor is turned on, so that the driving transistor is turned on according to the data signal written in the data writing period, and the first reset signal is transmitted to the first electrode and the second electrode of the driving transistor connected to the light-emitting circuit, respectively, to reset the first electrode and the second electrode of the driving transistor.

[0005] An embodiment of the present application further provides a display device, comprising the display panel described above.

[0006] In the display panel provided in the present application, a first reset transistor connected to the light-emitting circuit is provided in the pixel driving circuit, and in the first period after the data writing period of a display frame, the first reset transistor is turned on according to the first gate control signal at the effective level, so that the driving transistor is turned on according to the data signal written in the data writing period, and the first reset signal connected to the first reset transistor is transmitted to the first electrode and the second electrode (source / drain) of the driving transistor respectively, thereby resetting the source / drain of the driving transistor, so that the pixel unit has an OBS function to improve the frequency cutting effect. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] The present application is further described below with reference to the accompanying drawings. It should be noted that the drawings described below are only used to illustrate some embodiments of the present application, and those skilled in the art can also derive other drawings based on these drawings without inventive effort.

[0008] Figure 1 An exemplary block diagram of a display device including a display panel provided in an embodiment of the present application.

[0009] Figure 2 This is an exemplary block diagram of a pixel unit of a display panel provided in an embodiment of the present application.

[0010] Figure 3 A circuit for a pixel unit of a display panel provided in an embodiment of the present application Figure 1 .

[0011] Figure 4 Provided in the embodiments of this application Figure 3 Schematic diagram of driving timing of the pixel unit shown.

[0012] Figure 5 An exemplary schematic diagram of obtaining a data signal provided in an embodiment of the present application.

[0013] Figure 6 A circuit for a pixel unit of a display panel provided in an embodiment of the present application Figure 2 .

[0014] Figure 7 Provided in the embodiments of this application Figure 6 Schematic diagram of driving timing of the pixel unit shown. DETAILED DESCRIPTION

[0015] The specific implementation methods of this application are described in detail below with reference to the accompanying drawings.

[0016] The terms "first", "second" and similar words do not indicate any order, quantity or importance, but are only used to distinguish different technical features. The term "plurality" and similar words mean two or more, unless otherwise expressly limited.

[0017] The embodiments of the present application may be combined with each other.

[0018] like Figure 1As shown, the display device provided in the embodiments of the present application may be, for example, an organic light emitting diode (OLED) display device. Of course, the display device may also be a Mini-LED display device or a Micro-LED display device. The display device may include a source driver circuit, a gate driver circuit, a timing controller, a light controller, a power management chip, a substrate, a data line for transmitting a data signal Data, a scan signal line for transmitting a scan signal SCAN, a first power line for transmitting a voltage VDD or a second power line for transmitting a voltage VSS, a light control signal line for transmitting a light control signal EM, a pixel array, an encapsulation layer, a polarizer, a color filter, and the like.

[0019] The substrate may be, for example, a glass substrate, a flexible substrate (e.g., a polyimide substrate), etc. The pixel array is composed of a plurality of pixel units PX arranged in rows and columns, forming a plurality of pixel rows arranged along the row direction and a plurality of pixel columns arranged along the column direction, and each pixel row and each pixel column includes a plurality of pixel units. For ease of description, the pixel rows and pixel columns may also be referred to as "rows" and "columns" hereinafter. Taking the display device as an OLED display device as an example, the pixel unit PX may include an organic light-emitting device and a pixel driving circuit. The pixel driving circuit may include a driving transistor, which is used to control the brightness of the corresponding organic light-emitting device in the display panel. In an actual pixel unit, the driving transistor may include but is not limited to a thin film transistor (TFT) of low temperature polycrystalline silicon (LTPS) and a metal oxide (Oxide) semiconductor. To reduce power consumption, the driving transistor may be an Oxide transistor. The TFT may adopt a dual-gate structure, and the organic light-emitting device is electrically connected to the first electrode or the second electrode of the TFT, wherein the first electrode of the TFT may be the source or drain electrode of the TFT, and correspondingly, the second electrode of the TFT may be the drain or source electrode of the TFT. The organic light-emitting device may include a light-emitting layer, an electron transport layer, a hole transport layer, a cathode, and an anode, etc. Different organic materials may emit light of different wavelengths to achieve full-color display. The encapsulation layer includes an alternating organic / inorganic multilayer structure. The gate driver on array (GOA) is mainly used to scan and drive pixel rows. For example, the GOA circuit may include cascaded gate driver units, wherein each level of gate driver units controls one or more pixel rows to achieve pixel unit gating. In some embodiments, the GOA may adopt unilateral drive or bilateral drive for multiple pixel rows, wherein the unilateral drive may be to arrange gate driver units on only one side (such as the left or right side), and drive the multiple pixel rows row by row-by-row scanning in a cascade manner. Bilateral drive may be to arrange driver units on both the left and right sides of the multiple pixel rows, and drive the multiple pixel rows row by row-by-row scanning by working together on both sides. The source driver circuit is used to provide data signals to the pixel units. The timing controller is used to receive external input image data and synchronization signals, and generate the signals required by the gate drive circuit and the source drive circuit. The power management chip is used to provide the required operating voltage for each part of the display panel. It should be noted that Figure 1 This is an exemplary schematic diagram, and the connection relationship of the components shown is only used to explain the functional logical relationship of the display panel, rather than to limit the actual physical structure.

[0020] The display panel provided by the embodiments of the present application incorporates a reset transistor connected to the light-emitting circuit in the pixel drive circuit and controls the on / off switching of the reset transistor to reset the source and drain of the drive transistor in the pixel drive circuit. This enables the pixel unit to have an OBS function, thereby improving the frequency switching effect and meeting market demands for high-quality display effects and more stable performance.

[0021] The following is a detailed description with reference to the accompanying drawings.

[0022] See also Figure 2 As shown, an embodiment of the present application provides an exemplary display panel. The display panel 100 may include a plurality of pixel units 101 arranged in an array. The pixel units 101 may include a red pixel unit, a green pixel unit, and a blue pixel unit. Each of the pixel units 101 may include a light-emitting device 1011 and a pixel driving circuit 1012, wherein the light-emitting device 1011 may be, but not limited to, an OLED, an MLED, a Min-LED, etc. The pixel driving circuit 1012 may include a driving transistor T1 and a first reset transistor T2. 复 . The driving transistor T1 can be an oxide transistor. The light-emitting device 1011 and the driving transistor T1 are connected in series in a light-emitting circuit 1013 between a first power line (such as a power line connected to a voltage VDD) and a second power line (such as a power line connected to a voltage VSS), wherein the anode of the light-emitting device is connected to the second electrode of the driving transistor T1, and the cathode of the light-emitting device is connected to the second power line to access the voltage VSS. It should be noted that a first light-emitting control transistor T6 as described later may exist between the driving transistor T1 described here and the anode of the light-emitting device. Therefore, Figure 2 The block diagram shows the connection relationship between the driving transistor T1 and the anode of the light emitting device with ellipsis. The first electrode of the driving transistor T1 is connected to the first power line to access the VDD voltage. 复 The first electrode of the reset transistor T is used to receive the first reset signal. 复 The second electrode of the first reset transistor T is connected to the light emitting circuit 1013. 复 The control electrode of is used to access the first gate control signal; wherein, in the first period after the data writing period of a display frame of the display panel 100, when the first gate control signal is at an effective level, the first reset transistor T 复The driving transistor T1 is turned on according to the data signal written in the data writing period, and the first reset signal is transmitted to the first electrode and the second electrode of the driving transistor T1 connected to the light-emitting circuit 1013, respectively, to reset the first electrode and the second electrode of the driving transistor T1, thereby realizing the OBS function.

[0023] It should be noted that, as mentioned above, the driving transistor T1 can be an oxide transistor to reduce power consumption. This pixel unit including an oxide transistor as the driving transistor T1 has certain advantages in frequency adaptability and can support low frequencies, such as 1 Hz or even lower. When switching at half the required frequency, the color brightness difference is small, and the human eye can hardly see the flicker phenomenon. The effective level can refer to the voltage that can make the first reset transistor T 复 The conduction level, for example, if the first reset transistor T 复 is a T-type transistor, the effective level of the first gate control signal is high level; if the first reset transistor T 复 It is a P-type transistor, and the effective level of the first gate control signal is a low level.

[0024] The following two specific embodiments are used to describe in detail how the present application implements the OBS function.

[0025] Example 1

[0026] like Figure 3 As shown, it shows a circuit of a pixel unit of a display panel Figure 1 .exist Figure 3 The pixel driving circuit 1012 may include: a driving transistor T1, a data writing transistor T2, a transmission transistor T3, a reset transistor T4 (the first reset transistor T4 mentioned above), 复 ), a first light emitting control transistor T6, a second light emitting control transistor T5, a second reset transistor T7 and a storage capacitor Cst.

[0027] The first electrode of the driving transistor T1 is connected to the first node A, the second electrode of the driving transistor T1 is connected to the second node B, and the control electrode of the driving transistor T1 is connected to the third node Q. The first electrode of the data writing transistor T2 is connected to the data line for receiving the corresponding data signal Data, the second electrode of the data writing transistor T2 is connected to the second node B, and the control electrode of the data writing transistor T2 is used to receive the second scan signal SCAN2. The first electrode of the transmission transistor T3 is connected to the first node A, the second electrode of the transmission transistor T3 is connected to the third node Q, and the control electrode of the transmission transistor T3 is used to receive the first scan signal SCAN1. The first electrode of the reset transistor T4 is connected to the anode of the light-emitting device 1011 in the light-emitting circuit 1013 to the fourth node C, and the second electrode of the reset transistor T4 is connected to the reset signal V T4 (is the first reset signal), the control electrode of the reset transistor T4 is used to receive the first gate control signal. The first electrode of the second light-emitting control transistor T5 is connected to the first power line to receive the voltage VDD, the second electrode of the second light-emitting control transistor T5 is connected to the first node A, and the control electrode of the second light-emitting control transistor T5 is used to receive the fourth gate control signal. The second electrode of the first light-emitting control transistor T6 is connected to the fourth node C, and the control electrode of the first light-emitting control transistor T6 is used to receive the second gate control signal. The first electrode and the anode of the second reset transistor T7 are connected to the fourth node C, and the second electrode of the second reset transistor T7 is connected to the corresponding second reset signal V T7 The control electrode of the second reset transistor T7 is used to receive the third gate control signal. The storage capacitor Cst is connected between the third node Q and the fourth node C.

[0028] Based on this, Figure 3 The pixel driving circuit shown in the embodiment of the present application also provides a pixel unit driving timing for the display panel, as shown in FIG. Figure 4 As shown. Figure 4 In the example, the driving transistor T1, the data writing transistor T2, the transmission transistor T3, the reset transistor T4 and the second reset transistor T7 are N-type transistors. The first light emission control transistor T6 and the second light emission control transistor T5 are P-type transistors. In addition, as mentioned above Figure 1 As described above, GOA performs row-by-row scanning and driving on each pixel row, and each gate driving unit contained therein controls one pixel row. Figure 4 The pixel unit shown is one of the Nth pixel row, then, Figure 4The first scanning signal SCAN1, the second light emitting control signal EM1, the first light emitting control signal EM2, and the second scanning signal SCAN2 shown can be provided by the Nth stage gate driving unit. It can be understood that Figure 4 The second scanning signal SCAN2(N+X) of the N+3th stage can be provided by the gate driving unit of the N+Xth stage, wherein X is an integer greater than or equal to 3, but X cannot be too large, otherwise the period of a display frame will be relatively long. In actual application, the value of X can be selected as long as it can satisfy the requirement that the reset transistor T4 and the second reset transistor T7 are not turned on at the same time. The first light-emitting control signal EM2(N+1) of the N+1th stage can be provided by the gate driving unit of the N+1th stage. Based on this, Figure 3 In the embodiment, the first gate control signal connected to the control terminal of the reset transistor T4 is the first light emitting control signal EM2 of the N+1 stage, that is, Figure 4 EM2(N+1) shown. The second gate control signal of the first light emitting control transistor T6 is the first light emitting control signal EM2(N) of the Nth stage. The third gate control signal of the second reset transistor T7 is the second scan signal SCAN2(N+X) of the N+3th stage. The fourth gate control signal of the second light emitting control transistor T5 is the second light emitting control signal EM1(N) of the Nth stage. It should be noted that the second light emitting control signal EM1(N) of the Nth stage can be referred to as EM1, and the rest of the signals of the Nth stage can also be referred to as EM1. Based on Figure 4 As shown in the timing sequence, the display frame includes 6 time periods, namely 1, 2, 3, 4, 5 and 6. The specific function of each time period is as follows.

[0029] Period 1: The first node A and the third node Q are reset.

[0030] The specific process is as follows: the transmission transistor T3 is turned on according to the first scan signal SCAN1, and the second light-emitting control transistor T5 is turned on according to the second light-emitting control signal EM1, and the voltage VDD of the first power line is transmitted to the first node A and the third node Q respectively to start resetting the first node A and the third node Q to a high potential.

[0031] Period 2: The fourth node C is reset.

[0032] The specific process is as follows: the reset transistor T4 is turned on according to the first gate control signal connected to its control electrode, and the reset signal V T4The first gate control signal is transmitted to the fourth node C to reset the fourth node C to a low potential, wherein the first gate control signal is the second light-emitting control signal EM2(N+1) for controlling the light-emitting devices in the (N+1)th pixel row. During period 2, the transmission transistor T3 remains on according to the first scan signal SCAN1, and the second light-emitting control transistor T5 remains on according to the second light-emitting control signal EM1, so that the potentials at the first node A and the third node Q remain at a high potential corresponding to the voltage VDD.

[0033] In period 3 (data writing period), the data signal Data is written into the third node Q.

[0034] The specific process is as follows: the data writing transistor T2 is turned on according to the second scanning signal SCAN2, and transmits the data signal Data to the second node B. The transmission transistor T3 continues to be turned on according to the first scanning signal SCAN1, and transmits the voltage VDD to the third node Q. The reset transistor T4 remains turned on according to the first gate control signal, and continues to transmit the reset signal V T4 In this case, the control electrode of the driving transistor T1 is connected to the third node Q and connected to the voltage VDD, and the second electrode (such as the source) is connected to the second node B to connect to the voltage V DATA , then the gate-source voltage Vgs of the driving transistor T1 can be VDD-V DATA , which is greater than the threshold voltage Vth of the driving transistor T1, thereby turning on the driving transistor T1, so that the data signal Data is transmitted to the third node Q through the data writing transistor T2, the driving transistor T1, and the transmission transistor T3, that is, the data signal is written to the third node Q.

[0035] It should be noted that the data signal Data written in period 2 can be based on the reset signal V T4 The change amount is generated with the initial data signal, wherein the reset signal V T4 The change in the reset signal V T4 The voltage difference before and after the change; the initial data signal can be a preset data signal.

[0036] In the display panel provided in the embodiment of the present application, in order to achieve relatively accurate data compensation for each pixel unit in the same pixel row by detecting only one signal, the reset transistors T4 of the pixel units 101 in the same row can be connected to the same reset signal V T4 , wherein the reset signal V T4 It can be a DC signal, for example, the reset signal V T4The aforementioned voltage VSS can be reused. In other embodiments, the reset signal V T4 It may also be a DC signal lower than a set voltage threshold, wherein the set voltage threshold may be less than or equal to Vdata.

[0037] Based on Figure 3 The display panel shown in FIG. 1 can be used to calculate the light emitting current of the pixel unit as follows: K(k1*Vdata-k2V T4 +k3) 2 , where K, k1, k2 and k3 are all known parameters, which are related to the size parameters of the driving transistor T1. Vdata is the voltage of the data signal connected to the first electrode of the data writing transistor through the data line. T4 is the first reset signal connected to the second electrode of the reset transistor T4. Figure 3 The light emitting current of the pixel unit of the display panel shown is related to the data signal and the reset signal V connected to the second electrode of the reset transistor T4. T4 Related. So, Figure 3 The light emitting current of the pixel unit of the display panel shown is affected by the data signal and the reset signal V T4 In some cases, the voltage V T4 Fluctuations will occur. At this time, in order to reduce the impact on the display effect of the pixel unit, the data signal can be compensated appropriately to offset the impact of the fluctuation of the first reset signal on the light-emitting current.

[0038] Based on this, the embodiment of the present application provides a Figure 3 The data compensation method of the pixel unit of the display panel shown is as follows: the control circuit connected to the display panel 100 (such as the main control of a notebook computer) can detect the reset signal V T4 , and according to the reset signal V T4 Generate data signals for each pixel row to perform data compensation on each pixel unit 101 in each pixel row. As an example, the control circuit detects the reset signal V corresponding to the Nth pixel row. T4 changes, according to the reset signal V T4 Then, during the data writing period within a display frame of the display panel, the data signal is written into each pixel unit in the Nth pixel row; and in the first period after the data writing period, the second reset signal V corresponding to each pixel unit in the Nth pixel row is reset. T7The voltage N is transmitted to the anode (fourth node C) of the light-emitting device of each pixel unit to reset the anode, wherein N is an integer greater than or equal to 1.

[0039] It should be noted that, as mentioned above, the pixel units in the same row are connected to the same reset signal V T4 , and the light-emitting current of the pixel unit is affected by the reset signal V T4 Therefore, for each row of pixel units, the control circuit can only detect the corresponding reset signal V T4 Then, when the reset signal V is detected T4 When the reset signal V T4 Then, the data signal is written into each pixel unit during a data writing period within a display frame of the display panel.

[0040] For example, if Figure 5 As shown in FIG, it shows an exemplary schematic diagram of obtaining the data signal corresponding to each pixel unit according to the change of the first reset signal. Figure 5 As shown, it is assumed that at time t0, the reset signal V T4 Changes have occurred, for example, the reset signal V T4 The voltage amplitude of the data signal corresponding to each pixel unit in the pixel row changes, and the voltage amplitude of the data signal corresponding to each pixel unit in the pixel row will also change. Based on this, the data signal corresponding to each pixel unit in the pixel row can be different or the same. In summary, the display panel provided in the first embodiment of the present application provides a first reset transistor in the pixel unit, and a reset signal V is connected to the first reset transistor. T4 Detection is performed to achieve data compensation for the data signal of each pixel unit in the same row of pixel units. Therefore, the embodiment of the present application does not require modification of the original control circuit in the display panel that can only detect one signal (such as the timing controller in the aforementioned display device). It can still detect only one signal, but can still perform relatively accurate data compensation for pixel units that receive different second reset signals, thereby improving low grayscale visual effects and optimizing pixel unit data compensation.

[0041] In period 4 (the first period after the data writing period in the display frame), the first node A and the second node B are reset to implement the OBS function.

[0042] The specific process is as follows: the reset transistor T4 remains in the on state according to the first gate control signal input, and the voltage of the fourth node C is maintained at the reset signal V T4The first light emitting control transistor T6 is turned on according to the second gate control signal (the second light emitting control signal EM2) connected to its control electrode, so that the reset signal V T4 The voltage V of the data signal Data is written to the third node Q during period 3. DATA , so that the voltage difference between the third node Q and the second node B (V DATA -V T4 ) is greater than the threshold voltage Vth of the driving transistor T1, the driving transistor T1 is turned on, so that the reset signal V T4 The voltage is also transmitted to the first node A through the driving transistor T1 to reset the first node A.

[0043] It should be noted that, in the first period between the data writing period and the light emitting period, the first gate control signal (EM2(n+1)) and the second gate control signal (EM2(n)) are at an effective level, that is, the first gate control signal is at a high level and the second gate control signal is at a low level. At this time, the reset transistor T4 and the first light emitting control transistor T6 are turned on, so that the reset signal V T4 is transmitted to the fourth node C, so that the driving transistor T1 is driven according to the data signal Data written in the data writing period and the reset signal V T4 is turned on, the reset signal V T4 The first node A and the second node B are respectively transmitted to the first node A to reset the second node B and the first node A. During the first period, the driving transistor T1 is applied with a continuous bias voltage (the voltage difference between the third node Q and the second node B) and is turned on, so that the driving transistor T1 continues to be in an on-state bias state. Therefore, the pixel unit has an OBS function, which can improve the influence of the hysteresis effect of the driving transistor T1 on the display effect of the display panel, thereby improving the frequency switching effect.

[0044] In period 5 (the second period after the data writing period in the display frame), the fourth node is reset again.

[0045] The specific process is as follows: the second reset transistor T7 is turned on according to the third gate control signal, and the second reset signal V T7 The third gate control signal may be a second scan signal SCAN2(N+X) corresponding to each pixel unit in the N+Xth pixel row.

[0046] It should be noted that, in the period 5, the first light emitting control transistor T6 is turned on according to the first light emitting control signal, and the second reset signal VT7 The voltage V of the third node Q is also transmitted to the second node B through the first light emitting control transistor T6, and the second node B is reset. Since the data signal Data is written into the third node Q during the data writing period, the third node has the voltage V of the data signal Data (which is the compensated data signal or the initial data signal). DATA , the second node B is reset to a low potential V T7 Therefore, in this period 5, the gate-source voltage Vgs (V DATA -V T7 ) is greater than the threshold voltage Vth, the driving transistor T1 is turned on, and the second reset signal V T7 It is also transmitted to the first node A through the driving transistor T1 to reset the first node A. Since the voltage of the reset signal VT4 is equal to the second reset signal V T7 The voltage of the storage capacitor Cst is different, and the storage capacitor Cst needs to make the third node Q and the second node B have a stable voltage difference. Based on this, the second node B is reset by the second reset signal V T7 is reset, then the data signal of the third node Q will also change accordingly due to the influence of the coupling effect.

[0047] In actual application, in order to improve the low grayscale visual effect, the second reset signal V ... T7 Different, for example, the second reset signal V T7 It can be the second reset signal V of Vi_R, green pixel unit and blue pixel unit T7 It can be Vi_GB, that is, the second reset signal V corresponding to the green pixel unit T7 The second reset signal V corresponding to the blue pixel unit T7 Similarly, the second reset signal V corresponding to the green pixel unit T7 The second reset signal V corresponding to the red pixel unit T7 Furthermore, in a second period after the first period, the third gate control signal is set to an effective level, and the second reset transistor T7 is turned on. After the second reset transistor T7 is turned on, the corresponding second reset signal V T7 The light is transmitted to the anode of the light-emitting device to reset the anode, thereby improving the visual effect of the light-emitting device in low grayscale display, ensuring consistent display of the display panel at different brightness levels, and thus improving the overall image quality. In this way, not only can the working state of the light-emitting device be optimized, but also a clearer and more accurate display effect can be provided under low grayscale conditions.

[0048] In period 6 (a light-emitting period within a display frame), the light-emitting device is driven to emit light.

[0049] The specific process is as follows: the first light emitting control transistor T6 and the second light emitting control transistor T5 are turned on according to the first light emitting control signal EM2 and the second light emitting control signal EM1 respectively, so that the driving transistor T1 generates a driving current according to the data signal to drive the light emitting device to emit light.

[0050] In the first embodiment, for example Figure 3 The display panel shown in FIG. detects the reset signal V connected to the reset transistor T4. T4 , and the reset signal V T4 When a change occurs, the automatic compensation (AVC) algorithm in the control circuit is used to calculate the compensated data signal, and the compensated data signal is written into the third node Q during the data writing period within the display frame to perform data compensation on the pixel unit, thereby optimizing the data compensation of the pixel unit. In the first period after the data writing period, the reset transistor T4 and the first light-emitting control transistor T6 are controlled to be turned on to reset the first node A and the second node B, so that the pixel unit has an OBS function, thereby improving the influence of the hysteresis effect of the driving transistor T1 on the display effect of the display panel. In the second period after the data writing period, at least two different second reset signals V T7 The signals are respectively transmitted to the fourth nodes of the corresponding pixel units (such as the red pixel unit and the blue / green pixel unit) to reset the anodes of the light-emitting devices connected to the fourth nodes, thereby improving the low grayscale visual effect of the display panel.

[0051] Example 2

[0052] like Figure 6 As shown, the embodiment of the present application also exemplarily provides a display panel 200, which may include a plurality of pixel units 101 arranged in an array. The pixel unit 101 may include a light-emitting device 1011 and a pixel driving circuit 1012, wherein the light-emitting device 1011 may be, but not limited to, an OLED, and the anode of the light-emitting device 1011 is connected to the fourth node C, and the cathode is connected to the second power line to access the voltage VSS. The pixel driving circuit 1012 may include: a driving transistor T1, a data writing transistor T2, a transmission transistor T3, a reset transistor T4 (a third reset transistor), a second light-emitting control transistor T5, a first light-emitting control transistor T6, a second reset transistor T7, a reset transistor T8 (a first reset transistor T9), a reset transistor T10 (a third reset transistor T11), a reset transistor T12 (a third reset transistor T12), a reset transistor T13 (a third reset transistor T13), a reset transistor T14 (a third reset transistor T14), a reset transistor T15 (a third reset transistor T15), a reset transistor T16 (a third reset transistor T16), a reset transistor T17 (a third reset transistor T17), a reset transistor T18 (a third reset transistor T18), a reset transistor T19 (a third reset transistor T19), a reset transistor T20 (a third reset transistor T19), a reset transistor T21 (a third reset transistor T19), a reset transistor T22 (a third reset transistor T19), a reset transistor T23 (a third reset transistor T19), a reset transistor T24 (a third reset transistor T19), a reset transistor T25 (a third reset transistor T19), a reset transistor T26 (a third reset transistor T19), a reset transistor T27 (a third reset transistor T19), a reset transistor T28 (a third reset transistor T19), a reset transistor T29 (a third reset transistor T19), a reset transistor T30 (a third reset transistor 复 ) and storage capacitor Cst.

[0053] The connection method of the driving transistor T1, the data writing transistor T2, the transmission transistor T3, the reset transistor T4, the second light emitting control transistor T5, the first light emitting control transistor T6, the second reset transistor T7 and the storage capacitor Cst included in the pixel driving circuit 1012 is the same as that of the aforementioned Figure 3 The connection method of the transistors T1, T2, T3, T4, T5, T6, T7 and Cst in the display panel shown is the same, which can be understood by reference and will not be repeated here. In the second embodiment, the main difference from the first embodiment is that a reset transistor T8 is added, the first electrode of the reset transistor T8 is connected to the second node B, the second electrode is connected to the reset signal Vibais (which is the first reset signal), and the control electrode is connected to the second scan signal SCAN2 corresponding to the pixel row after the current pixel row. For example, if the current pixel row is the Nth row, then the control electrode of the reset transistor T8 can be connected to the second scan signal SCAN2 (N+Y) in the N+Y pixel row. The reset signal V T4 In the second embodiment, it is the third reset signal.

[0054] In the second embodiment, Figure 6 The calculation formula of the light emitting current of the pixel unit included in the display panel shown is the same as the above Figure 3 The calculation formula of the light-emitting current of the pixel unit included in the display panel shown is the same, so, Figure 6 The light emitting current of the pixel unit of the display panel shown is also affected by the third reset signal connected to the third reset transistor T4. Figure 6 The data compensation method of the pixel unit of the display panel shown is the same as the aforementioned Figure 3 The data compensation method of the pixel unit of the display panel shown can be the same, which can be understood with reference to the above description and will not be repeated here.

[0055] In this application, the driving method of the pixel unit in the first embodiment is different from that in the second embodiment. The driving method of the pixel unit in the second embodiment can be exemplarily as follows: Figure 7 shown.

[0056] exist Figure 7 In the embodiment, the driving transistor T1, the data writing transistor T2, the transmission transistor T3, the transistor T4, the second reset transistor T7 and the reset transistor T8 are N-type transistors, and the first emission control transistor T6 and the second emission control transistor T5 are P-type transistors. Figure 7 The first scan signal SCAN1 , the first light emitting control signal EM2 , the second light emitting control signal EM1 , and the second scan signal SCAN2 shown may be provided by an Nth stage gate driving unit for driving pixel units of an Nth pixel row. Figure 7The second scan signal SCAN2(N+X) of the N+Xth stage shown can be provided by the N+Xth stage gate driving unit, where X is an integer greater than or equal to 3. However, X cannot be too large, otherwise the period of a display frame will be relatively long. In actual application, the value of X only needs to be able to ensure that the reset transistor T4 and the second reset transistor T7 are not turned on at the same time. Figure 7 The second scan signal SCAN2(N+Y) of the N+Y stage can be provided by the N+Y stage gate driving unit, wherein X and Y can be equal or different, but Y cannot be too large, otherwise the period of a display frame will be longer. Based on this, Figure 6 The control signals of the control electrodes of the various transistors in the pixel driving circuit of the display panel shown are as follows: the first gate control signal of the reset transistor T8 is SCAN2(N+Y). The fifth gate control signal of the second reset transistor T7 is SCAN2(N+X). The control signal connected to the control electrode of the reset transistor T4 is SCAN1 of the Nth level. The control signal of the transfer transistor T3 is SCAN1 of the Nth level. The control signal of the data write transistor T2 is SCAN2 of the Nth level. The control signal of the first light-emitting control transistor T6 is the first light-emitting control signal EM2. The control signal of the second light-emitting control transistor T5 is the second light-emitting control signal EM1. Based on this, Figure 7 The display frame shown may include four time periods: I, II, III, and IIII, wherein the specific function of each time period is as follows.

[0057] In period I, the first node A and the third node Q are reset.

[0058] The specific process is as follows: the transmission transistor T3 is turned on according to the first scan signal SCAN1, and the second light-emitting control transistor T5 is turned on according to the second light-emitting control signal EM1, and the voltage VDD is transmitted to the first node A and the third node Q to start resetting the first node A and the third node Q to a high potential. The reset transistor T4 is turned on according to the first scan signal SCAN1, and the reset signal V T4 (being the third reset signal) is transmitted to the fourth node to reset the anode of the light-emitting device 1011 to a low potential.

[0059] Period II (data writing period): a data signal is written into the third node Q.

[0060] The specific process is as follows: the data writing transistor T2 is turned on according to the second scan signal SCAN2, and the data signal is transmitted to the second node B. The transmission transistor T3 is turned on according to the first scan signal SCAN1, and the voltage VDD is transmitted to the third node Q. And the reset transistor T4 is turned on according to the first scan signal SCAN1. At this time, the control electrode of the driving transistor T1 is connected to the voltage VDD through the third node Q, and the second electrode is connected to the data voltage V through the second node B. DATA , the gate-source voltage Vgs of the driving transistor T1 is VDD-V DATA , which is greater than the threshold voltage Vth of the driving transistor T1, the driving transistor T1 is turned on, allowing the data signal to be transmitted to the third node Q via the data write transistor T2, the driving transistor T1, and the transmission transistor T3. This data signal can also be a compensated data signal or an initial data signal. For a detailed explanation, please refer to the description of the data write period in Example 1. The reset transistor T4 is turned on in response to the first scan signal SCAN1, leaving the fourth node at a low potential to prevent the light-emitting device from emitting light.

[0061] During period III (the first period after the data writing period in the display frame), the first node A, the second node B and the fourth node are reset. The first period and the third period are the same period.

[0062] The specific process is as follows: the second reset transistor T7 is turned on according to the fifth gate control signal, and the second reset signal V T7 The fifth gate control signal is transmitted to the fourth node C to reset the anode of the light-emitting device, wherein the fifth gate control signal is the second scan signal SCAN2(N+X) corresponding to the N+Xth pixel row. The reset transistor T8 is turned on according to the first gate control signal input, and transmits the reset signal Vibais (the first reset signal) to the second node B to reset the second node B. Since the data voltage V DATA , so that the voltage difference between the third node Q and the second node B (V DATA -Vibais) is greater than the threshold voltage Vth of the driving transistor T1, the driving transistor T1 is turned on, and the third reset signal Vibais is transmitted to the first node A through the driving transistor T1 to reset the first node A. Based on this, the pixel unit applies a continuous bias voltage to the driving transistor T1 during the period III and turns on the pixel unit, so that the pixel unit has an OBS function, thereby improving the display effect of the display panel affected by the hysteresis effect of the driving transistor T1.

[0063] It should be noted that, in this time period III, X=Y, that is, the fifth gate control signal and the first gate control signal are the same signal, and the first time period and the third time period are the same time period; the fifth gate control signal and the first gate control signal are the second scanning signals corresponding to the N+Xth pixel row after the Nth pixel row, where N is an integer greater than or equal to 1; and X is an integer greater than or equal to 3.

[0064] During period III (light-emitting period within a display frame), the light-emitting device is driven to emit light.

[0065] The specific process is as follows: the first light emitting control transistor T6 and the second light emitting control transistor T5 are turned on according to the first light emitting control signal EM2 and the second light emitting control signal EM1 respectively, so that the driving transistor T1 generates a driving current according to the data signal to drive the light emitting device to emit light.

[0066] In the second embodiment, for example Figure 5 The display panel shown in FIG. detects the reset signal V connected to the reset transistor T4. T4 , and the reset signal V T4 When a change occurs, the automatic compensation (AVC) algorithm in the control chip calculates a compensated data signal, and during the data writing period within the display frame, the compensated data signal is written to the third node Q to perform data compensation on the pixel unit, thereby optimizing the data compensation of the pixel unit. In the first period after the data is written, at least two different second reset signals are transmitted to the fourth node of the corresponding pixel unit via the second reset transistor T7 to reset the anode of the light-emitting device connected to the fourth node to improve the low-grayscale visual effect of the display panel; and the first node A and the second node B are reset via the reset transistor T8 to enable the pixel unit to have an OBS function, thereby improving the influence of the hysteresis effect of the driving transistor T1 on the display effect of the display panel. In this second embodiment, the OBS function and the step of resetting the anode of the pixel unit by the second reset signal can both occur in the first period after the data writing period, without the need to divide the period separately to implement the OBS function.

[0067] Based on the display panel provided above, an embodiment of the present application further provides a display device, comprising any one of the display panels described above.

[0068] The above is a detailed introduction to the display panel and display device provided in the embodiments of the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the technical solutions and core ideas of the present application. Ordinary technicians in this field should understand that they can still modify the technical solutions recorded in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. These modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present application.

Claims

1. A display panel, characterized in that: include: A plurality of pixel units arranged in an array, each pixel unit comprising a light-emitting device and a pixel driving circuit; The pixel driving circuit includes a driving transistor and a first reset transistor; the driving transistor is an oxide transistor; the driving transistor and the light-emitting device are connected in series in a light-emitting circuit between a first power line and a second power line; a first electrode of the first reset transistor is used to receive a first reset signal, a second electrode of the first reset transistor is connected to the light-emitting circuit, and a control electrode of the first reset transistor is used to receive a first gate control signal; Among them, in the first time period after the data writing period of a display frame of the display panel, when the first gate control signal is at a valid level, the first reset transistor is turned on, so that the driving transistor is turned on according to the data signal written in the data writing period, and the first reset signal is transmitted to the first electrode and the second electrode of the driving transistor respectively, so as to reset the first electrode and the second electrode of the driving transistor connected to the light-emitting circuit.

2. The display panel according to claim 1, wherein: The pixel driving circuit further includes a first light emitting control transistor; The first electrode of the driving transistor is connected to the first node, the second electrode of the driving transistor is connected to the second node, and the control electrode of the driving transistor is connected to the third node; the first electrode of the first reset transistor and the anode of the light-emitting device in the light-emitting circuit are connected to the fourth node, the second electrode of the first reset transistor is connected to the first reset signal, and the control electrode of the first reset transistor is used to connect to the first gate control signal; the first electrode of the first light-emitting control transistor is connected to the second node, the second electrode of the first light-emitting control transistor is connected to the fourth node, and the control electrode of the first light-emitting control transistor is used to connect to the second gate control signal; the cathode of the light-emitting device is connected to the second power line; In which, during the first time period, the first gate control signal and the second gate control signal are at an effective level, the first reset transistor and the first light-emitting control transistor are turned on, so that the first reset signal is transmitted to the fourth node, so that the driving transistor is turned on according to the data signal written in the data writing time period and the first reset signal, and the first reset signal is transmitted to the second node and the first node respectively to reset the second node and the first node.

3. The display panel according to claim 2, wherein: The control electrodes of the first light-emitting control transistors of the pixel units located in the same row are connected to the same light-emitting control signal line to access the same first light-emitting control signal; within the display frame, the second gate control signal is the first light-emitting control signal corresponding to the Nth pixel row; the first gate control signal is the first light-emitting control signal corresponding to the N+1th pixel row, where N is an integer greater than or equal to 1.

4. The display panel according to claim 2, wherein: The pixel driving circuit further includes: a second reset transistor, wherein a first electrode of the second reset transistor and the anode are connected to the fourth node, a second electrode of the second reset transistor is connected to a corresponding second reset signal, and a control electrode of the second reset transistor is connected to a third gate control signal; the second reset signals connected to the second reset transistors of at least two pixel units in the same row are different; In which, in a second period after the data writing period, the third gate control signal is at a valid level, the second reset transistor is turned on, and the corresponding second reset signal is transmitted to the anode of the light-emitting device to reset the anode; the second period is after the first period.

5. The display panel according to claim 4, wherein: The pixel unit includes a red pixel unit, a green pixel unit, and a blue pixel unit, wherein the second reset signal corresponding to the green pixel unit is the same as the second reset signal corresponding to the blue pixel unit; the second reset signal corresponding to the green pixel unit is different from the second reset signal corresponding to the red pixel unit.

6. The display panel according to claim 4, wherein: The pixel driving circuit further includes: a transmission transistor and a data writing transistor; The first electrode of the transmission transistor is connected to the first node, the second electrode of the transmission transistor is connected to the third node, and the control electrode of the transmission transistor is used to receive the first scanning signal; A first electrode of the data writing transistor is connected to the corresponding data signal, a second electrode of the data writing transistor is connected to the second node, and a control electrode of the data writing transistor is used to connect to the second scanning signal; In which, during the data writing period, the first scanning signal and the second scanning signal are at an effective level, the data writing transistor and the transmission transistor are turned on, and the driving transistor is turned on, so that the data signal is transmitted to the third node through the data writing transistor, the driving transistor, and the transmission transistor.

7. The display panel according to claim 6, wherein: The control electrodes of the transfer transistors of the pixel units located in the same row are connected to the same scanning signal line to receive the same first scanning signal; the control electrodes of the data writing transistors of the pixel units located in the same row are connected to the same scanning signal line to receive the same second scanning signal; In the display frame, the control electrode of the transfer transistor is connected to the first scanning signal corresponding to the Nth pixel row; the data write transistor is connected to the second scanning signal corresponding to the Nth pixel row; the third gate control signal is the second scanning signal corresponding to the N+Xth pixel row after the Nth pixel row, where N is an integer greater than or equal to 1; and X is an integer greater than or equal to 3.

8. The display panel according to claim 4, wherein: The second electrodes of the first reset transistors of the pixel units located in the same row are connected to the same first reset signal; the first reset signal is a direct current signal.

9. The display panel according to claim 8, wherein: If the first reset signal changes, the data signal is generated based on the change in the first reset signal and the initial data signal, wherein the change in the first reset signal is the voltage difference between before and after the change of the first reset signal; the initial data signal is a pre-set data signal.

10. The display panel according to claim 6, wherein: The pixel driving circuit further includes: a second light emitting control transistor, wherein a first electrode of the second light emitting control transistor is connected to the first power line, a second electrode of the second light emitting control transistor is connected to the first node, and a control electrode of the second light emitting control transistor is used to receive a fourth gate control signal; wherein, during the light-emitting period within the display frame, the second gate control signal and the fourth gate control signal are at an effective level, the first light-emitting control transistor and the second light-emitting control transistor are turned on, so that the driving transistor generates a driving current according to the data signal to drive the light-emitting device to emit light; In which, the control electrodes of the second light-emitting control transistors of the pixel units located in the same row are connected to the same light-emitting control signal line to access the same second light-emitting control signal; within the display frame, the fourth gate control signal is the second light-emitting control signal corresponding to the Nth pixel row, wherein N is an integer greater than or equal to 1.

11. The display panel according to claim 9, wherein The pixel driving circuit further includes a storage capacitor connected between the third node and the fourth node.

12. The display panel according to claim 1, wherein The first electrode of the driving transistor is connected to the first node, the second electrode of the driving transistor is connected to the second node, and the control electrode of the driving transistor is connected to the third node; the first electrode of the first reset transistor is connected to the second node, the second electrode of the first reset transistor is used to receive the first reset signal, and the control electrode of the first reset transistor is used to receive the first gate control signal; In which, during the first time period, the first gate control signal is at a valid level, and the first reset transistor is turned on, so that the driving transistor is turned on according to the data signal written in the data writing time period, and the first reset signal is transmitted to the second node and the first node respectively to reset the second node and the first node.

13. The display panel according to claim 12, wherein: The pixel driving circuit further includes a transmission transistor, a data writing transistor and a storage capacitor; The first electrode of the transfer transistor is connected to the first node, the second electrode of the transfer transistor is connected to the third node, and the control electrode of the transfer transistor is used to receive the first scanning signal of the Nth pixel row; the first electrode of the data write transistor is connected to the corresponding data signal, the second electrode of the data write transistor is connected to the second node, and the control electrode of the data write transistor is used to receive the second scanning signal of the Nth pixel row; the storage capacitor is connected between the third node and the fourth node; and the fourth node is connected to the anode of the light-emitting device. During the data writing period, the first scanning signal and the second scanning signal are at an effective level, the data writing transistor and the transfer transistor are turned on, and the driving transistor is turned on, so that the data signal is transmitted to the third node through the data writing transistor, the driving transistor, and the transfer transistor.

14. The display panel according to claim 13, wherein: The pixel driving circuit further includes a second reset transistor, wherein a first electrode of the second reset transistor and an anode of the light-emitting device are connected to a fourth node, a second electrode of the second reset transistor is connected to a corresponding second reset signal, and a control electrode of the second reset transistor is connected to a fifth gate control signal; In a third period after the data writing period, the fifth gate control signal is at an effective level, the second reset transistor is turned on, and the corresponding second reset signal is transmitted to the anode of the light emitting device to reset the anode.

15. The display panel according to claim 14, wherein: The fifth gate control signal is the same signal as the first gate control signal, and the first time period is the same time period as the third time period; the fifth gate control signal and the first gate control signal are second scanning signals corresponding to the N+Xth pixel row after the Nth pixel row, where N is an integer greater than or equal to 1; and X is an integer greater than or equal to 3.

16. The display panel according to claim 14, wherein: The pixel driving circuit also includes a third reset transistor, a first electrode of the third reset transistor and the anode of the light-emitting device are connected to a fourth node, a second electrode of the first reset transistor is connected to a third reset signal, and a control electrode of the third reset transistor is used to connect to the first scanning signal of the Nth pixel row; the second electrodes of the third reset transistors of the pixel units located in the same row are connected to the same third reset signal; and the third reset signal is a DC signal.

17. The display panel according to claim 16, wherein: If the third reset signal changes, the data signal is generated based on the change in the third reset signal and the initial data signal, wherein the change in the third reset signal is the voltage difference between before and after the third reset signal changes; the initial data signal is a pre-set data signal.

18. The display panel according to claim 16, wherein: The pixel driving circuit further includes: a first light-emitting control transistor and a second light-emitting control transistor; wherein a first electrode of the first light-emitting control transistor is connected to the second node, a second electrode of the first light-emitting control transistor and an anode of the light-emitting device are connected to a fourth node, and a control electrode of the first light-emitting control transistor is used to receive a first light-emitting control signal corresponding to the N-th pixel row; a first electrode of the second light-emitting control transistor is connected to the first power line, a second electrode of the second light-emitting control transistor is connected to the first node, and a control electrode of the second light-emitting control transistor is used to receive a second light-emitting control signal corresponding to the N-th pixel row; In which, during the light-emitting period of the display frame, the first light-emitting control signal and the second light-emitting control signal are at an effective level, the first light-emitting control transistor and the second light-emitting control transistor are turned on, so that the driving transistor generates a driving current according to the data signal to drive the light-emitting device to emit light.

19. A display device, characterized in that: The display panel comprises the display panel according to any one of claims 1 to 18.

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