Doping method based on a remote plasma source

Abstract

The embodiment of the present disclosure discloses a doping method based on a remote plasma source, which is used to solve the technical problem of how to realize uniform doping of a three-dimensional structure. The doping method comprises the following steps: placing a wafer on a susceptor in a process chamber; wherein the wafer comprises a laminated structure and a groove penetrating through the laminated structure; the groove exposes a plurality of semiconductor layers in the laminated structure, and a gap communicating with the groove is formed between two adjacent semiconductor layers; a doping gas is provided to an input end of a remote plasma source to generate a plasma; wherein an output end of the remote plasma source is connected to the process chamber, and the plasma comprises high-energy particles in a high-energy state and low-energy particles in a low-energy state; the high-energy particles in the plasma are filtered out, and the low-energy particles are provided to the process chamber to perform doping treatment on the plurality of semiconductor layers exposed by the groove and the gap. In this way, uniform doping of the three-dimensional structure can be realized, and lattice damage of the semiconductor layers can be reduced.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and relate to but are not limited to a doping method based on a remote plasma source. BACKGROUND

[0002] Semiconductor doping technology is one of the key technologies for semiconductor device processing, which mainly introduces a small amount of impurity elements (e.g., phosphorus, boron, etc.) into specific regions of a semiconductor structure (e.g., a silicon wafer) to form P-type and / or N-type doped regions in the semiconductor structure, thereby achieving PN junction formation, carrier concentration adjustment, and device performance optimization, etc.

[0003] Current semiconductor doping technology mainly realizes impurity doping through ion implantation and thermal diffusion. However, with the shrinking of semiconductor device size and the formation of three-dimensional (3D) structures through vertical stacking, the current semiconductor doping technology has limitations in controlling the uniform distribution of doped particles. Therefore, how to achieve uniform doping of 3D structures has become a technical problem to be solved. SUMMARY

[0004] Embodiments of the present disclosure provide a doping method based on a remote plasma source, comprising: placing a wafer on a susceptor in a process chamber; wherein the wafer comprises a stacked structure and a groove penetrating through the stacked structure; the groove exposes a plurality of semiconductor layers in the stacked structure, and a gap is formed between two adjacent semiconductor layers and communicates with the groove; providing a doping gas to an input end of the remote plasma source to generate a plasma; wherein an output end of the remote plasma source is connected to the process chamber, and the plasma comprises high-energy particles in a high-energy state and low-energy particles in a low-energy state; filtering out the high-energy particles in the plasma and providing the low-energy particles to the process chamber to perform doping treatment on the plurality of semiconductor layers exposed by the groove and the gap.

[0005] In some embodiments, the filtering out of the high-energy particles in the plasma and the providing of the low-energy particles to the process chamber comprises: providing a bias magnetic field or a bias electric field to a transmission channel to filter out the high-energy particles from the plasma; wherein the transmission channel is connected to the output end of the remote plasma source and the process chamber, respectively.

[0006] In some embodiments, the providing of the bias magnetic field or the bias electric field to the transmission channel to filter out the high-energy particles from the plasma comprises: under the action of the bias magnetic field or the bias electric field, the transmission direction of the high-energy particles transmitted in a preset direction changes and collides with the inner side wall of the transmission channel, so that the energy and / or density of the high-energy particles are reduced.

[0007] In some embodiments, the filtering out the high-energy particles in the plasma and providing the low-energy particles to the process chamber comprises: transmitting the low-energy particles through the transmission channel to the process chamber along the preset direction.

[0008] In some embodiments, each of the semiconductor layers is formed with a conformal doped region.

[0009] In some embodiments, the doping method further comprises: performing an annealing process on the doped wafer to activate the doped ions in the low-energy particles diffused into each of the semiconductor layers.

[0010] In some embodiments, the doping method further comprises: after the annealing process, performing a first surface treatment on the wafer with a mixed gas of hydrogen and nitrogen to repair dangling bonds on the surface of at least one of the semiconductor layers.

[0011] In some embodiments, the annealing process has a temperature range of 700-1100℃ and a time range of 5-120s.

[0012] In some embodiments, the doping method further comprises: before providing the doping gas, performing a second surface treatment on the wafer to remove oxides on the surface of at least one of the semiconductor layers.

[0013] In some embodiments, the doped ions in each of the semiconductor layers are uniformly distributed.

[0014] In some embodiments, the high-energy particles comprise at least one of positive ions, negative ions and electrons; and the low-energy particles comprise free radicals.

[0015] In the embodiments of the present disclosure, a plasma is generated in a remote plasma source away from a process chamber, and high-energy particles in the plasma are filtered out, and only low-energy particles in the plasma are allowed to enter the process chamber, so as to perform a doping process on a plurality of semiconductor layers in a stacked structure. In this way, in a first aspect, doping with low-energy particles can reduce lattice damage of the semiconductor layers; in a second aspect, isotropic plasma diffusion can achieve conformal doping of a three-dimensional structure and improve doping uniformity; in a third aspect, doping depth and concentration can be precisely controlled, which is particularly suitable for ultra-shallow junction formation; and in a fourth aspect, application of the remote plasma source technology not only improves the reliability of advanced processes, but also provides a new way for development of next-generation devices. BRIEF DESCRIPTION OF DRAWINGS

[0016] In the drawings, like reference numerals refer to same or similar components throughout the several views. The drawings are not necessarily to scale, the emphasis instead being placed upon illustrating the principles of the application. It should be understood that the drawings are merely for purposes of illustration and are not to be construed as limiting the scope of the application.

[0017] Figure 1 is a schematic diagram of several semiconductor doping techniques shown in an exemplary embodiment;

[0018] Figure 2 is a flow chart of a remote plasma source based doping method provided in an embodiment of the present disclosure;

[0019] Figure 3 is a schematic diagram of a process chamber connected to a remote plasma source provided in an embodiment of the present disclosure;

[0020] Figure 4 is a schematic diagram of a wafer being pre-processed provided in an embodiment of the present disclosure;

[0021] Figure 5 is a schematic diagram of low energy particles diffusing within a recess and gap provided in an embodiment of the present disclosure;

[0022] Figure 6 is a schematic diagram of low energy particles adsorbing on a surface of a semiconductor layer provided in an embodiment of the present disclosure;

[0023] Figure 7 is a schematic diagram of doping ions thermally diffusing into a semiconductor layer provided in an embodiment of the present disclosure;

[0024] Figure 8 is a schematic diagram of a plasma generated from B2H6 / H2 under excitation of radio frequency or microwave. DETAILED DESCRIPTION

[0025] In order to facilitate the understanding of the present disclosure, exemplary embodiments thereof will be described in detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments set forth herein. Rather, these embodiments are provided so that the present disclosure can be more thoroughly and completely conveyed to those skilled in the art.

[0026] In the following description, numerous specific details are set forth to provide a more thorough understanding of the present disclosure. However, it will be apparent to one of skill in the art upon

[0027] Generally, terminology can be understood at least in part from usage in context. For example, terms, as used herein, can be used in various ways at least in part depending on context, such as being used in a singular sense or in a plural sense. Similarly, terms, such as "a", "an" or "the" also can be understood, at least in part, depending on context, as having a singular or plural meaning. Additionally, terms, such as "based on" can be understood as not necessarily of exclusive alternatives, as such can also allow for adding additional factors as circumstances can warrant, at least in part, depending on context.

[0028] Unless otherwise defined, terms used herein are for descriptive purposes only and do not limit the present disclosure. As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will be further understood that the terms "comprises", "comprising", "includes" and / or "including", when used herein, specify the presence of stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof. As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0029] For a thorough understanding of the present disclosure, reference is made to the following description taken in conjunction with the accompanying drawings. The disclosure can be implemented in many embodiments other than those described below.

[0030] Before introducing the embodiments of the present disclosure, the technical terms involved in the following description are explained. A remote plasma source (RPS) is a device specially used for generating plasma. It mainly generates plasma by exciting the gas inside the device through radio frequency or microwave energy. Since this plasma is not generated directly on the surface of the processing object (for example, a wafer), but is generated inside the RPS device far from the processing object and then transported to the area of the surface that needs to be processed, it is called "remote plasma".

[0031] Current semiconductor doping techniques are mainly ion implantation and thermal diffusion. The following will combine Figure 1 to illustrate ion implantation and thermal diffusion.

[0032] Figure 1 is a schematic diagram of several semiconductor doping techniques shown in an exemplary embodiment. Figure 1 (a) of FIG. shows ion implantation doping. Ion implantation is a core process in integrated circuit manufacturing due to its high-precision dose and depth control (by adjusting energy and dose), but its lattice damage needs to be repaired by rapid thermal annealing. Figure 1 (b) of FIG. shows thermal diffusion doping. Thermal diffusion is mainly used for deep junction doping of power devices, but the lateral diffusion caused by high temperature limits its application in nanoscale devices.

[0033] With the miniaturization of semiconductor devices to the nanoscale, the limitations of traditional thermal diffusion and ion implantation techniques are increasingly prominent, such as uneven doping concentration, inaccurate junction depth control, and lattice damage caused by high-energy particles, which seriously affect device performance and yield. That is, the current doping process in semiconductor manufacturing is facing severe challenges.

[0034] Among emerging technologies, plasma doping (PLAD) can adapt to 3D structures (such as FinFET / trench, etc.) through low-energy ion implantation. Figure 1 (c) of FIG. shows plasma doping. Low-energy ion implantation (<1 keV) in plasma can meet the needs of advanced process ultra-shallow junctions. However, plasma doping cannot achieve uniform doping in high aspect ratio regions.

[0035] Based on one or more of the above technical problems, the present disclosure provides a doping method based on a remote plasma source, which can be applied to semiconductor devices with three-dimensional structures, including but not limited to three-dimensional dynamic random access memory (3D DRAM).

[0036] Figure 2 is a flowchart of a doping method based on a remote plasma source provided by the present disclosure. Referring to Figure 2 , the doping method includes:

[0037] S110: placing a wafer on a susceptor in a process chamber; wherein the wafer includes a stacked structure and a groove penetrating through the stacked structure; the groove exposes a plurality of semiconductor layers in the stacked structure, and a gap communicating with the groove is formed between two adjacent semiconductor layers;

[0038] S120: providing a doping gas to an input end of the remote plasma source to generate a plasma; wherein an output end of the remote plasma source is connected to the process chamber, and the plasma includes high-energy particles in a high-energy state and low-energy particles in a low-energy state;

[0039] S130: filtering out the high-energy particles in the plasma and providing the low-energy particles to the process chamber to perform a doping process on the plurality of semiconductor layers exposed by the groove and the gap.

[0040] Figure 3 is a schematic diagram of a process chamber connected to a remote plasma source provided by an embodiment of the present disclosure, Figures 4 to 7 is a perspective structural schematic diagram of wafer doping, and the following will combine Figure 2 , Figure 3 and Figures 4 to 7 to exemplarily describe a doping method based on a remote plasma source provided by an embodiment of the present disclosure.

[0041] Referring to Figure 2 , Figure 3 and Figure 4 , step S110 is performed: placing a wafer (Wafer, W) on a susceptor 204 in a process chamber 202; wherein the wafer W includes a laminated structure 304 and a groove 310 penetrating through the laminated structure 304; the groove 310 exposes a plurality of semiconductor layers 306 in the laminated structure 304, and a gap 312 communicating with the groove 310 is formed between two adjacent semiconductor layers 306.

[0042] In step S110, the wafer W shown in Figure 4 may be horizontally placed on the susceptor 204 shown in Figure 3 . It should be noted that before the wafer W is placed into the process chamber 202, a vacuum pump 208 (Vacuum Pump) can be used to vacuum the process chamber 202 to ensure that the process chamber 202 is in a vacuum environment.

[0043] The process chamber 202 (Process Chamber) is the main body of the semiconductor processing equipment, also known as the main chamber (Main Chamber). The process chamber 202 refers to a space in the semiconductor processing equipment that provides a controllable atmosphere or environment for a specific process step, which is usually equipped with a susceptor 204, a gas distribution system, a heating / cooling unit, and a vacuum exhaust system, etc. to realize deposition, etching, doping, annealing or cleaning processes on the surface of the wafer W. It should be noted that the process chamber 202 can also be equipped with other components not shown in Figure 3 .

[0044] The base 204 is a platform within the process chamber 202 used to support and fix the wafer W. The base 204 is typically equipped with a heater, an electrostatic chuck, or a vacuum adsorption channel, which enables horizontal positioning of the wafer W, uniform temperature control, and thermal stress release during the process, ensuring stable and repeatable interaction between the reactive gas or plasma and the surface of the wafer W.

[0045] Wafer W refers to an intermediate structure at any stage of the semiconductor fabrication process. For example, see [reference needed]. Figure 4 As shown, wafer W may include a substrate 302, a stacked structure 304 located on the substrate 302, and a groove 310 penetrating the stacked structure 304. The groove 310 exposes a plurality of semiconductor layers 306 in the stacked structure 304, and a gap 312 communicating with the groove 310 is formed between two adjacent semiconductor layers 306. The gap 312 exposes an insulating layer 308 in the stacked structure 304. It should be noted that wafer W may also be other three-dimensional structures that need to be doped, and this disclosure does not have any special limitations in this regard.

[0046] The wafer W formation process includes: forming an initial stacked structure on a substrate 302, the initial stacked structure including sacrificial layers and an initial semiconductor layer 306S stacked alternately in a vertical direction; etching to form multiple vias penetrating the initial stacked structure; laterally etching away a portion of the sacrificial layer through each via, and forming a structure such as... at the location where the sacrificial layer is removed. Figure 4 The insulating layer 308 is shown; a groove 310 is etched to form a penetration through the initial stacked structure, the bottom of which may extend to the surface of the substrate 302 or into the substrate 302; the remaining sacrificial layer is removed by lateral etching through the groove 310 to expose a portion of the initial semiconductor layer 306S; the exposed initial semiconductor layer 306S is thinned to form a structure as shown. Figure 4 The gap 312 and semiconductor layer 306 are shown.

[0047] The material of the substrate 302 may include elemental semiconductor materials (e.g., silicon (Si) or germanium (Ge), III-V compound semiconductor materials (e.g., gallium nitride (GaN), gallium arsenide (GaAs) or indium phosphide (InP), II-VI compound semiconductor materials (e.g., zinc sulfide (ZnS), cadmium sulfide (CdS) or cadmium telluride (CdTe), organic semiconductor materials or other semiconductor materials known in the art).

[0048] The forming process of the sacrificial layers and the initial semiconductor layers 306S includes, but is not limited to, an epitaxial growth process, a Chemical Vapor Deposition (CVD) process, a Physical Vapor Deposition (PVD) process, an Atomic Layer Deposition (ALD) process, or any combination thereof.

[0049] The material of each initial semiconductor layer 306S includes silicon, and the material of each sacrificial layer includes silicon germanium. As an example, the silicon germanium can be epitaxially grown on a monocrystalline silicon surface, and the silicon germanium can be selectively oriented and grown on the monocrystalline silicon surface, and the process flow is simple and controllable. Of course, the initial semiconductor layers 306S can also select other semiconductor materials, and the sacrificial layers can also select other sacrificial materials that have an etching selectivity with the initial semiconductor layers 306S, and the present disclosure does not have special limitations in this regard.

[0050] The forming process of the through holes and the grooves 310 includes, but is not limited to, a dry etching process. For example, a patterned mask layer is formed on the initial stack structure; a dry etching process is used to etch downwardly the initial stack structure until the substrate 302 is exposed, thereby forming the through holes or the grooves 310 that penetrate through the initial stack structure. Of course, the substrate 302 can be further etched downwardly, so that the bottom of the through holes or the grooves 310 extends into the substrate 302.

[0051] The forming process of the insulating layers 308 includes, but is not limited to, a CVD process, a PVD process, an ALD process, or any combination thereof. The material of the insulating layers 308 includes, but is not limited to, silicon oxide.

[0052] The removing process of the sacrificial layers includes, but is not limited to, a wet etching process. For example, a wet etching process is used to selectively etch each sacrificial layer exposed by the through holes or the grooves 310. The material of the sacrificial layers includes, but is not limited to, silicon germanium.

[0053] The process of thinning the initial semiconductor layers 306S can include, but is not limited to, a dry etching process, and the structure after the initial semiconductor layers 306S are thinned is shown in FIG. 3C. Figure 4 As shown in FIG. 3C, the thinned initial semiconductor layers 306S form the semiconductor layers 306, and the thickness of the semiconductor layers 306 is less than the thickness of the initial semiconductor layers 306S.

[0054] It should be noted that, since the semiconductor layers 306 are thinned from the initial semiconductor layers 306S, the semiconductor layers 306 are not shown in FIG. 3C. Figure 4 FIG. 3D is a perspective structure diagram of the wafer W, and the structures shown in the grooves 310 (for example, the isolation sidewalls 314 in the grooves 310) are structures seen through the grooves 310, rather than structures actually located in the grooves 310. The subsequent Figure 4 , Figure 5 , Figure 6 , Figure 7are also schematic perspective views of the wafer W, and the structures shown in the grooves 310 are not actually located therein, and will not be described again later.

[0055] Referring to Figure 2 and Figure 3 is shown, step S120 is performed: the dopant gas 214 is provided to the input end 210a of the remote plasma source, so as to generate the plasma 216; wherein the output end 210b of the remote plasma source 210 is connected to the process chamber 202, and the plasma 216 includes high-energy particles in a high-energy state and low-energy particles 218 in a low-energy state.

[0056] In step S120, the gas containing the doping element (i.e., the dopant gas 214) can be input Figure 3 is shown, the dopant gas 214 enters the excitation chamber of the remote plasma source 210 via the input end 210a, and forms the plasma 216 including active particles such as ions, electrons, and radicals (not shown) under the excitation of radio frequency or microwaves. The low-energy particles 218 such as radicals in the plasma 216 can be transported to the process chamber 202 through the output end 210b of the remote plasma source 210, so as to dope the wafer W in the process chamber 202.

[0057] The dopant gas 214 can be provided by a gas supply device, for example, the gas supply device is connected to the input end 210a of the remote plasma source 210. The dopant gas 214 can include a gas containing elements such as boron, phosphorus, or arsenic, for example, B2H6, PH3, AsH3, BF3, etc. It should be noted that the gas provided to the input end 210a of the remote plasma source 210 can also include a mixed gas of the dopant gas 214 and a carrier gas, and the carrier gas can include H2, He, Ar, or other inert gases.

[0058] For example, the dopant gas 214 is B2H6, and the carrier gas is H2. Figure 8 is a schematic diagram of the plasma generated by B2H6 / H2 under the excitation of radio frequency or microwaves. Referring to Figure 8 is shown, B2H6 / H2 can generate reactive radicals, energetic ions, and electrons under the excitation of radio frequency or microwaves. In actual applications, the dopant gas 214 and the carrier gas can be reasonably selected according to the doping type of a specific region, and the present disclosure has no special limitation thereon.

[0059] Based on their kinetic energy and chemical reactivity, plasmas can be classified. For example, plasmas in a high-energy state are designated as high-energy particles, and those in a low-energy state are designated as low-energy particles. Generally, positive ions, negative ions, and electrons in plasma are considered to have high kinetic energy; that is, high-energy particles include at least one of these three types. Free radicals in plasma, being electrically neutral and not accelerated by an electric field, have kinetic energies close to room temperature and can be considered low-energy particles; therefore, low-energy particles include free radicals.

[0060] Reference Figure 2 , Figure 3 and Figure 5 As shown, step S130 is performed: high-energy particles in plasma 216 are filtered out, and low-energy particles 218 are provided to process chamber 202 to dope multiple semiconductor layers 306 exposed in groove 310 and gap 312.

[0061] In step S130, during the process of transporting the plasma 216 generated in the excitation chamber to the process chamber 202, high-energy particles in the plasma 216 are filtered out, allowing only low-energy particles 218 from the plasma 216 to enter the process chamber 202. The low-energy particles 218 entering the process chamber 202 can enter the nanoscale gaps 312 between adjacent semiconductor layers 306 through the grooves 310, thereby achieving conformal, low-damage, and highly uniform doping on all exposed surfaces of each semiconductor layer 306. Here, the doped ions in each semiconductor layer 306 are uniformly distributed.

[0062] Reference Figure 5 As shown, the surface of wafer W can expose grooves 310, allowing low-energy particles 218 entering the process chamber 202 to diffuse uniformly into each gap 312 via the grooves 310; the low-energy particles 218 diffused into each gap 312 can be uniformly adsorbed onto the surface of each semiconductor layer 306, such as... Figure 6 As shown; the adsorbed low-energy particles 218 can thermally diffuse into each semiconductor layer 306 at low temperatures to form ultra-shallow junctions or conformal doped regions in each semiconductor layer 306, such as... Figure 7 As shown. It should be noted that different dopants have different diffusion coefficients and solid solubilities in silicon, and their diffusion temperatures also vary. In practical applications, the diffusion temperature can be reasonably selected according to the type of dopant element, and this disclosure does not impose any restrictions on this.

[0063] It should be noted that since plasma 216 is generated at a location far from wafer W (i.e., within the remote plasma source 210), when it is transported to the surface of wafer W, it is mainly free radicals that participate in the reaction, rather than ions and electrons, which can reduce the damage and heat accumulation caused by ion bombardment to the material.

[0064] In the embodiments of the present disclosure, the plasma is generated in a remote plasma source away from the process chamber, and high-energy particles in the plasma are filtered out, and only low-energy particles in the plasma are allowed to enter the process chamber, so as to perform doping treatment on the plurality of semiconductor layers in the stacked structure. In this way, in a first aspect, the use of low-energy particles for doping can reduce the lattice damage of the semiconductor layers; in a second aspect, the use of isotropic plasma diffusion can realize conformal doping of three-dimensional structures and improve the doping uniformity; in a third aspect, the doping depth and concentration can be accurately controlled, and the method is particularly suitable for ultra-shallow junction formation; and in a fourth aspect, the use of the remote plasma source technology not only improves the reliability of advanced processes, but also provides a new way for the development of next-generation devices.

[0065] In some embodiments, referring to Figure 3 As shown in FIG. 1, the step S130 includes providing a bias magnetic field or a bias electric field to the transmission channel 212 to filter out high-energy particles from the plasma 216.

[0066] Referring to Figure 3 As shown in FIG. 1, the transmission channel 212 is connected to the output end 210b of the remote plasma source 210 and the process chamber 202, respectively, and is used to transport the generated plasma 216 into the process chamber 202. A controllable bias magnetic field or bias electric field (for example, electrostatic bias) is applied in the transmission channel 212, so that the high-energy particles are deflected in the transmission channel 212, thereby filtering out the high-energy particles from the plasma 216, allowing only radicals to enter the process chamber 202, and thereby realizing low-damage and high-uniformity doping of three-dimensional structures. It should be noted that the diffusion distance and uniformity of the radicals can be realized by pressure adjustment.

[0067] In some embodiments, the above-mentioned providing a bias magnetic field or a bias electric field to the transmission channel 212 to filter out high-energy particles from the plasma 216 includes: under the action of the bias magnetic field or the bias electric field, the transmission direction of the high-energy particles transmitted in the preset direction changes and collides with the inner side wall of the transmission channel 212, so that the energy and / or density of the high-energy particles are reduced.

[0068] Referring to Figure 3 As shown in FIG. 1, the plasma 216 output by the remote plasma source 210 can be transmitted in the axial direction of the transmission channel 212, and under the action of the bias magnetic field or the bias electric field, the high-energy particles transmitted in the axial direction are deflected and collide with the inner side wall of the transmission channel 212, the energy and / or density of the high-energy particles are reduced, and the high-energy particles are captured. In actual application, a plurality of collision baffles can be arranged on the inner side wall of the transmission channel 212 to further consume the residual kinetic energy of the high-energy particles.

[0069] It should be noted that the preset direction refers to the direction in which the plasma 216 is transmitted in the transmission channel 212 without applying a bias field. The preset direction includes but is not limited to the axial direction of the transmission channel 212, and can also be other directions, and the present disclosure has no special limitation thereon.

[0070] In some embodiments, the step S130 described above includes: transmitting the low-energy particles 218 through the transmission channel 212 in the preset direction into the process chamber 202.

[0071] Referring to Figure 3 As shown, the low-energy particles 218 are hardly affected by the bias magnetic field or the bias electric field, continue to be transmitted in the axial direction of the transmission channel 212, and enter the process chamber 202 through the input end of the process chamber 202. The input end of the process chamber 202 can be provided at the top of the process chamber 202.

[0072] The process chamber 202 can also be equipped with a gas baffle 206, which can be located between the input end of the process chamber 202 and the wafer W. The gas baffle 206 is used to locally shield or redefine the flow field of the reaction gas or plasma entering the process chamber 202 from the input end of the process chamber 202, to weaken the direct impact of the plasma and improve the flow uniformity, so as to achieve more uniform doping in the three-dimensional structure with high aspect ratio. Figure 3 The dashed arrows in FIG. 6 show an enlarged schematic view of the uniform distribution of the low-energy particles 218 on the surface of the wafer W.

[0073] In actual applications, the depth and concentration of doping can be controlled by controlling the length of time during which the wafer W is exposed to the low-energy particles 218. For example, the length of time during which the wafer W is exposed to the radical flow after the low-energy particles 218 (e.g., radicals) enter the process chamber 202 can be controlled to be 10-120 seconds (s), thereby controlling the depth and concentration of doping. Here, the length of time during which the wafer W is exposed to the radical flow is not limited thereto, and can also be other lengths of time.

[0074] In some embodiments, the doping method described above further includes: performing an annealing process on the doped wafer W to activate the doping ions in the low-energy particles 218 that diffuse into each semiconductor layer 306.

[0075] The annealing process includes a transient heat treatment technique such as rapid thermal annealing, laser annealing, or microwave annealing. During the annealing process, the impurity ions are activated, i.e., the impurity ions are heated to a sufficient temperature so that they can change from an ionic state to an atomic state and migrate from occupying a lattice gap or defect position to replace a lattice site and form an electrically active doping center with a lattice atom, thereby increasing the free carrier concentration while repairing lattice defects, so that the semiconductor layer 306 has a desired conductivity type and controllable resistivity. The conductivity type of the semiconductor layer 306 can include P-type and / or N-type. Here, the annealing process can be performed in an inert atmosphere such as nitrogen to avoid oxidation of the surface of the semiconductor layer 306.

[0076] In some embodiments, the annealing process has a temperature range of 700°C to 1100°C. For example, the annealing process can have a temperature of 700°C, 800°C, 900°C, 950°C, 1000°C, 1050°C, 1100°C, or other values. In practical applications, the temperature of the annealing process can be reasonably selected according to process requirements, and the present disclosure is not limited in this regard.

[0077] In some embodiments, the annealing process has a time range of 5s to 120s, but is not limited thereto. For example, the annealing process can have a time of 5s, 7s, 10s, 20s, 50s, 80s, 100s, 120s, or other values. In practical applications, the time of the annealing process can be reasonably selected according to process requirements, and the present disclosure is not limited in this regard.

[0078] In some embodiments, the above-described doping method further includes, after the annealing process, performing a first surface treatment on the wafer W using a mixed gas of hydrogen and nitrogen to repair the dangling bonds on the surface of the at least one semiconductor layer 306.

[0079] The process of the first surface treatment includes: placing the wafer W in the process chamber 202; and exciting active hydrogen radicals generated by the hydrogen gas by radio frequency or microwave to diffuse along the grooves 310 and the gaps 312 to the exposed surface of each semiconductor layer 306, and react with the silicon dangling bonds remaining on the surface of each semiconductor layer 306 to generate silicon-hydrogen bonds, thereby passivating the dangling bond defects on the surface of the at least one semiconductor layer 306 in situ, reducing the interface state density and suppressing the leakage current, and providing a low-defect and high-stability interface for the subsequent deposition of the gate dielectric layer material.

[0080] In practical applications, the power of the first surface treatment and the time of the first surface treatment can be reasonably selected according to process requirements, and the present disclosure is not limited in this regard.

[0081] In some embodiments, the above-described doping method further includes, before the providing of the doping gas 214, performing a second surface treatment on the wafer W to remove the oxide on the surface of the at least one semiconductor layer 306.

[0082] The second surface treatment process includes: placing the wafer W in a pretreatment chamber; introducing a hydrogen-containing plasma (e.g., generated from NF3 / H2, NH3, or HF gas) into the pretreatment chamber; the hydrogen-containing plasma diffuses along the groove 310 and the gap 312 to the exposed surface of each semiconductor layer 306, and reacts with the oxide on the surface of the semiconductor layer 306 to remove the oxide on the surface of at least one semiconductor layer 306. In this way, a clean, oxide-free interface can be provided for subsequent doping and improve doping uniformity. Here, the gas generated by the reaction of the hydrogen-containing plasma and the oxide can be pumped out by the vacuum pump 208.

[0083] In some embodiments, the second surface treatment lasts for 10s to 30s. For example, the second surface treatment can last for 10s, 12s, 15s, 20s, 25s, 30s, or other values. In actual applications, the duration of the second surface treatment can be reasonably selected according to the thickness of the oxide, and the present disclosure does not limit this.

[0084] In some embodiments, a conformal doping region is formed in each semiconductor layer 306. It should be noted that conformality means that low-energy particles generated by a remote plasma source can be uniformly adsorbed on the surface of the semiconductor layer, and can well cover the surface of the semiconductor layer in the case of forming a high aspect ratio groove, so as to perform uniform doping. Generally, if the ratio of the depth and width of the formed groove is greater than 10, it can be considered as a high aspect ratio groove.

[0085] After the low-energy particle 218 doping and the annealing treatment, a conformal doping region with uniform thickness and concentration is formed on the entire exposed surface of each semiconductor layer 306, thereby ensuring that each semiconductor layer 306 in the multi-layer structure 304 has uniform and consistent junction characteristics, thereby providing a unified basis for the threshold voltage, on-resistance, and reliability of the subsequent three-dimensional device.

[0086] The method for doping based on a remote plasma source provided by the embodiments of the present disclosure can realize low-damage and high-uniformity doping by optimizing the plasma generation, transmission, and doping activation processes.

[0087] The method for doping based on a remote plasma source provided by the embodiments of the present disclosure can be applied to high-uniformity doping processes of advanced logic devices, memories, and new 3D structure devices.

[0088] Based on the above-mentioned doping method, the embodiments of the present disclosure further provide a semiconductor structure which can be doped by the method in any of the above-mentioned embodiments.

[0089] The methods disclosed in the several method embodiments provided by the present disclosure can be combined arbitrarily without conflict to obtain new method embodiments.

[0090] It is to be understood that the terminology "one embodiment" or "an embodiment" used throughout this specification means that a particular feature, structure or characteristic described is included in at least one embodiment of the disclosure. Therefore, appearances of the phrases "in one embodiment" or "in an embodiment" in various places throughout this specification are not necessarily referring to the same embodiment. Furthermore, the particular features, structures or characteristics can be combined in any suitable manner in one or more embodiments. It is to be understood that the sequence of the above-described processes is not meant to be limiting in terms of the order of execution, and the execution order of the processes should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the disclosure. The above-mentioned sequence of the embodiments of the disclosure is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0091] It should be noted that the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without further limitation, an element preceded by "comprises... " does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0092] The above describes only the embodiments of the disclosure, but the protection scope of the disclosure is not limited thereto, and any skilled person in the art can easily think of changes or replacements within the technical range disclosed by the disclosure, which should be covered by the protection scope of the disclosure.

Claims

1. A method of doping based on a remote plasma source, characterized in that, The method comprises the following steps: placing a wafer on a susceptor in a process chamber; wherein the wafer comprises a stack structure and a groove penetrating through the stack structure; the groove exposes a plurality of semiconductor layers in the stack structure, and a gap is formed between two adjacent semiconductor layers and communicates with the groove; providing a doping gas to an input end of a remote plasma source to generate a plasma; wherein an output end of the remote plasma source is connected to the process chamber, and the plasma comprises high-energy particles in a high-energy state and low-energy particles in a low-energy state; filtering out the high-energy particles in the plasma and providing the low-energy particles to the process chamber to perform a doping treatment on the plurality of semiconductor layers exposed by the groove and the gap; the filtering out of the high-energy particles in the plasma and the providing of the low-energy particles to the process chamber comprises: providing a bias magnetic field or a bias electric field to a transmission channel to filter out the high-energy particles from the plasma; wherein the transmission channel is connected to the output end of the remote plasma source and the process chamber respectively; the providing of the bias magnetic field or the bias electric field to the transmission channel to filter out the high-energy particles from the plasma comprises: under the action of the bias magnetic field or the bias electric field, the transmission direction of the high-energy particles transmitted in a preset direction is changed and collides with the inner side wall of the transmission channel, so that the energy and / or density of the high-energy particles are reduced.

2. The method of claim 1, wherein, the filtering out of the high-energy particles in the plasma and the providing of the low-energy particles to the process chamber comprises: the low-energy particles transmitted through the transmission channel are transmitted to the process chamber in the preset direction.

3. The doping method according to claim 1 or 2, characterized in that, a conformal doping region is formed in each of the semiconductor layers.

4. The method of claim 1 or 2, wherein the doping method further comprises: performing an annealing treatment on the doped wafer to activate the doping ions in the low-energy particles diffused into each of the semiconductor layers.

5. The doping method according to claim 4, characterized in that, the doping method further comprises: after the annealing treatment, performing a first surface treatment on the wafer by using a mixed gas of hydrogen and nitrogen to repair the dangling bonds on the surface of at least one of the semiconductor layers.

6. The doping method according to claim 4, characterized in that, the temperature range of the annealing treatment is 700-1100℃, and the time range of the annealing treatment is 5-120s.

7. The doping method according to claim 1, characterized in that, the doping method further comprises: before the providing of the doping gas, performing a second surface treatment on the wafer to remove the oxide on the surface of at least one of the semiconductor layers.

8. The doping method according to claim 1, characterized in that, the ratio of the depth to the width of the groove is greater than 10.

9. The doping method according to claim 1, characterized in that, the doping ions are uniformly distributed in each of the semiconductor layers.

10. The method of claim 1, wherein, the high-energy particles comprise at least one of positive ions, negative ions and electrons; and the low-energy particles comprise free radicals.

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