A clock calibration system and method

Abstract

This application provides a clock calibration system and method. The output of the phase-locked loop is connected to the input of a plurality of second multiplexing modules; the output of the first multiplexing module is connected to the input of the calibration module; the output of the calibration module is connected to the input of a resistor-capacitor oscillator; the output of the resistor-capacitor oscillator is connected to the input of the calibration module and the input of the plurality of second multiplexing modules; the output of each second multiplexing module is connected to one module; the calibration module is used to receive a clock signal of the first frequency and / or a clock signal of the second frequency as a reference clock signal through the first multiplexing module to perform clock calibration on the resistor-capacitor oscillator. It is evident that the solution of this application embodiment can reduce system power consumption.

Description

Technical Field

[0001] This application relates to the field of clock technology, and in particular to a clock calibration system and method. Background Technology

[0002] As a core component of embedded systems, if the clock frequency deviation is too large, various functions that depend on the clock communication module will not function properly.

[0003] The SOC clock typically comes from an external oscillator (such as 26MHz / 32KHz); for example, an external 26MHz oscillator outputs 26MHz to the SOC, and then the SOC uses a phase-locked loop to upscale the frequency to provide a higher frequency for use by various modules in the system; alternatively, an external 32KHz oscillator outputs 32KHz to the SOC, and then the SOC provides the clock for timing in sleep scenarios;

[0004] In sleep mode, to reduce power consumption, the external 26MHz oscillator is usually turned off. However, the 32KHz frequency is too low to meet the frequency requirements of some modules that need to work in sleep mode. To address this, the SOC adds an internal resistor-capacitor oscillator that can be used in sleep mode. However, the clock generated by the internal resistor-capacitor oscillator has relatively poor accuracy and is prone to excessive frequency deviation. Some modules have requirements for clock accuracy, and excessive frequency deviation will prevent them from operating normally. Summary of the Invention

[0005] The purpose of this application is to provide a clock calibration system and method to reduce system power consumption. The specific technical solution is as follows:

[0006] A first aspect of this application provides a clock calibration system, the system comprising: an oscillator of a first frequency, an oscillator of a second frequency, a clock management module, a phase-locked loop, a resistor-capacitor oscillator, a calibration module, a first multiplexing module, and a plurality of second multiplexing modules; wherein the frequency of the second frequency oscillator is greater than the frequency of the first frequency oscillator;

[0007] The oscillator at the first frequency and the oscillator at the second frequency are respectively connected to the clock management module; the clock management module is used to output a clock signal at the first frequency through a first output terminal and a clock signal at the second frequency through a second output terminal; the first output terminal is connected to the input terminal of the first multiplexing module, and the output terminal of the first multiplexing module is connected to the input terminals of the plurality of second multiplexing modules; the second output terminal is connected to the input terminal of the first multiplexing module, the input terminal of the phase-locked loop, and the input terminals of the plurality of second multiplexing modules; the output terminal of the phase-locked loop is connected to the input terminals of the plurality of second multiplexing modules; the output terminal of the first multiplexing module is connected to the input terminal of the calibration module; the output terminal of the calibration module is connected to the input terminal of the resistor-capacitor oscillator; the output terminal of the resistor-capacitor oscillator is connected to the input terminal of the calibration module and the input terminals of the plurality of second multiplexing modules; the output terminal of each second multiplexing module is connected to one module;

[0008] The resistor-capacitor oscillator is used to output a clock signal of a third frequency to the input of the calibration module and the input of the plurality of second multiplexing modules through the output terminal;

[0009] The calibration module is configured to receive a clock signal of the first frequency and / or a clock signal of the second frequency as a reference clock for the calibration module through the first multiplexing module; calibrate the clock signal of the third frequency output by the resistor-capacitor oscillator; and output calibration parameter values ​​to the resistor-capacitor oscillator through the output terminal of the calibration module, so that the resistor-capacitor oscillator calibrates and outputs the clock signal of the third frequency according to the calibration parameter values.

[0010] In one possible implementation, the oscillator at the second frequency is turned off during system sleep mode;

[0011] Each of the second multiplexing modules is configured to, in system sleep mode, receive a first frequency clock signal output from the output terminal of the first frequency oscillator and / or a third frequency clock signal output from the output terminal of the resistor-capacitor oscillator; and send the first frequency clock signal and / or the third frequency clock signal to the module connected to the current second multiplexing module.

[0012] In one possible implementation, each of the second multiplexing modules is configured to, in an operational state, receive one or more of the following clock signals: a first frequency clock signal sent by the first frequency oscillator, a second frequency clock signal sent by the second frequency oscillator, a third frequency clock signal sent by the resistor-capacitor oscillator, and a fourth frequency clock signal sent by the phase-locked loop, and to send the four frequency clock signals to a module connected to the current second multiplexing module.

[0013] In one possible implementation, the calibration module is configured to receive a second-frequency clock signal from the second-frequency oscillator and a third-frequency clock signal from the resistor-capacitor oscillator when the system is powered on or in operation; calibrate the third-frequency clock signal from the resistor-capacitor oscillator using the second-frequency clock signal from the second-frequency oscillator as a reference clock; and output calibration parameter values ​​to the resistor-capacitor oscillator via its output terminal, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the third-frequency clock signal.

[0014] In system sleep mode, the system receives a first-frequency clock signal from the first-frequency oscillator and a third-frequency clock signal from the resistor-capacitor oscillator; using the first-frequency clock signal from the first-frequency oscillator as a reference clock, the system calibrates the third-frequency clock signal from the resistor-capacitor oscillator; the calibration module outputs calibration parameter values ​​to the resistor-capacitor oscillator through its output terminal, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the third-frequency clock signal.

[0015] A second aspect of this application provides a clock calibration method applied to a clock calibration system. The system includes: an oscillator of a first frequency, an oscillator of a second frequency, a clock management module, a phase-locked loop (PLL), a resistor-capacitor oscillator, a calibration module, a first multiplexing module, and multiple second multiplexing modules. The frequency of the second-frequency oscillator is greater than the frequency of the first-frequency oscillator. The first-frequency oscillator and the second-frequency oscillator are respectively connected to the clock management module. A clock supply chip is used to output a clock signal of the first frequency through a first output terminal and a clock signal of the second frequency through a second output terminal. The first output terminal is connected to the input terminal of the first multiplexing module. The output terminal of the first multiplexing module is connected to the input terminals of the plurality of second multiplexing modules; the second output terminal is connected to the input terminal of the first multiplexing module, the input terminal of the phase-locked loop, and the input terminals of the plurality of second multiplexing modules respectively; the output terminal of the phase-locked loop is connected to the input terminals of the plurality of second multiplexing modules; the output terminal of the first multiplexing module is connected to the input terminal of the calibration module; the output terminal of the calibration module is connected to the input terminal of the resistor-capacitor oscillator; the output terminal of the resistor-capacitor oscillator is connected to the input terminal of the calibration module and the input terminals of the plurality of second multiplexing modules; the output terminal of each second multiplexing module is connected to a processor; the method includes:

[0016] The resistor-capacitor oscillator outputs a clock signal of the third frequency to the input of the calibration module and the input of the plurality of second multiplexing modules through the output terminal.

[0017] The calibration module uses the first multiplexing module to receive a clock signal of the first frequency and / or a clock signal of the second frequency as a reference clock for the calibration module; it calibrates the clock signal of the third frequency input to the resistor-capacitor oscillator; and it outputs calibration parameter values ​​to the resistor-capacitor oscillator through the output terminal, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the clock signal of the third frequency.

[0018] In one possible implementation, the method further includes:

[0019] The oscillator at the second frequency is turned off when the system is in sleep mode;

[0020] Each of the second multiplexing modules receives a first-frequency clock signal output from the oscillator output terminal and / or a third-frequency clock signal output from the resistor-capacitor oscillator output terminal in the system sleep state; and sends the first-frequency clock signal and / or the third-frequency clock signal to the module connected to the current second multiplexing module.

[0021] In one possible implementation, the method further includes:

[0022] When each of the second multiplexing modules is in operation, it receives one or more of the following clock signals: a first frequency clock signal sent by the first frequency oscillator, a second frequency clock signal sent by the second frequency oscillator, a third frequency clock signal sent by the resistor-capacitor oscillator, and a fourth frequency clock signal sent by the phase-locked loop. It then sends these four clock signals to the module connected to the current second multiplexing module.

[0023] In one possible implementation, the method further includes:

[0024] The calibration module receives a second-frequency clock signal from the second-frequency oscillator and a third-frequency clock signal from the resistor-capacitor oscillator when the system is powered on or in operation. It uses the second-frequency clock signal from the second-frequency oscillator as a reference clock to calibrate the third-frequency clock signal from the resistor-capacitor oscillator. The calibration module outputs calibration parameter values ​​to the resistor-capacitor oscillator, enabling the oscillator to calibrate according to the calibration parameter values ​​and output the third-frequency clock signal.

[0025] In sleep mode, the system receives a first-frequency clock signal from the first-frequency oscillator and a third-frequency clock signal from the resistor-capacitor oscillator; using the first-frequency clock signal from the first-frequency oscillator as a reference clock, the system calibrates the third-frequency clock signal from the resistor-capacitor oscillator; the calibration module outputs calibration parameter values ​​to the resistor-capacitor oscillator, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the third-frequency clock signal.

[0026] Another aspect of the embodiments of this application also provides an electronic device, including:

[0027] Memory, used to store computer programs;

[0028] The processor, when executing a program stored in memory, implements any of the above clock calibration methods.

[0029] In another aspect of the embodiments of this application, a computer-readable storage medium is provided, wherein a computer program is stored therein, and the computer program, when executed by a processor, implements any of the above-described clock calibration methods.

[0030] In another aspect of the embodiments of this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform any of the clock calibration methods described above.

[0031] Beneficial effects of the embodiments in this application:

[0032] This application provides a clock calibration system and method. The system includes: a first-frequency oscillator, a second-frequency oscillator, a clock management module, a phase-locked loop (PLL), a resistor-capacitor oscillator, a calibration module, a first multiplexing module, and multiple second multiplexing modules. The frequency of the second-frequency timer is greater than the frequency of the first-frequency timer. The first-frequency timer and the second-frequency timer are respectively connected to a clock supply chip. The clock supply chip is used to output a clock signal of the first frequency through a first output terminal and a clock signal of the second frequency through a second output terminal. The first output terminal is connected to the input terminal of the first multiplexing module, and the output terminal of the first multiplexing module is connected to the input terminals of the multiple second multiplexing modules. The second output terminal is connected to the input terminal of the first multiplexing module, the input terminal of the PLL, and the input terminals of the multiple second multiplexing modules. The output terminal of the PLL is connected to the input terminals of the multiple second multiplexing modules. The input terminal of the multiplexing module is connected; the output terminal of the first multiplexing module is connected to the input terminal of the calibration module; the output terminal of the calibration module is connected to the input terminal of the resistor-capacitor oscillator; the output terminal of the resistor-capacitor oscillator is connected to the input terminal of the calibration module and the input terminals of the plurality of second multiplexing modules; the output terminal of each second multiplexing module is connected to a processor; the resistor-capacitor oscillator is used to output a clock signal of a third frequency to the input terminal of the calibration module and the input terminals of the plurality of second multiplexing modules through its output terminal; the calibration module receives the clock signal of the first frequency and / or the clock signal of the second frequency through the first multiplexing module as a reference clock for the calibration module; calibrates the clock signal of the third frequency output by the resistor-capacitor oscillator; the output terminal of the calibration module outputs calibration parameter values ​​to the resistor-capacitor oscillator; so that the frequency deviation of the clock signal of the third frequency output by the resistor-capacitor oscillator meets the requirements. As can be seen, the solution of this application embodiment can transmit clock signals using an oscillator of a first frequency, an oscillator of a second frequency, and a resistor-capacitor oscillator. In the working mode, the clock signal can be transmitted using the oscillator of the first frequency and / or the oscillator of the second frequency and / or the resistor-capacitor oscillator. In the energy-saving mode, the usage signal is transmitted using the oscillator of the first frequency and / or the resistor-capacitor oscillator, thereby solving the problem of high oscillator power consumption.

[0033] Of course, implementing any product or method of this application does not necessarily require achieving all of the advantages described above at the same time. Attached Figure Description

[0034] To more clearly illustrate the technical solutions in the embodiments of this application or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other embodiments can be obtained based on these drawings.

[0035] Figure 1 A schematic diagram of a clock calibration system provided in an embodiment of this application;

[0036] Figure 2 A schematic diagram of the clock calibration process provided in an embodiment of this application;

[0037] Figure 3 A schematic flowchart of a clock calibration method provided in an embodiment of this application;

[0038] Figure 4 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0039] The technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. Based on the embodiments of this application, all other embodiments obtained by those skilled in the art based on this application are within the scope of protection of this application.

[0040] A first aspect of the embodiments of this application provides a clock calibration system, see [link to previous document]. Figure 1 The system includes: an oscillator 101 with a first frequency, an oscillator 102 with a second frequency, a clock management module 103, a phase-locked loop 104, a resistor-capacitor oscillator 105, a calibration module 106, a first multiplexing module 107, and multiple second multiplexing modules 108; the frequency of the second frequency oscillator 102 is greater than the frequency of the first frequency oscillator 101.

[0041] The oscillator 101 at the first frequency and the oscillator 102 at the second frequency are respectively connected to the clock management module 103; the clock management module 103 is used to output a clock signal at the first frequency through a first output terminal and a clock signal at the second frequency through a second output terminal; the first output terminal is connected to the input terminal of the first multiplexing module 107, and the output terminal of the first multiplexing module is connected to the input terminals of the plurality of second multiplexing modules 108; the second output terminal is connected to the input terminal 107 of the first multiplexing module and the input terminal of the phase-locked loop 104. The output terminal of the first multiplexing module 107 is connected to the input terminal of the multiple second multiplexing modules 108; the output terminal of the calibration module 106 is connected to the input terminal of the resistor-capacitor oscillator 105; the output terminal of the resistor-capacitor oscillator 105 is connected to the input terminal of the calibration module 106 and the input terminals of the multiple second multiplexing modules 108; the output terminal of each second multiplexing module 108 is connected to a processor.

[0042] The resistor-capacitor oscillator 105 is used to output a clock signal of a third frequency to the input terminal of the calibration module and the input terminal of the plurality of second multiplexing modules through the output terminal.

[0043] The calibration module 106 is configured to receive a clock signal of the first frequency and / or a clock signal of the second frequency as a reference clock for the calibration module through the first multiplexing module; calibrate the clock signal of the third frequency output by the resistor-capacitor oscillator; and output calibration parameter values ​​to the resistor-capacitor oscillator through the output terminal of the calibration module, so that the resistor-capacitor oscillator calibrates and outputs the clock signal of the third frequency according to the calibration parameter values.

[0044] In this embodiment, the frequency of the second-frequency oscillator is greater than the frequency of the first-frequency oscillator, and can be greater than an order of magnitude of a frequency, such as Hz, kHz, or MHz. Therefore, when the frequency of the first-frequency oscillator is in the Hz range, the frequency of the second-frequency oscillator is in the kHz range; and when the frequency of the first-frequency oscillator is in the kHz range, the frequency of the second-frequency oscillator is in the MHz range. Both the first-frequency and second-frequency oscillators are used to transmit clock signals. Both can operate in the working or startup state, while the second-frequency oscillator is turned off in the sleep or low-power state to reduce power consumption. The time management module can receive the signals transmitted by the first-frequency and second-frequency oscillators and transmit the first-frequency clock signal and the second-frequency clock signal. A phase-locked loop (PLL) is a negative feedback control system that uses voltage generated by phase synchronization to tune a voltage-controlled oscillator to generate a target frequency. Based on the principles of automatic control, a feedback control circuit can use an externally input reference signal to control the frequency and phase of the oscillation signal within the control loop, thereby achieving automatic tracking of the output signal frequency to the input signal frequency. This allows the second-frequency clock signal to be converted into a higher-frequency output. A resistor-capacitor oscillator, as an energy conversion device, can convert DC power into AC power with a certain frequency; the circuit it forms is called an oscillation circuit. The resistor-capacitor oscillator outputs a third-frequency clock signal to the input of the calibration module and the input of the multiple second multiplexing modules. The calibration module receives the first-frequency clock signal and / or the second-frequency clock signal as its reference clock through the first multiplexing module; it calibrates the third-frequency clock signal input to the resistor-capacitor oscillator; and it outputs calibration parameter values ​​to the resistor-capacitor oscillator, ensuring that the frequency deviation of the third-frequency clock signal output by the resistor-capacitor oscillator meets the requirements. In this embodiment, the first multiplexing module receives two signals, while the second multiplexing module receives four signals. In one example, the first frequency is 32kHz and the second frequency is 26MHz. The 26MHz and 32KMHz sources in the SOC are generated by external crystal oscillators. The 26MHz clock entering the SOC is multiplied to generate a high-frequency clock PLL (phase-locked loop). The PLL (or further divided) then provides the clock to various modules within the processors. The RCO (Resistor-Capacitor Oscillator) calibration module uses both 32KMHz and 26MHz reference clocks. After calibration, it outputs an RCO clock, which is then provided to the modules in the coprocessor. Modules in the coprocessor can use either the PLL or the 26MHz clock source during power-on or operating mode. The PLL / 26MHz clocks themselves are highly accurate and do not require calibration after power-on.In sleep mode, since 26M is turned off, PLL / 26M has no clock and needs to be switched to the RCO clock source.

[0045] As can be seen, the solution of this application embodiment can transmit clock signals using an oscillator of a first frequency, an oscillator of a second frequency, and a resistor-capacitor oscillator. Thus, in the working mode, clock signals can be transmitted using the oscillator of the first frequency, the resistor-capacitor oscillator, and the second frequency oscillator. In the energy-saving mode, by turning off the high-power second frequency oscillator, the first frequency oscillator and / or the resistor-capacitor oscillator are used to transmit usage signals. Since the power consumption of the first frequency oscillator and the resistor-capacitor oscillator is relatively low, energy consumption can be saved, achieving low power consumption.

[0046] In one possible implementation, the oscillator at the second frequency is turned off during system sleep mode;

[0047] Each of the second multiplexing modules is configured to, in a system sleep state, receive a first-frequency clock signal output from the output terminal of the first-frequency oscillator and / or a third-frequency clock signal output from the output terminal of the resistor-capacitor oscillator; and send the first-frequency clock signal and / or the third-frequency clock signal to a module connected to the current second multiplexing module. In one possible implementation, each of the second multiplexing modules is configured to, in an operating state, receive one or more of the following: a first-frequency clock signal from the first-frequency oscillator, a second-frequency clock signal from the second-frequency oscillator, a third-frequency clock signal from the resistor-capacitor oscillator, and a fourth-frequency clock signal from the phase-locked loop; and send the four clock signals to a module connected to the current second multiplexing module.

[0048] The system in this embodiment can be part of a host device, and the aforementioned sleep state and working state refer to the host's state. In sleep state, the second frequency oscillator is turned off, and the clock signal is transmitted through the first frequency oscillator and the resistor-capacitor oscillator. Since the first frequency oscillator and the resistor-capacitor oscillator have low power consumption, energy consumption can be saved, achieving low power consumption. In working state, the clock signal can be transmitted through the first frequency oscillator, the resistor-capacitor oscillator, and the second frequency oscillator. The clock signal transmitted by the second frequency oscillator can also pass through a phase-locked loop, so that the first multiplexing module can receive four signals for clock signal transmission. Since the second frequency clock signal has a high frequency and high accuracy, the accuracy of the clock signal can be guaranteed.

[0049] In one possible implementation, the calibration module is configured to receive a second-frequency clock signal from the second-frequency oscillator and a third-frequency clock signal from the resistor-capacitor oscillator when the system is powered on or in operation; calibrate the third-frequency clock signal from the resistor-capacitor oscillator using the second-frequency clock signal from the second-frequency oscillator as a reference clock; and output calibration parameter values ​​to the resistor-capacitor oscillator via its output terminal, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the third-frequency clock signal.

[0050] In system sleep mode, the system receives a first-frequency clock signal from the first-frequency oscillator and a third-frequency clock signal from the resistor-capacitor oscillator; using the first-frequency clock signal from the first-frequency oscillator as a reference clock, the system calibrates the third-frequency clock signal from the resistor-capacitor oscillator; the calibration module outputs calibration parameter values ​​to the resistor-capacitor oscillator through its output terminal, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the third-frequency clock signal.

[0051] In practical use, when calibrating the resistor-capacitor oscillator, the second frequency clock signal can be used as a reference to ensure the accuracy and speed of calibration during the working state, power-on state, and startup state. In the low power consumption state or sleep state, calibration can be performed using the first frequency oscillator. At this time, the second frequency oscillator can be turned off to ensure reduced power consumption.

[0052] To illustrate the method of the embodiments of this application, the following description is based on a specific example. (See attached image.) Figure 2 ,include:

[0053] 1. Power on the terminal;

[0054] 2. During the power-on process, a quick RCO calibration initialization configuration is performed, using 26MHz as the reference clock for rapid calibration. The calibration method, such as the binary search method, is used, calibrating N times to achieve coarse calibration. This 26MHz quick calibration only takes up a few milliseconds of startup time. Without RCO calibration at startup, the frequency deviation can reach 30%-50%; through this quick calibration, the frequency deviation can be reduced to within 1%. If the module does not have an excessively large frequency deviation in sleep mode, it can still function normally. However, the RCO will experience frequency deviation due to factors such as usage time and temperature changes, so even after startup calibration, the accuracy requirements cannot always be met.

[0055] 3. When the SOC is about to enter a low-power state, the system will generate an interrupt;

[0056] 4. After receiving the interrupt, the coprocessor performs calibration initialization configuration for RCO using a 32K reference clock; such as configuring the frequency offset gate threshold, calibration step value, etc.

[0057] 5. Initiate 32kHz automatic calibration. When the frequency deviation exceeds the frequency deviation threshold, RCO calibration will be performed automatically. Since a 26MHz fast calibration has already been performed upon startup, and the deviation is relatively small, step value calibration or binary search calibration can be used here. This will reduce the number of calibrations, making the 32kHz calibration faster and more accurate. The reason why 26MHz calibration cannot be used in sleep mode is that the external crystal oscillator for 26MHz is turned off in sleep mode, and RCO cannot be calibrated using 26MHz at this time.

[0058] 6. SoC exits low power mode;

[0059] 7. Wait until the next hibernation / wake-up;

[0060] As can be seen, the method in this application solves the problem of: excessive RCO clock frequency offset in low-power sleep mode, causing modules on the low-power coprocessor to malfunction; using a 32K clock to calibrate the RCO in low-power sleep mode, but because 32K calibration is relatively slow, it leads to excessive time spent on RCO calibration during the boot process. Furthermore, because the fast calibration during boot provides coarse calibration, the speed and accuracy of the corresponding 32K calibration during sleep mode are also faster and higher.

[0061] A second aspect of this application provides a clock calibration method applied to a clock calibration system. The system includes: an oscillator of a first frequency, an oscillator of a second frequency, a clock management module, a phase-locked loop, a resistor-capacitor oscillator, a calibration module, a first multiplexing module, and multiple second multiplexing modules. The frequency of the second-frequency oscillator is greater than the frequency of the first-frequency oscillator. The first-frequency oscillator and the second-frequency oscillator are respectively connected to the clock management module. A clock supply chip is used to output a clock signal of the first frequency through a first output terminal and a clock signal of the second frequency through a second output terminal. The first output terminal is respectively connected to the input terminal of the first multiplexing module. The first multiplexing module's output is connected to the inputs of the plurality of second multiplexing modules; the second output is connected to the inputs of the first multiplexing module, the phase-locked loop (PLL), and the plurality of second multiplexing modules; the PLL's output is connected to the inputs of the plurality of second multiplexing modules; the first multiplexing module's output is connected to the input of the calibration module; the calibration module's output is connected to the input of the resistor-capacitor oscillator; the resistor-capacitor oscillator's output is connected to the input of the calibration module and the plurality of second multiplexing modules; each second multiplexing module's output is connected to a processor; see also... Figure 3 The method includes:

[0062] Step S31: The resistor-capacitor oscillator outputs a clock signal of the third frequency to the input of the calibration module and the input of the plurality of second multiplexing modules through the output terminal.

[0063] Step S31: The calibration module uses the first multiplexing module to receive the clock signal of the first frequency and / or the clock signal of the second frequency as the reference clock of the calibration module; calibrates the clock signal of the third frequency input to the resistor-capacitor oscillator; and outputs calibration parameter values ​​to the resistor-capacitor oscillator through the output terminal, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the clock signal of the third frequency.

[0064] In one possible implementation, the method further includes:

[0065] The oscillator at the second frequency is turned off when the system is in sleep mode;

[0066] Each of the second multiplexing modules receives a first-frequency clock signal output from the oscillator output terminal and / or a third-frequency clock signal output from the resistor-capacitor oscillator output terminal in the system sleep state; and sends the first-frequency clock signal and / or the third-frequency clock signal to the module connected to the current second multiplexing module.

[0067] In one possible implementation, the method further includes:

[0068] When each of the second multiplexing modules is in operation, it receives one or more of the following clock signals: a first frequency clock signal sent by the first frequency oscillator, a second frequency clock signal sent by the second frequency oscillator, a third frequency clock signal sent by the resistor-capacitor oscillator, and a fourth frequency clock signal sent by the phase-locked loop. It then sends these four clock signals to the module connected to the current second multiplexing module.

[0069] In one possible implementation, the method further includes:

[0070] The calibration module receives a second-frequency clock signal from the second-frequency oscillator and a third-frequency clock signal from the resistor-capacitor oscillator when the system is powered on or in operation. Using the second-frequency clock signal as a reference clock, the third-frequency clock signal from the resistor-capacitor oscillator is calibrated. The calibration module outputs calibration parameter values ​​to the resistor-capacitor oscillator, enabling it to calibrate and output the third-frequency clock signal according to the calibration parameter values. In sleep mode, the module receives a first-frequency clock signal from the first-frequency oscillator and a third-frequency clock signal from the resistor-capacitor oscillator. Using the first-frequency clock signal as a reference clock, the third-frequency clock signal from the resistor-capacitor oscillator is calibrated. The calibration module outputs calibration parameter values ​​to the resistor-capacitor oscillator, enabling it to calibrate and output the third-frequency clock signal according to the calibration parameter values. As can be seen, the solution of this application embodiment can transmit clock signals using an oscillator of a first frequency, an oscillator of a second frequency, and a resistor-capacitor oscillator. Thus, in the working mode, clock signals can be transmitted using the oscillator of the first frequency, the resistor-capacitor oscillator, and the second frequency oscillator. In the energy-saving mode, by turning off the high-power second frequency oscillator, the first frequency oscillator and / or the resistor-capacitor oscillator are used to transmit usage signals. Since the power consumption of the first frequency oscillator and the resistor-capacitor oscillator is relatively low, energy consumption can be saved, achieving low power consumption.

[0071] This application also provides an electronic device, such as... Figure 4 As shown, it includes:

[0072] Memory 401 is used to store computer programs;

[0073] When processor 402 executes the program stored in memory 401, it performs the following steps:

[0074] The resistor-capacitor oscillator outputs a clock signal of the third frequency to the input of the calibration module and the input of the plurality of second multiplexing modules through the output terminal.

[0075] The calibration module utilizes the first multiplexing module to receive a clock signal of the first frequency and / or a clock signal of the second frequency as a reference clock for the calibration module; it calibrates the clock signal of the third frequency input to the resistor-capacitor oscillator; and it outputs calibration parameter values ​​to the resistor-capacitor oscillator through the output terminal, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the clock signal of the third frequency.

[0076] The communication bus mentioned in the above electronic devices can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. This communication bus can be divided into address bus, data bus, control bus, etc. For ease of illustration, only one thick line is used to represent it in the diagram, but this does not mean that there is only one bus or one type of bus.

[0077] The communication interface is used for communication between the aforementioned electronic devices and other devices.

[0078] The memory may include random access memory (RAM) or non-volatile memory (NVM), such as at least one disk storage device. Optionally, the memory may also be at least one storage device located remotely from the aforementioned processor.

[0079] The processors mentioned above can be general-purpose processors, including central processing units (CPUs), network processors (NPs), etc.; they can also be digital signal processors (DSPs), application-specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs), or other programmable logic devices, discrete gate or transistor logic devices, or discrete hardware components.

[0080] In another embodiment provided in this application, a computer-readable storage medium is also provided, which stores a computer program that, when executed by a processor, implements the steps of any of the clock calibration methods described above.

[0081] In another embodiment provided in this application, a computer program product containing instructions is also provided, which, when run on a computer, causes the computer to perform any of the clock calibration methods described above.

[0082] In the above embodiments, implementation can be achieved entirely or partially through software, hardware, firmware, or any combination thereof. When implemented using software, it can be implemented entirely or partially in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, all or part of the processes or functions described in the embodiments of this application are generated. The computer can be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions can be stored in a computer-readable storage medium or transmitted from one computer-readable storage medium to another. For example, the computer instructions can be transmitted from one website, computer, server, or data center to another website, computer, server, or data center via wired (e.g., coaxial cable, fiber optic, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) means. The computer-readable storage medium can be any available medium that a computer can access or a data storage device such as a server or data center that integrates one or more available media. The available medium can be a magnetic medium (e.g., floppy disk, hard disk, magnetic tape), an optical medium (e.g., DVD), or a solid-state drive (SSD), etc.

[0083] It should be noted that, in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or apparatus. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or apparatus that includes said element.

[0084] The various embodiments in this specification are described in a related manner. Similar or identical parts between embodiments can be referred to mutually. Each embodiment focuses on describing the differences from other embodiments. In particular, the system, electronic device, and storage medium embodiments are basically similar to the method embodiments, so the descriptions are relatively simple; relevant parts can be referred to the descriptions of the method embodiments.

[0085] The above description is merely a preferred embodiment of this application and is not intended to limit the scope of protection of this application. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of this application are included within the scope of protection of this application.

Claims

1. A clock calibration system, characterized in that, The system includes: an oscillator of a first frequency, an oscillator of a second frequency, a clock management module, a phase-locked loop, a resistor-capacitor oscillator, a calibration module, a first multiplexing module, and multiple second multiplexing modules; the frequency of the second frequency oscillator is greater than the frequency of the first frequency oscillator. The oscillator at the first frequency and the oscillator at the second frequency are respectively connected to the clock management module; the clock management module is used to output a clock signal at the first frequency through a first output terminal and a clock signal at the second frequency through a second output terminal; the first output terminal is connected to the input terminal of the first multiplexing module, and the output terminal of the first multiplexing module is connected to the input terminals of the plurality of second multiplexing modules; the second output terminal is connected to the input terminal of the first multiplexing module, the input terminal of the phase-locked loop, and the input terminals of the plurality of second multiplexing modules; the output terminal of the phase-locked loop is connected to the input terminals of the plurality of second multiplexing modules; the output terminal of the first multiplexing module is connected to the input terminal of the calibration module; the output terminal of the calibration module is connected to the input terminal of the resistor-capacitor oscillator; the output terminal of the resistor-capacitor oscillator is connected to the input terminal of the calibration module and the input terminals of the plurality of second multiplexing modules; the output terminal of each second multiplexing module is connected to one module; The oscillator at the second frequency is turned off in system sleep mode; Each of the second multiplexing modules is used to receive, in system sleep mode, a first frequency clock signal output from the output terminal of the first frequency oscillator and / or a third frequency clock signal output from the output terminal of the resistor-capacitor oscillator; and to send the first frequency clock signal and / or the third frequency clock signal to the module connected to the current second multiplexing module. The resistor-capacitor oscillator is used to output a clock signal of a third frequency to the input of the calibration module and the input of the plurality of second multiplexing modules through the output terminal; The calibration module is configured to receive a clock signal of the first frequency and / or a clock signal of the second frequency as a reference clock for the calibration module through the first multiplexing module; calibrate the clock signal of the third frequency output by the resistor-capacitor oscillator; and output calibration parameter values ​​to the resistor-capacitor oscillator through the output terminal of the calibration module, so that the resistor-capacitor oscillator calibrates and outputs the clock signal of the third frequency according to the calibration parameter values.

2. The system according to claim 1, characterized in that, Each of the second multiplexing modules is configured to, in the working state, receive one or more of the following clock signals: a first frequency clock signal sent by the first frequency oscillator, a second frequency clock signal sent by the second frequency oscillator, a third frequency clock signal sent by the resistor-capacitor oscillator, and a fourth frequency clock signal sent by the phase-locked loop, and send the four frequency clock signals to the module connected to the current second multiplexing module.

3. The system according to claim 1, characterized in that, The calibration module is used to receive a second-frequency clock signal sent by the second-frequency oscillator and a third-frequency clock signal sent by the resistor-capacitor oscillator when the system is powered on or in operation; and to calibrate the third-frequency clock signal sent by the resistor-capacitor oscillator using the second-frequency clock signal sent by the second-frequency oscillator as a reference clock. The calibration module outputs calibration parameter values ​​to the resistor-capacitor oscillator through its output terminal, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the clock signal of the third frequency. In system sleep mode, the system receives a first frequency clock signal sent by the first frequency oscillator and a third frequency clock signal sent by the resistor-capacitor oscillator; and calibrates the third frequency clock signal sent by the resistor-capacitor oscillator using the first frequency clock signal sent by the first frequency oscillator as a reference clock. The calibration module outputs calibration parameter values ​​to the resistor-capacitor oscillator through its output terminal, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the clock signal of the third frequency.

4. A clock calibration method, characterized in that, This invention relates to a clock calibration system, comprising: an oscillator at a first frequency, an oscillator at a second frequency, a clock management module, a phase-locked loop (PLL), a resistor-capacitor oscillator, a calibration module, a first multiplexing module, and multiple second multiplexing modules. The frequency of the second-frequency oscillator is higher than the frequency of the first-frequency oscillator. The first-frequency oscillator and the second-frequency oscillator are respectively connected to the clock management module. A clock supply chip is used to output a clock signal at the first frequency through a first output terminal and a clock signal at the second frequency through a second output terminal. The first output terminal is connected to the input terminal of the first multiplexing module, and the output of the first multiplexing module... The first output terminal is connected to the input terminals of the plurality of second multiplexing modules; the second output terminal is connected to the input terminals of the first multiplexing module, the input terminal of the phase-locked loop, and the input terminals of the plurality of second multiplexing modules respectively; the output terminal of the phase-locked loop is connected to the input terminals of the plurality of second multiplexing modules; the output terminal of the first multiplexing module is connected to the input terminal of the calibration module; the output terminal of the calibration module is connected to the input terminal of the resistor-capacitor oscillator; the output terminal of the resistor-capacitor oscillator is connected to the input terminal of the calibration module and the input terminals of the plurality of second multiplexing modules; the output terminal of each second multiplexing module is connected to a processor; the method includes: The resistor-capacitor oscillator outputs a third-frequency clock signal to the input of the calibration module and the input of the plurality of second multiplexing modules; the second-frequency oscillator is turned off in the system sleep state; each of the second multiplexing modules receives the first-frequency clock signal output from the first-frequency oscillator and / or the third-frequency clock signal output from the resistor-capacitor oscillator in the system sleep state; and sends the first-frequency clock signal and / or the third-frequency clock signal to the modules connected to the current second multiplexing module. The calibration module uses the first multiplexing module to receive a clock signal of the first frequency and / or a clock signal of the second frequency as a reference clock for the calibration module; it calibrates the clock signal of the third frequency input to the resistor-capacitor oscillator; and it outputs calibration parameter values ​​to the resistor-capacitor oscillator through the output terminal, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the clock signal of the third frequency.

5. The method according to claim 4, characterized in that, The method further includes: When each of the second multiplexing modules is in operation, it receives one or more of the following clock signals: a first frequency clock signal from the first frequency oscillator, a second frequency clock signal from the second frequency oscillator, a third frequency clock signal from the resistor-capacitor oscillator, and a fourth frequency clock signal from the phase-locked loop. It then sends these four clock signals to the module connected to the current second multiplexing module.

6. The method according to claim 4, characterized in that, The calibration module receives a second-frequency clock signal from the second-frequency oscillator and a third-frequency clock signal from the resistor-capacitor oscillator when the system is powered on or in operation. The second-frequency clock signal from the second-frequency oscillator is used as a reference clock to calibrate the third-frequency clock signal from the resistor-capacitor oscillator. The calibration module outputs calibration parameter values ​​to the resistor-capacitor oscillator, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the clock signal of the third frequency. In sleep mode, the system receives a first-frequency clock signal from the first-frequency oscillator and a third-frequency clock signal from the resistor-capacitor oscillator; and calibrates the third-frequency clock signal from the resistor-capacitor oscillator using the first-frequency clock signal from the first-frequency oscillator as a reference clock. The calibration module outputs calibration parameter values ​​to the resistor-capacitor oscillator, so that the resistor-capacitor oscillator calibrates according to the calibration parameter values ​​and outputs the clock signal of the third frequency.

7. An electronic device, characterized in that, include: Memory, used to store computer programs; A processor, when executing a program stored in memory, implements the method described in any one of claims 4-6.

8. A computer-readable storage medium, characterized in that, The computer-readable storage medium contains a computer program that, when executed by a processor, implements the method described in any one of claims 4-6.

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