Managing three-dimensional semiconductor devices

Abstract

Systems, devices, and methods for managing three-dimensional (3D) semiconductor devices are provided. In one aspect, a semiconductor device includes a stack structure having at least one gate line, a select gate layer, and at least one channel structure. The at least one gate line includes a first material. The select gate layer includes a second material different from the first material. The at least one channel structure extends along a first axis through the stack structure and the select gate layer. Each of the at least one channel structure includes a layered structure.

Description

Technical Field

[0001] The present disclosure relates to semiconductor devices and fabrication processes for semiconductor devices. Background Art

[0002] Semiconductor devices, such as memory devices, can have various structures to increase the density of memory cells and lines on a chip. For example, three-dimensional (3D) memory devices are attractive due to their ability to increase array density by stacking more layers in a similar footprint. A 3D memory device typically includes a memory array of memory cells and peripheral circuitry for facilitating the operation of the memory array. The memory cells may include a vertical structure. Summary of the Invention

[0003] The present disclosure describes methods, devices, systems, and techniques for managing select gates in three-dimensional (3D) semiconductor devices.

[0004] One aspect of the present disclosure is characterized by a semiconductor device comprising: a stacked structure including at least one gate line, wherein the at least one gate line comprises a first material; a select gate layer comprises a second material different from the first material; at least one channel structure extends along a first axis through the stacked structure and the select gate layer; each of the at least one channel structure comprises a layered structure.

[0005] In some embodiments, the second material includes doped polysilicon.

[0006] In some embodiments, the layered structure includes a blocking layer, a charge trapping layer, a dielectric layer, and a semiconductor channel layer. The semiconductor channel layer is in contact with and laterally surrounded by the dielectric layer. The dielectric layer is in contact with and laterally surrounded by the charge trapping layer. The charge trapping layer is in contact with and laterally surrounded by the blocking layer.

[0007] In some embodiments, the blocking layer comprises silicon oxide, the charge trapping layer comprises silicon nitride, the dielectric layer comprises silicon oxide, and the semiconductor channel layer comprises doped polysilicon.

[0008] In some embodiments, the semiconductor device further comprises a select gate cut structure, wherein the select gate cut junction extends through the select gate layer along the first axis. The select gate cut junction is configured to divide the select gate layer into a plurality of isolated portions. The select gate cut structure contacts one or more of the at least one channel structure.

[0009] In some embodiments, the select gate cutting structure has a straight line shape or a wavy shape in a first plane of the semiconductor device, wherein the first plane is orthogonal to the first axis.

[0010] In some embodiments, each of the channel structures further includes a channel plug. The channel plug and the layered structure are stacked together along the first axis. The channel plug contacts the semiconductor channel layer. The width of the channel plug is greater than the width of the semiconductor channel layer.

[0011] In some embodiments, the width of the trench plug is a dimension along a second axis, wherein the second axis is orthogonal to the first axis.

[0012] Another aspect of the present disclosure is characterized by a semiconductor device comprising: a stacked structure including at least one gate line; and a select gate layer. At least one channel structure extends through at least the stacked structure along a first axis. Each of the at least one channel structure comprises: a layered structure including a blocking layer, a charge trapping layer, a dielectric layer, and a semiconductor channel layer. Each channel structure further comprises a channel plug. The channel plug and the layered structure are stacked together along the first axis. The channel plug contacts the semiconductor channel layer. The channel plug at least partially contacts a channel contact. A select gate cut structure extends through at least the select gate layer along the first axis and is configured to divide the select gate layer into a plurality of isolated portions. The select gate cut structure contacts one or more of the at least one channel structure.

[0013] In some embodiments, the first material of the select gate layer is different from the second material of the at least one gate line.

[0014] In some embodiments, the first material of the select gate layer includes doped polysilicon, and the second material of the at least one gate line includes tungsten.

[0015] In some embodiments, the at least one channel structure extends through the stacked structure and the select gate layer along the first axis, and wherein the blocking layer comprises silicon oxide, the charge trapping layer comprises silicon nitride, the dielectric layer comprises silicon oxide, and the semiconductor channel layer comprises doped polysilicon.

[0016] In some embodiments, a width of the channel plug is greater than a width of the semiconductor channel layer.

[0017] In some embodiments, the select gate cutting structure has a straight line shape or a wavy shape in a first plane of the semiconductor device, wherein the first plane is orthogonal to the first axis.

[0018] Another aspect of the present disclosure features a method comprising: forming a stacked structure including a plurality of insulating layers along a first axis; forming a select gate layer; and forming at least one channel structure extending through the stacked structure and the select gate layer along the first axis. Each of the at least one channel structure comprises a layered structure including a blocking layer, a charge trapping layer, a dielectric layer, and a semiconductor channel layer. The method further comprises forming a select gate cut structure extending through at least the select gate layer. The select gate cut structure is configured to divide the select gate layer into a plurality of isolated portions.

[0019] In some embodiments, the stack structure further comprises a plurality of sacrificial layers interleaved with the plurality of insulating layers. The method further comprises replacing the plurality of sacrificial layers with a plurality of conductive layers.

[0020] In some embodiments, the first material of the select gate layer is different from the second material of the plurality of conductive layers.

[0021] In some embodiments, each of the at least one channel structure further includes a channel plug. The channel plug and the layered structure are stacked together along the first axis. The channel plug contacts the semiconductor channel layer. The width of the channel plug is greater than the width of the semiconductor channel layer.

[0022] In some embodiments, the select gate cut structure contacts one or more channel structures of the at least one channel structure.

[0023] In some embodiments, the select gate cutting structure has a straight line shape or a wavy shape in a first plane of the semiconductor device, wherein the first plane is orthogonal to the first axis.

[0024] The details of one or more implementations of the subject matter of the present disclosure are set forth in the accompanying drawings and the description below. Other features, aspects, and advantages of the subject matter will become apparent from the description, drawings, and claims. BRIEF DESCRIPTION OF THE DRAWINGS

[0025] The accompanying drawings, which are incorporated herein and form a part of this disclosure, illustrate aspects of the disclosure and, together with the description, serve to explain the principles of the disclosure and enable one skilled in the relevant art to make and use the disclosure.

[0026] Figure 1 A cross-sectional view of an example semiconductor device is shown.

[0027] Figures 2A-2D Cross-sectional views of an example semiconductor device at various stages of the fabrication process are shown.

[0028] Figures 3A-3H Views of an example semiconductor device with a trench plug at various stages of the fabrication process are shown.

[0029] Figures 4A-4B A top plan view of an example memory device is shown.

[0030] Figure 5 A flow chart illustrating an example process for forming a semiconductor device is shown.

[0031] Figure 6 A block diagram of a system having one or more semiconductor devices is shown.

[0032] It should be understood that the various exemplary embodiments shown in the figures are merely illustrative representations and are not necessarily drawn to scale. DETAILED DESCRIPTION

[0033] In some 3D memory devices (such as 3D NAND memory devices), a stack of gate electrodes can be arranged above a substrate, wherein multiple semiconductor channels pass through and intersect word lines and enter the implanted substrate. The bottom / lower gate electrode (single or multiple) serves as a source select gate line, also referred to as a bottom select gate (BSG) in some cases. The top / upper gate electrode (single or multiple) serves as a drain select gate line, also referred to as a top select gate (TSG) in some cases. The gate electrode between the top / upper select gate electrode and the bottom / lower gate electrode serves as a word line (WL). The intersection of the word line and the semiconductor channel forms a memory cell.

[0034] The present disclosure describes a semiconductor device and a method for forming such a semiconductor device. The semiconductor device includes a stacked structure having at least one gate line and a select gate layer. The select gate layer comprises a material different from that of the gate line. For example, the gate line may comprise tungsten (W), while the select gate layer comprises doped polysilicon. At least one channel structure extends through the stacked structure and the select gate layer along a first axis. Each channel structure has a layered structure, wherein the layered structure may include a blocking layer, a charge trapping layer, a dielectric layer, and a semiconductor channel layer distributed along a radial direction. The layered structure extends along the first axis. In some embodiments, a select gate cut structure extends through the select gate layer along the first axis and divides the select gate layer into a plurality of isolated portions. The select gate cut structure may contact or partially interfere with at least one channel structure. In some embodiments, at least one channel structure includes a channel plug stacked with the layered structure along the first axis. The channel plug contacts the semiconductor channel layer, and the width of the channel plug is greater than the width of the semiconductor channel.

[0035] Embodiments of the present disclosure may provide one or more of the following technical advantages and / or benefits. First, a channel trench for forming a memory string is formed that extends through a stacked structure (e.g., an interleaved insulating layer and gate lines) and a select gate layer (e.g., a top select gate or a bottom select gate). No additional trench etching process is required for the select gate layer, which helps to reduce manufacturing costs. In addition, the formation of the channel trench and the select gate cut structure can be performed before replacing the sacrificial layer with a conductive material for the gate line. This sequential process alleviates alignment issues between the select gate cut structure and the channel trench caused by thermal stress during the replacement process.

[0036] Secondly, the top select gate and / or the bottom select gate can have a floating gate configuration. A layered structure for the floating gate is formed on the sidewalls of the channel and is configured to extend along the axial direction of the channel trench. Because the channel trench also extends through the select gate layer, the layered structure is partially surrounded by the select gate layer in the lateral direction, thereby forming a floating gate configuration for the select gate. A gate select voltage can be applied to the select gate for selecting the corresponding memory string during operation. With this floating gate configuration, the top select gate and / or the bottom select gate can have better Vt adjustment and control.

[0037] Third, the select gate cut structure is located between two adjacent rows of channel structures. The select gate cut structure contacts these channel structures or partially cuts off these channel structures. Because the select gate cut structure does not fully or completely cut off the channel structures, the channel structures that contact the select gate cut structure can still be functional channels in which memory cells are formed. Therefore, the requirement for creating dummy channel rows is reduced. In the absence of dummy channels, the density of memory cells is increased and manufacturing costs are reduced.

[0038] Furthermore, in some embodiments, a trench plug is disposed within a trench trench stacked with the layered structure. This trench plug can increase the contact area for the contact or via, thereby improving alignment margins in subsequent process steps. It can also reduce the contact resistance between the contact / via and the trench structure.

[0039] This technology can be applied to various types of semiconductor devices, volatile memory devices (such as DRAM memory devices) or non-volatile memory (NVM) devices (such as NAND flash memory, NOR flash memory, resistive random-access memory (RRAM), phase-change memory (PCM) (such as phase-change random-access memory (PCRAM)), spin-transfer torque (STT)-magnetoresistive random-access memory (MRAM), etc.). This technology can also be applied to charge trapping-based memory devices, such as silicon-oxide-nitride-oxide-silicon (SONOS) memory devices and floating gate-based memory devices. These technologies can be applied to three-dimensional (3D) memory devices. The technology can be applied to various memory types, such as SLC (single-level cell) devices, MLC (multi-level cell) devices (such as 2-level cell devices), TLC (triple-level cell) devices, QLC (quad-level cell) devices, or PLC (penta-level cell) devices. Additionally or alternatively, the technology can be applied to various types of devices and systems, such as secure digital (SD) cards, embedded multimedia cards (eMMC) or solid-state drives (SSDs), embedded systems, etc.

[0040] Figure 1A cross-section of an exemplary 3D memory device 100 is shown. The 3D memory device 100 may include a substrate 102, which is a doped semiconductor layer and may include silicon (e.g., single crystal silicon), silicon germanium (SiGe), gallium arsenide (GaAs), germanium (Ge), silicon on insulator (SOI), germanium on insulator (GOI), or any other suitable material. In some embodiments, the substrate 102 is a thinned substrate (e.g., a semiconductor layer) that is thinned by grinding, etching, chemical mechanical polishing (CMP), or any combination thereof. The substrate 102 of the 3D memory device 100 includes two surfaces (e.g., a top surface and a bottom surface) extending laterally in the X direction (i.e., the lateral direction). As used herein, whether a component (e.g., a layer or device) is “on,” “above,” or “below” another component (e.g., a layer or device) in a 3D memory device (e.g., 3D memory device 100) is determined relative to a substrate (e.g., substrate 102) of the 3D memory device in the Y direction (i.e., the vertical direction) when the substrate is located in the lowest plane of the 3D memory device in the Y direction.

[0041] In some embodiments, the 3D memory device 100 is a NAND flash memory device in which memory cells are provided in an array of NAND strings, each NAND string extending vertically above the substrate 102 .

[0042] like Figure 1 As shown, the 3D memory device 100 may include a stacked structure 104 having interlaced gate lines 136 and a first dielectric layer 106. The gate lines 136 may include a conductive material, including but not limited to tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The first dielectric layer 106 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0043] A select gate (SG) layer 120 may be formed on top of the stack structure 104, isolated from the gate line 136. The select gate layer may include a different conductive material than the gate line. For example, the select gate layer may include doped polysilicon, while the gate line may include tungsten (W). The NAND memory string may include one or more channel structures 110 extending vertically in the Y direction through the stack structure 104 and the select gate layer 120. In some embodiments, an additional dielectric layer is formed between the select gate layer 120 and the stack structure 104.

[0044] The channel structure 110 may include a channel hole or a channel trench having a layered structure 140. In some embodiments, the remaining space of the channel structure 110 may be partially or completely filled with a filling layer 112 comprising a dielectric material (such as silicon oxide). In some embodiments, the layered structure 140 includes a blocking layer, a charge trapping layer (also referred to as a storage layer in some cases), a dielectric layer (also referred to as a tunneling layer in some cases), and a semiconductor channel layer. The semiconductor channel layer 114 is in contact with and laterally surrounded by the dielectric layer 116. The dielectric layer 116 is in contact with and laterally surrounded by the charge trapping layer 118. The charge trapping layer 118 is in contact with and laterally surrounded by the blocking layer 122. In other words, the filling layer 112, the semiconductor channel layer 114, the dielectric layer 116, the charge trapping layer 118, and the blocking layer 122 are arranged radially from the center of the channel trench toward the outer surface in the order of the filling layer 112, the semiconductor channel layer 114, the dielectric layer 116, the charge trapping layer 118, and the blocking layer 122. The semiconductor channel layer 114 may include doped polysilicon or silicon germanium (SiGe). The dopant may be an N-type dopant (e.g., phosphorus (P) or arsenic (As)) or a P-type dopant (e.g., boron (B) or gallium (Ga)) at a desired doping level. The dielectric layer 116 may include silicon oxide, silicon oxynitride, or any combination thereof. The charge trapping layer 118 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer 122 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. In one example, layered structure 140 may include silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide / polysilicon (ONOP) for blocking layer 122 , charge trapping layer 118 , dielectric layer 116 , and semiconductor channel layer 114 , respectively.

[0045] The channel structure 110 may have a cylindrical shape (eg, a pillar shape). In some embodiments, the channel structure 110 may be formed by stacking more than one pillar structure, such as Figure 1 It should be understood that the channel structure 110 may have other shapes (eg, an elliptical cylinder or an irregular shape).

[0046] In some embodiments, the channel structure 110 may further include a channel contact (not shown), also referred to as a semiconductor plug, located in a lower portion (e.g., at a lower end) of the channel structure 110. As used herein, the "upper end" of a component (e.g., the channel structure 110) is the end further away from the substrate 102 in the positive Y direction, while the "lower end" of a component (e.g., the channel structure 110) is the end closer to the substrate 102 in the negative Y direction. The channel contact may include a semiconductor material, such as silicon, epitaxially grown from the substrate 102 in any suitable direction. It should be understood that in some embodiments, the channel contact includes single crystal silicon of the same material as the substrate 102. In other words, the channel contact may include an epitaxially grown semiconductor layer of the same material as the substrate 102. In some embodiments, a portion of the channel contact is above the top surface of the substrate 102 and in contact with the semiconductor channel layer 114. The channel contact may serve as a channel controlled by the source select gate of the NAND memory string. It should be understood that in some embodiments, the 3D memory device 100 does not include a channel contact, such as Figure 1 shown.

[0047] In some embodiments, the channel structure 110 further includes a channel plug 124 in an upper portion (e.g., at an upper end) of the channel structure 110, which may be stacked above the layered structure 140. The channel plug 124 may contact the upper end of the semiconductor channel layer 114 of the layered structure 140. In some embodiments, the channel plug 124 material may include, but is not limited to, TiN, TaN, Al, W, Cu, doped polysilicon, silicide, or any combination thereof. By covering the upper end of the channel structure 110 during the manufacture of the 3D memory device 100, the channel plug 124 may serve as an etch stop layer to prevent etching of dielectrics filled in the channel structure 110, such as silicon oxide and silicon nitride. In some embodiments, the channel plug 124 also serves as a drain of the NAND memory string.

[0048] As described above, the memory array device may include NAND memory strings extending through the interlaced gate lines 136 and the first dielectric layer 106, and the stacked conductive / dielectric layer pair is also referred to as a memory stack. The memory array device may also include a select gate layer 120. The channel structure 110 extends through the stack structure 104 and at least partially through the select gate layer 120. In this way, better threshold voltage Vt adjustment or control of the select gate layer 120 can be achieved using the layered structure 140 in a floating gate configuration (e.g., ONOP).

[0049] In some embodiments, each gate line 136 in the stacked structure 104 (e.g., a memory stack) serves as a gate conductor for a memory cell in a NAND memory string. The gate line 136 can extend laterally to couple multiple memory cells. In some embodiments, the memory cell transistor in the NAND memory string includes a semiconductor channel layer 114, a storage film (including a dielectric layer 116, a charge trapping layer 118, and a blocking layer 122), and a gate line 136. The gate line 136 can also include a gate conductor made of tungsten, an adhesion layer including titanium / titanium nitride (Ti / TiN) or tantalum / tantalum nitride (Ta / TaN), and a gate dielectric layer made of a high-k dielectric material. As described above, the select gate layer 120, such as a drain select layer or a source select layer, can include a different conductive material than the gate line 136. For example, the gate line 136 can include tungsten (W), while the select gate layer 120 can include doped polysilicon.

[0050] like Figure 1 As shown, the select gate layer 120 extends along the X direction and is divided into two or more parts by the select gate cutting structure 126. Each part can be a select gate line for a corresponding memory string. A gate select voltage can be applied to the select gate line to select the corresponding string during operation.

[0051] The select gate cut structure 126 may be in contact with the channel structure 110 and the channel plug 124. In other words, the select gate cut structure 126 partially extends into the channel structure 110 and / or the channel plug 124. In some embodiments, the select gate cut structure 126 is formed of a dielectric material. The select gate cut structure 126 is used to electrically insulate the select gate line between two adjacent memory strings. By forming the select gate layer 120 around the layered structure 140, a better Vt adjustment of the select gate can be achieved using a floating gate structure (e.g., ONOP). In some embodiments, although not in Figure 1 , but it should be understood that in a memory array, multiple channel structures 110 are included. As described below, in some embodiments, the select gate cutting structure 126 contacts at least one of the channel structures 110, although not all of them.

[0052] Since the select cut structure 126 only partially extends into the channel structure 110, the channel structure 110 can still be a functional channel in which a memory cell is formed. Therefore, this memory device structure reduces the number of dummy channel structures, thereby allowing the density of memory strings to be increased.

[0053] In some embodiments, the memory array device includes a channel contact 128 atop the select gate cut structure 126 and the channel plug 124. As described above, the select gate cut structure 126 partially extends into at least one of the channel structures 110. Thus, the channel contact 128 can at least partially contact the top of the channel plug 124. The channel contact 128 can include a conductive material including, but not limited to, tungsten (W), cobalt (Co), copper (Cu), aluminum (Al), polysilicon, doped silicon, silicide, or any combination thereof. The channel contact 128 can be configured to connect the memory cell to a bit line (not shown), back-end of line (BEOL) metal wiring (not shown), and / or peripheral circuitry (not shown). It should be understood that in some embodiments, the channel plug 124 may not be included in the channel structure 110. In this case, the channel contact 128 lands on the top of the channel structure 110, including the semiconductor channel layer 114.

[0054] Figures 2A-2D 1 shows cross-sectional views of an example 3D semiconductor device at various stages of the fabrication process. Figure 2A As shown, an interleaved structure 204 is formed, which includes interleaved sacrificial layers 202 and insulating layers (e.g., first dielectric layer 106). The sacrificial layer 202 can be configured to be replaced with a conductive material at a later stage of the process to form gate line 136, as described below. The first dielectric layer 106 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The sacrificial layer 202 may also include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The sacrificial layer 202 may include a different material from the first dielectric layer 106 so that it can be selectively removed and replaced with a conductive material at a later stage of processing. For example, the sacrificial layer includes silicon nitride and the first dielectric layer includes silicon oxide.

[0055] In some embodiments, before forming the staggered structure 204, a select gate layer 120, for example, for a bottom select gate or a source select gate, is formed on the substrate 102. Another select gate layer 120, for example, for a top select gate or a drain select gate, is formed on top of the staggered structure 204 along the positive Y-axis, as shown in FIG. Figure 2AAs shown. The select gate layer 120 may include materials including but not limited to doped polysilicon. The first dielectric layer 106 and the sacrificial layer 202 may be deposited using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or any combination thereof. In some embodiments, the second dielectric layer 222 may be formed on top of the select gate layer 120, such as Figure 2A shown.

[0056] One or more channel trenches 206 are formed extending through the select gate layer 120 and the staggered structure 204 and contacting the substrate 102 . Figure 2A An example channel trench 206 is shown. In some embodiments, the channel trench 206 extends partially into the substrate 102. In some embodiments, the channel trench has a cylindrical shape. Due to the etching process, the cylinder can have a larger top opening than the bottom opening. In some embodiments, the channel trench can be formed by stacking more than one cylindrical trench, such as Figure 2A As shown. In this case, a first portion 204(a) of the staggered structure 204 is deposited on the substrate 102, followed by a trench etch extending through the first portion of the staggered structure 204. The first portion of the trench 206 is then filled with a sacrificial fill material 208, which is removed at a later stage, as described below. The sacrificial fill material 208 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0057] The second portion 204 ( b ) of the staggered structure 204 and the select gate layer 120 are deposited on top of the first portion 204 ( a ) of the staggered structure 204 , followed by a trench etching process to form the second portion of the channel trench 206 . Figure 2AAs shown, the channel trench 206 can have a stacked cylindrical shape that extends through the second dielectric layer 222, the select gate layer 120, the interleaved structure 204, the further select gate layer 120, and into the substrate 102. It should be understood that one or more additional dielectric layers can be deposited between the interleaved structure 204 and the select gate layer 120 for isolation purposes. The trench etching can involve one or more dry etching and / or wet etching processes, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputter etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), Piranha solution (H2SO4 / H2O2), or any combination thereof.

[0058] like Figure 2B As shown, sacrificial fill material 208 is removed by etching. A layered structure 140 is deposited on the sidewalls of channel trench 206. As described above, layered structure 140 includes blocking layer 122, charge trapping layer 118 (also referred to as a storage layer in some cases), dielectric layer 116 (also referred to as a tunneling layer in some cases), and semiconductor channel layer 114. Semiconductor channel layer 114, dielectric layer 116, charge trapping layer 118, and blocking layer 122 are radially arranged from the center of channel trench 206 toward the outer surface in the order of semiconductor channel layer 114, dielectric layer 116, charge trapping layer 118, and blocking layer 122. This arrangement can be achieved by sequentially depositing these layers on the sidewalls of channel trench 206 in reverse order. Dielectric layer 116 may include silicon oxide, silicon oxynitride, or any combination thereof. Charge trapping layer 118 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The barrier layer 122 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. The semiconductor channel layer 114 may include polysilicon. In one example, the layered structure 140 includes silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide / polysilicon (ONOP). The layered structure 140 may be deposited using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or any combination thereof. In some embodiments, an implantation process is performed to dope the polysilicon used for the semiconductor channel layer.

[0059] Filling layer 112 is deposited into the vacant space of channel trench 206. Channel structure 110 is formed including at least layered structure 140 and filling layer 112. Filling layer 112 may be a dielectric material including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0060] In some embodiments, the top portion of the filling layer 112 may be recessed by an etching process, and the recessed space may then be filled with a conductive material (eg, the same material as the semiconductor channel material).

[0061] The layered structure 140 extends at least partially through the select gate layer 120 and the staggered structure 204 along the Y-axis. Figure 2B The layered structure 140 may form a floating gate structure for the select gate layer 120, providing the benefit of better threshold voltage Vt control for the top select gate and / or the bottom select gate.

[0062] like Figure 2C As shown, a selection gate cut structure 126 is formed, which extends through the selection gate layer 120 along the Y axis and partially enters the channel structure 110 along the X axis. The selection gate cut structure 126 divides the selection gate layer 120 into a plurality of isolated portions for electrically insulating the selection gate lines between two adjacent memory strings. As described below in FIG. 4 , the selection gate cut structure 126 is formed between two adjacent rows of channel structures 110 and contacts or extends into the channel structures 110 in the two adjacent rows. The selection gate cut structure 126 may have a straight line shape or a wavy shape extending along the Z axis on a top plane (e.g., an XZ plane orthogonal to the Y axis), as shown in FIG. 4 . In some embodiments, the selection gate cut structure 126 may be configured to avoid any contact or interference with the channel structure 110.

[0063] Return Reference Figure 2C , a select gate cut structure 126 can be formed by etching a trench in the select gate layer 120 in combination with a photolithography process. A portion of the upper side of the channel structure 110 can be removed during the trench etching process, thereby exposing the semiconductor channel layer 114. The trench is then filled with a suitable material (e.g., a dielectric material) to form the select gate cut structure 126. Therefore, the select gate cut structure 126 can partially extend into the channel structure 110 and contact the semiconductor channel layer 114. At this stage, the top surface 201 of the channel structure 110 is at least partially exposed. In some embodiments, the select gate cut structure 126 extends along the Y-axis (not shown) through at least one sacrificial layer 202 or the first dielectric layer 106 of the stacked structure 104.

[0064] In some embodiments, the select gate cut structure 126 includes a dielectric material. In some embodiments, the select gate cut structure 126 includes an insulating layer, an adhesion layer, and a conductive layer. The insulating layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The adhesion layer may include a material including but not limited to TiN, TaN, or any combination thereof. The conductive layer may include a material including but not limited to TiN, TaN, Al, W, Cu, doped polysilicon, silicide, or any combination thereof. The insulating layer may be deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, MOCVD, MBE, sputtering, or any combination thereof. The conductive layer and adhesion layer may be deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, metal-organic chemical vapor deposition (MOCVD), sputtering, electroplating, electroless plating, electron beam evaporation, or any combination thereof.

[0065] like Figure 2D As shown, the channel contact 128 is formed on top of the select gate cut structure 126 and the channel structure 110. In some embodiments, when the channel structure 110 does not interfere with the select gate cut structure 126 (see Figure 4A 4 ), the channel contacts 128 are formed only on the top of the channel structures 110. The channel contacts 128 can be isolated from each other by a dielectric material therebetween. The channel contacts 128 can be configured to connect the memory cells to bit lines (not shown), back-end-of-line (BEOL) metal wiring (not shown), and / or peripheral circuitry (not shown). The channel contacts 128 can include a conductive material including, but not limited to, TiN, TaN, Al, W, Cu, doped polysilicon, silicide, or any combination thereof.

[0066] The sacrificial layer 202 is replaced by a conductive material to form the gate line 136, such as Figure 2DAs shown. The gate lines 136 are isolated from each other by the first dielectric layer 106. In some embodiments, the sacrificial layer 202 can be removed by a wet etching and / or dry etching process. After removing the sacrificial layer 202, a plurality of openings can be formed between adjacent first dielectric layers 106. Then, a conductive material is deposited into the openings to form the gate lines 136. In some embodiments, the gate lines 136 may include a conductive material, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the gate lines 136 can be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, MOCVD, MBE, sputtering, or any combination thereof.

[0067] Figures 3A-3F 1 shows cross-sectional views of an example semiconductor device having a trench plug at various stages of the fabrication process. Figure 3A As shown, a staggered structure 204, a selection gate layer 120 and a channel trench 206 are formed. The formation process can be the same as Figure 2A The process steps are the same or similar to those described in . A staggered structure 204 is formed, which includes staggered sacrificial layers 202 and insulating layers, such as the first dielectric layer 106. The sacrificial layers 202 can be configured to be replaced with conductive materials at a later stage of the process to form gate lines 136, as shown below. Figure 3H As described in

[15] , the first dielectric layer 106 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The sacrificial layer 202 may include a dielectric material including, but not limited to, silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The sacrificial layer 202 may include a different material than the first dielectric layer 106 so that it can be selectively removed at a later processing stage. For example, the sacrificial layer may include silicon nitride while the first dielectric layer includes silicon oxide.

[0068] In some embodiments, before forming the staggered structure 204, a select gate layer 120, for example, for a bottom select gate or a source select gate, is formed on the substrate 102. Another select gate layer 120 (for example, for a top select gate or a drain select gate) is formed on top of the staggered structure 204 along the positive Y-axis, as shown in FIG. Figure 3A As shown. The select gate layer 120 may include materials including but not limited to doped polysilicon. The first dielectric layer 106 and the sacrificial layer 202 may be deposited using one or more thin film deposition processes including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or any combination thereof. In some embodiments, a second dielectric layer 222 may be formed on top of the select gate layer 120, such as Figure 3A shown.

[0069] One or more channel trenches 206 are formed that extend through the select gate layer 120 and the staggered structure 204 and contact the substrate 102. In some embodiments, the channel trenches 206 extend partially into the substrate 102. In some embodiments, the channel trenches have a cylindrical shape. Due to the etching process, the cylinder can have a larger top opening than the bottom opening. In some embodiments, the channel trenches can be formed by stacking more than one cylindrical trench, such as Figure 3A As shown. In this case, a first portion 204(a) of the staggered structure 204 is deposited on the substrate 102, followed by a trench etch extending through the first portion of the staggered structure 204. The first portion of the trench 206 is then filled with a sacrificial fill material 208, which is configured to be removed at a later stage, as described below. The sacrificial fill material 208 may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0070] The second portion 204 ( b ) of the staggered structure 204 and the select gate layer 120 are deposited on top of the first portion 204 ( a ) of the staggered structure 204 , followed by a trench etching process to form the second portion of the channel trench 206 . Figure 3A As shown, the channel trench 206 may have a stacked cylindrical shape that extends through the second dielectric layer 222, the select gate layer 120, the interleaved structure 204, the further select gate layer 120, and into the substrate 102. It should be understood that one or more additional dielectric layers may be deposited between the interleaved structure 204 and the select gate layer 120 for isolation purposes. The trench etching may involve one or more dry etching and / or wet etching processes including, but not limited to, reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputter etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof.

[0071] like Figure 3B As shown, a layered structure 140 is formed on the sidewall of the trench. The formation process can be the same as that in the above Figure 2BThe process described in

[14] is the same as or similar to that described in

[14] . As described above, the layered structure 140 includes a blocking layer 122, a charge trapping layer 118 (also referred to as a storage layer in some cases), a dielectric layer 116 (also referred to as a tunneling layer in some cases), and a semiconductor channel layer 114. The semiconductor channel layer 114, the dielectric layer 116, the charge trapping layer 118, and the blocking layer 122 are radially arranged from the center of the channel trench 206 toward the outer surface in the order of semiconductor channel layer 114, dielectric layer 116, charge trapping layer 118, and blocking layer 122. This arrangement can be achieved by sequentially depositing these layers on the sidewalls of the channel trench 206 in reverse order. The dielectric layer 116 may include silicon oxide, silicon oxynitride, or any combination thereof. The charge trapping layer 118 may include silicon nitride, silicon oxynitride, silicon, or any combination thereof. The blocking layer 122 may include silicon oxide, silicon oxynitride, a high dielectric constant (high-k) dielectric, or any combination thereof. The semiconductor channel layer 114 may include polysilicon. In one example, the layered structure 140 includes silicon oxide / silicon oxynitride (or silicon nitride) / silicon oxide / polysilicon (ONOP). The layered structure 140 can be deposited using one or more thin film deposition processes, including but not limited to chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), sputtering, or any combination thereof. In some embodiments, an implantation process is performed to dope the polysilicon used for the semiconductor channel layer.

[0072] The layered structure 140 extends at least partially through the select gate layer 120 and the staggered structure 204 along the Y-axis. Figure 3B The layered structure 140 may form a floating gate structure for the select gate layer 120, providing the benefit of better threshold voltage Vt control for the top select gate and / or the bottom select gate.

[0073] Filling layer 112 is deposited into the vacant space of channel trench 206. Channel structure 110 is formed including at least layered structure 140 and filling layer 112. Filling layer 112 may be a dielectric material including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof.

[0074] like Figure 3CAs shown, the top portion of the fill layer 112 is recessed by an etching process. It should be understood that the remaining fill layer 112 after the recessing can be higher or lower than the top surface 301 of the select gate layer 120 along the Y-axis. In some embodiments, the top portion of the layered structure 140 is recessed along with the top portion of the fill layer 112 (not shown). The recessing or etching process can involve one or more dry etching and / or wet etching processes, including but not limited to reactive ion etching (RIE), plasma etching, hydrofluoric acid (HF) etching, sputter etching, KOH etching (potassium hydroxide), TMAH etching (tetramethylammonium hydroxide), buffered oxide etchant (BOE), piranha solution (H2SO4 / H2O2), or any combination thereof.

[0075] like Figure 3D As shown, the recessed space can then be filled with one or more materials to form a trench plug 124. In some embodiments, the trench plug 124 can be made of materials including, but not limited to, TiN, TaN, Al, W, Cu, doped polysilicon, silicide, or any combination thereof. In some embodiments, the trench plug 124 can be first filled with an insulating material. More specifically, the trench plug 124 can be first formed using an insulating material. The insulating material of the trench plug 124 is replaced with a conductive material in a later process stage. To replace the insulating material with a conductive material, the insulating material can be partially or completely removed by dry etching or wet etching. Then, after etching, the conductive material is filled into the vacant space.

[0076] In some embodiments, as Figures 3D-3E As shown, the channel plug 124 fills the vacancy at the top portion of the channel structure 110, where the filling layer 112 and the layered structure 140 are recessed. The remaining layered structure 140 after the recess at least partially extends through the select gate layer 120. In other words, the top surface 305 of the remaining layered structure 140 is above the bottom surface 303 of the select gate layer 120 along the Y axis (see FIG. Figure 3D ). This allows for a floating gate configuration for the select gate and provides the benefit of better threshold voltage Vt control. Figure 3E Illustration (a) shows a top view (eg, XZ plane) of the channel structure 110 before recessing, and illustration (b) shows a top view of the channel structure 110 after recessing and forming the channel plug 124 .

[0077] In some embodiments, the top portion of the channel structure 110 is not completely recessed along the lateral direction (e.g., X-axis and / or Z-axis). Thus, the width (e.g., diameter) of the channel plug 124 may be smaller than the width of the channel structure 110 but larger than the width of the semiconductor channel layer 114. Figure 3FAs shown, illustration (a) shows a top view of the channel structure 110 before partial recessing, and illustration (b) shows a top view (eg, XZ plane) of the channel structure 110 after partial recessing and forming the channel plug 124 . Figure 3F Illustration (b) shows that after the partial recessing, the width (eg, diameter 307 ) of the channel plug 124 is smaller than the diameter 311 of the channel structure 110 , but larger than the diameter 309 of the semiconductor channel layer 114 .

[0078] In some embodiments, the cross-section of the channel structure 110 is circular, and the width of the channel plug 124 (eg, diameter 311 or diameter 307) is greater than the width of the semiconductor channel layer 114 in contact with the channel plug 124 (eg, diameter 309) (see FIG. Figures 3E-3F In some embodiments, the cross-section of the channel structure 110 is square, pentagonal, hexagonal, or other shapes. In these cases, the width can be a plane orthogonal to the axial axis (e.g., the Y axis) of the channel structure 110 (e.g., Figures 3E-3F For example, the width is the length of a side of a square, pentagon, hexagon, or other shape. In another example, the width is the distance from the center to the outer edge of the channel structure 110.

[0079] In some embodiments, after depositing the trench plug 124, a chemical mechanical polishing (CMP) process is performed on the surface of the trench plug 124 to align the top of the trench plug 124 with the upper surface of the surrounding dielectric material (see FIG. Figure 3D ).

[0080] like Figure 3G As shown, a selection gate cutting structure 126 is formed. The formation process of the selection gate cutting structure 126 can be the same as that of Figure 2C The process described in is the same or similar to that described in . A selection gate cut structure 126 is formed, which extends through the selection gate layer 120 along the Y axis and partially enters the channel structure 110 along the X axis. The selection gate cut structure 126 divides the selection gate layer 120 into a plurality of isolated portions for electrically insulating the selection gate lines between two adjacent storage strings. As described below in FIG. 4 , the selection gate cut structure 126 is formed between two adjacent rows of the channel structure 110 and contacts or extends into the channel structure 110 in the two adjacent rows. The selection gate cut structure 126 may have a straight line shape or a wavy shape extending along the Z axis on a top plane (e.g., an XZ plane orthogonal to the Y axis), as shown in FIG. 4 . In some embodiments, the selection gate cut structure 126 may be configured to avoid any contact or interference with the channel structure 110.

[0081] Return Reference Figure 3G, a select gate cut structure 126 can be formed by etching a trench in the select gate layer 120 in combination with a photolithography process. Portions of the upper side of the channel structure 110 and the channel plug 124 can be removed during the trench etching process, thereby exposing the semiconductor channel layer 114. The trench is then filled with a suitable material (e.g., a dielectric material) to form the select gate cut structure 126. Therefore, the select gate cut structure 126 partially extends into the channel structure 110 and the channel plug 124, and contacts the semiconductor channel layer 114.

[0082] In some embodiments, the select gate cut structure 126 includes a dielectric material. In some embodiments, the select gate cut structure 126 includes an insulating layer, an adhesion layer, and a conductive layer. The insulating layer may include a dielectric material, including but not limited to silicon oxide, silicon nitride, silicon oxynitride, or any combination thereof. The adhesion layer may include a material including but not limited to TiN, TaN, or any combination thereof. The conductive layer may include a material including but not limited to TiN, TaN, Al, W, Cu, doped polysilicon, silicide, or any combination thereof. The insulating layer may be deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, MOCVD, MBE, sputtering, or any combination thereof. The conductive layer and the adhesion layer may be deposited by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, metal organic chemical vapor deposition (MOCVD), sputtering, electroplating, electroless plating, electron beam evaporation, or any combination thereof.

[0083] like Figure 3H As shown, the channel contact 128 is formed on top of both the select gate cut structure 126 and the channel plug 124. In some embodiments, when the channel structure 110 does not interfere with the select gate cut structure 126 (see Figure 4A 4 ), the channel contacts 128 are formed only on top of the channel plugs 124. The channel contacts 128 may be isolated from each other by a dielectric material therebetween. The channel contacts 128 may be configured to connect the memory cell to a bit line (not shown), back-end-of-line (BEOL) metal wiring (not shown), and / or peripheral circuitry (not shown). The channel contacts 128 may include a conductive material including, but not limited to, TiN, TaN, Al, W, Cu, doped polysilicon, silicide, or any combination thereof.

[0084] The sacrificial layer 202 is replaced with a conductive material to form the gate line 136, such as Figure 3HAs shown. The gate lines 136 are isolated from each other by the first dielectric layer 106. In some embodiments, the sacrificial layer 202 can be removed by a wet etching and / or dry etching process. After removing the sacrificial layer 202, a plurality of openings can be formed between adjacent first dielectric layers 106. Then, a conductive material is deposited into the openings to form the gate lines 136. In some embodiments, the gate lines 136 may include a conductive material, including but not limited to W, Co, Cu, Al, polysilicon, doped silicon, silicide, or any combination thereof. In some embodiments, the gate lines 136 can be formed by one or more thin film deposition processes, including but not limited to CVD, PVD, ALD, MOCVD, MBE, sputtering, or any combination thereof.

[0085] Figures 4A-4B A top plan view of a memory block or portion of a memory block in the memory device 100 is shown. Figure 4A Multiple select gate cut structures 126 are shown distributed in the array of channel structures 110 . Figure 4B A close-up view of the relative position of the select gate cut structure 126 with respect to two adjacent channel structures 110 is shown.

[0086] In some embodiments, the memory device 100 is a NAND flash memory device in which memory cells are provided in the form of an array of NAND memory strings 406. The memory strings 406 may include a plurality of channel structures 110, each extending vertically along the Y axis above the substrate 102 (see FIG. Figure 1 ). The memory device 100 may include one or more memory blocks. A memory block may include a plurality of memory cells arranged between a pair of slit structures (not shown). The memory cells arranged in an array are formed in a plurality of channel structures 110 between the slit structures. The memory device 100 may include one or more select gate cut structures 126, each select gate cut structure 126 being between a pair of adjacent memory strings 406.

[0087] like Figure 4A As shown in Figures (a) and (b), the channel structures 110 are arranged in rows, each row extending along the Z direction. One or more rows of channel structures 110 form a channel structure array 402. In some embodiments, a channel structure array 402 having 12 channels, 16 channels, 20 channels, or even more channels can be formed. The select gate cutting structure 126 can divide the select gate layer 120 and the channel structure array 402 into multiple sections.

[0088] In some embodiments, the select gate cut structure 126 can be a straight or wavy structure in the top plane (e.g., the XZ plane) of the 3D memory device 100. In some embodiments, the wavy shape of the select gate cut structure 126 has reduced interference with the channel structure 110 compared to a straight shape. As a result, a larger amount of gate material from the select gate layer surrounding the affected channel structure 110 remains intact in the wavy configuration. The presence of more gate material enhances select gate control. It should be understood that in some embodiments, the select gate cut structure 126 has other suitable shapes (e.g., a zigzag shape).

[0089] In some embodiments, the select gate cut structure 126 contacts or partially extends into the channel structures 110 in two adjacent rows of channel structures 110. This configuration reduces the need for dummy rows of channel structures. Thus, the density of the channel structures 110 or memory cells is increased without dummy rows. This increased density is particularly beneficial in highly integrated circuits, where a three-dimensional memory with greater storage capacity is required within a compact package.

[0090] In some embodiments, the select gate cutting structure 126 contacts the semiconductor channel layer 114 of the channel structure 110, such as Figure 4B In some embodiments, the gate cutting structure 126 does not contact the semiconductor channel layer 114 of the channel structure 110, as shown in FIG. Figure 4B As shown in figure (a).

[0091] Although not shown, it should be understood that in some embodiments, the select gate cut structure 126 can be configured to avoid any contact or interference with any channel structures 110 in two adjacent rows.

[0092] Figure 5 A flow chart of an example process for forming a semiconductor device is shown. In step 502, a stacked structure is formed along a first axis. The stacked structure includes a plurality of insulating layers. The stacked structure may be, for example: Figure 1 、 Figure 2D and Figure 3H A stacked structure 104; Figures 2A-2C 、 Figures 3A-3D and Figure 3G The first axis can be, for example, Figures 2A-2D 、 Figures 3A-3D and Figures 3G-3H The insulating layer can be, for example, Figure 1-3D and Figures 3G-3H The first dielectric layer 106 is formed.

[0093] At step 504, a select gate layer is formed. The select gate layer may be, for example, Figure 1-3D and Figures 3G-3H The select gate layer 120 is formed.

[0094] At step 506, at least one channel structure is formed that extends vertically along a first axis through the stack structure and the select gate layer. Each channel structure may include a layered structure. The layered structure includes a blocking layer, a charge trapping layer, a dielectric layer, and a semiconductor channel layer. The channel structure may be, for example, Figure 1-3H The channel structure 110. The layered structure may be Figure 1-3H The barrier layer may be, for example, Figure 1 、 Figures 2B-2D and Figures 3B-3H The charge trapping layer may be, for example, Figure 1 、 Figures 2B-2D and Figures 3B-3H The charge trapping layer 118. The dielectric layer may be, for example, Figure 1 、 Figures 2B-2D and Figures 3B-3H The semiconductor channel layer may be, for example, Figure 1 、 Figures 2B-2D and Figures 3B-3H The semiconductor channel layer 114 is formed.

[0095] In some embodiments, each channel structure further comprises a channel plug. The channel plug and the layered structure are stacked together along the first axis. The channel plug contacts the semiconductor channel layer. The width of the channel plug is greater than the width of the semiconductor channel layer. The channel plug can be, for example, Figure 1 and Figures 3D-3H The semiconductor channel layer may be, for example, Figure 1 、 Figures 2B-2D and Figures 3B-3H The semiconductor channel layer 114 is formed.

[0096] At step 508, a select gate cut structure is formed that extends at least through the select gate layer. The select gate cut structure is configured to divide the select gate layer into a plurality of isolated portions. The select gate cut structure may be, for example, Figure 1 、 Figures 2C-2D and Figures 3G-3H The select gate cut structure 126. The select gate layer may be, for example, Figure 1-3D and Figures 3G-3H The select gate layer 120 is formed.

[0097] In some embodiments, the stacked structure includes a plurality of sacrificial layers interleaved with a plurality of insulating layers, and the plurality of sacrificial layers are replaced with a plurality of conductive layers. The sacrificial layers may be, for example, Figure 1-2C 、 Figures 3A-3D and Figure 3GThe sacrificial layer 202. The insulating layer may be, for example, Figure 1-3D and Figures 3G-3H The first dielectric layer 106. The conductive layer may be, for example, Figure 1 、 Figure 2D and Figure 3H gate line 136.

[0098] In some embodiments, the first material of the select gate layer is different from the second material of at least one gate line. For example, the select gate layer includes polysilicon, and the conductive layer (eg, gate line 136) includes tungsten (W).

[0099] In some embodiments, the select gate cut structure is in contact with one or more of the at least one channel structure. The select gate cut structure may be, for example, Figure 1 、 Figures 2C-2D and Figures 3G-3H The select gate cut structure 126. The channel structure can be, for example Figure 1-3H The channel structure 110 is shown in FIG.

[0100] In some embodiments, the selection gate cut structure has a straight line shape or a wavy shape in a first plane of the semiconductor device, such as Figures 4A-4B As shown, the first plane (eg, XZ plane) is orthogonal to the first axis (eg, Y axis). The select gate cut structure may be, for example, Figure 1 、 Figures 2C-2D and Figures 3G-3H The select gate cut structure 126 is shown.

[0101] Figure 6 A block diagram of a system 600 having one or more semiconductor devices (e.g., memory devices) according to one or more embodiments of the present disclosure is shown. The system 600 may be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a car computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having memory therein. Figure 6As shown, system 600 may include a host device 608 and a memory system 602, wherein the memory system 602 has one or more 3D memory devices 604 and a memory controller 606. The host device 608 may include a processor of an electronic device, such as a central processing unit (CPU), or a system-on-chip (SoC), such as an application processor (AP). The host device 608 may be configured to send data to or receive data from the one or more 3D memory devices 604.

[0102] The 3D memory device 604 may be any 3D memory device disclosed herein, such as Figure 1 The semiconductor device 100, or Figure 1-4B portion of the semiconductor device 100, or Figures 2A-3H The structure of the semiconductor device 100 in the intermediate manufacturing process.

[0103] In some implementations, the 3D memory device 604 includes NAND flash memory. A memory controller 606 (also referred to as a controller circuit) is coupled to the 3D memory device 604 and a host device 608. Consistent with embodiments of the present disclosure, the 3D memory device 604 may include a plurality of conductive interconnects passing through the cover layer, the plurality of conductive interconnects contacting the conductive pads in the conductive pad layer, and the memory controller 606 may be coupled to the 3D memory device 604 via at least one of the plurality of conductive interconnects. The memory controller 606 is configured to control the 3D memory device 604. For example, the memory controller 606 may be configured to operate the plurality of channel structures 110 via the gate lines 136. The memory controller 606 may manage data stored in the 3D memory device 604 and communicate with the host device 608.

[0104] In some implementations, the memory controller 606 is designed / configured to operate in low-duty-cycle environments, such as secure digital (SD) cards, compact flash (CF) cards, universal serial bus (USB) flash drives, or other media used in electronic devices (such as personal computers, digital cameras, mobile phones, etc.). In some embodiments, the memory controller 606 is designed / configured to operate in high-duty-cycle environments, such as SSDs or embedded multi-media cards (eMMCs), and enterprise storage arrays, which are used as data storage for mobile devices (such as smartphones, tablets, laptops, etc.). The memory controller 606 can be configured to control operations of the 3D memory device 604, such as read, erase, and program (or write) operations. The memory controller 606 can also be configured to manage various functions related to data stored or to be stored in the 3D memory device 604, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc. In some embodiments, the memory controller 606 is further configured to process error correction code (ECC) on data read from or written to the 3D memory device 604. The memory controller 606 may also perform any other suitable functions, such as formatting the 3D memory device 604.

[0105] The memory controller 606 may communicate with an external device (e.g., the host device 608) according to a specific communication protocol. For example, the memory controller 606 may communicate with the external device through at least one of various interface protocols, such as a USB protocol, an MMC protocol, a peripheral component interconnection (PCI) protocol, a PCI express (PCI-E) protocol, an advanced technology attachment (ATA) protocol, a serial ATA protocol, a parallel ATA protocol, a small computer small interface (SCSI) protocol, an enhanced small disk interface (ESDI) protocol, an integrated drive electronics (IDE) protocol, a FireWire protocol, and the like.

[0106] The memory controller 606 and one or more 3D memory devices 604 can be integrated into various types of storage devices, for example, included in the same package, such as a universal flash storage (UFS) package or an eMMC package. In other words, the storage system 602 can be implemented and packaged into different types of terminal electronic products. Figure 6 In one example shown, a memory controller 606 and a single 3D memory device 604 may be integrated into a memory card 602. The memory card 602 may include a PC card (PCMCIA, personal computer memory card international association), a CF card, a smart media (SM) card, a memory stick, a multimedia card (MMC, RS-MMC, MMCmicro), an SD card (SD, miniSD, microSD, SDHC), a UFS, and the like.

[0107] The subject matter described in this disclosure and the implementation of the actions and operations can be implemented in digital electronic circuitry, tangibly embodied computer software or firmware, computer hardware, including the structures disclosed in this disclosure and their structural equivalents, or in a combination of one or more of them. The implementation of the subject matter described in this disclosure can be implemented as one or more computer programs, for example, one or more modules of computer program instructions encoded on a computer program carrier, for execution by a data processing device or to control the operation of the data processing device. The carrier can be a tangible, non-transitory computer storage medium. Alternatively, or in addition, the carrier can be an artificially generated propagated signal, for example, a machine-generated electrical, optical, or electromagnetic signal, which is generated to encode information for transmission to a suitable receiver device for execution by the data processing device. The computer storage medium can be a machine-readable storage device, a machine-readable storage substrate 102, a random or serial access memory device, or a combination of one or more of them, or a portion thereof. A computer storage medium is not a propagated signal.

[0108] It should be noted that references in this disclosure to "one embodiment," "an embodiment," "an example embodiment," "some embodiments," "some implementations," etc., indicate that the described embodiments may include a particular feature, structure, or characteristic, but not every embodiment necessarily includes the particular feature, structure, or characteristic. Furthermore, such phrases do not necessarily refer to the same embodiment. Furthermore, when a particular feature, structure, or characteristic is described in conjunction with an embodiment, whether or not explicitly described, it is within the knowledge of a person skilled in the relevant art to affect such feature, structure, or characteristic in conjunction with other implementations.

[0109] In general, terms can be understood, at least in part, from usage in context. For example, as used herein, the term "one or more" can be used to describe any feature, structure, or characteristic in the singular, or can be used to describe a combination of features, structures, and characteristics in the plural, depending, at least in part, on the context. Similarly, terms such as "a," "an," or "the" can be understood to convey the singular or to convey the plural, depending, at least in part, on the context. Furthermore, the term "based on" can be understood to not necessarily be intended to convey an exclusive set of factors, and to the contrary, can allow for the presence of additional factors that are not necessarily explicitly described, again, depending, at least in part, on the context.

[0110] It should be readily understood that the meanings of “on,” “over,” and “over” in this disclosure should be interpreted in the broadest manner, such that “on” not only means “directly on something,” but also includes the meaning of “on something” with intervening features or layers therebetween. Furthermore, “over,” or “over…” not only means “over something” or “on something,” but also includes the meaning of “over something” or “over something” with no intervening features or layers therebetween (i.e., directly on something).

[0111] Additionally, for ease of description, spatially relative terms, such as "below," "beneath," "lower," "above," "upper," and the like, may be used herein to describe the relationship of one element or feature to another element(s) or feature(s) as shown in the figures. Spatially relative terms are intended to encompass different orientations of the device in use or process steps other than the orientation shown in the figures. The device may be otherwise oriented (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein should be interpreted accordingly.

[0112] As used herein, the term "substrate" refers to a material to which subsequent layers of material are added. A substrate includes a "top" surface and a "bottom" surface. The top surface of a substrate is typically where semiconductor devices are formed, and therefore, unless otherwise specified, semiconductor devices are formed on the top side of the substrate. The bottom surface is opposite the top surface, and therefore, the bottom side of the substrate is opposite the top side of the substrate. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include a wide range of semiconductor materials, such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material, such as glass, plastic, or a sapphire wafer.

[0113] As used herein, the term "layer" refers to a material portion including an area with thickness. The layer has a top side and a bottom side, wherein the bottom side of the layer is relatively close to the substrate, and the top side is relatively far away from the substrate. The layer can extend over the entire underlying or overlying structure, or can have a range that is smaller than the range of the underlying or overlying structure. In addition, a layer can be an area of ​​a uniform or uneven continuous structure, the thickness of which is less than the thickness of the continuous structure. For example, a layer can be located between or between any set of horizontal planes between the top surface and the bottom surface of the continuous structure. The layer can extend horizontally, vertically and / or along a tapered surface. The substrate can be a layer, can include one or more layers therein, and / or can have one or more layers on, above and / or below it. The layer can include multiple layers. For example, an interconnect layer can include one or more conductive and contact layers (wherein contact portions, interconnect lines and / or vertical interconnect accesses (VIAs) are formed) and one or more dielectric layers.

[0114] As used herein, the term "nominal / nominally" refers to an expected or target value for a characteristic or parameter of a component or process step that is set during the design phase of a product or process, as well as a range of values ​​above and / or below the expected value. As used herein, a range of values ​​may be due to slight variations in manufacturing processes or tolerances. As used herein, the term "approximately" refers to a value of a given quantity that may vary based on a particular technology node associated with the subject semiconductor device. Based on a particular technology node, the term "approximately" may refer to a value of a given quantity that varies within a range of, for example, 10-30% of that value (e.g., ±10%, ±20%, or ±30% of that value).

[0115] In this disclosure, the term “horizontal / horizontally / lateral / laterally” refers to the finger nominally parallel to the lateral surface of the substrate, and the term “vertical” or “vertically” refers to the finger nominally orthogonal to the lateral surface of the substrate.

[0116] As used herein, the term "3D memory" refers to a three-dimensional (3D) semiconductor device having a vertically oriented string of memory cell transistors (referred to herein as a "memory string," such as a NAND string) on ​​a laterally oriented substrate, such that the memory string extends in a vertical direction relative to the substrate.

[0117] The present disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify the present disclosure. Of course, these are merely examples and are not limiting. For example, in the description below, forming a first feature above or on a second feature may include embodiments in which the first feature and the second feature may be in direct contact, and may also include embodiments in which additional features may be formed between the first feature and the second feature so that the first feature is not in direct contact with the second feature. In addition, the present disclosure may repeat reference numbers and / or letters in various examples. Such repetition is for simplicity and clarity and does not, in itself, dictate the relationship between the various embodiments and / or configurations discussed.

[0118] The foregoing description of specific embodiments can be readily modified and / or adapted to various applications. Therefore, such adaptations and modifications are intended to be within the meaning and range of equivalents of the disclosed embodiments, based on the teaching and guidance presented herein.

[0119] Although this disclosure contains many specific implementation details, these should not be interpreted as limitations on the scope of what is claimed as defined by the claims themselves, but rather as descriptions of features that may be specific to a particular implementation of a particular invention. Certain features described in this disclosure in the context of separate implementations may also be implemented in combination in a single embodiment. Conversely, various features described in the context of a single embodiment may also be implemented in multiple implementations, either individually or in any suitable subcombination. Furthermore, although features may be described above as functioning in certain combinations and even initially claimed, in some cases one or more features from a claimed combination may be deleted from that combination, and the claim may be directed to a subcombination or variant of a subcombination.

[0120] Similarly, although operations are described in the drawings and recited in the claims in a particular order, this should not be construed as requiring that such operations be performed in the particular order or sequential order shown, or that all illustrated operations be performed, in order to achieve the desired result. In certain circumstances, multitasking and parallel processing may be advantageous. Furthermore, the separation of various system modules and components in the above-described embodiments should not be construed as requiring such separation in all embodiments, and it should be understood that the described program components and systems may generally be integrated together in a single software product or packaged into multiple software products.

[0121] Specific embodiments of the subject matter have been described. Other embodiments are also within the scope of the following claims. For example, the actions recited in the claims can be performed in a different order and still achieve the desired results. As an example, the processes depicted in the accompanying drawings do not necessarily require the particular order or sequential sequence shown to achieve the desired results. In some cases, multitasking and parallel processing may be advantageous.

[0122] The breadth and scope of the present disclosure should not be limited by any of the above-described exemplary embodiments, but should be defined only in accordance with the following claims and their equivalents.

Claims

1. A semiconductor device comprising: A stacked structure comprising at least one gate line, wherein the at least one gate line comprises a first material; a select gate layer, wherein the select gate layer comprises a second material different from the first material; and At least one channel structure extends along a first axis through the stacked structure and the select gate layer, wherein each of the at least one channel structure comprises a layered structure.

2. The semiconductor device according to claim 1, wherein The second material includes doped polysilicon.

3. The semiconductor device according to claim 1 or 2, wherein The layered structure includes a blocking layer, a charge trapping layer, a dielectric layer and a semiconductor channel layer, wherein the semiconductor channel layer contacts the dielectric layer and is laterally surrounded by the dielectric layer, wherein the dielectric layer contacts the charge trapping layer and is laterally surrounded by the charge trapping layer, and The charge capture layer is in contact with the blocking layer and is laterally surrounded by the blocking layer.

4. The semiconductor device according to claim 3, wherein The blocking layer includes silicon oxide, the charge trapping layer includes silicon nitride, the dielectric layer includes silicon oxide, and the semiconductor channel layer includes doped polysilicon.

5. The semiconductor device according to claim 1 , further comprising a select gate cut structure, the select gate cut structure extending through the select gate layer along the first axis and configured to divide the select gate layer into a plurality of isolated portions, wherein The select gate cutting structure contacts one or more channel structures of the at least one channel structure. The semiconductor device according to claim 5 , wherein: The selection gate cutting structure has a straight line shape or a wavy shape in a first plane of the semiconductor device, wherein the first plane is orthogonal to the first axis.

7. The semiconductor device according to claim 3, wherein Each of the at least one channel structure includes a channel plug, and The channel plug and the layered structure are stacked together along the first axis, the channel plug is in contact with the semiconductor channel layer, and a width of the channel plug is greater than a width of the semiconductor channel layer.

8. The semiconductor device according to claim 7, wherein The width of the trench plug is a dimension along a second axis, wherein the second axis is orthogonal to the first axis.

9. A semiconductor device comprising: A stacked structure comprising at least one gate line; select gate layer; at least one channel structure extending through at least the stacked structure along a first axis, each of the at least one channel structure comprising: A layered structure comprising a blocking layer, a charge trapping layer, a dielectric layer, and a semiconductor channel layer, and a channel plug, wherein the channel plug and the layered structure are stacked together along the first axis, wherein the channel plug is in contact with the semiconductor channel layer, and wherein the channel plug is at least partially in contact with a channel contact; and A select gate cutting structure extends through at least the select gate layer along the first axis and is configured to divide the select gate layer into a plurality of isolated portions, wherein the select gate cutting structure contacts one or more of the at least one channel structure.

10. The semiconductor device according to claim 9, wherein The first material of the select gate layer is different from the second material of the at least one gate line. The semiconductor device according to claim 10 , wherein: The first material of the select gate layer includes doped polysilicon, and the second material of the at least one gate line includes tungsten.

12. The semiconductor device according to any one of claims 9 to 11, wherein The at least one channel structure extends through the stacked structure and the select gate layer along the first axis, and wherein the blocking layer comprises silicon oxide, the charge trapping layer comprises silicon nitride, the dielectric layer comprises silicon oxide, and the semiconductor channel layer comprises doped polysilicon.

13. The semiconductor device according to any one of claims 9 to 12, wherein The width of the channel plug is greater than the width of the semiconductor channel layer.

14. The semiconductor device according to any one of claims 9 to 13, wherein The selection gate cutting structure has a straight line shape or a wavy shape in a first plane of the semiconductor device, wherein the first plane is orthogonal to the first axis.

15. A method for forming a semiconductor device, comprising: forming a stack structure including a plurality of insulating layers along a first axis; forming a select gate layer; forming at least one channel structure extending along the first axis through the stacked structure and the select gate layer, wherein each of the at least one channel structure comprises: A layered structure comprising a blocking layer, a charge trapping layer, a dielectric layer, and a semiconductor channel layer; and a select gate cut structure formed extending through at least the select gate layer, the select gate cut structure being configured to divide the select gate layer into a plurality of isolated portions.

16. The method for forming a semiconductor device according to claim 15, wherein: The stack structure further includes a plurality of sacrificial layers interleaved with the plurality of insulating layers, and wherein the method further includes replacing the plurality of sacrificial layers with a plurality of conductive layers.

17. The method for forming a semiconductor device according to claim 16, wherein: The first material of the select gate layer is different from the second material of the plurality of conductive layers.

18. The method for forming a semiconductor device according to any one of claims 15 to 17, wherein: Each of the at least one channel structure further includes a channel plug, wherein the channel plug and the layered structure are stacked together along the first axis, wherein the channel plug contacts the semiconductor channel layer, and Wherein, the width of the channel plug is greater than the width of the semiconductor channel layer.

19. The method for forming a semiconductor device according to any one of claims 15 to 18, wherein: The select gate cutting structure contacts one or more channel structures of the at least one channel structure.

20. The method for forming a semiconductor device according to any one of claims 15 to 19, wherein: The selection gate cutting structure has a straight line shape or a wavy shape in a first plane of the semiconductor device, wherein the first plane is orthogonal to the first axis.

Images