Semiconductor structure and forming method thereof

Abstract

A method of forming a semiconductor structure includes providing a substrate having a plurality of active regions, and forming a first gate layer on the active regions of the substrate. The method further includes conformally forming an inter-gate dielectric layer over the substrate and the first gate layers, the inter-gate dielectric layer forming a first opening between the first gate layers. The method further includes forming a second gate layer on the inter-gate dielectric layer, the second gate layer filling the first opening, and forming a patterned photoresist layer on the second gate layer. The method further includes taking the patterned photoresist layer as a mask, patterning the second gate layer to form a second opening, the second opening being located directly above the first opening, and patterning the second gate layer, the inter-gate dielectric layer, and the first gate layer to form a word line structure on the substrate.

Description

Technical Field

[0001] The present invention relates to a method for forming a semiconductor structure, and in particular to a method for forming a flash memory structure. Background Art

[0002] Memory devices can generally be divided into two categories: volatile memory and non-volatile memory. Volatile memory requires a continuous power supply to maintain and retain the data within the memory, while non-volatile memory retains the data within the memory even if the system power is interrupted. Non-volatile memory includes one-time programmable devices (such as electronic programmable read-only memory (EPROM)) or re-programmable devices (such as electronic erasable read-only memory (EEPROM)). Among various non-volatile memories, flash memory is the most quickly writeable and erasable.

[0003] To increase device density and improve overall performance within flash memory devices, manufacturing technology continues to strive towards device miniaturization, presenting numerous challenges. For example, due to variations in environmental structure, incomplete etching of the conductive layer during the etching process used to pattern the memory device's wordline structure can result in short circuits between wordlines. Furthermore, over-etching of the conductive layer can damage the sidewalls of the wordline structure, leading to reliability issues for the memory device. Therefore, the industry continues to need improvements in flash memory device manufacturing methods to maintain memory yield. Summary of the Invention

[0004] An embodiment of the present invention provides a method for forming a semiconductor structure, comprising providing a substrate having multiple active areas; forming a first gate layer on the active area of ​​the substrate; conformably forming an intergate dielectric layer on the substrate and the first gate layer, wherein the intergate dielectric layer forms a first opening between the first gate layer; forming a second gate layer on the intergate dielectric layer, wherein the second gate layer fills the first opening; forming a patterned photoresist layer on the second gate layer; using the patterned photoresist layer as a mask, patterning the second gate layer to form a second opening, wherein the second opening is located directly above the first opening; and patterning the second gate layer, the intergate dielectric layer, and the first gate layer to form a word line structure on the substrate.

[0005] An embodiment of the present invention further provides a semiconductor structure comprising a substrate including a plurality of active regions and a plurality of isolation structures arranged in an alternating manner, wherein the top surface of the isolation structure is higher than the top surface of the active region; and a word line structure including a floating gate formed on each active region of the substrate; an intergate dielectric layer conformally covering the floating gate and the substrate; and a control gate formed above the floating gate and separated from the floating gate by the intergate dielectric layer, wherein the word line structure has a plurality of protrusions formed correspondingly above each active region.

[0006] In summary, compared to conventional word line structure formation processes, the embodiments of the present invention effectively avoid the possibility that the second gate layer may undesirably remain in the first opening by pre-etching the second gate layer after forming the second opening, thereby reducing incomplete etching of the first gate layer, the intergate dielectric layer, and the second gate layer, further avoiding short circuits in the word line structure and reducing the occurrence of excessive damage to the sidewalls of the word line structure during the etching process, thereby maintaining the yield and performance of the memory device. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figures 1 to 5 FIG. 1 is a perspective view illustrating an intermediate stage of forming a semiconductor structure according to an embodiment of the present invention.

[0008] Figures 6 and 7 FIG. 1 is a schematic cross-sectional view of a semiconductor structure according to an embodiment of the present invention.

[0009] Reference numerals:

[0010] 10: Semiconductor structure

[0011] 100:Substrate

[0012] 105: Active area

[0013] 105s: top surface

[0014] 110: Lining

[0015] 115: Isolation Structure

[0016] 115s: top surface

[0017] 120, 120': first gate layer

[0018] 120s: top surface

[0019] 125, 125': inter-gate dielectric layer

[0020] 130: First Opening

[0021] 135, 135': second gate layer

[0022] 140: Patterned photoresist layer

[0023] 145: Second opening

[0024] 150: mask layer

[0025] 155: Oxide layer

[0026] 160: core shaft layer

[0027] 165: Covering layer

[0028] 170: word line structure

[0029] 175: protrusion

[0030] D1, D2: Depth

[0031] S1, S2: Spacing

[0032] W1, W2, W3, W4: width

[0033] W5: Top width

[0034] X: first direction

[0035] Y: Second direction

[0036] Z: Third direction DETAILED DESCRIPTION

[0037] Figure 1 FIG1 is a perspective diagram illustrating a semiconductor structure 10 according to an embodiment of the present invention. A substrate 100 includes a plurality of active regions 105, a liner 110, and a plurality of isolation structures 115. An appropriate etching process is performed on the substrate 100 to etch isolation trenches and define the plurality of active regions 105. Subsequently, a liner 110 is formed to cover the sidewalls and bottom surfaces of the active regions 105 and the isolation trenches. The liner 110 on the top surface of the active regions 105 serves as a tunnel oxide layer for the memory device. In some embodiments, the liner 110 is formed of silicon oxide.

[0038] Next, a first gate layer 120 can be formed on the substrate 100. The first gate layer 120 can subsequently serve as a floating gate of the semiconductor structure. In some embodiments, a conductive layer (not shown) can be formed on the substrate 100 using a deposition process such as chemical vapor deposition, other suitable processes, or a combination thereof, and isolation trenches can be exposed using a suitable etching process to form the first gate layer 120. More specifically, the first gate layer 120 is formed on each active region 105 of the substrate 100. In some embodiments, the material of the first gate layer 120 can include doped polysilicon, undoped polysilicon, metal, polycide, or a combination thereof.

[0039] Subsequently, a spin-on coating process, chemical vapor deposition process, atomic layer deposition process, other suitable processes, or a combination thereof is performed to deposit an insulating material layer (not shown), and a suitable etching process is performed to form the isolation structure 115. The isolation structure 115 is located between the active regions 105, and the active regions 105 and the isolation structure 115 are arranged in an alternating manner. In some embodiments, the top surface 115s of the isolation structure 115 is higher than the top surface 105s of the active region 105, and the top surface 115s of the isolation structure 115 is lower than the top surface 120s of the first gate layer 120, effectively reducing leakage current that may occur between different active regions 105. The liner 110 is located between the substrate 100 and the isolation structure 115.

[0040] See also Figure 1 An intergate dielectric layer 125 is conformally formed on the substrate 100 and the first gate layer 120. The intergate dielectric layer 125 conformally covers the sidewalls and top surface 120s of the first gate layer 120, as well as the top surface 115s of the isolation structure 115. Since the first gate layer 120 is formed on each active region 105, the intergate dielectric layer 125 forms a first opening 130 between the first gate layers 120. The intergate dielectric layer 125 includes a composite layer composed of oxide / nitride / oxide (ONO), but the present invention is not limited thereto. The composite layer may also include five or more film layers.

[0041] See also Figure 1A second gate layer 135 is formed on the intergate dielectric layer 125, and the second gate layer 135 fills the first opening 130. The second gate layer 135 can subsequently serve as a control gate of the semiconductor structure. In some embodiments, the second gate layer 135 can be formed by a deposition process such as chemical vapor deposition, other suitable processes, or a combination thereof. In some embodiments, the material of the second gate layer 135 can include doped polysilicon, undoped polysilicon, metal, polysilicide, or a combination thereof.

[0042] Figure 2 FIG2 is a perspective view illustrating forming a patterned photoresist layer 140 on the semiconductor structure 10 according to an embodiment of the present invention. After forming the second gate layer 135, the patterned photoresist layer 140 is formed on the second gate layer 135. The patterned photoresist layer 140 is formed only above the first gate layer 120. In other words, the patterned photoresist layer 140 partially overlaps the active region 105, and a spacing S1 between the patterned photoresist layer 140 is greater than the width W1 of the first opening 130.

[0043] Figure 3 FIG1 is a perspective view of the semiconductor structure 10 after etching the second gate layer 135 according to an embodiment of the present invention. After forming a patterned photoresist layer 140, the second gate layer 135 is patterned using the patterned photoresist layer 140 as a mask to form a second opening 145. The second opening 145 is located directly above the first opening 130. Using the patterned photoresist layer 140 as a mask, the second gate layer 135 is pre-etched to form the second opening 145 directly above the first opening 130 (i.e., the portion of the second gate layer 135 directly above the first opening 130 is pre-etched). This allows the subsequent wordline structure etching process to completely remove the portion of the second gate layer 135 that fills the first opening 130, thus preventing wordline short circuits in the memory device caused by incomplete etching. The width W2 of the second opening 145 is greater than the width W1 of the first opening 130. The depth D1 of the first opening 130 is greater than the depth D2 of the second opening 145. The ratio or relative relationship between the widths of the first opening 130 and the second opening 145 can be adjusted or varied according to different designs. For example, if the first opening 130 is deeper, the second opening 145 can be further deepened to ensure that the relevant film layer can be completely etched. After forming the second opening 145, the patterned photoresist layer 140 can be removed by, for example, etching, stripping, ashing, or a combination thereof.

[0044] Figure 4FIG1 is a perspective view illustrating the formation of a mask layer 150 on the semiconductor structure 10 according to an embodiment of the present invention. The mask layer 150 is formed on the second gate layer 135 and fills the second opening 145. The mask layer 150 is subsequently patterned by a related photolithography process and serves as a mask for patterning the second gate layer 135, the intergate dielectric layer 125, and the first gate layer 120. In some embodiments, the mask layer 150 may further include an oxide layer 155, a mandrel layer 160, and a capping layer 165. A photoresist pattern (not shown) is first formed on the mask layer 150 by optical lithography and etching processes. The photoresist pattern is then transferred to the mask layer 150 by an etching process to form a mask for patterning the wordline structure 170 (described in detail below). In some embodiments, similar to the step of forming the patterned photoresist layer 140, the photoresist pattern can be formed by a photolithography process (e.g., optical lithography or electron beam lithography) and then etched by an etching process, which will not be repeated here. In some embodiments, the mask layer 150 can be formed by processes such as chemical vapor deposition (CVD), atomic layer deposition (ALD), or a combination thereof. In some embodiments, the material of the oxide layer 155 can include an oxide formed with tetraethylorthosilicate (TEOS). The material of the mandrel layer 160 can include carbon. The material of the cap layer 165 can include silicon oxynitride (SiON), a bottom anti-reflective coating (BARC), or a combination thereof.

[0045] Figure 5FIG1 is a perspective view illustrating the formation of a wordline structure 170 according to an embodiment of the present invention. After patterning the mask layer 150 (not shown), an etching process is performed using the patterned mask layer 150 as a mask to sequentially pattern the second gate layer 135, the intergate dielectric layer 125, and the first gate layer 120 to form the wordline structure 170 on the substrate 100. The second gate layer 135 is patterned first, and the intergate dielectric layer 125 serves as an etch stop layer for patterning the second gate layer 135 due to differences in etching selectivity. Subsequently, the intergate dielectric layer 125 and the first gate layer 120 are sequentially etched in the same manner. From bottom to top in the third direction Z, the wordline structure 170 includes a first gate layer 120' (serving as the floating gate of the memory device), an intergate dielectric layer 125', and a second gate layer 135' (serving as the control gate of the memory device). The control gate (second gate layer 135') is formed above the floating gate (first gate layer 120') and separated from the floating gate (first gate layer 120') by the intergate dielectric layer 125'. Due to the formation of the second opening 145, the wordline structure 170 has a plurality of protrusions 175 formed above each active area 105. The width W3 of each protrusion 175 is less than or equal to the width W4 of each active area 105.

[0046] Figure 6 FIG. 1 is a schematic cross-sectional view of a semiconductor structure 10 in a first direction X (a plane between the first direction X and the third direction Z) according to an embodiment of the present invention. Figure 7 According to an embodiment of the present invention, a cross-sectional view of the semiconductor structure 10 in the second direction Y (the second direction Y-third direction Z plane) is shown. Figures 5 to 7 As shown, the word line structure 170 extends along a first direction X, and the active area 105 extends along a second direction Y. The first direction X intersects the second direction Y, and the first direction X, the second direction Y, and the third direction Z intersect each other. The protrusions 175 extend along the second direction Y and are arranged in the first direction X. Figure 6 As shown, due to the formation of the second opening 145 and the protrusion 175, the word line structure 170 is crown-shaped in a cross-sectional view along the first direction X. Figure 7As shown, the formation of the second opening 145 allows for pre-etching of a portion of the second gate layer 135. This eliminates the need for increased etching intensity (i.e., over-etching) during the etching process for patterning the wordline structure 170 to reduce short circuits caused by incomplete etching. Consequently, the wordline structure 170 can maintain an ideal rectangular shape in a cross-sectional view taken along the second direction Y. The spacing S2 between the protrusions 175 is greater than the top width W5 of each isolation structure 115. After forming the wordline structure 170, semiconductor processes such as deposition, photolithography, and etching can be performed to form other components of the memory device, which will not be further described herein.

[0047] In summary, compared to conventional word line structure formation processes, the embodiments of the present invention effectively avoid the possibility that the second gate layer may undesirably remain in the first opening by pre-etching the second gate layer after forming the second opening, thereby reducing incomplete etching of the first gate layer, the intergate dielectric layer, and the second gate layer, further avoiding short circuits in the word line structure and reducing the occurrence of excessive damage to the sidewalls of the word line structure during the etching process, thereby maintaining the yield and performance of the memory device.

[0048] The above overview of the features of the various embodiments is intended to enable those skilled in the art to understand that other processes and structures can be easily designed or modified based on the various embodiments to achieve the same objectives and / or advantages, and that various changes, substitutions, and replacements can be made without departing from the spirit and scope of the present invention. Therefore, the scope of protection of the present invention shall be determined by the scope defined in the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate having a plurality of active regions; forming a first gate layer on the plurality of active regions of the substrate; Conformably forming an inter-gate dielectric layer on the substrate and the first gate layer, wherein the inter-gate dielectric layer forms a first opening between the first gate layers; forming a second gate layer on the inter-gate dielectric layer, wherein the second gate layer fills the first opening; forming a patterned photoresist layer on the second gate layer; Using the patterned photoresist layer as a mask, patterning the second gate layer to form a second opening, wherein the second opening is located directly above the first opening; as well as The second gate layer, the intergate dielectric layer, and the first gate layer are patterned to form a word line structure on the substrate.

2. The method for forming a semiconductor structure according to claim 1, wherein: The substrate includes a plurality of isolation structures between the plurality of active regions, wherein top surfaces of the plurality of isolation structures are higher than top surfaces of the plurality of active regions and lower than a top surface of the first gate layer, wherein a liner is provided between the substrate and the plurality of isolation structures.

3. The method for forming a semiconductor structure according to claim 1, wherein: The word line structure has a plurality of protrusions formed correspondingly above the plurality of active regions, wherein the width of each protrusion is less than or equal to the width of each active region.

4. The method for forming a semiconductor structure according to claim 1, wherein: The width of the second opening is greater than the width of the first opening.

5. The method for forming a semiconductor structure according to claim 1, wherein: The depth of the first opening is greater than the depth of the second opening.

6. The method for forming a semiconductor structure according to claim 1, wherein: The step of patterning the second gate layer, the intergate dielectric layer, and the first gate layer further includes: forming a mask layer on the second gate layer and filling the second opening; and An etching process is performed to sequentially pattern the second gate layer, the intergate dielectric layer, and the first gate layer to form the word line structure.

7. A semiconductor structure, characterized in that include: A substrate comprising a plurality of active regions and a plurality of isolation structures arranged in a staggered manner, wherein top surfaces of the plurality of isolation structures are higher than top surfaces of the plurality of active regions; as well as One-line structure, including: a floating gate formed on each of the active regions of the substrate; an inter-gate dielectric layer conformably covering the floating gate and the substrate; and a control gate formed above the floating gate and separated from the floating gate by the intergate dielectric layer; The word line structure has a plurality of protrusions formed correspondingly above each of the active regions.

8. The semiconductor structure according to claim 7, wherein: Top surfaces of the plurality of isolation structures are lower than a top surface of the floating gate.

9. The semiconductor structure according to claim 7, wherein: The width of each protrusion is smaller than or equal to the width of each active region.

10. The semiconductor structure according to claim 7, wherein: The word line structure extends along a first direction, the active regions extend along a second direction, the first direction intersects the second direction, and the protrusions extend along the second direction and are arranged in the first direction.

11. The semiconductor structure according to claim 7, wherein: The intervals between the plurality of protrusions are greater than the top width of each isolation structure.

12. The semiconductor structure according to claim 7, wherein: A liner is provided between the substrate and the plurality of isolation structures.

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