A semiconductor device and its fabrication method

Abstract

This invention discloses a semiconductor device and its fabrication method, belonging to the field of semiconductor technology. The fabrication method includes: providing a substrate having a well region therein; forming a photoresist pattern on the well region and using it as a mask; implanting ions into the well region to form a pair of first lightly doped regions spaced apart by the well region; forming a gate structure on the substrate between the pair of first lightly doped regions; using the gate structure as a mask, implanting ions into the first lightly doped regions to form a pair of second lightly doped regions spaced apart by the well region, wherein the orthographic projection of the gate structure on the substrate surface partially overlaps with the second lightly doped regions; forming a sidewall structure on the sidewall of the gate structure; and using the sidewall structure and the gate structure as masks, implanting ions into the second lightly doped regions to form a source region and a drain region. The semiconductor device and its fabrication method provided by this invention can avoid device performance degradation caused by light doping offset, reduce gate-induced drain leakage current, and improve semiconductor device performance.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor technology, and specifically relates to a semiconductor device and its fabrication method. Background Technology

[0002] As the integration density of semiconductor devices continues to increase, the feature size of transistors gradually decreases, and the channel length of transistors also gradually decreases. Semiconductor devices are prone to short-channel effect and hot carrier injection (HCI) effect. Both short-channel effect and hot carrier injection effect can cause transistors to turn on prematurely.

[0003] To prevent transistor performance degradation caused by hot carrier injection, the current approach involves forming a lightly doped drain (LDD) region before the source and drain electrodes to mitigate the electric field between the channel and drain regions. However, during the formation of the LDD region, injected ions can easily penetrate the gate structure and enter the channel region. While forming the LDD region before the gate structure is possible, it can also lead to a misalignment between the LDD region and the gate structure, resulting in a shift in electrical performance. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and its fabrication method. The semiconductor device and its fabrication method provided by this invention can avoid the performance degradation caused by light doping offset, reduce gate-induced drain leakage current, improve the energy efficiency, stability and reliability of semiconductor devices, extend the service life of semiconductor devices, and reduce maintenance costs.

[0005] To address the aforementioned technical problems, this invention provides a method for fabricating a semiconductor device, comprising the following steps:

[0006] A substrate is provided, and a well region is formed within the substrate;

[0007] A photoresist pattern is formed on the well region;

[0008] Using a photoresist pattern as a mask, ions are implanted into the well region to form a pair of first lightly doped regions spaced apart by the well region;

[0009] A gate structure is formed on the substrate between a pair of first lightly doped regions;

[0010] Using the gate structure as a mask, ions are implanted into the first lightly doped region to form a pair of second lightly doped regions spaced apart by the well region. The orthogonal projection of the gate structure onto the substrate surface partially overlaps with the second lightly doped region, with a set overlap size.

[0011] A sidewall structure is formed on the sidewall of the gate structure;

[0012] Using the sidewall structure and the gate structure as masks, ions are implanted into the second lightly doped region to form the source region and the drain region.

[0013] In one embodiment of the present invention, the manufacturing method includes:

[0014] An oxide film is formed on the substrate, and a photoresist pattern is formed on the oxide film;

[0015] Tilted ion implantation is performed on the well regions on both sides of the photoresist pattern to form a pair of first lightly doped regions;

[0016] The photoresist pattern is removed, a polycrystalline silicon film is formed on the oxide film, and the gate structure and gate oxide layer are formed through photolithography and etching processes; and

[0017] Using the gate structure as a mask, tilted ion implantation is performed on the first lightly doped regions on both sides of the gate structure to form the second lightly doped region.

[0018] In one embodiment of the present invention, the implantation angle when forming the second lightly doped region is smaller than the implantation angle when forming the first lightly doped region.

[0019] In one embodiment of the present invention, the photomask used in the photolithography process is the same as the photomask used to form the photoresist pattern.

[0020] In one embodiment of the present invention, the source region and the drain region are formed by vertical ion implantation, and the depth of the source region and the drain region is greater than the depth of the first lightly doped region.

[0021] In one embodiment of the present invention, the depth of the first lightly doped region is greater than the thickness of the gate structure, and the depth of the second lightly doped region is less than the thickness of the gate structure.

[0022] In one embodiment of the present invention, the orthographic projection of the gate structure onto the substrate surface partially coincides with the second lightly doped regions on both sides, and the overlap size between the two second lightly doped regions and the gate structure is equal.

[0023] In one embodiment of the present invention, the distance separating the well regions between a pair of first lightly doped regions is less than the distance separating the well regions between a pair of second lightly doped regions.

[0024] The present invention also provides a semiconductor device comprising at least:

[0025] A substrate, wherein a well region is disposed therein;

[0026] A pair of first lightly doped regions are spaced apart within the well region;

[0027] A gate structure is disposed on the substrate between adjacent first lightly doped regions;

[0028] A pair of second lightly doped regions are disposed at intervals within the first lightly doped regions on both sides of the gate structure;

[0029] Sidewall structures are disposed on both sides of the gate structure; and

[0030] The source region and drain region are respectively disposed in the second lightly doped region on both sides of the gate structure.

[0031] In one embodiment of the present invention, the gate structure at least covers a portion of the first lightly doped region on one side.

[0032] In summary, this invention provides a semiconductor device and its fabrication method. Through improvements to the semiconductor device and its fabrication method, the unexpected technical effect of this application is that it can compensate for the problem of misalignment between the lightly doped region and the gate structure caused by the initial formation of a lightly doped region, thereby improving the performance of the semiconductor device. It effectively reduces the electric field near the source and drain, thus reducing the probability of high-energy carrier generation in the source and drain regions, reducing the risk of hot carrier effects, and helping to reduce leakage current near the source and drain, improving the device's performance and reliability. It avoids device performance degradation caused by light doping misalignment, reduces gate-induced drain leakage current, improves the energy efficiency, stability, and reliability of the semiconductor device, extends its lifespan, and reduces maintenance costs. The second lightly doped region can reduce the electrical characteristic shift caused by misalignment when the gate structure and the first lightly doped region are misaligned, and the dopant ions in the lightly doped region will not penetrate the gate structure into the channel region, thereby improving the conductivity, threshold voltage, stability, and reliability of the semiconductor device.

[0033] Of course, any product implementing this invention does not necessarily need to achieve all of the advantages described above at the same time. Attached Figure Description

[0034] To more clearly illustrate the technical solutions of the embodiments of the present invention, the accompanying drawings used in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0035] Figure 1 This is a cross-sectional schematic diagram of a semiconductor device according to an embodiment of the present invention.

[0036] Figure 2 This is a cross-sectional schematic diagram of a semiconductor device according to another embodiment of the present invention.

[0037] Figure 3 This is a schematic diagram of a well region formed in a substrate according to an embodiment of the present invention.

[0038] Figure 4 This is a schematic diagram of the formation of a first lightly doped region in one embodiment of the present invention.

[0039] Figure 5 This is a schematic diagram of a gate structure formed in one embodiment of the present invention.

[0040] Figure 6 This is a schematic diagram of the formation of a second lightly doped region in one embodiment of the present invention.

[0041] Figure 7 This is a schematic diagram of the formation of the source region and the drain region in one embodiment of the present invention.

[0042] Figure 8 This is a schematic diagram showing the relationship between the position offset and the turn-off current ratio in Example 1 and Comparative Example 1.

[0043] Figure 9 This is a schematic diagram of the simulation results of the inter-band channel current intensity distribution in Example 1 and Comparative Example 1.

[0044] Figure 10 This is a schematic diagram showing the intensity of the inter-channel current in Example 1 and Comparative Example 1.

[0045] Figure 11 This is a schematic diagram showing the concentration ratio of the lightly doped region in the examples and comparative examples. Detailed Implementation

[0046] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0047] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein in the specification of this application is for the purpose of describing particular embodiments only and is not intended to be limiting of this application.

[0048] In the description of this specification, it should be understood that the terms "center," "upper," "lower," "front," "rear," "left," and "right," etc., indicating orientation or positional relationships, are based on the orientation or positional relationships shown in the accompanying drawings and are only for the convenience of describing this solution and simplifying the description, and do not indicate or imply that the device or component referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation on this solution. Furthermore, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0049] Please see Figure 1 As shown, Figure 1 This is a cross-sectional schematic diagram of a semiconductor device 11 according to an embodiment of the present invention. The semiconductor device 11 is, for example, a metal-oxide-semiconductor field-effect transistor (MOSFET), or, for example, a medium-voltage MOS transistor. The semiconductor device 11 is used, for example, in a display driver IC platform and operates at a voltage of 6V to 8V. In this embodiment, the semiconductor device 11 is described using an n-channel MOS transistor (NMOS) as an example.

[0050] Please see Figure 1 As shown, in one embodiment of the present invention, the semiconductor device 11 is disposed, for example, within the well region 14 of the substrate 12, wherein the substrate 12 is, for example, a silicon wafer, and the well region 14 is, for example, a doped region doped with p-type impurities such as boron (B).

[0051] Please see Figure 1 As shown, in one embodiment of the present invention, a shallow trench isolation structure (STI) 13 is provided between adjacent components for insulation between adjacent components, and the material of the shallow trench isolation structure 13 is, for example, silicon oxide. The source region 21, drain region 22, first lightly doped regions 23a, 23b, second lightly doped regions 24a, 24b, and gate oxide layer 16 are surrounded within the shallow trench isolation structure 13.

[0052] Please see Figure 1 As shown, in one embodiment of the present invention, a gate oxide layer 16 and a gate structure 15 are formed on the surface of the well region 14. The gate structure 15 is formed on the gate oxide layer 16, and the material of the gate structure 15 is, for example, polysilicon. The polysilicon is doped with n-type impurities, such as phosphorus (P) or arsenic (As). In other embodiments, the gate structure 15 may also be a structure such as a metal layer, a metal silicide layer, a polysilicon layer and a metal layer stack, or a polysilicon layer and a metal silicide layer stack.

[0053] Please see Figure 1 As shown, in one embodiment of the present invention, the material of the gate oxide layer 16 is, for example, silicon oxide. A sidewall spacer 17 is provided on the side of the gate structure 15 and the gate oxide layer 16, and the sidewall spacer 17 is, for example, one or a stack of silicon oxide or silicon nitride films.

[0054] Please see Figure 1 As shown, in one embodiment of the present invention, a channel region 18 is formed on the surface of the well region 14. The channel region 18 is located below the gate structure 15, and the channel region 18 is doped with, for example, p-type impurities such as boron to adjust the threshold voltage of the semiconductor device 11. The channel region 18 is separated from the gate structure 15 by a gate oxide layer 16. A source region 21 and a drain region 22 are disposed at intervals on both sides of the channel region 18. The source region 21 and the drain region 22 are doped with n-type impurities such as phosphorus or arsenic.

[0055] Please see Figure 1 As shown, in one embodiment of the present invention, a pair of first lightly doped regions, denoted as 23a and 23b, are spaced apart on both sides of the channel region 18. The first lightly doped region 23a is connected to the source region 21, and the first lightly doped region 23b is connected to the drain region 22. The doping type of the first lightly doped regions 23a and 23b is, for example, n-type, and the impurity is, for example, phosphorus. The first lightly doped regions 23a and 23b extend from the surface of the well region 14 into the well region, and extend from the surface of the well region 14 to the junction position with the well region 14. The first lightly doped regions 23a and 23b form a PN junction with the well region 14, that is, the vertical distance in the depth direction is defined as the depth of the first lightly doped region. Wherein, the thickness of the gate structure 15 is denoted as Tg, and the depth of the first lightly doped region in the well region 14 is denoted as Df, then Df>Tg.

[0056] Please see Figure 1As shown, in one embodiment of the present invention, a pair of second lightly doped regions, denoted as 24a and 24b, are spaced apart on both sides of the channel region 18. The second lightly doped region 24a is connected to the source region 21, and the second lightly doped region 24b is connected to the drain region 22. The positions of each second lightly doped region 24a and 24b are determined by a set overlap dimension OL, wherein the set overlap dimension OL is the dimension by which the orthographic projection of the gate structure 15 on the surface of the substrate 12 coincides with the second lightly doped regions 24a and 24b on both sides. In this embodiment, the overlap dimension OL is set to be equal at the two second lightly doped regions 24a and 24b. Since the second lightly doped regions 24a and 24b are formed relative to the gate structure 15, they can be formed by self-alignment. Therefore, the overlap dimension OL of the formed second lightly doped region 24a with the gate structure 15 and the overlap dimension OL of the second lightly doped region 24b with the gate structure 15 are equal. The second lightly doped regions 24a and 24b are connected to their respective first lightly doped regions 23a and 23b. The doping type of the second lightly doped regions 24a and 24b is, for example, n-type, and the impurity is, for example, phosphorus. The second lightly doped regions 24a and 24b extend from the surface of the well region 14 into the well region, and the depth of the second lightly doped region is defined as the vertical distance in the depth direction up to the point where the extension stops. A PN junction is formed between the second lightly doped regions 24a and 24b and the well region 14. The depth of the second lightly doped region within the well region 14 is denoted as Ds. <Tg。

[0057] Please see Figure 1 As shown, in one embodiment of the present invention, before forming the gate structure 15, a pair of first lightly doped regions 23a and 23b are first formed, and the overlap between each of the first lightly doped regions 23a and 23b and the gate structure 15 is greater than the overlap dimension OL. In other words, the distance of the well region 14 separating the pair of first lightly doped regions 23a and 23b is less than the distance of the well region 14 separating the pair of second lightly doped regions 24a and 24b, that is, the distance between the first lightly doped region 23a and the first lightly doped region 23b is less than the distance between the second lightly doped region 24a and the second lightly doped region 24b. By increasing the overlap between the first lightly doped regions 23a and 23b and the gate structure 15, and setting the depth of the first lightly doped regions 23a and 23b to be greater than the thickness of the gate structure 15, the electric field between the source region 21, the drain region 22 and the channel region 18 can be sufficiently mitigated, thereby reducing the probability of high-energy carriers being generated in the source / drain regions, reducing the risk of hot carrier effects, helping to reduce leakage current near the source and drain, and improving the performance and reliability of the device.

[0058] Please see Figure 1As shown, in one embodiment of the present invention, the depths of the source region 21 and the drain region 22 are greater than the depth Df of the first lightly doped regions 23a and 23b, and the depth Df of the first lightly doped regions 23a and 23b is greater than the depth Ds of the second lightly doped regions 24a and 24b.

[0059] Please see Figure 2 As shown, in another embodiment of the present invention, in the semiconductor device 11, due to the misalignment of the photolithography process forming the first lightly doped regions 23a and 23b and the photolithography process forming the gate structure 15, the position of the gate structure 15 is shifted relative to the position of the first lightly doped regions 23a and 23b, that is, the gate structure 15 at least covers a portion of the first lightly doped region on one side. In this case, in the semiconductor device 11, the relative positional relationship between the gate structure 15 and the two second lightly doped regions 24a and 24b, the source region 21, and the drain region 22 remains constant. Therefore, the overlap dimension OL between the second lightly doped region 24a and the gate structure 15, and the overlap dimension OL between the second lightly doped region 24b and the gate structure 15 are equal. Since the source region 21 and the drain region 22 are formed by self-alignment after the gate structure 15 and the sidewall structure 17 are formed, the distance between the source region 21 and the sidewall of the adjacent gate structure 15, and the distance between the drain region 22 and the sidewall of the adjacent gate structure 15, are equal.

[0060] Please see Figures 1 to 2 As shown, in one embodiment of the present invention, by setting the depth Df of the first lightly doped regions 23a and 23b to be greater than the film thickness Tg of the gate structure 15, and by setting the overlap between the first lightly doped regions 23a and 23b and the gate structure 15 to be large, the electric field between the drain region 22 and the channel region 18 can be sufficiently mitigated. However, when the position of the gate structure 15 is shifted relative to the position of the first lightly doped regions 23a and 23b, if the first lightly doped region 23b on the drain region 22 side does not overlap with the gate structure 15, or if the overlap is small, the ion concentration of the lightly doped region in the gate-drain overlap region is significantly reduced. That is, the doping concentration of the region where the gate-induced drain leakage current (GIDL) is generated is low. Therefore, the effect of mitigating the electric field between the drain region 22 and the channel region 18 cannot be fully achieved.

[0061] Please see Figure 2As shown, in another embodiment of the present invention, the second lightly doped regions 24a and 24b, formed by a predetermined overlap size OL, overlap with the gate structure 15. The second lightly doped regions 24a and 24b are formed directly below the boundary between the gate structure 15 and the sidewall structure 17, and are located on the surface of the well region 14. The second lightly doped regions 24a and 24b can serve as GIDL generation regions to suppress GIDL. Even if the depth Ds of the second lightly doped regions 24a and 24b is less than the film thickness Tg of the gate structure 15, the electric field in the GIDL generation region can be mitigated. Since the depth Ds of the second lightly doped regions 24a and 24b is less than the film thickness Tg of the gate structure 15, when ions are self-aligned and implanted to form the second lightly doped regions 24a and 24b after the gate structure 15 is formed, the implanted ions will not penetrate the gate structure 15. That is, the implanted n-type impurities will not invade the channel region 18 between the source region 21 and the drain region 22, and will not affect the threshold voltage and other characteristics of the semiconductor device 11. This is because during the formation of the second lightly doped regions 24a and 24b, the implanted ions did not enter the channel region 18, and the first lightly doped regions 23a and 23b were formed before the formation of the gate structure 15. Therefore, the channel region 18 does not contain the ions contained in the first lightly doped regions 23a and 23b. Consequently, the channel region 18 does not contain the ions that form the lightly doped regions.

[0062] Please see Figures 3 to 7 As shown, in one embodiment of the present invention, a method for manufacturing a semiconductor device 11 will be described. For example... Figure 3 As shown, the substrate 12 is, for example, a p-type silicon wafer, and a shallow trench isolation structure 13 is formed within the substrate 12. P-type ions such as boron (B) are implanted into the substrate 12, and then annealed to form a well region 14.

[0063] Please see Figure 1 , Figure 4As shown, in one embodiment of the present invention, first lightly doped regions 23a and 23b are formed in the substrate 12 before the gate structure 15 is formed. Specifically, an oxide film 32 is formed on the substrate 12 where the shallow trench isolation structure 13 and the well region 14 are formed. In subsequent processes, the oxide film 32 forms, for example, a gate oxide layer 16, wherein the thickness of the oxide film 32 is, for example, 18 nm. Photoresist is coated on the oxide film 32 and patterned to form a photoresist pattern 31 covering a portion of the well region 14 on each transistor for forming a pair of first lightly doped regions 23a and 23b. When forming the first lightly doped regions 23a and 23b, using the photoresist pattern 31 as a mask, n-type ions, such as phosphorus, are implanted by tilted ion implantation. The ion implantation angle is α, which is the angle between the implantation direction and the normal to the substrate 12. The value of the implantation angle α is, for example, 40°, and the ion implantation energy is, for example, 50 keV to 90 keV, with an ion implantation dose of, for example, 1.0 × 10⁻⁶. 13 atoms / cm 2 ~3.0×10 13 atoms / cm 2 In a specific embodiment of the present invention, when forming the first lightly doped regions 23a and 23b, the ion implantation energy is, for example, 70 keV, and the ion implantation dose is, for example, 2.0 × 10⁻⁶. 13 atoms / cm 2 By using tilted ion implantation, the first lightly doped regions 23a and 23b formed can mitigate the electric field between the subsequently formed drain region 22 and channel region 18, thereby reducing impact ionization. To mitigate the electric field between the drain region 22 and channel region 18 and reduce impact ionization, the depth Df of the first lightly doped regions 23a and 23b is, for example, 200 nm to 300 nm, and the doping concentration is, for example, 1.0 × 10⁻⁶. 18 atoms / cm 3 ~1.0×10 19 atoms / cm 3 Furthermore, the depth Df is greater than the film thickness Tg of the gate structure 15 formed later. By forming a photoresist pattern 31, a pair of first lightly doped regions 23a and 23b are separated from each other by the well region 14 below the photoresist pattern 31.

[0064] Please see Figures 4 to 5As shown, in one embodiment of the present invention, a gate oxide layer 16 and a gate structure 15 are formed on a well region 14 between the first lightly doped regions 23a and 23b in the substrate 12 for each transistor. Specifically, after removing the photoresist pattern 31, a highly doped n-type polysilicon film is formed on the oxide film 32, and the thickness of the polysilicon film is set to be equal to the thickness of the gate structure 15. The thickness of the polysilicon film is less than the depth Df of the first lightly doped regions 23a and 23b, and in a specific embodiment, it is set to, for example, 100 nm. The patterning of the gate structure 15 and the gate oxide layer 16 is completed through photolithography and etching processes. In one embodiment of this application, the mask used for patterning the gate structure 15 and the gate oxide layer 16 is, for example, the same mask used to form the photoresist pattern 31, thereby controlling the overlap between the gate structure 15 and the first lightly doped regions 23a and 23b after the etching process to be within a predetermined management range. However, due to alignment deviations, the amount of overlap between the gate structure 15 and the first lightly doped region 23a may differ from the amount of overlap between the gate structure 15 and the first lightly doped region 23b.

[0065] Please see Figure 6 As shown, in one embodiment of the present invention, second lightly doped regions 24a and 24b are formed in the substrate 12, and the second lightly doped regions 24a and 24b correspond to the first lightly doped regions 23a and 23b, respectively. When forming the second lightly doped regions 24a and 24b, the gate structure 15 is used as a mask, and n-type ions such as phosphorus and arsenic are self-aligned and implanted through tilted ion implantation. The ion implantation angle is β, which is the angle between the implantation direction and the normal to the substrate 12. The value of the implantation angle β is, for example, less than the implantation angle α, and for example, 30°. The ion implantation energy is, for example, 10 keV to 30 keV, and the ion implantation dose is, for example, 5.0 × 10⁻⁶. 12 atoms / cm 2 ~2.0×10 13 atoms / cm 2 In a specific embodiment of the present invention, when forming the second lightly doped regions 24a and 24b, the ion implantation energy is, for example, 20 keV, and the ion implantation dose is, for example, 1.0 × 10⁻⁶. 13 atoms / cm 2 By employing tilted ion implantation, the formed second lightly doped regions 24a and 24b ensure the ion concentration of the lightly doped regions within the GIDL generation area and mitigate the electric field between the subsequently formed drain region 22 and channel region 18. The depth Ds of the second lightly doped regions 24a and 24b is, for example, 40 nm to 80 nm, and the doping concentration is, for example, 1.0 × 10⁻⁶. 18 atoms / cm 3 ~5×10 18 atoms / cm 3Since the depth Ds is less than the film thickness Tg of the gate structure 15, when forming the second lightly doped regions 24a and 24b, the dopant ions in the lightly doped regions will not penetrate the gate structure 15 into the channel region. Because the second lightly doped regions 24a and 24b are formed by self-alignment relative to the gate structure 15, they overlap with the gate structure 15 at a predetermined overlap size OL.

[0066] Please see Figure 7 As shown, in one embodiment of the present invention, a source region 21 and a drain region 22 are formed within a substrate 12. Specifically, after forming second lightly doped regions 24a and 24b, an insulating film such as a silicon oxide film (not shown in the figure) is formed on the substrate 12. The insulating film is etched by anisotropic etching to form a sidewall structure 17 along the side of the gate structure 15 and the gate oxide layer 16. Using the gate structure 15 and the sidewall structure 17 as a mask, n-type ions such as phosphorus and arsenic are self-aligned and implanted by vertical ion implantation to form the source region 21 and the drain region 22. In a specific embodiment of the present invention, the ion implantation energy is, for example, 20 keV, and the ion implantation dose is, for example, 5.0 × 10⁻⁶. 15 atoms / cm 2 In this configuration, by simultaneously controlling the injection energy and injection dose, the depths of the formed source region 21 and drain region 22 are greater than the depth Df of the first lightly doped regions 23a and 23b. The source region 21 and drain region 22 are separated by the sidewall structure 17 and the channel region 18. The first lightly doped regions 23a and 23b and the second lightly doped regions 24a and 24b are disposed below the sidewall structure 17 between the source region 21 and drain region 22 and the channel region 18. Since the source region 21 and drain region 22 are self-aligned relative to the sidewall structure 17, they overlap with the sidewall structure 17 at a predetermined overlap size. For each transistor, the first lightly doped region 23a and the second lightly doped region 24a are connected to the source region 21, and the first lightly doped region 23b and the second lightly doped region 24b are connected to the drain region 22. By forming a second lightly doped region, the device performance degradation caused by light doping offset can be avoided, the gate-induced drain leakage current can be reduced, the energy efficiency, stability and reliability of semiconductor devices can be improved, the lifespan of semiconductor devices can be extended, and maintenance costs can be reduced.

[0067] Please see Figure 8 As shown, in one embodiment of the present invention, the characteristics of the semiconductor device 11 were verified by simulation. During verification, the semiconductor device 11 was obtained using the fabrication method of this application. Figure 2 The device shown is Example 1, and a device obtained by omitting the second lightly doped regions 24a and 24b is used as Comparative Example 1. Figure 8The diagram illustrates the relationship between the positional offset of the first lightly doped regions 23a and 23b relative to the gate structure and the Loff ratio of the semiconductor device 11. The horizontal axis represents the size of the positional offset, and the positive side of the horizontal axis represents the offset Sf, as shown in the diagram. Figure 2 The first lightly doped regions 23a and 23b shown are shifted relative to the gate structure 15 towards the drain region 22. The negative side represents the offset Sf, which is as follows: Figure 2 The first lightly doped regions 23a and 23b shown are shifted relative to the gate structure 15 toward the source region 21. The vertical axis represents the turn-off current ratio of the semiconductor device 11, which is a normalized value obtained by setting the current value to 1 when the position offset Sf is zero.

[0068] Please see Figure 8 As shown, when the first lightly doped regions 23a and 23b are offset towards the drain region 22 relative to the gate structure 15, the turn-off current ratio increases. However, compared to Comparative Example 1, the turn-off current ratio of Example 1 is less affected by the offset. When the offset Sf is 0.08 μm, the turn-off current ratio of Example 1 is suppressed to about 1 / 10 of that of Comparative Example 1. It can be considered that in Comparative Example 1, the overlap between the first lightly doped region 23b and the gate structure 15 is small, and the turn-off current ratio increases due to the electric field between the drain region 22 and the channel region 18. In contrast, in this Example 1, the electric field between the drain region 22 and the channel region 18 is mitigated by the second lightly doped region 24b, thereby reducing the turn-off current ratio.

[0069] Please see Figure 9 The simulation results for the inter-band channel current intensity distribution are shown in the figure. Please refer to [link / reference]. Figure 10 As shown, a graph representing the intensity of inter-band channel current is presented. This inter-band channel current can cause GIDL (Growth Intensity Difference). In Example 1 and Comparative Example 1, the position offset Sf was set to 0.08 μm. Figure 9 As shown, compared to Comparative Example 1, the region where the interband channel current is generated (the lighter gray area) in Example 1 is significantly reduced, and the number of charge carriers generated per unit time (number / cm²) is also significantly reduced. 3 The frequency ( / s) decreases, therefore, the resulting interband channel current decreases. For example... Figure 10 As shown, compared with Comparative Example 1, the intensity of the inter-band channel current in Example 1 is also reduced.

[0070] Please see Figure 11The diagram shows simulated LDD ion concentrations in the first lightly doped region 23a (23b), the second lightly doped region 24a (24b), and the source region 21 (or drain region 22) on the surface of the well region 14. Examples 1, 2, 1, and 2 are included. Example 1 shows a case where the offset Sf is shifted in the direction of decreasing overlap size OL; Example 2 shows a case where the offset Sf is 0; Comparative Example 1 shows a case where the offset Sf is shifted in the direction of decreasing overlap size OL without the second lightly doped region 24a (24b); and Comparative Example 2 shows a case where the offset Sf is 0 without the second lightly doped region 24a (24b). The diagram shows the LDD concentrations relative to the lateral position on the surface of the well region 14. The LDD concentration ratio represents the value normalized by setting the ion concentration of the source region 21 (or drain region 22) to 1. Figure 11 As shown, the LDD concentration ratio gradually decreases from the source region 21 (or drain region 22) towards the gate structure 15. Since the second lightly doped region 24a (24b) is omitted in the comparative examples, the LDD concentration ratio is smaller compared to the embodiments, especially in the case of misalignment in Comparative Example 1, where the LDD concentration ratio is significantly reduced compared to the case without misalignment (Comparative Example 2). In this application, even in the case of misalignment in Embodiment 1, the change in the LDD concentration ratio is suppressed. The area on the surface of the well region 14 immediately below the boundary between the gate structure 15 and the sidewall structure 17 is the GIDL generation region. In order to suppress GIDL, it is necessary to increase the LDD concentration. However, in this application, whether there is a misalignment or not, the LDD concentration of the GIDL generation region is maintained at a high level of more than 1 / 3 of the ion concentration of the source region 21 (or drain region 22). This confirms the effect of the second lightly doped region 24a (24b). In the event of a misalignment between the gate structure and the first lightly doped region, the electrical characteristic shift caused by the misalignment can be reduced, thereby improving the conductivity, threshold voltage, stability and reliability of the semiconductor device.

[0071] In summary, this invention provides a semiconductor device and its fabrication method. Through improvements to the semiconductor device and its fabrication method, the unexpected technical effect of this application is that it can compensate for the problem of misalignment between the lightly doped region and the gate structure caused by the initial formation of a lightly doped region, thereby improving the performance of the semiconductor device. It effectively reduces the electric field near the source and drain, thus reducing the probability of high-energy carrier generation in the source and drain regions, reducing the risk of hot carrier effects, and helping to reduce leakage current near the source and drain, improving the device's performance and reliability. It avoids device performance degradation caused by light doping misalignment, reduces gate-induced drain leakage current, improves the energy efficiency, stability, and reliability of the semiconductor device, extends its lifespan, and reduces maintenance costs. The second lightly doped region can reduce the electrical characteristic shift caused by misalignment when the gate structure and the first lightly doped region are misaligned, and the dopant ions in the lightly doped region will not penetrate the gate structure into the channel region, thereby improving the conductivity, threshold voltage, stability, and reliability of the semiconductor device.

[0072] The above description of the embodiments shown in this invention (including the content set forth in the abstract of the specification) is not intended to be an exhaustive enumeration or to limit the invention to the precise forms disclosed herein. Although specific embodiments and examples of the invention have been described herein for illustrative purposes only, various equivalent modifications are possible within the spirit and scope of the invention, as will be recognized and understood by those skilled in the art. As indicated, these modifications can be made to the invention in accordance with the above description of the embodiments described herein, and such modifications will be within the spirit and scope of the invention.

[0073] The above description is merely a preferred embodiment of this application and an explanation of the technical principles employed. Those skilled in the art should understand that the scope of the invention involved in this application is not limited to the technical solutions formed by specific combinations of the above-described technical features. It should also cover other technical solutions formed by arbitrary combinations of the above-described technical features or their equivalents without departing from the inventive concept. For example, technical solutions formed by substituting the above-described features with (but not limited to) technical features with similar functions disclosed in this application. Except for the technical features described in the specification, the remaining technical features are known to those skilled in the art. To highlight the innovative features of this invention, the remaining technical features will not be described further here.

Claims

1. A method for fabricating a semiconductor device, characterized in that, Includes the following steps: A substrate is provided, and a well region is formed within the substrate; An oxide film is formed on the substrate, and a photoresist pattern is formed on the oxide film; Using a photoresist pattern as a mask, tilted ion implantation is performed on the well regions on both sides of the photoresist pattern to form a pair of first lightly doped regions spaced apart by the well regions. The photoresist pattern is removed, and a polysilicon film is formed on the oxide film. A gate structure and a gate oxide layer are formed through photolithography and etching processes. The photolithography process uses the same mask as the photoresist pattern. Using the gate structure as a mask, tilted ion implantation is performed on the substrates on both sides of the gate structure to form a pair of second lightly doped regions spaced apart by the well region. The orthogonal projection of the gate structure on the substrate surface partially overlaps with the second lightly doped regions, with a set overlap size. A sidewall structure is formed on the sidewall of the gate structure; Using the sidewall structure and the gate structure as masks, ions are implanted into the substrate outside the sidewall structure and the gate structure to form a source region and a drain region.

2. The method for fabricating a semiconductor device according to claim 1, characterized in that, The implantation angle for forming the second lightly doped region is smaller than the implantation angle for forming the first lightly doped region.

3. The method for fabricating a semiconductor device according to claim 1, characterized in that, The source region and the drain region are formed by vertical ion implantation, and the depth of the source region and the drain region is greater than the depth of the first lightly doped region.

4. The method for fabricating a semiconductor device according to claim 1, characterized in that, The depth of the first lightly doped region is greater than the thickness of the gate structure, and the depth of the second lightly doped region is less than the thickness of the gate structure.

5. The method for fabricating a semiconductor device according to claim 1, characterized in that, The orthographic projection of the gate structure onto the substrate surface partially overlaps with the second lightly doped regions on both sides, and the overlap size between the two second lightly doped regions and the gate structure is equal.

6. The method for fabricating a semiconductor device according to claim 1, characterized in that, The distance separating the well regions between a pair of first lightly doped regions is less than the distance separating the well regions between a pair of second lightly doped regions.

7. A semiconductor device, obtained by the fabrication method according to any one of claims 1-6, characterized in that, At least including: A substrate, wherein a well region is disposed therein; A pair of first lightly doped regions are spaced apart within the well region; A gate structure is disposed on the substrate between adjacent first lightly doped regions; A pair of second lightly doped regions are disposed at intervals in the substrate on both sides of the gate structure; Sidewall structures are disposed on both sides of the gate structure; as well as The source region and the drain region are respectively disposed in the substrate outside the gate structure and the sidewall structure.

8. The semiconductor device according to claim 7, characterized in that, The gate structure covers at least a portion of the first lightly doped region on one side.

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