Metal oxide semiconductor high electron mobility transistor and preparation method thereof

Abstract

The invention relates to the technical field of semiconductors, and discloses a metal oxide semiconductor high electron mobility transistor and a preparation method thereof. The metal oxide semiconductor high electron mobility transistor comprises an epitaxial wafer; the source electrode and the drain electrode are located on one side of the epitaxial wafer and are arranged at intervals; the composite gate dielectric layer is located on one side of the epitaxial wafer and located between the source electrode and the drain electrode; the composite gate dielectric layer comprises at least two gate dielectric sub-layers which are arranged along the arrangement direction of the source electrode and the drain electrode and are made of different materials; the dielectric constant of the preparation material of the gate dielectric sub-layer close to the drain electrode in the at least two gate dielectric sub-layers is maximum and is greater than 3.9 F / m; the grid electrode is located on the side, away from the epitaxial wafer, of the composite gate dielectric layer and at least covers the orthographic projection of the interface of the gate dielectric sub-layer with the maximum dielectric constant and the adjacent gate dielectric sub-layer on the epitaxial wafer. The metal oxide semiconductor high-electron-mobility transistor can realize high-frequency and high-voltage collaborative optimization of devices, and meets the requirements of novel application fields.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a metal oxide semiconductor high electron mobility transistor and a preparation method thereof. Background Art

[0002] The significant spontaneous polarization and piezoelectric polarization effects at the heterojunction within the high electron mobility transistor (HEMT) give it excellent electrical properties: high carrier concentration, high mobility, and high breakdown field strength, as well as low on-resistance and high switching speed.

[0003] Traditional power electronic devices typically require HEMTs to have very high breakdown voltages, such as gallium nitride (GaN) fast chargers and photovoltaic inverters. However, emerging applications are driving the development of HEMTs towards high-frequency, high-voltage, and coordinated optimization, including industrial plasma generators (e.g., plasma-enhanced chemical vapor deposition (PECVD) equipment), medical and scientific equipment (e.g., magnetic resonance imaging (MRI) systems), and biomedical radiofrequency thermal therapy (e.g., 13.56 MHz tumor ablation systems).

[0004] Current methods for increasing the breakdown voltage of HEMTs include increasing the gate-drain spacing, lengthening the gate length, or introducing a metal oxide semiconductor (MOS) structure. Because increasing device size significantly increases on-resistance, leading to degradation in power density and high-frequency performance, MOS structures are often used to improve performance. MOS structures are primarily implemented by depositing an oxide gate dielectric layer between the device's metal gate and the semiconductor material. However, the device's high-frequency characteristics and withstand voltage characteristics are inversely proportional. While the gate dielectric material increases the breakdown voltage, it inevitably affects the device's cutoff frequency.

[0005] Therefore, there is an urgent need to provide a metal oxide semiconductor high electron mobility transistor that can achieve high frequency and high voltage coordinated optimization of the device. Summary of the Invention

[0006] The present application discloses a metal oxide semiconductor high electron mobility transistor and a preparation method thereof. By optimizing its own structure, the metal oxide semiconductor high electron mobility transistor can achieve high-frequency and high-voltage coordinated optimization of the device, while meeting the needs of new application fields.

[0007] To achieve the above objectives, this application provides the following technical solutions: In a first aspect, the present application provides a metal oxide semiconductor high electron mobility transistor, comprising: epitaxial wafers; A source electrode and a drain electrode are located on one side of the epitaxial wafer and are spaced apart; a composite gate dielectric layer located on one side of the epitaxial wafer and between the source and the drain; the composite gate dielectric layer comprising at least two gate dielectric sublayers arranged along the direction of arrangement of the source and the drain and made of different materials; of the at least two gate dielectric sublayers, the gate dielectric sublayer proximal to the drain has the largest dielectric constant and is greater than 3.9 F / m; The gate is located on the side of the composite gate dielectric layer away from the epitaxial wafer, and the orthographic projection of the gate on the epitaxial wafer at least covers the orthographic projection of the interface between the gate dielectric sublayer with the largest dielectric constant and the adjacent gate dielectric sublayer on the epitaxial wafer.

[0008] In some embodiments, adjacent gate dielectric sub-layers are in seamless contact at the interface.

[0009] In some embodiments, the composite gate dielectric layer includes two gate dielectric sublayers; the two gate dielectric sublayers are a first gate dielectric sublayer and a second gate dielectric sublayer, wherein the second gate dielectric sublayer is close to the drain along the arrangement direction of the source and the drain; the first gate dielectric sublayer is close to the source along the arrangement direction of the source and the drain; the orthographic projection of the gate on the epitaxial wafer covers the orthographic projection of the interface between the first gate dielectric sublayer and the second gate dielectric sublayer on the epitaxial wafer.

[0010] In some embodiments, the first gate dielectric sublayer forms a first region in an area where the orthographic projection of the epitaxial wafer is covered by the orthographic projection of the gate on the epitaxial wafer, and the second gate dielectric sublayer forms a second region in an area where the orthographic projection of the epitaxial wafer is covered by the orthographic projection of the gate on the epitaxial wafer, and the size ratio of the second region to the first region in the arrangement direction of the source and the drain is set according to a preset ratio.

[0011] In some embodiments, the preset ratio is 1:1.

[0012] In some embodiments, the first gate dielectric sublayer is made of a material selected from the group consisting of aluminum oxide and silicon dioxide. And / or, the second gate dielectric sub-layer is made of one of aluminum oxide, hafnium dioxide or hafnium zirconium oxide.

[0013] In some embodiments, the dielectric constants of the materials used to make the first gate dielectric sub-layer and the second gate dielectric sub-layer are both greater than 3.9 F / m.

[0014] In a second aspect, the present application further provides a method for preparing a metal oxide semiconductor high electron mobility transistor, which is used to prepare a metal oxide semiconductor high electron mobility transistor as provided by any technical solution in the first aspect above, the preparation method comprising: Isolate the mesa and evaporate the source and drain electrodes on the epitaxial wafer; A composite gate dielectric layer is formed on the epitaxial wafer and between the source and the drain; the composite gate dielectric layer includes at least two gate dielectric sublayers arranged along the arrangement direction of the source and the drain and made of different materials; among the at least two gate dielectric sublayers, the gate dielectric sublayer near the drain has the largest dielectric constant and is greater than 3.9 F / m; A gate is formed on the composite gate dielectric layer, and an orthographic projection of the gate on the epitaxial wafer at least covers an orthographic projection of an interface between the gate dielectric sublayer with the largest dielectric constant and an adjacent gate dielectric sublayer on the epitaxial wafer.

[0015] In some embodiments, the composite gate dielectric layer includes two gate dielectric sublayers; the two gate dielectric sublayers are a first gate dielectric sublayer and a second gate dielectric sublayer; wherein the second gate dielectric sublayer is close to the drain along the arrangement direction of the source and the drain; and the first gate dielectric sublayer is close to the source along the arrangement direction of the source and the drain; The method of forming a composite gate dielectric layer on the epitaxial wafer and between the source and the drain comprises: The first gate dielectric sublayer is formed first, and then the second gate dielectric sublayer is formed.

[0016] In some embodiments, the method of first forming the first gate dielectric sublayer and then forming the second gate dielectric sublayer includes: Depositing and forming the first gate dielectric sublayer on a side of the epitaxial wafer close to the source electrode; The preparation material of the second gate dielectric sublayer is deposited entirely on the epitaxial wafer and the first gate dielectric sublayer; and a portion of the preparation material of the second gate dielectric sublayer on the first gate dielectric sublayer is removed to form the second gate dielectric sublayer.

[0017] One embodiment of the present application has at least the following advantages or beneficial effects: Specifically, the working principle of the metal oxide semiconductor high electron mobility transistor provided by the present application is as follows: the dielectric constants of the materials used to prepare the composite gate dielectric layer under the area covered by the gate are different. At the material interface of the two gate dielectric sublayers with different dielectric constants, the potential perpendicular to the interface direction is continuous, but the corresponding electric field strength has a discontinuous jump due to the difference in dielectric constants. Due to Gauss's law of electric field, the jump in electric field strength will affect the electric field distribution in the epitaxial wafer, that is, it will have a lifting effect on the lateral channel electric field directly below the interface, and a lateral electric field spike will appear. Therefore, the electric field can be ultimately controlled by regulating the dielectric constant of the materials at different positions of the composite gate dielectric layer.

[0018] It should be noted that the metal oxide semiconductor high electron mobility transistor provided in this application forms different gate dielectric sublayers using materials with different dielectric constants, thereby forming a non-uniform composite gate dielectric layer through the different gate dielectric sublayers, effectively regulating the electric field distribution in the epitaxial wafer, and having better gate control capability and higher transconductance. At the same time, based on the material properties of its high dielectric constant, the composite gate dielectric layer can form a stronger electric field shield under the gate, reducing the surface electric field and suppressing the dynamic capture and decapture process of trapped charge, effectively alleviating the self-heating effect of the device and improving the reliability of the device.

[0019] Moreover, the metal oxide semiconductor high electron mobility transistor uses a material with the largest dielectric constant to prepare the gate dielectric sublayer on the drain side, which can achieve a higher breakdown voltage and reduce the equivalent capacitance of the composite gate dielectric layer while maintaining a high breakdown voltage, thereby significantly increasing the cutoff frequency and thus improving the frequency characteristics of the device.

[0020] Based on this, the metal oxide semiconductor high electron mobility transistor provided in this application can synergistically optimize high frequency and high voltage, while meeting the needs of emerging application fields such as advanced industrial manufacturing, cutting-edge scientific research and medical equipment, and has huge application potential. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 A schematic diagram of the cross-sectional structure of a metal oxide semiconductor high electron mobility transistor provided in an embodiment of the present application; Figure 2 A schematic diagram of the cross-sectional structure of a metal oxide semiconductor high electron mobility transistor provided in an embodiment of the present application; Figures 3a to 3f A flow chart of the preparation process of a metal oxide semiconductor high electron mobility transistor provided in an embodiment of the present application; Figure 4a is the transfer characteristic curve of the metal oxide semiconductor high electron mobility transistor when Al2O3 is used as the gate dielectric layer; Figure 4b is the transfer characteristic curve of the metal oxide semiconductor high electron mobility transistor when HfO2 is used as the gate dielectric layer; Figure 4c The transfer characteristic curve of the metal oxide semiconductor high electron mobility transistor when Al2O3 / HfO2 is used as the composite gate dielectric layer; Figure 4d A data summary diagram of peak transconductance of metal oxide semiconductor high electron mobility transistors prepared from different materials; Figure 5a Breakdown voltage curves of the metal oxide semiconductor high electron mobility transistor provided in the embodiments of the present application and the metal oxide semiconductor high electron mobility transistor in the related art; Figure 5b A data summary diagram of the breakdown voltage of metal oxide semiconductor high electron mobility transistors prepared from different materials; Figure 6a The gate capacitance curves of the metal oxide semiconductor high electron mobility transistor provided in the embodiment of the present application and the metal oxide semiconductor high electron mobility transistor in the related art; Figure 6b A data summary diagram of gate capacitance of metal oxide semiconductor high electron mobility transistors made of different materials; Figure 7a Cutoff frequency curves of the metal oxide semiconductor high electron mobility transistor provided in the embodiment of the present application and the metal oxide semiconductor high electron mobility transistor in the related art; Figure 7b A data summary diagram of the cutoff frequency of metal oxide semiconductor high electron mobility transistors made of different materials; Figure 8 A grayscale image of the two-dimensional electric field distribution under the gate of a metal oxide semiconductor high electron mobility transistor provided in an embodiment of the present application; Figure 9 A data summary of the breakdown voltage and cutoff frequency of metal oxide semiconductor high electron mobility transistors made of different materials; Figure numerals: 100, epitaxial wafer; 110, substrate; 120, nucleation layer; 130, buffer layer; 140, channel layer; 150, insertion layer; 160, barrier layer; 170, cap layer; 200, source; 300, drain; 400, composite gate dielectric layer; 410, first gate dielectric sublayer; 420, second gate dielectric sublayer; 500, gate. DETAILED DESCRIPTION

[0022] An embodiment of the present application provides a metal oxide semiconductor high electron mobility transistor (MOSHMT), which is a semiconductor device that combines the advantages of a metal-oxide-semiconductor structure and a high electron mobility transistor.

[0023] The following will clearly and completely describe the technical solutions in the embodiments of the present application in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without making creative work are within the scope of protection of this application. Among them, in the description of the embodiments of the present application, unless otherwise specified, " / " means or, for example, A / B can mean A or B; "and / or" in the text is only a description of the association relationship of associated objects, indicating that there can be three relationships, for example, A and / or B can mean: A exists alone, A and B exist at the same time, and B exists alone. In addition, in the description of the embodiments of the present application, "multiple" refers to two or more than two.

[0024] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood to imply or suggest relative importance or implicitly indicate the number of the technical features indicated. Therefore, the features defined as "first" and "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0025] In a first aspect, embodiments of the present application provide a metal oxide semiconductor high electron mobility transistor. Figure 1 This is a schematic diagram of the cross-sectional structure of a metal oxide semiconductor high electron mobility transistor provided in an embodiment of the present application. Figure 1 As shown, the metal oxide semiconductor high electron mobility transistor provided in the embodiment of the present application includes: an epitaxial wafer 100, a source 200, a drain 300, a composite gate dielectric layer 400, and a gate 500. The source 200 and the drain are located on one side of the epitaxial wafer 100 and spaced apart. The composite gate dielectric layer 400 is located on one side of the epitaxial wafer 100 and between the source 200 and the drain 300. The composite gate dielectric layer 400 includes at least two gate dielectric sublayers arranged along the arrangement direction of the source 200 and the drain 300 and made of different materials. Of the at least two gate dielectric sublayers, the gate dielectric sublayer near the drain has the largest dielectric constant and is greater than 3.9 F / m. The gate 500 is located on the side of the composite gate dielectric layer 400 facing away from the epitaxial wafer 100, and the orthographic projection of the gate 500 on the epitaxial wafer 100 at least covers the orthographic projection of the interface between the gate dielectric sublayer with the largest dielectric constant and the adjacent gate dielectric sublayer on the epitaxial wafer.

[0026] It should be understood that when the dielectric constant of a material is greater than 3.9 F / m, the material is referred to as a high dielectric constant material, i.e., the dielectric constant K value is high. Of course, the dielectric constant of the material can also be greater than 10 F / m, or even reach several tens or higher, and the details will not be repeated here. The epitaxial wafer 100 can be prepared in advance in the previous process, or the epitaxial wafer can be prepared by an upstream manufacturer. Figure 2 Schematic diagram of the cross-sectional structure of a metal oxide semiconductor high electron mobility transistor provided in an embodiment of the present application; Figure 2 As shown, epitaxial wafer 100 may include, for example, a substrate 110, a nucleation layer 120, a buffer layer 130, a channel layer 140, an insertion layer 150, a barrier layer 160, and a cap layer 170, which are arranged in sequence. These film layers are pre-formed in epitaxial wafer 100, wherein insertion layer 150, barrier layer 160, and cap layer 170 are also located between source 200 and drain 300. Of course, epitaxial wafer 100 may also include other film layers as required, which will not be described in detail.

[0027] Figure 1 and Figure 2 In the example shown, the composite gate dielectric layer 400 includes a first gate dielectric sublayer 410 and a second gate dielectric sublayer 420. Of course, the number of gate dielectric sublayers in the composite gate dielectric layer 400 can also be three or more, and can be set according to specific needs. However, it is necessary to ensure that the orthographic projection of the gate 500 on the substrate 110 at least covers the orthographic projection of the interface between the gate dielectric sublayer with the highest dielectric constant and the adjacent gate dielectric sublayer on the substrate 110. High dielectric constant materials can include hafnium-based oxides such as hafnium dioxide (HfO2), aluminum-based oxides such as aluminum oxide (Al2O3), and zirconium-based oxides such as zirconium dioxide (ZrO2).

[0028] In addition, it is worth noting that since the dielectric constant of the preparation material of the gate dielectric sublayer close to the drain 300 is the largest, the dielectric constant K value of the preparation material of the remaining gate dielectric sublayers is lower than that of the gate dielectric sublayer with the highest dielectric constant K value.

[0029] The operating principle of the metal oxide semiconductor high electron mobility transistor provided in the embodiments of the present application is as follows: the dielectric constant K values ​​of the composite gate dielectric layer 400 below the region covered by the gate 500 are different. It should be understood that at the interface between the two gate dielectric sublayers with different dielectric constants, the potential perpendicular to the interface (e.g., the second direction) is continuous, but the corresponding electric field strength undergoes a discontinuous transition due to the different dielectric constants. Due to Gauss's law of electric field, this transition in electric field strength affects the electric field distribution in the epitaxial wafer 100, increasing the channel electric field in the lateral direction (i.e., the second direction) directly below the interface, resulting in a lateral electric field spike. Therefore, by adjusting the dielectric constant of the material at different locations in the composite gate dielectric layer 400, the electric field can ultimately be controlled.

[0030] It should be noted that the metal oxide semiconductor high electron mobility transistor provided in the embodiments of the present application uses materials with different dielectric constants to form different gate dielectric sublayers, thereby forming a non-uniform composite gate dielectric layer 400 through the different gate dielectric sublayers. This effectively regulates the electric field distribution in the epitaxial wafer 100, resulting in better gate control capability and higher transconductance. It should be understood that transconductance reflects the ability of the gate 500 voltage to control the channel in the epitaxial wafer 100.

[0031] At the same time, based on its material properties of high dielectric constant, the composite gate dielectric layer 400 can form a stronger electric field shield under the gate 500 to reduce the surface electric field and inhibit the dynamic capture and de-capture process of trapped charges, effectively alleviating the self-heating effect of the device and improving the reliability of the device.

[0032] Since the breakdown of the device often occurs on the side of the gate 500 close to the drain 300, the metal oxide semiconductor high electron mobility transistor provided in the embodiment of the present application uses a material with the largest dielectric constant to prepare the gate dielectric sublayer on the side of the drain 300, so that the device with a non-uniform composite gate dielectric layer 400 has a breakdown voltage that is almost the same as the high-k device with a single uniform composite gate dielectric layer 400 in the related art, that is, it can achieve a higher breakdown voltage. In contrast to the breakdown voltage, the higher the dielectric constant of the gate dielectric layer material, the greater its capacitance and the lower the cutoff frequency. However, the metal oxide semiconductor high electron mobility transistor provided in the embodiment of the present application can also reduce the equivalent capacitance of the composite gate dielectric layer 400 while maintaining a high breakdown voltage, thereby significantly improving the cutoff frequency and thereby improving the frequency characteristics of the device.

[0033] Based on this, the metal oxide semiconductor high electron mobility transistor provided in the embodiment of the present application can coordinately optimize high frequency and high voltage, while meeting the needs of emerging application fields such as advanced industrial manufacturing, cutting-edge scientific research and medical equipment, and has huge application potential.

[0034] When setting the composite gate dielectric layer 400 in the embodiment of the present application, the gate dielectric sublayer close to the drain 300 is in contact with or not in contact with the drain 300. Similarly, the gate dielectric sublayer close to the source 200 is in contact with or not in contact with the source 200. The specific setting is performed according to the needs and will not be repeated here.

[0035] like Figure 1 and Figure 2 As shown, in one embodiment of the present application, adjacent gate dielectric sub-layers are in seamless contact at the interface position, thereby avoiding gate leakage caused by gaps between the interfaces.

[0036] Please continue to refer to Figure 1 and Figure 2 In the structure shown, in one embodiment of the present application, among the at least two gate dielectric sub-layers, the dielectric constant of the material preparing the gate dielectric sub-layer close to the source 200 is the smallest; alternatively, when there is more material in the composite gate dielectric layer 400, the dielectric constant of the material preparing the gate dielectric sub-layer close to the source 200 side may also be greater than the dielectric constant of the material preparing the gate dielectric sub-layer located in the middle, because there is also a risk of breakdown on the source 200 side.

[0037] In a specific embodiment of the present application, Figure 1 and Figure 2 As shown, the composite gate dielectric layer 400 includes two gate dielectric sublayers; the two gate dielectric sublayers are a first gate dielectric sublayer 410 and a second gate dielectric sublayer 420, wherein the second gate dielectric sublayer 420 is close to the drain 300 along the source and drain arrangement direction; the first gate dielectric sublayer 410 is close to the source 200 along the source and drain arrangement direction; the orthographic projection of the gate 500 on the substrate 110 covers the orthographic projection of the interface between the first gate dielectric sublayer 410 and the second gate dielectric sublayer 420 on the substrate 110.

[0038] It should be noted that in this specific embodiment, the composite gate dielectric layer 400 is configured to include only two gate dielectric sub-layers, so as to simplify the manufacturing process and improve the manufacturing efficiency while ensuring the structural performance of the metal oxide semiconductor high electron mobility transistor.

[0039] Please continue to refer to Figure 1 and Figure 2In the structure shown, the gate 500 not only covers the interface between the first gate dielectric sublayer 410 and the second gate dielectric sublayer 420, but also covers a portion of the first gate dielectric sublayer 410 and a portion of the second gate dielectric sublayer 420, thereby further optimizing the structural performance of the metal oxide semiconductor high electron mobility transistor. In one embodiment of the present application, the first gate dielectric sublayer 410 forms a first region in the area where the orthographic projection of the substrate 110 is covered by the orthographic projection of the gate 500 on the substrate 110, and the second gate dielectric sublayer 420 forms a second region in the area where the orthographic projection of the substrate 110 is covered by the orthographic projection of the gate 500 on the substrate 110. The size ratio of the second region to the first region in the source and drain arrangement direction is set according to a preset ratio.

[0040] In one specific embodiment, the preset ratio is 1:1. For example, the area of ​​the first gate dielectric sublayer 410 covered by the gate 500 in the source and drain arrangement direction is 2 microns; the area of ​​the second gate dielectric sublayer 420 covered by the gate 500 in the source and drain arrangement direction is 2 microns. In this case, along the source and drain arrangement direction, the length of the gate 500 is 4 microns, the spacing between the gate 500 and the source 200 is 3 microns, and the spacing between the gate 500 and the drain 300 is 14 microns. Therefore, the total length of the first gate dielectric sublayer 410 is 3 plus 2, which equals 5 microns, and the total length of the second gate dielectric sublayer 420 is 14 plus 2, which equals 16 microns.

[0041] Of course, this does not mean that only 1:1 can be used as the preset ratio. The size ratio of the first gate dielectric sublayer 410 and the second gate dielectric sublayer 420 in the composite gate dielectric layer 400 can be further expanded to 7:3, 9:1, etc., and the details will not be repeated here.

[0042] In one embodiment of the present application, the first gate dielectric sub-layer 410 is made of Al 2 O 3 . Of course, there are other options for making the first gate dielectric sub-layer 410 besides Al 2 O 3 , such as silicon dioxide (SiO 2 ).

[0043] In one embodiment of the present application, the second gate dielectric sub-layer 420 is made of one of Al 2 O 3 , hafnium dioxide, or hafnium zirconium oxide.

[0044] In a specific embodiment, the dielectric constants of the materials used to prepare the first gate dielectric sub-layer 410 and the second gate dielectric sub-layer 420 are both greater than 3.9 F / m, that is, the materials used to prepare the first gate dielectric sub-layer 410 excluding SiO 2 .

[0045] Furthermore, the dielectric constant of the material used to prepare each gate dielectric sub-layer in the composite gate dielectric layer 400 is greater than 3.9 F / m to optimize device efficiency.

[0046] In a second aspect, the present application also provides a method for preparing a metal oxide semiconductor high electron mobility transistor, which is used to prepare a metal oxide semiconductor high electron mobility transistor as provided by any technical solution in the first aspect. Figure 1 and Figure 2 The structure shown, the preparation method includes: Isolate the mesa and evaporate the source 200 and drain 300 on the epitaxial wafer 100; A composite gate dielectric layer 400 is formed on the epitaxial wafer 100 and between the source 200 and the drain 300. The composite gate dielectric layer 400 includes at least two gate dielectric sublayers arranged along the arrangement direction of the source 200 and the drain 300 and made of different materials. Of the at least two gate dielectric sublayers, the gate dielectric sublayer near the drain 300 has the largest dielectric constant and is greater than 3.9 F / m. A gate 500 is formed on the composite gate dielectric layer 400 , and the orthographic projection of the gate 500 on the epitaxial wafer 100 at least covers the orthographic projection of the interface between the gate dielectric sublayer with the largest dielectric constant and the adjacent gate dielectric sublayer on the epitaxial wafer 100 .

[0047] It should be noted that the metal oxide semiconductor high electron mobility transistor produced by the preparation method provided in the embodiment of the present application uses different gate dielectric sublayers formed from materials with different dielectric constants. This allows for a non-uniform composite gate dielectric layer 400 formed by the different gate dielectric sublayers. This effectively regulates the electric field distribution within the epitaxial wafer 100, resulting in improved gate control capability and higher transconductance. It should be understood that transconductance reflects the ability of the gate 500 voltage to control the channel layer 140 within the epitaxial wafer 100.

[0048] At the same time, based on its material properties of high dielectric constant, the composite gate dielectric layer 400 can form a stronger electric field shield under the gate 500 to reduce the surface electric field and inhibit the dynamic capture and de-capture process of trapped charges, effectively alleviating the self-heating effect of the device and improving the reliability of the device.

[0049] Since the breakdown of the device often occurs on the side of the gate 500 close to the drain 300, the metal oxide semiconductor high electron mobility transistor uses a material with the largest dielectric constant to prepare the gate dielectric sublayer on the side of the drain 300, so that the device with a non-uniform composite gate dielectric layer 400 has a breakdown voltage that is almost the same as the high-k device with a single uniform composite gate dielectric layer 400 in the related art, that is, it can achieve a higher breakdown voltage. In contrast to the breakdown voltage, the higher the dielectric constant of the gate dielectric layer material, the greater its capacitance and the lower the cutoff frequency. However, the metal oxide semiconductor high electron mobility transistor provided in the embodiment of the present application can also reduce the equivalent capacitance of the composite gate dielectric layer 400 while maintaining a high breakdown voltage, thereby achieving a significant increase in the cutoff frequency and thus improving the frequency characteristics of the device.

[0050] Based on this, the metal oxide semiconductor high electron mobility transistor can coordinately optimize high frequency and high voltage, while meeting the needs of emerging application fields such as advanced industrial manufacturing, cutting-edge scientific research and medical equipment, and has huge application potential.

[0051] In one embodiment of this application, please continue to refer to Figure 1 and Figure 2 In the structure shown, the composite gate dielectric layer 400 includes two gate dielectric sublayers; the two gate dielectric sublayers are a first gate dielectric sublayer 410 and a second gate dielectric sublayer 420; wherein the second gate dielectric sublayer 420 is close to the drain 300 along the direction of the source and drain arrangement; the first gate dielectric sublayer 410 is close to the source 200 along the direction of the source and drain arrangement; The method of forming the composite gate dielectric layer 400 on the epitaxial wafer 100 and between the source 200 and the drain 300 includes: The first gate dielectric sub-layer 410 is formed first, and then the second gate dielectric sub-layer 420 is formed.

[0052] It should be noted that in the preparation method provided in the embodiment of the present application, a first gate dielectric sublayer 410 with a lower dielectric constant is first prepared, and then a second gate dielectric sublayer 420 with a high dielectric constant is prepared, which can ensure the quality effect of the composite gate dielectric layer 400, thereby enabling the composite gate dielectric layer 400 to effectively play a regulatory role in the metal oxide semiconductor high electron mobility transistor.

[0053] Exemplarily, the composite gate dielectric layer 400 is formed using an atomic layer deposition (ALD) growth process. Because the material used to form the first gate dielectric sublayer 410 (e.g., Al2O3) has a relatively low growth temperature, while the material used to form the second gate dielectric sublayer 420 (e.g., HfO2) has a relatively high growth temperature, if the material used to form the second gate dielectric sublayer 420 is deposited first, the quality of the material used to form the subsequently deposited first gate dielectric sublayer 410 will be poor.

[0054] In a specific embodiment of the present application, a method of first forming the first gate dielectric sub-layer 410 and then forming the second gate dielectric sub-layer 420 includes: Depositing and forming a first gate dielectric sublayer 410 on a side of the epitaxial wafer 100 close to the source 200; The material for preparing the second gate dielectric sublayer 420 is deposited entirely on the epitaxial wafer 100 and the first gate dielectric sublayer 410 ; and a portion of the material for preparing the second gate dielectric sublayer 420 on the first gate dielectric sublayer 410 is removed to form the second gate dielectric sublayer 420 .

[0055] It should be noted that when forming the first gate dielectric sublayer 410, the material for preparing the first gate dielectric sublayer 410 is directly deposited into a predetermined position, that is, deposited into the hollow region formed by the source 200, the drain 300, and the epitaxial wafer 100 on the side close to the source 200, to simplify the preparation process. When forming the second gate dielectric sublayer 420, the material for preparing the second gate dielectric sublayer 420 is deposited as a whole layer onto the surface of the first gate dielectric sublayer 410 and the uncovered surface of the epitaxial wafer 100. The portion of the material for preparing the second gate dielectric sublayer 420 located on top of the first gate dielectric sublayer 410 will be etched in subsequent operations to ensure that the remaining hollow region between the first gate dielectric sublayer 410 and the drain 300 can be fully filled with the material for preparing the second gate dielectric sublayer 420, thereby ensuring the quality of the composite gate dielectric layer 400 and thereby enabling the composite gate dielectric layer 400 to effectively play a regulatory role in the metal oxide semiconductor high electron mobility transistor.

[0056] It should be understood that the epitaxial wafer can be prepared in advance in the front-end process, or the epitaxial wafer can be prepared by an upstream manufacturer. Figure 2 As shown, the epitaxial wafer 100 may include a substrate 110, a nucleation layer 120, a buffer layer 130, a channel layer 140, an insertion layer 150, a barrier layer 160, and a cap layer 170, which are arranged in sequence. These film layers are also pre-formed in the epitaxial wafer. Of course, the epitaxial wafer may also include other film layers as required, which will not be described in detail.

[0057] Exemplarily, a method for preparing a metal oxide semiconductor high electron mobility transistor is provided.

[0058] The nucleation layer 120 is made of AlN; the buffer layer 130 is made of GaN; the channel layer 140 is made of GaN; the insertion layer 150 is made of AlN; the barrier layer 160 is made of AlGaN; and the cap layer 170 is made of GaN. The preparation method includes the following steps: Step 1, cleaning the original wafer: ultrasonically clean the epitaxial wafer 100. After cleaning, blow dry with nitrogen and then check with an optical microscope to ensure that the sample surface is free of contamination to form Figure 3a The structure shown.

[0059] Step 2, perform the first photolithography on the epitaxial wafer 100. The first photolithography exemplarily includes processes such as coating, pre-baking, exposure, post-baking, development and hardening; and perform mesa isolation, such as Figure 3b As shown, an AlGaN / AlN / GaN heterojunction is etched by inductively coupled plasma (ICP) to form an active region on the surface of the epitaxial wafer 100, thereby achieving mutual isolation of devices.

[0060] Step 3: Perform a second photolithography on the epitaxial wafer 100 after the mesa isolation; and evaporate the materials for the source 200 and the drain 300. Use an electron beam evaporation system to deposit titanium (Ti) / aluminum (Al) / nickel (Ni) / gold (Au) and other materials to form contact electrodes of the source 200 and the drain 300 on the channel layer 140. Then, perform rapid annealing to form ohmic contacts between the source 200 and the channel layer 140 and between the drain 300 and the channel layer 140 to form Figure 3c The structure shown.

[0061] Step 4: Perform a third photolithography on the epitaxial wafer 100 after the step 3 operation and deposit the first gate dielectric sublayer 410. For example, the material Al2O3 of the first gate dielectric sublayer 410 is deposited in the hollow region near the source 200 by atomic layer deposition technology. Figure 3d As shown, the hollowed-out area in step 4 is partially filled to form the first gate dielectric sub-layer 410 , and the remaining hollowed-out area remains hollowed-out.

[0062] Step 5, such as Figure 3e As shown, a second gate dielectric sublayer 420 is deposited on the epitaxial wafer 100 after the first gate dielectric sublayer 410 is deposited. For example, HfO2, a material of the second gate dielectric sublayer 420, is deposited on the entire composite gate dielectric layer 400 by atomic layer deposition technology.

[0063] Step 6: Perform the fourth photolithography on the epitaxial wafer 100 after the second gate dielectric sublayer 420 is deposited. Then, perform ICP etching. For example, the excess HfO2 covering one side of the first gate dielectric sublayer 410 is etched away by ICP, so that the material of the second gate dielectric sublayer 420 is only filled in the Figure 3f The remaining hollow area.

[0064] Step 7: After etching the excess HfO2 on one side of the gate 500 source 200 electrode, the epitaxial wafer 100 is subjected to a fifth photolithography and the gate 500 preparation material is evaporated. For example, Ni / Au is deposited by an electron beam evaporation system to metallize the gate 500, forming a Schottky contact between the gate 500 and the composite gate dielectric layer 400 to form a gate 500. Figure 2 The structure in .

[0065] In order to make the technical solution, implementation purpose and implementation details of the metal oxide semiconductor high electron mobility transistor provided in the embodiments of the present application clearer, each step is further described in detail through the following specific embodiments. The specific steps are as follows.

[0066] Specific steps 1. Clean the original wafer: Ultrasonic cleaning is performed in acetone (3 times), isopropyl alcohol (3 times), deionized water (2 times), dilute hydrochloric acid (1:3 hydrochloric acid: water) (1 time), and deionized water (1 time), for 5 minutes each time. The ultrasonic cleaning machine is set to 80W power and 100kHz frequency. After cleaning, blow dry with nitrogen gas and inspect the sample using an optical microscope to ensure that the sample surface is free of contamination.

[0067] Specific step 2, first patterning lithography: First, clean epitaxial wafer 100 in a plasma cleaner for 5 minutes, with an oxygen (O2) flow rate of 100 sccm and an RF power of 100 W. Epitaxial wafer 100 is attached to a benchtop spin coater and spin-coated with SUN 9i negative photoresist at a speed of 500 rpm for 6 seconds, followed by a further spin-coating speed of 5000 rpm for 60 seconds. After the spin coat is complete, epitaxial wafer 100 is removed and placed on a 110°C hot plate in a benchtop baker for 90 seconds. The corresponding mask is then installed, and the exposure machine parameters are set to 3.8 seconds for exposure time, 20μm for gap, and soft contact for contact type, and the epitaxial wafer is exposed. Afterwards, the exposed epitaxial wafer 100 was placed on a 110°C hot plate in a benchtop adhesive baker and post-baked for 90 seconds. The epitaxial wafer 100 was then immersed in SUN-238D photoresist developer for 47 seconds, rinsed in deionized water for 20 seconds, and finally dried with nitrogen. The dried epitaxial wafer 100 was then placed on a 120°C hot plate in a benchtop adhesive baker for 4 minutes to harden the film.

[0068] Next, mesa isolation was performed: the epitaxial wafer was cleaned for 5 minutes using a plasma cleaner with an O2 flow rate of 100 sccm and an RF power of 100 W. A high-power inductively coupled plasma (ICP) system was used to etch the AlGaN / AlN / GaN heterojunction to a depth of approximately 100 nm using a Cl2 / BCl3 / Ar gas mixture (flow ratio of 10 / 25 / 5 sccm). The ICP power was 550 W, the RF power was 100 W, and the etching temperature was 0°C. This was to isolate the active area.

[0069] Specific step 3 involves a second patterning process and evaporation of materials for the source 200 and drain 300 electrodes. Before evaporation, the epitaxial wafer 100 must be cleaned using a plasma cleaner for 5 minutes with an O2 flow rate of 100 sccm and an RF power of 100 W. Ti / Al / Ni / Au (thicknesses of 20 / 120 / 45 / 55 nm, respectively) are deposited using an electron beam evaporation system to form the metal electrodes for the source 200 and drain 300 electrodes. The epitaxial wafer 100 is then immersed in an acetone solution for at least 10 minutes. The surface of the epitaxial wafer is then rinsed with a syringe to remove excess metal. If removal is difficult, ultrasonic evaporation can be used. The epitaxial wafer is then rinsed twice with ethanol and deionized water, respectively, and then blown dry with nitrogen. Afterwards, ohmic contacts are made between the source 200 and the channel layer 140 , and between the drain 300 and the channel layer 140 : the epitaxial wafer 100 is rapidly annealed at 850° C. for 30 seconds in nitrogen to form ohmic contacts, and then cleaned twice each with acetone, ethanol, and deionized water.

[0070] Specifically, step 4 involves performing a third patterning lithography step and growing the first gate dielectric sublayer 410 made of Al2O3 material. The epitaxial wafer 100 is first cleaned in a plasma cleaner for 5 minutes with an O2 flow rate of 100 sccm and an RF power of 100 W. Before the actual atomic layer deposition (ALD) process, the growth furnace is left empty for a period of time to stabilize the ALD state. A 20 nm thick layer of Al2O3 is then deposited at 160°C with a carrier gas flow rate of 80 sccm and a vent gas flow rate of 400 sccm. Finally, ultrasonic cleaning is performed twice each with acetone, SUN-80R photoresist stripper, ethanol, and deionized water, optionally with heat as an auxiliary, to form the first gate dielectric sublayer 410.

[0071] Specifically, step 5 involves growing HfO2 material to form the second gate dielectric sublayer 420: The epitaxial wafer is first cleaned in a plasma cleaner for 5 minutes with an O2 flow rate of 100 sccm and an RF power of 100 W. Before the actual atomic layer deposition (ALD) process, the growth furnace is left empty for a period of time to stabilize the ALD state. A 20 nm thick layer of HfO2 is then deposited at 250°C with a carrier gas flow rate of 80 sccm and a vent gas flow rate of 400 sccm. Finally, ultrasonic cleaning is performed twice each with acetone, SUN-80R photoresist stripper, ethanol, and deionized water, optionally with heating as an auxiliary.

[0072] Specific step 6 involves a fourth patterning and etching of the HfO2 material layer on the surface of the first gate dielectric sublayer 410: First, perform plasma cleaning for 5 minutes using the same parameters as above. Then, etch the epitaxial wafer 100 using a Cl2 / BCl3 / Ar gas mixture (flow ratio of 10 / 25 / 5 sccm) to a depth of approximately 20 nm, using an ICP power of 550 W, an RF power of 100 W, and an etching temperature of 0°C. This is to remove the HfO2 on the surface of the first gate dielectric sublayer 410. Repeat the stripping and cleaning steps.

[0073] Specific step 7, fifth patterning photolithography and evaporation of gate 500 materials: First, plasma clean for 5 minutes, then electron beam evaporation to form Schottky gate 500. Finally, soak the epitaxial wafer in acetone for at least 10 minutes to strip off excess metal. If stripping is difficult, ultrasonic assisted removal can be used. Then, rinse twice with ethanol and deionized water, respectively, and then blow dry with nitrogen. The device is complete.

[0074] In order to further clearly illustrate the advantages of the metal oxide semiconductor high electron mobility transistor using the composite gate dielectric layer 400 provided in the embodiment of the present application compared to the metal oxide semiconductor high electron mobility transistor using a single gate dielectric layer in the related art, simulation data analysis of the two is now performed.

[0075] Figure 4a The transfer characteristic curve of the metal oxide semiconductor high electron mobility transistor when Al2O3 is used as the gate dielectric layer, that is, the transfer characteristic curve of the Al2O3 MOS-HEMT; Figure 4b is the transfer characteristic curve of the metal oxide semiconductor high electron mobility transistor when HfO2 is used as the gate dielectric layer, that is, the transfer characteristic curve of the HfO2 MOS-HEMT; Figure 4c is the transfer characteristic curve of the metal oxide semiconductor high electron mobility transistor when Al2O3 / HfO2 is used as the composite gate dielectric layer 400, that is, the transfer characteristic curve of the Al2O3 / HfO2 MOS-HEMT. It can be understood that, if Figures 4a to 4c As shown, the horizontal axis is the gate voltage (V g ); the left vertical axis is the drain current (I ds ), the right vertical axis is the transconductance (g m ). Figure 4a-4c The solid line is the curve of drain current changing with gate voltage, the dotted line is the curve of transconductance changing with gate voltage, and the source-drain voltage V ds Fixed at 10 V, the gate voltage V g Sweep from -10 V to 10 V.

[0076] Specifically, Figure 4a Medium Al2O3 MOS-HEMT, peak transconductance (g m,max ) is 65.1 mS / mm, and the threshold voltage (V th ) is -4.77 V. Figure 4b Medium HfO2MOS-HEMT, g m,max 74.5 mS / mm, V th -0.85 V. g m,max The improvement is because the higher dielectric constant of HfO2 enhances the gate 500 control capability.th The positive shift of is also due to the increase in dielectric constant.

[0077] Figure 4c Al2O3 / HfO2 MOS-HEMT, g m,max 78.7 mS / mm, V th is -1.96 V. Compared with HfO2MOS-HEMT, the g of the MOS-HEMT using Al2O3 / HfO2 as the composite gate dielectric layer 400 in the embodiment of the present application is m,max This is attributed to the optimization of the electric field distribution and the improvement of electron transfer efficiency by the local electric field control technology, V th The negative shift of is due to the reduction of gate capacitance per unit area due to the incorporation of lower dielectric constant materials.

[0078] Figure 4d This is a data summary of the peak transconductance of metal oxide semiconductor high electron mobility transistors made of different materials. The horizontal axis represents the type of gate dielectric material used in the device. Specifically, the gate dielectric materials used are Al2O3, Al2O3 / HfO2, Al2O3 / HfZrO, HfO2, and HfZrO. It should be understood that the dielectric constant values ​​of the materials increase from left to right in this order. The vertical axis represents the peak transconductance (g m,max ). Figure 4d The white solid color bar graph in the middle represents the devices using a single gate dielectric layer (such as Al2O3, HfO2 and HfZrO), and the shaded bar graph represents the devices using a composite gate dielectric layer 400 (such as Al2O3 / HfO2 and Al2O3 / HfZrO). Obviously, the g of the device using the composite gate dielectric layer 400 is m,max This is higher than the corresponding device with a single gate dielectric layer, which is consistent with the previous trend.

[0079] Figure 5a The breakdown voltage curves of the metal oxide semiconductor high electron mobility transistor provided in the embodiment of the present application and the metal oxide semiconductor high electron mobility transistor in the related art are shown. Figure 5a The horizontal axis is the breakdown voltage (V bd ), the vertical axis is the drain current (I ds ). Figure 5a The solid line is the breakdown curve of Al2O3 / HfO2 MOS-HEMT, the dashed line is the breakdown curve of HfO2MOS-HEMT, and the dotted line is the breakdown curve of Al2O3 MOS-HEMT. g Fixed to -7 V, ensuring that all devices are in the off state. It should be understood that Figure 5a The breakdown voltage is defined as the gate voltage (V g) is kept at -7 V to maintain the device in the off state, the drain-source voltage (V ds ).

[0080] Specifically, Figure 5a For Al2O3 MOS-HEMT, HfO2 MOS-HEMT and V of Al2O3 / HfO2 MOS-HEMT bd The V of Al2O3 / HfO2MOS-HEMT is compared. bd V of HfO2 MOS-HEMT bd This is because the non-uniform electric field distribution causes the breakdown of the device to be a local breakdown close to the drain side rather than a uniform breakdown.

[0081] Figure 5b This graph summarizes the breakdown voltage of metal oxide semiconductor high electron mobility transistors fabricated from different materials. The horizontal axis represents the type of gate dielectric material used in the device. Specifically, the gate dielectric materials used are Al2O3, Al2O3 / HfO2, Al2O3 / HfZrO, HfO2, and HfZrO. It should be understood that the dielectric constant values ​​of the materials increase in this order from left to right. The vertical axis represents the breakdown voltage. Figure 5b The white solid color bar graph in the middle represents devices that uniformly use a single gate dielectric layer (such as Al2O3, HfO2, and HfZrO), and the shaded bar graph represents devices that use a composite gate dielectric layer 400 (such as Al2O3 / HfO2 and Al2O3 / HfZrO). Obviously, from left to right, V bd The breakdown voltage of the Al2O3 / HfO2 MOS-HEMT and Al2O3 / HfZrO MOS-HEMT is very close to that of their corresponding uniform high-k devices, demonstrating the feasibility and effectiveness of the embodiments of the present invention in improving breakdown performance and device reliability.

[0082] Figure 6a The gate 500 capacitance curves of the metal oxide semiconductor high electron mobility transistor provided in the embodiment of the present application and the metal oxide semiconductor high electron mobility transistor in the related art are shown. Figure 6a The horizontal axis is the gate voltage (V g ), the vertical axis is the gate 500 capacitance (C g ). Figure 6aThe solid line is the capacitance curve of Al2O3 / HfO2 MOS-HEMT, the dashed line is the capacitance curve of HfO2 MOS-HEMT, and the dotted line is the capacitance curve of Al2O3 MOS-HEMT. The source-drain voltage V ds Fixed to 10V. Specifically, Figure 6a shows the source-drain voltage V ds = 10 V and a sweep frequency of 1 MHz, the capacitance-voltage (C g -V g ) curve. Capacitor C g In V g = 3 V. C g The values ​​are 396 pF / mm, 474 pF / mm and 428 pF / mm respectively, and the differences are due to the dielectric constant of the composite gate dielectric layer 400 material.

[0083] Figure 6b The gate capacitance (C) of the metal oxide semiconductor high electron mobility transistor prepared by different materials is g ). The horizontal axis represents the type of gate dielectric material used in the device. Specifically, the gate dielectric materials are Al2O3, Al2O3 / HfO2, Al2O3 / HfZrO, HfO2, and HfZrO. It should be understood that the dielectric constant values ​​of the materials increase from left to right in this order. The vertical axis represents the breakdown voltage (V bd ). Figure 6b The white solid color bar graph in the middle represents devices that uniformly use a single gate dielectric layer (such as Al2O3, HfO2, and HfZrO), and the shaded bar graph represents devices that use a composite gate dielectric layer 400 (such as Al2O3 / HfO2 and Al2O3 / HfZrO). Obviously, the C g values, showing a positive correlation with the dielectric constant.

[0084] Figure 7a Cutoff frequency curves of the metal oxide semiconductor high electron mobility transistor provided in the embodiment of the present application and the metal oxide semiconductor high electron mobility transistor in the related art. Figure 7a The horizontal axis is the gate voltage (V g ), the vertical axis is the cut-off frequency (f T ). Figure 7a The solid line is the (cut-off) frequency curve of Al2O3 / HfO2MOS-HEM, the dashed line is the frequency curve of HfO2MOS-HEM, and the dotted line is the frequency curve of Al2O3MOS-HEM. The source-drain voltage Vds Fixed to 10 V. Specifically, Figure 7a As shown, Al2O3MOS-HEMT has a V g = -1.4 V when the cutoff frequency is reached. T Peak (36.5 MHz), HfO2MOS-HEMT and Al2O3 / HfO2MOS-HEMT at V g = 2.8 V and 2.2 V when f T Peaks at 24.5 MHz and 29.4 MHz. T The increase is mainly due to C g The decrease of g m,max The increase also contributed to the

[0085] Figure 7b The cutoff frequency (f T ) data summary chart. Figure 7b Source-drain voltage V ds The value is fixed at 10 V, and the peak cutoff frequency of the device is taken. The horizontal axis is the type of gate dielectric material used in the device, and the materials are Al2O3, Al2O3 / HfO2, Al2O3 / HfZrO, HfO2 and HfZrO. The vertical axis is the cutoff frequency (f T ). Figure 7b The white solid color bar graph in the middle represents devices that uniformly use a single gate dielectric layer (such as Al2O3, HfO2, and HfZrO), and the shaded bar graph represents devices that use a composite gate dielectric layer 400 (such as Al2O3 / HfO2 and Al2O3 / HfZrO). Figure 7b The f of five devices is summarized in T value, f T The results show that the local electric field controlled non-uniform composite gate dielectric can effectively alleviate the typical f T Performance degradation problem, to achieve a balance between frequency and performance.

[0086] Figure 8 This is a grayscale image of the two-dimensional electric field distribution under the gate of the metal oxide semiconductor high electron mobility transistor provided in an embodiment of the present application. Figure 8 The horizontal axis in the middle is the position from left to right relative to the gate 500, and there is no vertical axis. The example on the left is the scale of the electric field, that is, the actual electric field value is 20log 10 It is worth noting that the scale values ​​are not the actual electric field values, but the relative relationship of the electric field distribution.

[0087] Figure 8Region a in the center represents the composite gate dielectric layer 400 (insulating) directly beneath the gate 500. The region outlined by the dashed box b in the vertical direction corresponding to horizontal axis 2 represents the interface. It should be understood that region b is merely illustrative and does not fully correspond to the vertically darkened region in the diagram. Horizontal axis 0 represents the composite gate dielectric layer 400 directly beneath the leftmost side of the gate 500 (on the source 200 side), and horizontal axis 4 represents the composite gate dielectric layer 400 directly beneath the rightmost side of the gate 500 (on the drain 300 side). The left side of the interface shows the lateral electric field distribution beneath the first gate dielectric sublayer 410 (Al2O3) (including the channel layer 140 and barrier layer 160), while the right side of the interface shows the lateral electric field distribution beneath the second gate dielectric sublayer 420 (HfO2) (including the channel layer 140 and barrier layer 160). Figure 8 FIG. 4 shows that there is an electric field peak at the 2 μm interface between the first gate dielectric sub-layer 410 and the second gate dielectric sub-layer 420 .

[0088] Figure 9 This is a data summary of the breakdown voltage and cutoff frequency of metal oxide semiconductor high electron mobility transistors prepared with different materials. Figure 9 The data in the figure show that the V bd Comparable to high-k devices using a uniform single gate dielectric layer, while providing better g m,max and f T Specifically, compared with HfO2 MOS-HEMT and HfZrO MOS-HEMT, Al2O3 / HfO2 MOS-HEMT and Al2O3 / HfZrO MOS-HEMT respectively make f T increased by 20.0% and 35.2%, while the breakdown voltage V bd They only decreased by 1.7% and 2.3% respectively.

[0089] Obviously, those skilled in the art may make various changes and modifications to the embodiments of the present application without departing from the spirit and scope of the present application. Thus, if such modifications and variations of the present application fall within the scope of the claims of the present application and their equivalents, the present application is intended to include such modifications and variations.

Claims

1. A metal oxide semiconductor high electron mobility transistor, characterized in that: include: epitaxial wafers; A source electrode and a drain electrode are located on one side of the epitaxial wafer and are spaced apart; a composite gate dielectric layer located on one side of the epitaxial wafer and between the source and the drain; the composite gate dielectric layer comprising at least two gate dielectric sublayers arranged along the direction of arrangement of the source and the drain and made of different materials; of the at least two gate dielectric sublayers, the gate dielectric sublayer proximal to the drain has the largest dielectric constant and is greater than 3.9 F / m; The gate is located on the side of the composite gate dielectric layer away from the epitaxial wafer, and the orthographic projection of the gate on the epitaxial wafer at least covers the orthographic projection of the interface between the gate dielectric sublayer with the largest dielectric constant and the adjacent gate dielectric sublayer on the epitaxial wafer.

2. The metal oxide semiconductor high electron mobility transistor according to claim 1, characterized in that Adjacent gate dielectric sublayers are in seamless contact at the interface.

3. The metal oxide semiconductor high electron mobility transistor according to claim 1 or 2, characterized in that: The composite gate dielectric layer includes two gate dielectric sublayers; the two gate dielectric sublayers are a first gate dielectric sublayer and a second gate dielectric sublayer, wherein the second gate dielectric sublayer is close to the drain along the arrangement direction of the source and the drain; the first gate dielectric sublayer is close to the source along the arrangement direction of the source and the drain; the orthographic projection of the gate on the epitaxial wafer covers the orthographic projection of the interface between the first gate dielectric sublayer and the second gate dielectric sublayer on the epitaxial wafer.

4. The metal oxide semiconductor high electron mobility transistor according to claim 3, characterized in that The first gate dielectric sublayer forms a first region in an area where the orthographic projection of the epitaxial wafer is covered by the orthographic projection of the gate on the epitaxial wafer, and the second gate dielectric sublayer forms a second region in an area where the orthographic projection of the epitaxial wafer is covered by the orthographic projection of the gate on the epitaxial wafer. The size ratio of the second region to the first region in the arrangement direction of the source and the drain is set according to a preset ratio.

5. The metal oxide semiconductor high electron mobility transistor according to claim 4, characterized in that The preset ratio is 1:

1.

6. The metal oxide semiconductor high electron mobility transistor according to claim 3, characterized in that The first gate dielectric sublayer is made of a material selected from the group consisting of aluminum oxide and silicon dioxide. And / or, the second gate dielectric sub-layer is made of one of aluminum oxide, hafnium dioxide or hafnium zirconium oxide.

7. The metal oxide semiconductor high electron mobility transistor according to claim 6, characterized in that The dielectric constants of the materials used to make the first gate dielectric sublayer and the second gate dielectric sublayer are both greater than 3.9 F / m.

8. A method for preparing a metal oxide semiconductor high electron mobility transistor, characterized in that: For preparing the metal oxide semiconductor high electron mobility transistor according to any one of claims 1 to 7, the preparation method comprises: Isolate the mesa and evaporate the source and drain electrodes on the epitaxial wafer; A composite gate dielectric layer is formed on the epitaxial wafer and between the source and the drain; the composite gate dielectric layer includes at least two gate dielectric sublayers arranged along the arrangement direction of the source and the drain and made of different materials; among the at least two gate dielectric sublayers, the gate dielectric sublayer near the drain has the largest dielectric constant and is greater than 3.9 F / m; A gate is formed on the composite gate dielectric layer, and an orthographic projection of the gate on the epitaxial wafer at least covers an orthographic projection of an interface between the gate dielectric sublayer with the largest dielectric constant and an adjacent gate dielectric sublayer on the epitaxial wafer.

9. The method for preparing a metal oxide semiconductor high electron mobility transistor according to claim 8, wherein: The composite gate dielectric layer includes two gate dielectric sublayers; the two gate dielectric sublayers are a first gate dielectric sublayer and a second gate dielectric sublayer; wherein the second gate dielectric sublayer is close to the drain along the arrangement direction of the source and the drain; and the first gate dielectric sublayer is close to the source along the arrangement direction of the source and the drain; The method of forming a composite gate dielectric layer on the epitaxial wafer and between the source and the drain comprises: The first gate dielectric sublayer is formed first, and then the second gate dielectric sublayer is formed.

10. The method for preparing a metal oxide semiconductor high electron mobility transistor according to claim 9, wherein: The method of first forming the first gate dielectric sublayer and then forming the second gate dielectric sublayer includes: Depositing and forming the first gate dielectric sublayer on a side of the epitaxial wafer close to the source electrode; The preparation material of the second gate dielectric sublayer is deposited entirely on the epitaxial wafer and the first gate dielectric sublayer; and a portion of the preparation material of the second gate dielectric sublayer on the first gate dielectric sublayer is removed to form the second gate dielectric sublayer.

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