Pixel circuit and display device

Abstract

Some embodiments of the present application disclose a pixel circuit and a display device wherein the pixel circuit may include a first transistor, a second transistor, a third transistor and a light-emitting element wherein the first transistor may be used to provide a driving signal for the light-emitting element and the second transistor may be used to provide a driving signal for the light-emitting element; the second transistor can be used for providing a control signal for controlling the light-emitting duration of the light-emitting element for the first transistor, and the third transistor can be used for providing a reset signal for the second transistor and the first transistor in response to a reset control signal received by the grid electrode. According to the pixel circuit, the first transistor and the second transistor are combined with a pulse amplitude modulation and pulse width modulation driving mode, and meanwhile, only one third transistor is used for providing reset signals for the first transistor and the second transistor, so that the number of devices in the pixel circuit is reduced, and the cost is reduced. The area occupied by a pixel circuit in the display panel is saved, and the pixel density and the resolution of the display panel can be effectively improved.

Description

Pixel circuit and display device

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to Chinese patent applications filed on July 18, 2023, with application number 202310882614.6; filed on September 18, 2023, with application number 202311206387.1; and filed on September 22, 2023, with application number 202311230211.X, the entire contents of which are incorporated by reference into this application. Technical Field

[0003] The present application relates to the technical field of display devices, and in particular to a pixel circuit and a display device. Background Art

[0004] In the related art, a display panel has multiple pixel circuits. Since micro light emitting diodes (Micro-LEDs, also known as micro LEDs, μLEDs) have advantages over active matrix organic light emitting diodes or active matrix organic light emitting diodes (AMOLEDs), such as smaller size, faster response speed, higher luminous efficiency, greater stability, and longer service life, each pixel circuit includes the above-mentioned micro LEDs.

[0005] Because the IV characteristic curve of micro-LEDs is very steep, that is, the change in the voltage between the two poles corresponding to the micro-LED current from low grayscale to high grayscale is extremely small, if traditional driving methods such as pulse amplitude modulation (PAM) driving are adopted, the driving circuit requires an extremely fast clock signal to meet the extremely high voltage resolution. For example, complementary metal oxide semiconductor (CMOS) driving is adopted. However, CMOS driving has adverse effects on the flexibility, transparency, and thickness of the panel. If another traditional driving method such as pulse width modulation (PWM) driving method is adopted, the gate drive on array (GOA) integrated circuit on the array substrate can be used to generate the driving control signal to achieve higher grayscale. However, the driving speed of the GOA circuit is limited. When the resolution is high, multiple activations will cause the light-emitting element to be unable to emit light for a long period of time, which in turn limits the increase in the number of grayscales.

[0006] Therefore, combining PWM and PAM drive methods allows the PAM module to increase the driving voltage of the light-emitting element while the PWM module prolongs the light-emitting element's emission time, thereby achieving a higher grayscale without excessively demanding circuit drive speed. However, using both drive methods inevitably increases the number of components in the pixel circuit and occupies more area on the display panel.

[0007] Summary of the Invention

[0008] According to some embodiments of the present application, a pixel circuit may include a first transistor, a second transistor, a third transistor and a light-emitting element, wherein: the first electrode of the first transistor and the first electrode of the second transistor can be used to receive a power supply signal, the second electrode of the first transistor is connected to the light-emitting element, and the second electrode of the second transistor is connected to the gate of the first transistor; the second electrode of the third transistor is connected to the gate of the first transistor and the gate of the second transistor, the first electrode of the third transistor can be used to receive a reset signal, and the gate of the third transistor can be used to receive a reset control signal; the first transistor can be used to provide a driving signal for the light-emitting element, the second transistor can be used to provide a control signal to the first transistor to control the light-emitting duration of the light-emitting element, and the third transistor can be used to provide the reset signal to the second transistor and the first transistor in response to the reset control signal received at the gate.

[0009] According to some embodiments of the present application, a pixel circuit may include a first transistor, a second transistor, a third transistor, a fifth transistor and a light-emitting element, wherein the first electrode of the first transistor and the first electrode of the second transistor can be used to receive a power supply signal, the second electrode of the first transistor is connected to the light-emitting element, the second electrode of the second transistor is connected to the gate of the first transistor, the first electrode of the fifth transistor is connected to the gate of the second transistor, the second electrode of the fifth transistor is connected to the second electrode of the second transistor, the gate of the fifth transistor can be used to receive a second compensation and reset control signal, the second electrode of the third transistor is connected to the gate of the first transistor and the second electrode of the fifth transistor, the first electrode of the third transistor can be used to receive a reset signal, and the gate of the third transistor The pole can be used to receive a reset control signal; the driving stage of the pixel circuit may include a first reset stage, a first compensation stage, a first data writing stage, a second reset stage, a second compensation stage, a second data writing stage and a light-emitting stage, wherein: the reset control signal is a valid level in the first reset stage and the second reset stage, and the reset control signal is an invalid level in the first compensation stage, the first data writing stage, the second compensation stage, the second data writing stage and the light-emitting stage; the second compensation and reset control signal are valid levels in the first reset stage and the first compensation stage, and the second compensation and reset control signal are invalid levels in the first data writing stage, the second reset stage, the second compensation stage, the second data writing stage and the light-emitting stage.

[0010] According to some embodiments of the present application, a pixel circuit may include a first transistor, a second transistor, a third transistor, a tenth transistor and a light-emitting element; the second electrode of the first transistor is connected to the light-emitting element, and the second electrode of the second transistor is connected to the gate of the first transistor; the second electrode of the third transistor is connected to the gate of the first transistor and the gate of the second transistor, and the gate of the third transistor is used to receive a reset control signal; the second electrode of the tenth transistor is connected to the gate of the first transistor, and the gate of the tenth transistor is used to receive a third data write control signal; the driving stage of the pixel circuit may include a first reset stage, a first compensation stage, a first data write stage, a second reset stage, a second compensation stage, a second data write stage and a light-emitting stage, wherein: the reset control signal is at a valid level in the first reset stage and the second reset stage; the third data write control signal is at a valid level in the second data write stage.

[0011] A display device according to some embodiments of the present application may include a data driving circuit, a scan driving circuit, data lines, scan lines, and any one of the above pixel circuits. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] FIG1 is a schematic diagram of a planar structure of a display device according to some embodiments of the present application;

[0013] FIG2 is a schematic structural diagram of a pixel circuit according to some embodiments of the present application;

[0014] FIG3 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0015] FIG4 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0016] FIG5 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0017] FIG6 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0018] FIG7 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0019] FIG8 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0020] FIG9 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0021] FIG10 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0022] FIG11 is a timing diagram of driving signals of a pixel circuit according to some embodiments of the present application;

[0023] FIG12 is a schematic diagram of a transistor conduction state in a pixel circuit according to some embodiments of the present application;

[0024] FIG13 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0025] FIG14 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0026] FIG15 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0027] FIG16 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0028] FIG17 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0029] FIG18 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0030] FIG19 is a timing diagram of driving signals of a pixel circuit according to some other embodiments of the present application;

[0031] FIG20 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0032] FIG21 is a timing diagram of driving signals of a pixel circuit according to some other embodiments of the present application;

[0033] FIG22 is a timing diagram of driving signals of a pixel circuit according to some other embodiments of the present application;

[0034] FIG23 is a schematic structural diagram of a pixel circuit according to yet other embodiments of the present application;

[0035] FIG24 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0036] FIG25 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0037] FIG26 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0038] FIG27 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0039] FIG28 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0040] FIG29 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0041] FIG30 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0042] FIG31 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0043] FIG32 is a timing diagram of driving signals of a pixel circuit according to some other embodiments of the present application;

[0044] FIG33 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0045] FIG34 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0046] FIG35 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0047] FIG36 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0048] FIG37 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0049] FIG38 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0050] FIG39 is a schematic diagram of a transistor conduction state in a pixel circuit according to some other embodiments of the present application;

[0051] FIG40 is a timing diagram of driving signals of a pixel circuit according to other embodiments of the present application;

[0052] FIG41 is a timing diagram of driving signals of a pixel circuit according to some other embodiments of the present application;

[0053] FIG42 is a schematic structural diagram of a pixel circuit according to some other embodiments of the present application;

[0054] FIG43 is a timing diagram of driving signals of a pixel circuit according to other embodiments of the present application;

[0055] FIG44 is a timing diagram of driving signals of a pixel circuit according to some other embodiments of the present application;

[0056] FIG45 is a timing diagram of driving signals of a pixel circuit according to some other embodiments of the present application;

[0057] FIG46 is a schematic structural diagram of another display device according to some embodiments of the present application;

[0058] FIG47 is a first structural diagram of a pixel circuit according to still other embodiments of the present application;

[0059] FIG48 is a first timing diagram of control signals according to still other embodiments of the present application;

[0060] FIG49 is a schematic diagram of a pixel circuit in a first reset phase according to still other embodiments of the present application;

[0061] FIG50 is a schematic diagram of a pixel circuit in a first compensation stage according to some further embodiments of the present application;

[0062] FIG51 is a schematic diagram of a pixel circuit in a first data writing phase according to still other embodiments of the present application;

[0063] FIG52 is a schematic diagram of a pixel circuit in a second reset phase according to still other embodiments of the present application;

[0064] FIG53 is a schematic diagram of a pixel circuit in a second compensation stage according to still other embodiments of the present application;

[0065] FIG54 is a schematic diagram of a pixel circuit in a second data writing phase according to still other embodiments of the present application;

[0066] FIG55 is a first schematic diagram of a pixel circuit in a light-emitting phase according to still other embodiments of the present application;

[0067] FIG56 is a second schematic diagram of a pixel circuit in a light-emitting phase according to still other embodiments of the present application;

[0068] FIG57 is a second structural diagram of a pixel circuit according to still other embodiments of the present application;

[0069] Figure 58 is a second timing diagram of control signals according to some further embodiments of the present application. DETAILED DESCRIPTION

[0070] In order to make the purpose, implementation methods and advantages of this application clearer, some implementation methods of this application will be clearly and completely described below in combination with the drawings in some embodiments of this application. Obviously, some of the described embodiments are only part of the embodiments of this application, not all of the embodiments.

[0071] FIG1 is a plan view of a display device according to some embodiments of the present application. Referring to FIG1 , the display device may include a pixel array unit 100, a control circuit 300, a data driver circuit 500 (e.g., a data driver), and a scan driver circuit 700 (e.g., a gate driver). The pixel array unit 100 may include a plurality of scan lines SL and a plurality of data lines DL disposed on a substrate, and a plurality of pixels P disposed in a plurality of pixel regions defined by intersections of the plurality of scan lines SL and the plurality of data lines DL.

[0072] Each of the plurality of pixels P may include a pixel circuit in an embodiment of the present application that displays an image based on a scan signal provided by an adjacent scan line SL and a data signal provided by an adjacent data line DL. Specifically, the pixel circuit may include at least one thin-film transistor and at least one capacitor. The pixel circuit may be a liquid crystal unit that displays an image by driving the liquid crystal according to an electric field based on a data signal, or may be a self-luminous unit that displays an image by self-luminescence based on a data signal. In this case, the self-luminous unit may include a plasma discharge element, a quantum dot light-emitting element, an organic light-emitting element, an inorganic light-emitting element, or a micro-light-emitting diode. The signals received by the pixel circuits in the following embodiments of the present application are all provided by the above-mentioned control circuit 300, data drive circuit 500, and scan drive circuit 700.

[0073] The control circuit 300 may generate pixel data corresponding to each of the plurality of pixels P based on an image signal. The control circuit 300 may generate a data control signal based on a timing synchronization signal and provide the data control signal to the data driver circuit 500. According to one embodiment, the control circuit 300 may generate a scan control signal based on the timing synchronization signal, which may include a start signal and multiple scan clock signals, and provide the scan control signal to the scan driver circuit 700. The control circuit 300 may also generate multiple carry clock signals based on the drive mode of the scan driver circuit 700 and provide the multiple carry clock signals to the scan driver circuit 700. The data driver circuit 500 may be connected to a plurality of data lines DL provided in the pixel array unit 100. The data driver circuit 500 may receive the pixel data and data control signal from the control circuit 300, and may also receive multiple reference gamma voltages from a power supply circuit. The data driver circuit 500 may convert the pixel data into pixel-based analog data signals using the data control signal and the multiple reference gamma voltages, and may provide the pixel-based analog data signals to the corresponding data lines DL.

[0074] The scan driving circuit 700 may be connected to a plurality of scan lines SL provided in the pixel array unit 100. In detail, the scan driving circuit 700 may generate scan signals according to a predetermined order determined based on a scan control signal provided by the control circuit 300 and may provide the scan signals to corresponding scan lines SL.

[0075] As a specific embodiment, the scan driver circuit 700 can be integrated on one or both edges of the substrate according to the manufacturing process of the thin film transistor, and then connected to the multiple scan lines SL in a corresponding relationship. For example, the scan driver circuit 700 can be provided in an integrated circuit, can be packaged in a substrate or a flexible circuit film, and can be connected to the multiple scan lines SL in a one-to-one relationship.

[0076] In related art, in order to combine PWM and PAM drive methods, it is necessary to add corresponding thin-film transistors and / or capacitors to the pixel circuit. For example, both the PWM module and the PAM module require thin-film transistors for driving. To achieve a better display effect, additional circuit design is required for the thin-film transistors used for driving. This inevitably results in a larger number of components in the pixel circuit, causing the pixel array unit 100 to occupy more display panel area with the same number of light-emitting units, affecting the overall display effect of the display device. Furthermore, the number of scan lines SL and data lines DL, as well as the number of components in the control circuit 300, data driver circuit 500, and scan driver circuit 700, also need to be increased accordingly, resulting in an increase in the display device's frame area and overall weight and volume.

[0077] In view of this, according to a pixel circuit of some embodiments of the present application, as shown in FIG2 , the reference numeral 1 shown in FIG2 is a first electrode, 2 is a second electrode, and 3 is a gate. It can be understood by those skilled in the art that, due to the different levels of each signal in the pixel circuit in different implementation scenarios, for the same transistor, in one implementation scenario, the first electrode can be the source and the second electrode can be the drain, and in another implementation scenario, the first electrode can be the drain and the second electrode can be the source. In the embodiments of the present application, the first electrode and the second electrode are only used to distinguish the two pins of the transistor other than the gate, and no further limitations are given. The same is true for other embodiments of the present application and the drawings of other embodiments, and will not be repeated here.

[0078] The pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3 and a light emitting element LED, wherein:

[0079] The first electrode of the first transistor T1 and the first electrode of the second transistor T2 can be used to receive the power signal VDD, and the second electrode of the first transistor T1 is connected to the light emitting element LED. The first transistor T1 can be used to provide a driving signal for the light emitting element LED.

[0080] The second electrode of the second transistor T2 is connected to the gate of the first transistor T1. The second transistor T2 can be used to provide a control signal to the first transistor T1 to control the light emitting duration of the light emitting element.

[0081] Specifically, the first transistor T1 can provide drive signals of varying amplitudes to the light-emitting element LED, implementing a PAM drive mode, which can provide a higher drive voltage to the light-emitting element LED and thereby improve the circuit grayscale. The second transistor T2 can control the on and off state of the first transistor T1 via a light-emission duration control signal applied to the gate of the first transistor T1, thereby controlling the duration of time the first transistor T1 provides the drive signal to the light-emitting element LED. This can increase the proportion of the light-emitting device's light-emitting duration in the refresh frame, extending the light-emitting duration of the light-emitting element LED and thus implementing a PWM drive mode, thereby increasing the brightness perceived by the human eye and improving the circuit grayscale.

[0082] The second electrode of the third transistor T3 is connected to the gate of the first transistor T1 and the gate of the second transistor T2. The first electrode of the third transistor T3 can be used to receive the reset signal REF, and the gate of the third transistor T3 can be used to receive the reset control signal S3. The third transistor T3 can be used to provide the reset signal REF to the second transistor T2 and the first transistor T1 in response to the reset control signal S3 received at the gate. Specifically, when the reset control signal S3 is at an active level, the third transistor T3 is turned on, and the reset signal REF can be provided to the second electrode via the first electrode.

[0083] 1 and 2 , the reset control signal S3 is provided by the scan line SL. The reset signal REF can be provided by the data line DL or connected to a fixed potential.

[0084] The first transistor T1 and the second transistor T2 act as driving transistors. Each time the light-emitting element LED is controlled to emit light, the gate potential thereof will change. Therefore, in order to ensure that the state of the driving transistors is the same at the beginning of each light-emitting process, the first transistor T1 and the second transistor T2 need to be reset before controlling the light-emitting element LED to emit light. In the related art, since the two transistors are located at different positions in the pixel circuit, two reset transistors are usually provided for each of the two driving transistors, which increases the number of transistors in the pixel circuit to a certain extent. However, in this embodiment, the first transistor T1 and the second transistor T2 can be reset by a third transistor T3, which reduces one transistor for each pixel circuit. For the entire display device, this means that N transistors in N pixel circuits are reduced, which directly reduces the number of devices in the display device, thereby saving the area occupied by the pixel circuit in the display panel and effectively improving the pixel density and the resolution of the display panel.

[0085] In some embodiments, the light-emitting element LED may be a micro-LED, or other light-emitting elements applicable to pixel circuits, which are not limited herein.

[0086] During specific implementation, the specific model and parameters of the transistor in the embodiment of the present application can be set by those skilled in the art according to actual conditions. It can be a P-type transistor or an N-type transistor, and can be a thin film transistor (TFT), a metal-oxide-semiconductor field-effect transistor (MOSFET), or a low-temperature polysilicon (LTPS) thin film transistor. No further limitations are made here. The same applies to other transistors in the embodiment of the present application and will not be repeated.

[0087] In some embodiments, as shown in Figure 3, the above-mentioned pixel circuit may further include a first capacitor C1, the first end of the first capacitor C1 is connected to the gate of the first transistor T1, and the second pole of the first capacitor C1 can be used to receive the power supply signal VDD. Specifically, the third transistor T3 can reset the potential of the gate of the first transistor T1 to a reset voltage by charging the first capacitor C1 connected to the gate of the first transistor T1. In this embodiment, the working principle of the third transistor T3 is the same as that in the above-mentioned embodiment and will not be repeated here. In a specific embodiment, the specific model and capacitance of the first capacitor C1 can be set by those skilled in the art according to actual conditions, and no further restrictions are made here. The same applies to other capacitors in the embodiments of the present application and will not be repeated here.

[0088] In some embodiments, as shown in FIG4 , the pixel circuit may further include a fourth transistor T4 , wherein a first electrode of the fourth transistor T4 is connected to a gate of the first transistor T1 , a second electrode of the fourth transistor T4 is connected to a second electrode of the first transistor T1 , and the gate of the fourth transistor T4 may be configured to receive a first compensation control signal S41 . Specifically, as shown in FIG1 and FIG4 , the first compensation control signal S41 is provided by the scan line SL.

[0089] The fourth transistor T4 can be configured to provide threshold compensation for the first transistor T1 in response to a first compensation control signal S41 received by the gate. Specifically, when the first compensation control signal S41 is at an active level, the fourth transistor T4 is turned on, compensating the voltage level of the second electrode of the first transistor T1 to the gate, thereby completing the threshold compensation for the first transistor T1.

[0090] Specifically, due to the influence of process uniformity, the drift of the threshold voltage of the first transistor T1 will affect the magnitude of the driving current or driving voltage of the light-emitting element, resulting in uneven wavelength of the light emitted by the light-emitting element, thereby affecting the display color and display effect of the panel. In the above embodiment of the present application, by adding a fourth transistor T4 between the gate and the second electrode of the first transistor T1, the threshold voltage of the first transistor T1 can be compensated, thereby achieving a better display effect. In this embodiment, the operating principle of the third transistor T3 is the same as in the above embodiment and will not be repeated here.

[0091] In some embodiments, as shown in FIG5 , the pixel circuit may further include a fifth transistor T5 , wherein a first electrode of the fifth transistor T5 is connected to the gate of the second transistor T2 , a second electrode of the fifth transistor T5 is connected to the second electrode of the second transistor T2 and the second electrode of the third transistor T3 , and the gate of the fifth transistor T5 is configured to receive a second compensation and reset control signal S1 . As shown in FIG1 and FIG5 , the second compensation and reset control signal S1 may be provided by a scan line SL.

[0092] The fifth transistor T5 can be used to provide the reset signal REF provided by the third transistor T3 received at the second electrode to the gate of the second transistor T2 through the first electrode in response to the second compensation and reset control signal S1 received through the gate; and, in response to the second compensation and reset control signal S1 received through the gate, provide threshold compensation for the second transistor T2.

[0093] Specifically, when the third transistor T3 is turned on and the second transistor T2 needs to be reset, the second compensation and reset control signal S1 is at an active level, the fifth transistor T5 is turned on, and the reset signal REF provided by the third transistor T3 is provided to the gate of the second transistor T2. When threshold compensation is required for the second transistor T2, only the first compensation control signal S41 is at an active level, the fifth transistor T5 is turned on, and the voltage level of the second electrode of the second transistor T2 is compensated to the gate, thereby completing the threshold compensation for the second transistor T2.

[0094] Specifically, due to the influence of process uniformity, the drift of the threshold voltage of the second transistor T2 will affect the magnitude of the driving current or driving voltage of the light-emitting element, resulting in uneven wavelength of the light-emitting element, thereby affecting the display color and display effect of the panel. In the above embodiment of the present application, by adding a fifth transistor T5 between the gate and the second electrode of the second transistor T2, the threshold value of the second transistor T2 can be compensated, thereby achieving a better display effect. At the same time, the above-mentioned fifth transistor T5 can be arranged between the gate of the second transistor T2 and the second electrode of the third transistor T3, and can cooperate with the third transistor T3 to reset the second transistor T2.

[0095] In some embodiments, as shown in FIG6 , a sixth transistor T6 and a seventh transistor T7 may also be included. A first electrode of the sixth transistor T6 may be configured to receive the first data signal Date_PAM. A second electrode of the sixth transistor T6 is connected to the first electrode of the first transistor T1. A gate of the sixth transistor T6 may be configured to receive a first data write control signal S42. The sixth transistor T6 may be configured to write the first data signal Date_PAM into the first electrode of the first transistor T1 in response to the first data write control signal S42 received at the gate.

[0096] The first electrode of the seventh transistor T7 can be configured to receive the second data signal Date_PWM. The second electrode of the seventh transistor T7 is connected to the gate of the second transistor T2. The gate of the seventh transistor T7 can be configured to receive the second data write control signal S2. In response to the second data write control signal S1 received at the gate, the seventh transistor T7 can write the second data signal Date_PWM into the gate of the second transistor. Specifically, as shown in Figures 1 and 6, the first data write control signal S42 and the second data write control signal S2 are provided by the scan line SL, and the first data signal Date_PAM and the second data signal Date_PWM are provided by the data line DL.

[0097] Specifically, when the fourth transistor T4 is used to perform threshold compensation for the first transistor T1, the seventh transistor T7 simultaneously writes the first data signal Date_PAM into the first electrode of the first transistor T1. The first data signal Date_PAM is a PAM-modulated data signal that can adjust the brightness of the light-emitting element by adjusting the voltage amplitude of the input signal.

[0098] In this embodiment, the working principle of the third transistor T3 is the same as that in the above embodiment, and will not be described again here.

[0099] In some embodiments, as shown in FIG7 , the pixel circuit may further include a second capacitor C2, wherein a first electrode of the second capacitor C2 is connected to a second electrode of the seventh transistor T7, and a second electrode of the second capacitor C2 is connected to the second transistor T2. The second capacitor C2 may be used to couple the second data signal Date_PWM written by the seventh transistor T7 to the second transistor T2. In this embodiment, the operating principle of the third transistor T3 is the same as in the above embodiment and will not be further described here.

[0100] In some embodiments, as shown in Figure 8, the above-mentioned pixel circuit may further include a third capacitor C3, the first electrode of the third capacitor C3 is connected to the gate of the second transistor T2 through the second capacitor C2, and the third capacitor C3 can be used to couple the light-emitting duration control signal SWEEP to the second transistor T2 and control the on and off of the second transistor. The second transistor T2 provides a control signal for controlling the light-emitting duration of the light-emitting element to the first transistor T1 according to the control of the light-emitting duration control signal SWEEP.

[0101] Specifically, in the embodiment shown in FIG8 , the second transistor T2 and the first transistor T1 are both P-type transistors, whose gates are turned on in response to a low level. The aforementioned light-emission duration control signal SWEEP is an electrical signal with a gradually decreasing level. At the initial moment of the light-emitting phase of the light-emitting element LED, the second transistor T2 is in the off state. The level of the light-emission duration control signal SWEEP gradually decreases, causing the second transistor T2 to turn on at a certain moment. Since the first electrode of the second transistor T2 is connected to the power supply signal VDD, when it turns on, the high-level power supply signal VDD will pull up the potential of the gate of the first transistor T1 through the second electrode of the second transistor T2, causing the first transistor T1 to turn off, and the light-emitting element LED to stop emitting.

[0102] In another embodiment, the second transistor T2 and the first transistor T1 are both N-type transistors, whose gates can be turned on in response to a high level. The light-emission duration control signal SWEEP is an electrical signal with a gradually increasing level. At the initial moment of the light-emitting phase of the light-emitting element LED, the second transistor T2 is in the off state. The level of the light-emission duration control signal SWEEP gradually increases, causing the second transistor T2 to turn on at a certain moment. Since the first electrode of the second transistor T2 is connected to the power supply signal VSS, when it turns on, the low-level power supply signal VSS will pull down the potential of the gate of the first transistor T1 through the second electrode of the second transistor T2, turning off the first transistor T1 and stopping the light-emitting element LED from emitting light. Specifically, in this embodiment, the operating principle of the third transistor T3 is the same as in the above embodiment and will not be further described here.

[0103] In some embodiments, as shown in FIG9 , the pixel circuit may further include an eighth transistor T8 and a ninth transistor T9. The first electrode of the eighth transistor T8 may be configured to receive a power supply signal VDD, and the second electrode is connected to the first electrode of the first transistor T1. The eighth transistor T8 may be configured to, in response to a first drive control signal EM1 received at the gate, provide the power supply signal VDD received at the first electrode to the first transistor T1 via the second electrode 2. The ninth transistor T9 may have a first electrode connected to the second electrode of the first transistor T1, and a second electrode connected to the light-emitting element LED. The ninth transistor T9 may be configured to, in response to a second drive control signal EM2 received at the gate, provide the drive signal provided by the first transistor T1 received at the first electrode to the light-emitting element LED via the second electrode 2.

[0104] To prevent leakage current from the drive transistor from affecting the normal illumination of the light-emitting element, the above embodiment incorporates two control transistors in the drive circuit. This allows the drive circuit to be turned off when the light-emitting element is not emitting light and turned back on during the light-emitting phase. Specifically, as shown in Figures 1 and 9 , the first drive control signal EM1 and the second drive control signal EM2 are provided by the scan line SL. Specifically, in this embodiment, the operating principle of the third transistor T3 is the same as in the above embodiment and will not be further described here.

[0105] The overall operating principle of the above-mentioned pixel circuit is described below with reference to a specific embodiment. As shown in Figure 10, the above-mentioned pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, a sixth transistor T6, a seventh transistor T7, an eighth transistor T8, a ninth transistor T9, a first capacitor C1, a second capacitor C2, and a third capacitor C3. The operating principle of the transistors and capacitors in the embodiment shown in Figure 10 is the same as that in the above-mentioned embodiment, and the signals provided by the data lines and scan lines are also the same, which will not be repeated here.

[0106] In this embodiment, a single third transistor T3 can reset both the first transistor T1 and the second transistor T2, thereby reducing the number of components in the display device, conserving the area occupied by the pixel circuits in the display panel, and effectively improving pixel density and display panel resolution. Furthermore, the pixel circuit shown in the embodiment of FIG10 does not suffer from transistor cross-charging, thereby reducing the driving power consumption of the pixel circuit.

[0107] It should be noted that the types of transistors in the embodiment shown in Figure 10 are all examples and are not limited to P-type transistors. Those skilled in the art can choose different types of transistors according to actual conditions and set the effective level of the gate signal accordingly, which will not be elaborated here.

[0108] According to another pixel circuit of some embodiments of the present application, the pixel circuit may be any one of the pixel circuits in the above embodiments and Figures 2 to 10 of the embodiments. The driving phase of the pixel circuit may include, in sequence, a first reset phase, a first compensation phase, a first data writing phase, a second reset phase, a second compensation phase, a second data writing phase, and a light emitting phase. For the pixel circuit shown in the embodiment of Figure 2, wherein:

[0109] In the first reset phase, the reset control signal S3 is at an active level, the third transistor T3 is turned on and provides the reset signal REF to the gate of the second transistor T2, and the second transistor T2 is reset and turned on using the reset signal REF received at the gate. Specifically, in the embodiment shown in FIG2 , the first transistor T1, the second transistor T2, and the third transistor T3 are all P-type transistors, and their gates are turned on in response to a low level. Naturally, the above-mentioned active level is a low level, and the reset signal REF is also a low level. Since the third transistor T3 is turned on, the low-level reset signal REF can be provided to the gate of the second transistor T2 through the third transistor T3, thereby pulling down the gate potential of the second transistor T2, thereby resetting and turning on the second transistor T2.

[0110] In the second reset phase, the reset control signal S3 is at an active level, the third transistor T3 is turned on and provides the reset signal REF to the gate of the first transistor T1. The first transistor T1 is reset and turned on using the reset signal REF received at the gate. Specifically, because the reset signal REF is at a low level and the third transistor T3 is turned on, the low-level reset signal REF can be provided to the gate of the first transistor T1 through the third transistor T3, thereby lowering the gate potential of the first transistor T1 and resetting and turning on the first transistor T1.

[0111] During the light-emitting phase, the gate of the first transistor T1 receives an active level and turns on, using the power signal VDD received at the first electrode to provide a drive signal to the light-emitting element LED via the second electrode. Furthermore, the gate of the second transistor T2 receives an active level and turns on, using the power signal VDD received at the first electrode to provide a control signal for controlling the light-emitting duration of the light-emitting element LED to the gate of the first transistor T1 via the second electrode. Specifically, after the first transistor T1 turns on, it can provide drive signals of varying amplitudes to the light-emitting element LED, implementing a PAM drive mode. The second transistor T2 can control the on and off state of the first transistor T1 via the light-emitting duration control signal applied to the gate of the first transistor T1, thereby controlling the time when the first transistor T1 provides the drive signal to the light-emitting element LED, thereby implementing a PWM drive mode.

[0112] In this embodiment, the first transistor T1 and the second transistor T2 can be reset by a third transistor T3, which reduces the number of components in the display device, saves the area occupied by the pixel circuit in the display panel, and effectively improves the pixel density and the display panel resolution.

[0113] In the embodiment shown in FIG4 , during the second compensation phase and the second data writing phase, the first compensation control signal S41 is at an active level, the reset control signal S3 is at an inactive level, the fourth transistor T4 is turned on and provides threshold compensation for the first transistor T1, and the first transistor T1 receives the threshold compensation provided by the fourth transistor T4. Specifically, when the reset control signal S3 is at an inactive level, the third transistor T3 is turned off, the first compensation control signal S41 is at an active level, and the fourth transistor T4 is turned on, thereby compensating the voltage level of the second electrode of the first transistor T1 to the gate, completing the threshold compensation for the first transistor T1.

[0114] Specifically, in this embodiment, the principles of other driving stages are the same as those in the above embodiment and will not be described again here.

[0115] In the embodiment shown in FIG5 , in the first reset stage, the reset control signal S3 and the second compensation and reset control signal S1 are both at valid levels, the third transistor T3 and the fifth transistor T5 are turned on, the third transistor T3 provides the reset signal REF to the second electrode of the fifth transistor T5, the fifth transistor T5 provides the reset signal REF to the gate of the second transistor T2, and the second transistor T2 is reset and turned on by the reset signal REF received at the gate.

[0116] In the first compensation phase, the reset control signal S3 is at an inactive level, the second compensation and reset control signal S1 is at an active level, the fifth transistor T5 is turned on and provides threshold compensation for the second transistor T2, and the second transistor T2 receives the threshold compensation provided by the fifth transistor T5. Specifically, when the third transistor T3 needs to reset the second transistor T2, the reset control signal S3 and the second compensation and reset control signal S1 are at an active level, the third transistor T3 is turned on, and the reset signal REF is provided to the second electrode of the fifth transistor T5. The fifth transistor T5 is turned on and the reset signal REF provided by the third transistor T3 is provided to the gate of the second transistor T2. When threshold compensation is required for the second transistor T2, only the first compensation control signal S41 is at an active level, the third transistor T3 is turned off, and the fifth transistor T5 is turned on, compensating the voltage level of the second electrode of the second transistor T2 to the gate, thereby completing the threshold compensation for the second transistor T2.

[0117] Specifically, in this embodiment, the principles of other driving stages are the same as those in the above embodiment and will not be described again here.

[0118] In the embodiment shown in FIG6 , during the first data writing phase, the second data writing control signal S2 is at an active level, the first compensation control signal S41, the first data writing control signal S42, and the reset control signal S3 are at an inactive level, and the seventh transistor T7 is turned on and writes the second data signal Date_PWM into the gate of the second transistor T2. Specifically, because the two drive transistors need to write data at different phases, when the seventh transistor T7 is turned on and writes the second data signal Date_PWM into the gate of the second transistor T2, the third transistor T3, the fourth transistor T4, and the sixth transistor T6 need to remain off. Furthermore, because the second data signal Date_PWM is written into the gate of the second transistor T2, threshold compensation cannot be performed on the second transistor at the same time; otherwise, the threshold compensation on the gate of the second transistor would be interfered with by the second data signal Date_PWM.

[0119] During the second compensation phase and the second data writing phase, the first compensation control signal S41 and the first data writing control signal S42 are at an active level, the reset control signal S3 and the second data writing control signal S2 are at an inactive level, the fourth transistor T4 and the sixth transistor T6 are turned on, the fourth transistor T4 provides threshold compensation for the first transistor T1, the sixth transistor T6 writes the first data signal Date_PAM into the first electrode of the first transistor T1, and the first transistor T1 receives the threshold compensation provided by the fourth transistor T4 and the first data signal Date_PAM provided by the sixth transistor T6. Specifically, because the two drive transistors need to write data at different phases, when the sixth transistor T6 is turned on and writes the first data signal Date_PAM into the first electrode of the first transistor T1, the third transistor T3 and the seventh transistor T7 need to remain off. Furthermore, because the first data signal Date_PAM is written to the first electrode of the first transistor T1 and threshold compensation is performed on the gate of the first transistor T1, data writing and threshold compensation can be performed simultaneously on the first transistor.

[0120] Specifically, in this embodiment, the principles of other driving stages are the same as those in the above embodiment and will not be described again here.

[0121] The following describes the driving method of each stage of the pixel circuit shown in the embodiment of FIG10 in conjunction with a complete embodiment. The timing diagram of each signal in the circuit corresponding to the embodiment of FIG10 is shown in FIG11. The driving stage of the pixel circuit shown in the embodiment of FIG10 may include a first reset stage (1), a first compensation stage (2), a first data writing stage (3), a second reset stage (4), a second compensation stage and a second data writing stage (5), and a light emitting stage (6). In the pixel circuit shown in the embodiment of FIG10, each transistor may be a P-type transistor, and the gate is turned on in response to a low level, so the effective level is a low level.

[0122] In the first reset stage, corresponding to stage (1) in FIG11 , the reset control signal S3, the second compensation and reset control signal S1 become low level, and other signals remain high level, as shown in FIG12 (in FIG12 , the transistor marked with “×” indicates an off state, which does not mean that the transistor does not exist, and the unmarked transistor indicates an on state. The same is true for the drawings of other embodiments, which will not be repeated here). Since the reset control signal S3, the second compensation and reset control signal S1 are low level, the fifth transistor T5 and the third transistor T3 are turned on accordingly, and the other transistors are turned off. Since the fifth transistor T5 and the third transistor T3 are turned on, the first transistor T1 and the fourth transistor T4 are turned off, the reset signal REF will first pass through the third transistor T3, and then pass through the fifth transistor T5 to charge the second capacitor C2. The node A of the gate of the second transistor T2 is reset to the REF potential. At the same time, since the REF potential is low level for the embodiment shown in FIG10 , the second transistor T2 is turned on in response to the REF potential of the gate, which is also low level.

[0123] In the first compensation phase, corresponding to phase (2) in FIG. 11 , the second compensation and reset control signal S1 is at a low level, while other signals remain at a high level. As shown in FIG. 13 , since the second compensation and reset control signal S1 is at a low level, the fifth transistor T5 is turned on, while the other transistors are turned off. Since the second transistor T2 is in the on state at this time, the power supply signal VDD can reach the second electrode of the second transistor T2, and the fifth transistor T5 can use the potential of the second electrode of the second transistor T2 as the gate of the second transistor T2 to perform threshold voltage compensation. That is, VDD is written to node A of the gate of the second transistor T2 through T2 and T5. At this time, the potential of node A VA = VDD + Vth.

[0124] In the first data writing stage, corresponding to stage (3) in FIG11 , the second data writing control signal S2 and the second data signal Date_PWM become low levels, and other signals remain high levels. As shown in FIG14 , since the second data writing control signal S2 is low, the seventh transistor T7 is turned on. Since the seventh transistor T7 is turned on, the second data signal Date_PWM can pass through the seventh transistor T7 and be coupled to the node A of the gate of the second transistor T2 by the second capacitor C2. At this time, the potential of the node A is VA=V(Date_PWM)+VDD+Vth.

[0125] In the second reset phase, corresponding to phase (4) in FIG11 , the first reset control signal S3 becomes low, and other signals remain high. As shown in FIG15 , since the first reset control signal S3 is low, the third transistor T3 is turned on, and the other transistors are turned off. Since the third transistor T3 is turned on, the reset signal REF can charge the first capacitor C1 through the third transistor T3, and at the same time, the node B at the gate of the first transistor T1 is reset to the REF potential. For the embodiment shown in FIG10 , the REF potential is low, and the first transistor T1 is turned on in response to the REF potential of the gate, which is also low. It should be noted that although the third transistor T3 is also turned on in the first reset phase, after the above-mentioned first compensation phase and the first data writing phase, the power supply signal VDD reaches the node B through the turned-on T2, so that the potential of the node B is no longer the REF potential. Therefore, the node B at the gate of the first transistor T1 needs to be reset again in the second reset phase.

[0126] In the second compensation phase and the second data writing phase, corresponding to phase (5) in FIG. 11 , the first compensation control signal S41 and the first data writing control signal S42 become low, while other signals remain high. As shown in FIG. 16 , since the first compensation control signal S41 and the first data writing control signal S42 are low, the fourth transistor T4 and the sixth transistor T6 are turned on. Since the sixth transistor T6 is turned on and the eighth transistor T8 is turned off, the first data signal Date_PAM can be written into the first electrode of the first transistor T1 through the sixth transistor T6. At the same time, since the first transistor T1 and the fourth transistor T4 are turned on, the first data signal Date_PAM can continue to pass through T1 and T4 to compensate for the threshold voltage of the gate of the first transistor T1. At this time, the potential of the node B VB = V(Date_PAM) + Vth.

[0127] During the light-emitting phase, corresponding to phase (6) in FIG11 , the first drive control signal EM1 and the second drive control signal EM2 become low, the light-emitting duration control signal SWEEP gradually decreases from a high level, and other signals remain high. As shown in FIG17 , since the first drive control signal EM1 and the second drive control signal EM2 are low, the eighth transistor T8 and the ninth transistor T9 are turned on, while the fourth transistor T4 is turned off. Furthermore, since the first transistor T1 remains on during the second compensation phase and the second data writing phase, the power supply signal VDD drives the light-emitting element LED through T8, T1, and T9 to begin emitting light. As the light-emitting duration control signal SWEEP decreases in level, coupled with the coupling effect of C2 and C3, the potential VA of node A gradually decreases from V(Date_PWM)+VDD+Vth until the second transistor T2 is in the on state, as shown in FIG18 . After the second transistor T2 is turned on, the high-level VDD signal can charge the first capacitor C1 through the second transistor T2. At the same time, the potential of the node B at the gate of the first transistor T1 gradually increases until the first transistor T1 is turned off, as shown in Figure 18. At this time, the light-emitting element LED stops emitting light.

[0128] In a specific implementation, if the second data signal Date_PWM stops being written while the seventh transistor T7 is turned off, the second capacitor C2 and the third capacitor C3 will couple part of the second data signal Date_PWM, so that the second data signal Date_PWM cannot be completely written into the second transistor T2. Therefore, in some embodiments, as shown in the timing diagram of FIG19 , the rising edge of the low level of the second data signal Date_PWM needs to slightly lag behind the rising edge of the low level of the second data write control signal S2.

[0129] In other embodiments, such as the pixel circuit shown in Figure 20, each transistor is an N-type transistor, and the gate is turned on in response to a high level, that is, the effective level is a high level. The timing diagram of each signal in the circuit corresponding to the embodiment of Figure 20 is shown in Figure 21.

[0130] In the first reset stage, corresponding to stage (1) in Figure 21, the reset control signal S3, the second compensation and reset control signal S1 signals become high levels, and other signals remain low levels. Since the reset control signal S3, the second compensation and reset control signal S1 signals are high levels, the fifth transistor T5 and the third transistor T3 are turned on accordingly, and the other transistors are turned off. The reset signal REF first passes through T3 and then passes through T5 to charge the second capacitor C2. At the same time, the node A of the gate of the second transistor T2 is reset to the REF potential. For the embodiment shown in Figure 10, the REF potential is high level, and the second transistor T2 is turned on in response to the REF potential of the gate, that is, the high level.

[0131] In the first compensation phase, corresponding to phase (2) in FIG. 21 , the second compensation and reset control signal S1 is at a high level, while other signals remain at a low level. Since the second compensation and reset control signal S1 is at a high level, the fifth transistor T5 is turned on, while the other transistors are turned off. Since the second transistor T2 is on at this time, the power supply signal VSS can reach the second electrode of the second transistor T2. The fifth transistor T5 can then use the potential of the second electrode of the second transistor T2 as the gate of the second transistor T2 to perform threshold voltage compensation. That is, VSS is written to node A at the gate of the second transistor T2 through T2 and T5. At this time, the potential of node A, VA, equals VSS + Vth.

[0132] In the first data writing stage, corresponding to stage (3) in Figure 21, the second data writing control signal S2 and the second data signal Date_PWM become high levels, and other signals remain low levels. Since the second data writing control signal S2 is high, the seventh transistor T7 is turned on, and the second data signal Date_PWM can pass through the seventh transistor T7 and be coupled to the node A of the gate of the second transistor T2 by the second capacitor C2. At this time, the potential of node A VA = V(Date_PWM) + VSS + Vth.

[0133] In the second reset phase, corresponding to phase (4) in FIG. 21 , the first reset control signal S3 becomes high, and the other signals remain low. Since the first reset control signal S3 is high, the third transistor T3 is turned on, and the other transistors are turned off. The reset signal REF can charge the first capacitor C1 through the third transistor T3, and at the same time, the node B at the gate of the first transistor T1 is reset to the REF potential. For the embodiment shown in FIG. 10 , the REF potential is high, and the first transistor T1 is turned on in response to the REF potential of the gate, which is also the high level. It should be noted that although the third transistor T3 is also turned on in the first reset phase, after the first compensation phase and the first data writing phase, the power supply signal VSS reaches the node B through the turned-on T2, so that the potential of the node B is no longer the REF potential. Therefore, the node B at the gate of the first transistor T1 needs to be reset again in the second reset phase.

[0134] In the second compensation stage and the second data writing stage, corresponding to stage (5) in Figure 21, the first compensation control signal S41 and the first data writing control signal S42 become high levels, and other signals remain low levels. Since the first compensation control signal S41 and the first data writing control signal S42 are high levels, the fourth transistor T4 and the sixth transistor T6 are turned on, and the first data signal Date_PAM can be written into the first electrode of the first transistor T1 through the sixth transistor T6. At the same time, since the first transistor T1 and the fourth transistor T4 are turned on, the first data signal Date_PAM can continue to pass through T1 and T4 to perform threshold voltage compensation for the gate of the first transistor T1. At this time, the node B potential VB = V(Date_PAM) + Vth.

[0135] In the light-emitting phase, corresponding to phase (6) in FIG21 , the first drive control signal EM1 and the second drive control signal EM2 become high, the light-emitting duration control signal SWEEP level gradually increases from low, and other signals remain low. Since the first drive control signal EM1 and the second drive control signal EM2 are high, the eighth transistor T8 and the ninth transistor T9 are turned on. At the same time, since the first transistor T1 remains turned on in the previous second compensation phase and the second data writing phase, the power supply signal VSS drives the light-emitting element LED through T8, T1, and T9 to start emitting light. As the level of the light-emitting duration control signal SWEEP increases, coupled with the coupling effect of C2 and C3, the node A potential VA gradually increases from V(Date_PWM)+VSS+Vth until the second transistor T2 is in the on state. After the second transistor T2 is turned on, the low-level VSS signal can charge the first capacitor C1 through the second transistor T2. At the same time, the potential of the node B at the gate of the first transistor T1 gradually decreases until the first transistor T1 is turned off, at which point the light-emitting element LED stops emitting light.

[0136] In a specific implementation, if the second data signal Date_PWM stops being written while the seventh transistor T7 is turned off, the second capacitor C2 and the third capacitor C3 will couple part of the second data signal Date_PWM, so that the second data signal Date_PWM cannot be completely written into the second transistor T2. Therefore, in some embodiments, as shown in the timing diagram of FIG22 , the falling edge of the low level of the second data signal Date_PWM needs to slightly lag behind the falling edge of the low level of the second data write control signal S2.

[0137] According to another pixel circuit of some embodiments of the present application, as shown in FIG23, compared with the pixel circuit shown in FIG2, the pixel circuit may further include a tenth transistor T10. In the embodiment shown in FIG23, the third transistor T3 is a P-type transistor and is turned on in response to a low level. The effective level of the reset control signal S3 is a low level. When the reset control signal S3 is a low level, the third transistor T3 is turned on, and the reset signal REF can be provided to the second pole through the first pole. Specifically, as shown in FIG1 and FIG23, the reset control signal S3 is provided by the scan line SL. The reset signal REF can be provided by the data line DL or connected to a fixed potential.

[0138] The first electrode of the tenth transistor T10 can be configured to receive the first data signal Date_PAM. The second electrode of the tenth transistor T10 is connected to the gate of the first transistor T1. The gate of the tenth transistor T10 can be configured to receive the third data write control signal S5. In response to the third data write control signal S5 received at the gate, the tenth transistor T10 can write the first data signal Date_PAM into the gate of the first transistor T1. The first data signal Date_PAM is a PAM-modulated data signal that can adjust the brightness of the light-emitting element based on the voltage amplitude of the input signal. Specifically, when the third data write control signal S5 is at an active level, the tenth transistor T10 turns on, and the first data signal Date_PAM can be provided to the second electrode via the first electrode. In the embodiment shown in FIG23 , the tenth transistor T10 can be a P-type transistor and turns on in response to a low level. The active level of the third data write control signal S5 is a low level. When the third data write control signal S5 is at a low level, the tenth transistor T10 turns on, and the first data signal Date_PAM can be provided to the second electrode via the first electrode.

[0139] Specifically, as shown in FIG. 1 and FIG. 23 , the third data writing control signal S5 may also be provided by the scan line SL, and the first data signal Date_PAM may be provided by the data line DL.

[0140] In some embodiments, as shown in FIG24 , the pixel circuit shown in FIG23 may further include an eleventh transistor T11. Specifically, the connection method and operating principle of the eleventh transistor T11 are the same as those of the fifth transistor T5, the second transistor T2, and the third transistor T3, and are not further described here. However, when threshold compensation is required for the second transistor T2, the second compensation and reset control signal S1 is at an active level, the eleventh transistor T11 is turned on, and the voltage level of the second electrode of the second transistor T2 is compensated to the gate, thereby completing the threshold compensation for the second transistor T2.

[0141] In the embodiment shown in FIG24 , the third transistor T3 and the eleventh transistor T11 can both be P-type transistors and be turned on in response to a low level. The effective levels of the reset control signal S3 and the second compensation and reset control signal S1 are both low. When the third transistor T3 is turned on and the second transistor T2 needs to be reset, the second compensation and reset control signal S1 is low, the eleventh transistor T11 is turned on, and the reset signal REF provided by the third transistor T3 is provided to the gate of the second transistor T2. When threshold compensation is required for the second transistor T2, the second compensation and reset control signal S1 is low, the eleventh transistor T11 is turned on, and the voltage level of the second electrode of the second transistor T2 is compensated to the gate, thereby completing the threshold compensation of the second transistor T2. Thus, in the above embodiment of the present application, by adding the eleventh transistor T11 between the gate and the second electrode of the second transistor T2, the threshold compensation of the second transistor T2 can be performed, thereby achieving a better display effect. At the same time, the eleventh transistor T11 is disposed between the gate of the second transistor T2 and the second electrode of the third transistor T3, and can cooperate with the third transistor T3 to reset the second transistor T2, thereby eliminating the need to provide an additional reset transistor for the second transistor T2.

[0142] In some embodiments, as shown in FIG25 , the pixel circuit shown in FIG24 may further include a twelfth transistor T12. The first electrode of the twelfth transistor T12 is connected to the first electrode of the second transistor T2. The second electrode of the twelfth transistor T12 may be configured to receive the second data signal Date_PWM. The gate of the twelfth transistor T12 may be configured to receive the fourth data write control signal S6. The twelfth transistor T12 may be configured to write the second data signal Date_PWM into the first electrode of the second transistor T2 in response to the fourth data write control signal S6 received at the gate. Specifically, when the second transistor T2 is turned on, the second data signal Date_PWM is transmitted to the second electrode of the second transistor T2. Specifically, when the fourth data write control signal S6 is at an active level, the twelfth transistor T12 is turned on, and the second data signal Date_PWM can be provided to the first electrode via the second electrode. In the embodiment shown in Figure 25, the twelfth transistor T12 is a P-type transistor and is turned on in response to a low level. The effective level of the fourth data write control signal S6 is a low level. When the fourth data write control signal S6 is a low level, the twelfth transistor T12 is turned on, and the second data signal Date_PWM can be provided to the first electrode through the second electrode.

[0143] Specifically, as shown in FIG. 1 and FIG. 25 , the fourth data writing control signal S6 may be provided by the scan line SL, and the second data signal Date_PWM may still be provided by the data line DL.

[0144] The eleventh transistor T11 can also be configured to provide threshold compensation for the second transistor T2 in response to the second compensation and reset control signal S1 received via its gate, while also providing the second data signal Date_PWM, transmitted to the second electrode of the second transistor T2, to the gate of the second transistor T2. After the second data signal Date_PWM is written to the gate of the second transistor T2, it can cooperatively control the on-time of the second transistor T2, thereby causing the second transistor T2 to provide a control signal to the first transistor T1 for controlling the duration of light emission of the light-emitting element LED.

[0145] In this embodiment, the operating principle of the third transistor T3 is the same as that in the above embodiment, and will not be described again here.

[0146] In some embodiments, as shown in FIG26 , the pixel circuit shown in FIG23 may further include a thirteenth transistor T13, wherein a first electrode of the thirteenth transistor T13 is connected to the gate of the first transistor T1, a second electrode of the thirteenth transistor T13 is connected to the second electrode of the first transistor T1, and the gate of the thirteenth transistor T13 is configured to receive a third compensation control signal S7. Specifically, as shown in FIG1 and FIG5 , the third compensation control signal S7 may be provided by the scan line SL.

[0147] The thirteenth transistor T13 can be used to provide threshold compensation for the first transistor T1 in response to the third compensation control signal S7 received by the gate. Specifically, when the third compensation control signal S7 is at an effective level, the thirteenth transistor T13 is turned on, and the level of the second electrode of the first transistor T1 is compensated to the gate, thereby completing the threshold compensation for the first transistor T1. In the embodiment shown in Figure 26, the thirteenth transistor T13 can be a P-type transistor and is turned on in response to a low level. The effective level of the third compensation control signal S7 is a low level. When the third compensation control signal S7 is at a low level, the thirteenth transistor T13 is turned on, and the level of the second electrode of the first transistor T1 is compensated to the gate, thereby completing the threshold compensation for the first transistor T1. In this way, in the above embodiment of the present application, by adding the thirteenth transistor T13 between the gate and the second electrode of the first transistor T1, the threshold compensation of the first transistor T1 can be performed, thereby achieving a better display effect.

[0148] In this embodiment, the working principle of the third transistor T3 is the same as that in the above embodiment, and will not be described again here.

[0149] In some embodiments, as shown in FIG27 , the pixel circuit may further include a fourteenth transistor T14 and a fifteenth transistor T15. A first electrode of the fourteenth transistor T14 may be configured to receive a power supply signal VDD, a second electrode of the fourteenth transistor T14 may be connected to the first electrode of the second transistor T2, and a gate of the fourteenth transistor T14 may be configured to receive a drive control signal EM. The fourteenth transistor T14 may be configured to provide the power supply signal VDD to the first electrode of the second transistor T2 in response to the drive control signal EM received at the gate. Specifically, when the drive control signal EM is at an active level, the fourteenth transistor T14 turns on, and the power supply signal VDD can be provided to the first electrode of the second transistor T2 via the fourteenth transistor T14. In the embodiment shown in FIG27 , the fourteenth transistor T14 may be a P-type transistor and turns on in response to a low level. The active level of the drive control signal EM is a low level. When the drive control signal EM is at a low level, the fourteenth transistor T14 turns on, and the power supply signal VDD can be provided to the first electrode of the second transistor T2 via the fourteenth transistor T14.

[0150] A first electrode of the fifteenth transistor T15 is connected to the second electrode of the first transistor T1, and a second electrode of the fifteenth transistor T15 is connected to the light-emitting element LED. The gate of the fifteenth transistor T15 can be configured to receive a drive control signal EM. In response to the drive control signal EM received at the gate, the fifteenth transistor T15 can be configured to provide the drive signal provided by the first transistor T1 to the light-emitting element LED. Specifically, when the drive control signal EM is at an active level, the fifteenth transistor T15 is turned on, and the drive signal can be provided to the light-emitting element LED through the fifteenth transistor T15. In the embodiment shown in FIG27 , the fifteenth transistor T15 can be a P-type transistor and is turned on in response to a low level. The active level of the drive control signal EM is a low level. When the drive control signal EM is at a low level, the fifteenth transistor T15 is turned on, and the drive signal can be provided to the light-emitting element LED through the fifteenth transistor T15. Specifically, as shown in FIG1 and FIG27 , the drive control signal EM can be provided by the scan line SL.

[0151] In the above embodiment, two control transistors, namely a first transistor and a second transistor, can be provided in the drive circuit, thereby enabling the drive circuit to be shut down when the light-emitting element is not emitting light and to be turned on again during the light-emitting phase, thereby preventing leakage current generated by the drive transistor from affecting the normal light-emitting element. Specifically, the fourteenth transistor T14 and the fifteenth transistor T15 are turned on during the light-emitting phase, and the drive signal provided by the first transistor T1 can drive the light-emitting element LED to emit light through the fifteenth transistor T15. At the same time, the power supply signal VDD reaches the first electrode of the second transistor T2 through the turned-on fourteenth transistor T14. When the second transistor T2 controls the light-emitting duration of the light-emitting element LED, it turns on itself, allowing the power supply signal to pass through the second transistor T2 to the gate of the first transistor T1, thereby turning off the first transistor T1.

[0152] In this embodiment, the working principle of the third transistor T3 is the same as that in the above embodiment, and will not be described again here.

[0153] In some embodiments, as shown in FIG28 , the pixel circuit shown in FIG23 may further include a fourth capacitor C4. A first end of the fourth capacitor C4 may be connected to the gate of the second transistor T2, and a second end may be configured to receive a light-emission duration control signal SWEEP. The fourth capacitor C4 may be configured to couple the light-emission duration control signal SWEEP to the gate of the second transistor T2, thereby controlling the on / off switching of the second transistor T2. The second transistor T2, in turn, provides a control signal to the first transistor T1 for controlling the light-emission duration of the light-emitting element LED in accordance with the light-emission duration control signal SWEEP. Specifically, in the embodiment shown in FIG28 , both the second transistor T2 and the first transistor T1 may be P-type transistors, whose gates are turned on in response to a low level. The light-emission duration control signal SWEEP is an electrical signal with a gradually decreasing level. At the initial moment of the light-emitting phase of the light-emitting element LED, the second transistor T2 is in the off state, and the level of the light-emitting duration control signal SWEEP gradually decreases, thereby turning on the second transistor T2 at a certain moment. Since the first electrode of the second transistor T2 can receive the power supply signal VDD during the light-emitting phase, when it is turned on, the high-level power supply signal VDD will pull up the potential of the gate of the first transistor T1 through the second electrode of the second transistor T2, causing the first transistor T1 to be turned off, and the light-emitting element LED stops emitting light.

[0154] In other embodiments, both the second transistor T2 and the first transistor T1 may be N-type transistors, whose gates are turned on in response to a high level, and the aforementioned light-emission duration control signal SWEEP is an electrical signal with a gradually increasing level. At the initial moment of the light-emitting phase of the light-emitting element LED, the second transistor T2 is in an off state, and the level of the light-emission duration control signal SWEEP gradually increases, thereby turning on the second transistor T2 at a certain moment. Since the first electrode of the second transistor T2 can receive the power supply signal VSS during the light-emission phase, when it is turned on, the low-level power supply signal VSS will pull down the potential of the gate of the first transistor T1 through the second electrode of the second transistor T2, causing the first transistor T1 to turn off, and the light-emitting element LED to stop emitting light.

[0155] In this embodiment, the working principle of the third transistor T3 is the same as that in the above embodiment, and will not be described again here.

[0156] In some embodiments, as shown in Figure 29, the pixel circuit shown in Figure 23 may further include a fifth capacitor C5, a first end of the fifth capacitor C5 is connected to the second electrode of the tenth transistor T10, and a second end can be used to receive the first data signal Date_PAM. The fifth capacitor C5 can be used to couple the first data signal Date_PAM written by the tenth transistor T10 to the first transistor T1.

[0157] In this embodiment, the working principle of the third transistor T3 is the same as that in the above embodiment, and will not be described again here.

[0158] In some embodiments, as shown in FIG30 , the pixel circuit shown in FIG23 may further include a sixth capacitor C6 , wherein a first end of the sixth capacitor C6 is connected to the gate of the first transistor T1 , and a second end thereof is operable to receive a power supply signal VDD . Specifically, the third transistor T3 may reset the potential of the gate of the first transistor T1 to a reset voltage by charging the sixth capacitor C6 connected to the gate of the first transistor T1 .

[0159] In this embodiment, the working principle of the third transistor T3 is the same as that in the above embodiment, and will not be described again here.

[0160] During specific implementation, the specific models and capacitances of the fourth capacitor C4 , the fifth capacitor C5 , and the sixth capacitor C6 can be set by those skilled in the art according to actual conditions and are not limited here.

[0161] The overall operating principle of the above-mentioned pixel circuit is described below with reference to a specific embodiment. As shown in FIG31 , the above-mentioned pixel circuit may include a first transistor T1, a second transistor T2, a third transistor T3, a tenth transistor T10, an eleventh transistor T11, a twelfth transistor T12, a thirteenth transistor T13, a fourteenth transistor T14, a fifteenth transistor T15, a fourth capacitor C4, a fifth capacitor C5, and a sixth capacitor C6. The operating principle of the transistors and capacitors in the embodiment shown in FIG31 is the same as in the above-mentioned embodiment, and the signals provided by the data lines and scan lines are also the same, so they will not be described in detail here. In this embodiment, due to the presence of the third transistor T3, the first transistor T1 and the second transistor T2 can be reset by the third transistor T3, which directly reduces the number of components in the display device, saves the area occupied by the pixel circuit in the display panel, and effectively improves the pixel density and display panel resolution. Furthermore, the pixel circuit shown in the embodiment of FIG31 does not have a transistor charging phenomenon, which reduces the driving power consumption of the pixel circuit. It should be noted that the embodiment shown in FIG31 is only an example and does not limit all transistors in the circuit to P-type transistors. Therefore, no further details are given here.

[0162] According to another pixel circuit of some embodiments of the present application, the pixel circuit may be any one of the pixel circuits in the above embodiments and Figures 23 to 31 of the embodiments. The driving phase of the pixel circuit may further include a first reset phase, a first compensation phase, a second data writing phase, a second reset phase, a second compensation phase, a second data writing phase, and a light emitting phase. For the pixel circuit shown in the embodiment of Figure 23, wherein:

[0163] The principles in the first reset stage and the second reset stage are the same as those described above with respect to the principles of FIG. 10 . Please refer to the above content for details and will not be repeated here.

[0164] In the second data writing phase, the third data writing control signal S5 is at an active level, the tenth transistor T10 is turned on and provides the first data signal Date_PAM to the gate of the first transistor T1 .

[0165] During the light-emitting phase, the gate of the first transistor T1 receives an active voltage level and turns on. It uses the power signal VDD received at the first electrode and the first data signal Date_PAM received at the gate to provide a drive signal to the light-emitting element LED via its second electrode. Furthermore, the gate of the second transistor T2 receives an active voltage level and turns on. It uses the power signal VDD received at the first electrode to provide a control signal for controlling the light-emitting duration of the light-emitting element LED via its second electrode to the gate of the first transistor T1. Specifically, after turning on, the first transistor T1 can provide drive signals of varying amplitudes to the light-emitting element LED based on the first data signal Date_PAM, ensuring that the light-emitting element LED emits light at a fixed wavelength, thus implementing a PAM drive mode. The second transistor T2 can control the on and off state of the first transistor T1 via the light-emitting duration control signal applied to the gate of the first transistor T1, thereby controlling the timing of the drive signal provided by the first transistor T1 to the light-emitting element LED, thereby implementing a PWM drive mode.

[0166] In the embodiment shown in Figure 25, in the first reset stage, the second compensation and reset control signal S1 and the reset control signal S3 are at the valid level, the third transistor T3 is turned on and provides the reset signal REF to the second electrode of the eleventh transistor T11, the eleventh transistor T11 is turned on and provides the reset signal REF to the gate of the second transistor T2, and the second transistor T2 is reset and turned on using the reset signal REF received at the gate.

[0167] During the first compensation phase and the second data writing phase, the second compensation and reset control signal S1 and the fourth data writing control signal S6 are at an active level. The eleventh transistor T11 is turned on and provides threshold compensation for the second transistor T2. Simultaneously, the twelfth transistor T12 is turned on, and the second data signal Date_PWM is written to the gate of the second transistor T2 via the sequentially turned-on twelfth transistor T12, the second transistor T2, and the eleventh transistor T11. Since the second data signal Date_PWM is written to the first electrode of the second transistor T2 and threshold compensation is performed on the gate of the second transistor T2, data writing and threshold compensation can be performed simultaneously on the second transistor T2.

[0168] Specifically, in this embodiment, the principles of other driving stages are the same as those in the above embodiment and will not be described again here.

[0169] In the embodiment shown in FIG26 , during the second compensation phase, the third compensation control signal S7 is at an active level, the thirteenth transistor T13 is turned on, and the voltage level at the second electrode of the first transistor T1 is compensated to the gate, thereby completing the threshold compensation of the first transistor T1. Specifically, because the first data signal Date_PAM is written to the gate of the first transistor T1, the threshold compensation of the first transistor T1 cannot be performed simultaneously with the writing of the first data signal Date_PAM. Otherwise, the threshold compensation of the gate of the first transistor T1 will be interfered with by the first data signal Date_PAM.

[0170] Specifically, in this embodiment, the principles of other driving stages are the same as those in the above embodiment and will not be described again here.

[0171] In the embodiment shown in FIG27 , during the light-emitting stage, the driving control signal EM is at an effective level, the fourteenth transistor T14 and the fifteenth transistor T15 are turned on, and the driving signal provided by the first transistor T1 can drive the light-emitting element LED to emit light through the fifteenth transistor T15; at the same time, the power signal VDD reaches the first electrode of the second transistor T2 through the turned-on fourteenth transistor T14. When the second transistor T2 controls the light-emitting duration of the light-emitting element LED, it turns on itself, allowing the power signal to pass through the second transistor T2 to reach the gate of the first transistor T1, thereby turning off the first transistor T1.

[0172] In the embodiment shown in FIG28 , in the above-mentioned light-emitting stage, the light-emitting duration control signal transitions from an invalid level to a valid level. The valid level of the light-emitting duration control signal can turn on the second transistor T2. Since the first electrode of the second transistor T2 can receive the power supply signal VDD in the light-emitting stage, when it is turned on, the invalid level power supply signal VDD will pass through the second transistor T2 to reach the gate of the first transistor T1, causing the first transistor T1 to be turned off, and the light-emitting element LED stops emitting light.

[0173] Specifically, in this embodiment, the principles of other driving stages are the same as those in the above embodiment and will not be described again here.

[0174] The following describes the driving method of each stage of the pixel circuit shown in the embodiment of FIG31 in conjunction with a complete embodiment. The timing diagram of each signal in the circuit corresponding to the embodiment of FIG31 is shown in FIG32. The driving stage of the pixel circuit shown in the embodiment of FIG31 can still include a first reset stage (1), a first compensation stage (2), a first data writing stage (3), a second reset stage (4), a second compensation stage and a second data writing stage (5), and a light emitting stage (6). In the pixel circuit shown in the embodiment of FIG31, each transistor is a P-type transistor, and the gate is turned on in response to a low level, so the effective level is a low level.

[0175] In the first reset stage, corresponding to stage (1) in FIG32 , the reset control signal S3, the second compensation and reset control signal S1 become low, and other signals remain high, as shown in FIG33 (in FIG33 , the transistor marked with “×” indicates an off state, which does not mean that the transistor does not exist, and the unmarked transistor indicates an on state. The same applies to the drawings of other embodiments and will not be repeated). Since the reset control signal S3, the second compensation and reset control signal S1 are low, the eleventh transistor T11 and the third transistor T3 are turned on, and the other transistors are turned off. Since the eleventh transistor T11 and the third transistor T3 are turned on, the other transistors are all in the off state. The reset signal REF will first pass through the third transistor T3 and then pass through the eleventh transistor T11 to charge the fourth capacitor C4, so that the node of the gate of the second transistor T2 is reset to the REF potential. At the same time, since the REF potential is low for the embodiment shown in FIG31 , the second transistor T2 is turned on in response to the REF potential of the gate, which is also low.

[0176] In the first compensation phase and the first data writing phase, corresponding to phases (2) and (3) in FIG. 32 , the fourth data writing control signal S6 and the second compensation and reset control signal S1 are at a low level, and the other signals remain at a high level. As shown in FIG. 34 , since the fourth data writing control signal S6 and the second compensation and reset control signal S1 are at a low level, the eleventh transistor T11 and the twelfth transistor T12 are turned on, and the other transistors are turned off. Since the second transistor T2 is turned on at this time, the second data signal Date_PWM can reach the second electrode of the second transistor T2. The eleventh transistor T11 performs threshold compensation on the second transistor T2 and writes the second data signal Date_PWM to the node of the gate of the second transistor T2. At this time, the gate potential VA of the second transistor T2 is equal to V(Date_PWM)+Vth, and the second transistor T2 is turned off.

[0177] In the second reset phase, corresponding to phase (4) in FIG. 32 , the reset control signal S3 becomes low, and other signals remain high. As shown in FIG. 35 , since the reset control signal S3 is low, the third transistor T3 is turned on, and the other transistors are turned off. Since the third transistor T3 is turned on, the reset signal REF charges the sixth capacitor C6 through the third transistor T3, resetting the node at the gate of the first transistor T1 to the REF potential, and the first transistor T1 is turned on. It should be noted that although the third transistor T3 is also turned on in the first reset phase, after the first compensation phase and the first data writing phase, the second data signal Date_PWM reaches the gate node of the first transistor T1 through the turned-on second transistor T2, causing the potential of the gate of the first transistor T1 to no longer be the REF potential. Therefore, the gate of the first transistor T1 needs to be reset again in the second reset phase.

[0178] In the second compensation phase, corresponding to phase (5-1) in FIG. 32 , the third compensation control signal S7 becomes low, while the other signals remain high. As shown in FIG. 36 , due to the low level of the third compensation control signal S7, the thirteenth transistor T13 is turned on, while the other transistors are turned off. Since the thirteenth transistor T13 is conductive with the first transistor T1, the power supply signal VDD can pass through the first transistor T1 to the second electrode of the first transistor T1. The thirteenth transistor T13 can provide the signal at the second electrode of the first transistor T1 to the gate, thereby achieving threshold compensation for the first transistor T1. At this time, the gate potential VB of the first transistor T1 equals VDD + Vth.

[0179] During the second data write phase, corresponding to phase (5-2) in FIG. 32 , the third data write control signal S5 becomes low, while other signals remain high. As shown in FIG. 37 , since the third data write control signal S5 is low, the tenth transistor T10 is turned on. The first data signal Date_PAM can be coupled to the gate of the first transistor T1 via the tenth transistor T10 and the fifth capacitor C5. At this time, the gate potential of the first transistor T1 is VB = V(Date_PAM) + VDD + Vth.

[0180] During the light-emitting phase, corresponding to phase (6) in FIG32 , the drive control signal EM becomes low, the light-emitting duration control signal SWEEP gradually decreases from a high level, and other signals remain high. As shown in FIG38 , since the drive control signal EM is low, the fourteenth transistor T14 and the fifteenth transistor T15 are turned on. At the same time, since the first transistor T1 remains turned on in the previous phase, the power supply signal VDD drives the light-emitting element LED through the first transistor T1 and the fifteenth transistor T15 to begin emitting light. As the level of the light-emitting duration control signal SWEEP decreases, coupled with the coupling effect of C1, the potential VA at the gate of the second transistor T2 gradually decreases from V(Date_PWM)+Vth until the second transistor T2 is in the on state, as shown in FIG39 . After the second transistor T2 is turned on, and the fourteenth transistor T14 is also in the on state, the high-level VDD signal can charge the sixth capacitor C6 via the fourteenth transistor T14 and the second transistor T2, and at the same time gradually increase the node potential at the gate of the first transistor T1 until the first transistor T1 is turned off, as shown in Figure 39, at which time the light-emitting element LED stops emitting light.

[0181] In some embodiments, as shown in FIG40 , during the second data write phase, the start time of the active level of the first data signal Date_PAM lags behind the start time of the active level of the third data write control signal S5 by a first preset time. During the light-emitting phase, the end time of the active level of the first data signal Date_PAM lags behind the end time of the active level of the third data write control signal S5 by a second preset time. Both the first preset time and the second preset time are shorter than the duration of the active level of the third data write control signal S5. Based on this, the first preset time and the second preset time can be used to slightly lag the active level of the first data signal Date_PAM behind the active level of the third data write control signal S5. The specific values ​​are not limited.

[0182] In specific implementation, if the first data signal Date_PAM stops being written while the tenth transistor T10 is turned off, the fifth capacitor C5 will couple part of the first data signal Date_PAM, so that the first data signal Date_PAM cannot be completely written into the first transistor T1. Therefore, in some embodiments, as shown in the timing diagram of Figure 40, the overall timing of the first data signal Date_PAM needs to lag slightly behind the third data write control signal S5, that is, the falling edge of the high level of the first data signal Date_PAM needs to lag slightly behind the falling edge of the high level of the third data write control signal S5, and at the same time, the rising edge of the low level of the first data signal Date_PAM needs to lag slightly behind the rising edge of the low level of the third data write control signal S5.

[0183] In some embodiments, as shown in FIG. 41 , during the first reset phase, the start time of the inactive level of the light-emission duration control signal SWEEP lags behind the start time of the active level of the reset control signal S3 by a third preset time. The third preset time is shorter than the duration of the active level of the reset control signal S3 during the first reset phase. On this basis, the third preset time allows the start time of the inactive level of the light-emission duration control signal SWEEP to slightly lag behind the active level of the reset control signal S3 during the first reset phase. The specific value is not limited.

[0184] In a specific implementation, in order to ensure that the first transistor T1 is always turned off when the light-emitting element LED needs to stop emitting light, the rising edge of the light-emitting duration control signal SWEEP after the end of the light-emitting stage (6) can be slightly delayed from the time point when the light-emitting stage (6) ends. As shown in FIG41 , the rising edge of the low-level light-emitting duration control signal SWEEP in the first reset stage (1) of the next frame is slightly delayed from the falling edge of the high-level reset control signal S3. At the same time, since the circuit is still in the first reset stage (1) after the light-emitting duration control signal SWEEP returns to a high level, the influence of the voltage jump of the light-emitting duration control signal SWEEP on the gate of the second transistor T2 can be repaired by the reset signal REF, and will not affect the normal operation of the circuit.

[0185] In other embodiments, such as the pixel circuit shown in FIG42 , each transistor is an N-type transistor, and the gate is turned on in response to a high level, that is, the effective level is a high level. The timing diagram of each signal in the circuit corresponding to the embodiment of FIG42 is shown in FIG43 .

[0186] In the first reset stage, corresponding to stage (1) in Figure 43, the reset control signal S3, the second compensation and reset control signal S1 signals become high levels, and other signals remain low levels. Since the reset control signal S3, the second compensation and reset control signal S1 signals are high levels, the eleventh transistor T11 and the third transistor T3 are turned on accordingly, and the other transistors are turned off. Since the eleventh transistor T11 and the third transistor T3 are turned on, the other transistors are all in the off state. The reset signal REF will first pass through the third transistor T3, and then pass through the eleventh transistor T11 to charge the fourth capacitor C4, so that the node of the gate of the second transistor T2 is reset to the REF potential. At the same time, since for the embodiment shown in Figure 31, the REF potential is high level, the second transistor T2 is turned on in response to the REF potential of the gate, which is also high level.

[0187] During the first compensation phase and the first data writing phase, corresponding to phases (2) and (3) in FIG. 43 , the fourth data writing control signal S6 and the second compensation and reset control signal S1 are high, while the other signals remain low. Since the fourth data writing control signal S6 and the second compensation and reset control signal S1 are high, the eleventh transistor T11 and the twelfth transistor T12 are turned on, while the other transistors are turned off. Since the second transistor T2 is turned on at this time, the second data signal Date_PWM can reach the second electrode of the second transistor T2. The eleventh transistor T11 performs threshold compensation on the second transistor T2 while writing the second data signal Date_PWM to the node of the gate of the second transistor T2. At this time, the gate potential VA of the second transistor T2 is equal to V(Date_PWM)+Vth, and the second transistor T2 is turned off.

[0188] In the second reset phase, corresponding to phase (4) in FIG. 43 , the reset control signal S3 becomes high, and other signals remain low. Since the reset control signal S3 is high, the third transistor T3 is turned on, and the other transistors are turned off. Since the third transistor T3 is turned on, the reset signal REF charges the sixth capacitor C6 through the third transistor T3, resetting the node at the gate of the first transistor T1 to the REF potential, and turning on the first transistor T1. It should be noted that although the third transistor T3 is also turned on in the first reset phase, after the first compensation phase and the first data writing phase, the second data signal Date_PWM reaches the gate node of the first transistor T1 through the turned-on second transistor T2, causing the potential of the gate of the first transistor T1 to no longer be the REF potential. Therefore, the gate of the first transistor T1 needs to be reset again in the second reset phase.

[0189] In the second compensation phase, corresponding to phase (5-1) in FIG. 43 , the third compensation control signal S7 becomes high, while the other signals remain low. Since the third compensation control signal S7 is high, the thirteenth transistor T13 is turned on, while the other transistors are turned off. Since the thirteenth transistor T13 is conductive with the first transistor T1, the power supply signal VSS can pass through the first transistor T1 to the second electrode of the first transistor T1. The thirteenth transistor T13 can provide the signal at the second electrode of the first transistor T1 to the gate, thereby achieving threshold compensation for the first transistor T1. At this time, the gate potential VB of the first transistor T1 equals VSS + Vth.

[0190] During the second data write phase, corresponding to phase (5-2) in FIG. 43 , the third data write control signal S5 becomes high, while other signals remain low. Since the third data write control signal S5 is high, the tenth transistor T10 is turned on. The first data signal Date_PAM can be coupled to the gate of the first transistor T1 via the tenth transistor T10 and the fifth capacitor C5. At this time, the gate potential of the first transistor T1 is VB = V(Date_PAM) + VSS + Vth.

[0191] In the light-emitting stage, corresponding to stage (6) in FIG43 , the drive control signal EM becomes high, the light-emitting duration control signal SWEEP gradually increases from a low level, and other signals remain low. Since the drive control signal EM is high, the fourteenth transistor T14 and the fifteenth transistor T15 are turned on. At the same time, since the first transistor T1 remains turned on in the previous stage, the power supply signal VSS drives the light-emitting element LED to start emitting light through the first transistor T1 and the fifteenth transistor T15. As the level of the light-emitting duration control signal SWEEP increases, coupled with the coupling effect of C1, the potential VA at the gate of the second transistor T2 gradually increases from V(Date_PWM)+Vth until the second transistor T2 is in the on state. After the second transistor T2 is turned on, coupled with the fourteenth transistor T14 also being in the on state, the low-level VSS signal can charge the sixth capacitor C6 through the fourteenth transistor T14 and the second transistor T2, while gradually reducing the node potential at the gate of the first transistor T1 until the first transistor T1 is turned off, at which point the light-emitting element LED stops emitting light.

[0192] In a specific implementation, if the first data signal Date_PAM stops being written while the tenth transistor T10 is turned off, the fifth capacitor C5 will couple part of the first data signal Date_PAM, so that the first data signal Date_PAM cannot be completely written into the first transistor T1. Therefore, in some embodiments, as shown in the timing diagram of Figure 44, the overall timing of the first data signal Date_PAM needs to slightly lag behind the third data write control signal S5, that is, the rising edge of the low level of the first data signal Date_PAM needs to slightly lag behind the rising edge of the low level of the third data write control signal S5, and at the same time, the falling edge of the high level of the first data signal Date_PAM needs to slightly lag behind the falling edge of the high level of the third data write control signal S5.

[0193] In a specific implementation, in order to ensure that the first transistor T1 is always turned off when the light-emitting element LED needs to stop emitting light, the falling edge of the light-emitting duration control signal SWEEP after the end of the light-emitting stage (6) can be slightly delayed from the time point when the light-emitting stage (6) ends. As shown in FIG45 , that is, the falling edge of the high level of the light-emitting duration control signal SWEEP in the first reset stage (1) of the next frame is slightly delayed from the rising edge of the low level of the reset control signal S3. At the same time, since the circuit is still in the first reset stage (1) after the light-emitting duration control signal SWEEP returns to a low level, the influence of the voltage jump of the light-emitting duration control signal SWEEP on the gate of the second transistor T2 can be repaired by the reset signal REF, and will not affect the normal operation of the circuit.

[0194] It should be noted that the above embodiments of the present application respectively provide embodiments in which the pixel circuit comprises all N-type transistors and all P-type transistors. For embodiments in which the pixel circuit comprises some N-type transistors and some P-type transistors, those skilled in the art can derive the corresponding driving modes and driving timings based on the description of the above embodiments and Figures 10 to 22 and Figures 31 to 45, which are all within the protection scope of the present application.

[0195] FIG46 is a schematic structural diagram of another display device according to some embodiments of the present application. As shown in FIG46 , the display device is driven by a combination of PWM drive and PAM drive. Specifically, the display device may include at least one processor, a timing controller (TCON) board, and a display panel. The display panel may include a pixel matrix (i.e., the aforementioned pixel array unit) composed of multiple sub-pixels and a thin film transistor (TFT) drive circuit. The dotted box portion of the display panel in FIG46 represents the pixel matrix. Each sub-pixel in the pixel matrix may include a pixel circuit, and each pixel circuit is respectively connected to the TFT drive circuit and the TCON board. At least one processor is respectively connected to the TFT drive circuit and the TCON board. It should be noted that the TFT drive circuit may be located on the upper and lower sides of the display panel, on the left and right sides of the display panel, or on either side. The embodiments of the present application do not limit the position of the TFT drive circuit in the display panel.

[0196] During implementation, after acquiring image data, at least one processor outputs control signals to the pixel circuit based on the image data via the first control signal output terminal S8, the second control signal output terminal SWEEP, the third control signal output terminal S9, the fourth control signal output terminal S10, the fifth control signal output terminal S11, the sixth control signal output terminal S12, and the switch signal output terminal EM in the TFT driver circuit. Control signals and reset signals are also output to the pixel circuit via the pulse width modulation (PWM) drive signal output terminal Date_PWM, the pulse amplitude modulation (PAM) drive signal output terminal Date_PAM, and the reset signal output terminal REF in the TCON board. The pixel circuit controls the illumination and extinguishing of the micro-LEDs in the pixel circuit based on the control signals and reset signals. Therefore, the pixel circuit's drive method utilizes a combination of PWM and PAM drive. This allows the control signal outputted by the PWM drive signal output terminal Date_PWM to control the illumination duration of the micro-LEDs, and thus the brightness perceived by the human eye. The control signal outputted by the PAM drive signal output terminal Date_PAM can control the emission wavelength of the micro-LEDs. However, the TFTs included in the pixel circuit that implement PWM drive and PAM drive are prone to threshold voltage drift after long-term use, resulting in changes in the light-emitting duration and wavelength of the micro-LEDs, resulting in poor display effects.

[0197] Figure 47 is a structural schematic diagram of a pixel circuit according to some further embodiments of the present application. As shown in Figure 47, the pixel circuit may include a PWM drive circuit 11, a first compensation circuit 12, a PAM drive circuit 13, a second compensation circuit 14, a reset circuit 15, and a light-emitting circuit 16. A compensation circuit is added to the pixel circuit, and a compensation voltage is applied to the gate (also called the control end) of the TFT in the PWM drive circuit and the PAM drive circuit through the compensation circuit. On the basis of the compensation voltage, an additional voltage is applied to turn the TFT on and off, and it is not affected by the threshold voltage drift; thereby, the current flowing through the light-emitting element such as the micro LED is more stable, the light-emitting duration and the light-emitting wavelength will not change, and the display effect is improved.

[0198] The circuit structure of the above-mentioned pixel circuit of some embodiments of the present application is described below. As shown in Figure 47, the PWM drive circuit 11 may include a sixteenth transistor (also called a first switch circuit) T16, a seventh capacitor C7, an eighth capacitor C8, and a second transistor T2 (also called a second switch circuit, the same below and no further description will be given). It should be noted that Figure 47 shows an example in which each of the switch circuits included in the pixel circuit can be a P-type TFT. In some cases, at least one of the switch circuits included in the pixel circuit can be an N-type TFT.

[0199] The first electrode of the sixteenth transistor T16 is connected to the PWM drive signal output terminal Date_PWM, the second electrode is connected to the first terminal of the seventh capacitor C7 and the first terminal of the eighth capacitor C8, respectively, the gate is connected to the first control signal output terminal S8, the second terminal of the eighth capacitor C8 is connected to the second control signal output terminal SWEEP, the second terminal of the seventh capacitor C7 is connected to the gate of the second transistor T2 (denoted as control terminal 17), the first electrode of the second transistor T2 is connected to the first power supply terminal, which is the reference power supply output terminal VDD; the control terminal 17 of the second transistor T2 is the control terminal 17 of the PWM drive circuit 11. The sixteenth transistor T16 is controlled by the control signal output from the first control signal output terminal S8, that is, the S8 signal. When the S8 signal is at a first level, the sixteenth transistor T16 is in the on state; when the S8 signal is at a second level, the sixteenth transistor T16 is in the off state. It should be noted that when the switch circuit is a P-type TFT, the first level is a low level and the second level is a high level. The sixteenth transistor T16 can be used to set the voltage at the control terminal 17 of the second transistor T2 to the first drive voltage, thereby implementing drive voltage writing. The second transistor T2 is controlled by the voltage at its control terminal. When the switching circuit is a P-type TFT, when the voltage at the control terminal is less than the first compensation voltage, the second transistor T2 is in the on state; when the voltage at the control terminal is greater than or equal to the first compensation voltage, the second transistor T2 is in the off state. The second transistor T2 can be used to control the off state of the first transistor T1.

[0200] The reset circuit 15 is connected to the control terminal of the second transistor T2 through the first compensation circuit 12, and the second terminal of the second transistor T2 is connected to the first compensation circuit 12;

[0201] The control terminal 18 of the PAM driving circuit 13 is connected to the reset circuit 15 , the second compensation circuit 14 , and the second electrode of the second transistor T2 respectively. The light emitting circuit 16 is connected to the PAM driving circuit 13 .

[0202] The first compensation circuit 12 may include a seventeenth transistor T17, and the reset circuit 15 may include a third transistor T3. The first electrode of the seventeenth transistor T17 is connected to the gate of the second transistor T2, the second electrode is connected to the second electrode of the second transistor T2, and the gate is connected to the third control signal output terminal S9. The gate of the third transistor T3 is connected to the fourth control signal output terminal S10, the first electrode of the third transistor T3 is connected to the second electrode of the seventeenth transistor T17, and the second electrode of the third transistor T3 is connected to the reset signal output terminal REF.

[0203] The seventeenth transistor T17 is controlled by the control signal output from the third control signal output terminal S9, i.e., the S9 signal. When the S9 signal is at a first level, the seventeenth transistor T17 is in an on state; when the S9 signal is at a second level, the seventeenth transistor T17 is in an off state. The seventeenth transistor T17 can be used to set the voltage at the control terminal 17 of the second transistor T2 to a first compensation voltage, thereby achieving threshold voltage compensation. The third transistor T3 is controlled by the control signal output from the fourth control signal output terminal S10, i.e., the S10 signal. When the S10 signal is at a first level, the third transistor T3 is in an on state; when the S10 signal is at a second level, the third transistor T3 is in an off state. The third transistor T3 can be used to set the voltages at the control terminal 17 of the second transistor T2 and the control terminal 18 of the first transistor T1 to a reset voltage.

[0204] The PAM driver circuit 13 may include an eighteenth transistor T18, a ninth capacitor C9, a tenth capacitor C10, and a first transistor T1. The first electrode of the eighteenth transistor T18 is connected to the first end of the tenth capacitor C10, the second electrode is connected to the PAM drive signal output terminal Date_PAM, and the gate is connected to the fifth control signal output terminal S11. The second end of the tenth capacitor C10 is connected to the first end of the ninth capacitor C9 and the control terminal 18 of the first transistor T1, respectively. The first power supply terminal is the reference power supply output terminal VDD, which is connected to the second end of the ninth capacitor C9 and the first electrode of the first transistor T1. The control terminal 18 of the first transistor T1 serves as the control terminal 18 of the PAM driver circuit 13. The first electrode of the third transistor T3 is connected to the control terminal 18 of the first transistor T1.

[0205] The eighteenth transistor T18 can be controlled by the control signal output by the fifth control signal output terminal S11, that is, the S11 signal. When the S11 signal is at a first level, the eighteenth transistor T18 is in an on state; when the S11 signal is at a second level, the eighteenth transistor T18 is in an off state. The eighteenth transistor T18 can be used to set the voltage of the control terminal 18 of the first transistor T1 to a second driving voltage to achieve driving voltage writing. The first transistor T1 is controlled by the voltage of its control terminal. When the switching circuit is a P-type TFT, when the voltage of the control terminal is less than the second compensation voltage, the first transistor T1 is in an on state; when the voltage of the control terminal is greater than or equal to the second compensation voltage, the first transistor T1 is in an off state. The first transistor T1 can be used to control the light emission and extinguishing of the light emitting element. In some embodiments, the light emitting element can be a micro light emitting diode Micro-LED.

[0206] The second compensation circuit 14 may include a nineteenth transistor T19. A first electrode of the nineteenth transistor T19 is connected to the control terminal 18 of the first transistor T1, a second electrode is connected to the second electrode of the first transistor T1, and a gate is connected to the sixth control signal output terminal S12. The nineteenth transistor T19 is controlled by a control signal output from the sixth control signal output terminal S12, namely, the S12 signal. When the S12 signal is at a first level, the nineteenth transistor T19 is in an on state; when the S12 signal is at a second level, the nineteenth transistor T19 is in an off state. The nineteenth transistor T19 can be used to set the voltage at the control terminal 18 of the first transistor T1 to a second compensation voltage, thereby achieving threshold voltage compensation.

[0207] The light-emitting circuit 16 may include a twentieth transistor T20 and a light-emitting element. In some embodiments, the light-emitting element may be a micro-LED. The gate of the twentieth transistor T20 is connected to the switching signal output terminal EM, the first electrode is connected to the second electrode of the first transistor T1, the second electrode is connected to the first end of the light-emitting element, and the second end of the light-emitting element is connected to the second power supply terminal. The first end is a positive electrode, the second end is a negative electrode, and the second power supply terminal is the ground terminal VSS. The second electrode of the second transistor T2 is connected to the control terminal 18 of the first transistor T1. The twentieth transistor T20 can be controlled by a control signal output from the switching signal output terminal EM, namely, the EM signal. When the EM signal is at a first level, the twentieth transistor T20 is in an on state; when the EM signal is at a second level, the twentieth transistor T20 is in an off state. The twentieth transistor T20 can be used to control the lighting and extinguishing of the light-emitting element.

[0208] Fig. 48 is a first timing diagram of control signals according to some further embodiments of the present application, which can be used to control the pixel circuit shown in Fig. 47. The operation process of the pixel circuit is described below.

[0209] As shown in FIG48 , a display cycle T may include, arranged in time from earliest to latest, a first reset phase (1), a first compensation phase (2), a first data writing phase (also known as a first drive voltage writing phase) (3), a second reset phase (4), a second compensation phase and a second data writing phase (also known as a second drive voltage writing phase) (5), and a light-emitting phase (6). The control signal output by the second control signal output terminal SWEEP is a SWEEP signal, the control signal output by the PWM drive signal output terminal Date_PWM is a Date_PWM signal, and the control signal output by the PAM drive signal output terminal Date_PAM is a Date_PAM signal.

[0210] In the first reset phase, corresponding to phase (1) in FIG. 48 , the S9 signal, the S10 signal, and the Date_PWM signal are low-level signals, the S8 signal, the S11 signal, the S12 signal, the EM signal, and the Date_PAM signal are high-level signals, and the SWEEP signal remains low-level for a preset period of time before switching to a high level. Based on FIG. 47 , FIG. 49 is a schematic diagram of a pixel circuit in the first reset phase according to some further embodiments of the present application. As shown in FIG. 49 , a cross in the switching unit indicates disconnection, and an uncrossed unit indicates conduction. Because the S9 signal and the S10 signal are low-level signals, the seventeenth transistor T17 and the third transistor T3 are turned on; the S8 signal, the S11 signal, the S12 signal, and the EM signal are high-level signals, so the sixteenth transistor T16, the eighteenth transistor T18, the nineteenth transistor T19, and the twentieth transistor T20 are turned off. The reset signal output terminal REF outputs a reset signal of a reset voltage. The reset signal can pass through the third transistor T3 and the seventeenth transistor T17 in sequence, and reach the control terminal 17 of the second transistor T2 and the second end of the seventh capacitor C7, so that the voltage of the control terminal 17 of the second transistor T2 is the reset voltage, and the seventh capacitor C7 is charged. Because the reset voltage is a negative voltage, the second transistor T2 is turned on. The reset signal reaches the control terminal 18 of the first transistor T1, so that the voltage of the control terminal 18 of the first transistor T1 is the reset voltage, and the first transistor T1 is also turned on. Since the SWEEP signal remains at a low level signal for a preset period of time and then turns to a high level, the SWEEP signal is coupled through the eighth capacitor C8, so that after the voltage of the control terminal 17 of the second transistor T2 changes, the changed voltage remains unchanged.

[0211] In the first compensation phase, corresponding to phase (2) in FIG. 48 , the S9 signal and the Date_PWM signal are low-level signals, and the S8 signal, the S10 signal, the S11 signal, the S12 signal, the EM signal, the Date_PAM signal, and the SWEEP signal are high-level signals. Based on FIG. 47 , FIG. 50 is a schematic diagram of a pixel circuit in the first compensation phase according to some embodiments of the present application. As shown in FIG. 50 , a cross in the switching unit indicates disconnection, and an uncrossed unit indicates conduction. Because the S9 signal is a low-level signal, the seventeenth transistor T17 is turned on; the S8 signal, the S10 signal, the S11 signal, the S12 signal, and the EM signal are high-level signals, so the sixteenth transistor T16, the third transistor T3, the eighteenth transistor T18, the nineteenth transistor T19, and the twentieth transistor T20 are turned off. Because the second transistor T2 is turned on in the first reset phase, at the beginning of the first compensation phase, the reference power supply output terminal VDD applies a voltage to the control terminal 17 of the second transistor T2 through the second transistor T2 and the seventeenth transistor T17. When the voltage of the control terminal 17 of the second transistor T2 reaches the first compensation voltage, the second transistor T2 is turned off. It should be noted that the first compensation voltage is the critical voltage for the second transistor T2 to be turned on and off. A1 =V VDD +V th1 , where V VDD Indicates the voltage output by the reference power supply output terminal VDD, V th1 represents the threshold voltage of the second transistor T2, V th1 It should be noted that the second control signal output terminal SWEEP outputs a control signal of a second level to ensure that the voltage of the control terminal 17 of the second transistor T2 remains unchanged after reaching the first compensation voltage.

[0212] At the start of the first compensation phase, the reference power supply output terminal VDD applies a voltage to the control terminal 18 of the first transistor T1 through the second transistor T2, causing the voltage at the control terminal 18 of the first transistor T1 to gradually increase. When the first compensation voltage is greater than or equal to the second compensation voltage, the voltage at the control terminal 17 of the second transistor T2 reaches the first compensation voltage, and the second transistor T2 turns off. At this time, the voltage at the control terminal 18 of the first transistor T1 also reaches the first compensation voltage, and the first transistor T1 turns off. When the first compensation voltage is less than the second compensation voltage, the voltage at the control terminal 17 of the second transistor T2 reaches the first compensation voltage, and the second transistor T2 turns off. At this time, the voltage at the control terminal 18 of the first transistor T1 also reaches the first compensation voltage, and the voltage stops increasing, and the first transistor T1 turns on.

[0213] The embodiment of the present application does not limit the state of the first transistor T1 in the first reset phase.

[0214] In the first data writing phase, corresponding to phase (3) in FIG48, the S8 signal is a low-level signal, the S9 signal, the S10 signal, the S11 signal, the S12 signal, the EM signal, the Date_PAM signal, and the SWEEP signal are high-level signals, and the Date_PWM signal remains at a low-level signal for a preset period of time before turning to a high level. Based on FIG47, FIG51 is a schematic diagram of a pixel circuit in the fifth drive voltage writing phase according to some embodiments of the present application. As shown in FIG51, a cross in the switch unit in the figure indicates disconnection, and an uncrossed switch unit indicates conduction. Because the S8 signal is a low-level signal, the sixteenth transistor T16 is turned on; the S9 signal, the S10 signal, the S11 signal, the S12 signal, and the EM signal are high-level signals, so the seventeenth transistor T17, the third transistor T3, the eighteenth transistor T18, the nineteenth transistor T19, and the twentieth transistor T20 are turned off. The PWM drive signal output terminal Date_PWM applies a voltage to the control terminal 17 of the second transistor T2 through the sixteenth transistor T16 and the seventh capacitor C7 to the first drive voltage. The Date_PWM signal remains low for a preset period of time and then turns high, ensuring that after the second transistor T2 is turned off, the voltage of the control signal is coupled through the seventh capacitor C7 to the control terminal 17 of the second transistor T2, so that the voltage of the control terminal 17 is the first driving voltage. Because the first driving voltage is greater than the first compensation voltage, the second transistor T2 remains in the off state. It should be noted that the first driving voltage V A2 =V VDD +V th1 +V Date_PWM , where V VDD Indicates the voltage output by the reference power supply output terminal VDD, V th1 represents the threshold voltage of the second transistor T2, V th1 is a negative voltage, V Date_PWM Indicates the voltage of the Date_PWM signal, V Date_PWM It should be noted that the second control signal output terminal SWEEP outputs a control signal of a second level to ensure that the voltage of the control terminal 17 of the second transistor T2 remains unchanged after reaching the first driving voltage.

[0215] In the second reset phase, corresponding to phase (4) in FIG. 48 , the S10 signal and the Date_PWM signal are low-level signals, and the S8 signal, the S9 signal, the S11 signal, the S12 signal, the EM signal, the Date_PAM signal, and the SWEEP signal are high-level signals. Based on FIG. 47 , FIG. 52 is a schematic diagram of a pixel circuit in the second reset phase according to some further embodiments of the present application. As shown in FIG. 52 , a cross in the switching unit indicates disconnection, and an uncrossed unit indicates conduction. Because the S10 signal is a low-level signal, the third transistor T3 is turned on; the S8 signal, the S9 signal, the S11 signal, the S12 signal, and the EM signal are high-level signals, so the sixteenth transistor T16, the seventeenth transistor T17, the eighteenth transistor T18, the nineteenth transistor T19, and the twentieth transistor T20 are turned off. The reset signal output terminal REF outputs a reset signal with a reset voltage. The reset signal passes through the third transistor T3 and reaches the control terminal 18 of the first transistor T1, the first terminal of the ninth capacitor C9, and the second terminal of the tenth capacitor C10. This resets the voltage at the control terminal 18 of the first transistor T1 to the reset voltage and charges the ninth capacitor C9 and the tenth capacitor C10. Because the reset voltage is a negative voltage, the first transistor T1 is turned on. The second control signal output terminal SWEEP outputs a control signal of a second level to ensure that the voltage at the control terminal 17 of the second transistor T2 remains constant after reaching the first drive voltage.

[0216] In the second compensation phase, corresponding to phase (5-1) in FIG. 48 , the S12 and Date_PWM signals are low-level signals, while the S8, S9, S10, S11, EM, Date_PAM, and SWEEP signals are high-level signals. Based on FIG. 47 , FIG. 53 is a schematic diagram of a pixel circuit in the second compensation phase according to further embodiments of the present application. As shown in FIG. 53 , a switch unit marked with a cross indicates disconnection, while an unmarked switch unit indicates conduction. Because the S12 signal is low-level, the nineteenth transistor T19 is turned on; and because the S8, S9, S10, S11, and EM signals are high-level, the sixteenth transistor T16, the seventeenth transistor T17, the third transistor T3, the eighteenth transistor T18, and the twentieth transistor T20 are turned off. Because the first transistor T1 is turned on during the second reset phase, at the start of the second compensation phase, the reference power supply output terminal VDD applies a voltage to the control terminal 18 of the first transistor T1 via the first transistor T1 and the nineteenth transistor T19. When the voltage of the control terminal 18 of the first transistor T1 reaches the second compensation voltage, the first transistor T1 is turned off. It should be noted that the second compensation voltage is the critical voltage for the first transistor T1 to be turned on and off. The second compensation voltage V B1 =V VDD +V th2 , where VVDD Indicates the voltage output by the reference power supply output terminal VDD, V th2 represents the threshold voltage of the first transistor T1, V th2 It should be noted that the second control signal output terminal SWEEP outputs a control signal of a second level to ensure that the voltage of the control terminal 17 of the second transistor T2 remains unchanged after reaching the first compensation voltage.

[0217] In the second data writing phase, corresponding to phase (5-2) in FIG. 48 , the S11 signal and the Date_PWM signal are low-level signals, the S8 signal, the S9 signal, the S10 signal, the S12 signal, the EM signal, and the SWEEP signal are high-level signals, and the Date_PAM signal remains high-level for a preset period of time before turning low. Based on FIG. 47 , FIG. 54 is a schematic diagram of a pixel circuit in the sixth drive voltage writing phase according to some embodiments of the present application. As shown in FIG. 54 , a cross in the figure indicates disconnection of a switch unit, and an uncrossed one indicates conduction. Because the S11 signal is a low-level signal, the eighteenth transistor T18 is turned on; the S8 signal, the S9 signal, the S10 signal, the S12 signal, and the EM signal are high-level signals, so the sixteenth transistor T16, the seventeenth transistor T17, the third transistor T3, the nineteenth transistor T19, and the twentieth transistor T20 are turned off. The PAM drive signal output terminal Date_PAM applies a voltage to the control terminal 18 of the first transistor T1 to the second drive voltage through the eighteenth transistor T18 and the tenth capacitor C10. The Date_PAM signal remains high for a preset period of time and then turns to a low level, ensuring that after the first transistor T1 is turned off, the voltage of the control signal reaches the control terminal 18 of the first transistor T1 after coupling through the tenth capacitor C10, so that the voltage of the control terminal 18 is the second drive voltage. Because the second drive voltage is less than the second compensation voltage, the first transistor T1 is turned on. It should be noted that the second drive voltage Among them, V VDD Indicates the voltage output by the reference power supply output terminal VDD, V th2 represents the threshold voltage of the first transistor T1, V th2 is a negative voltage; V Date_PAM Indicates the voltage of the Date_PAM signal, V Date_PAM is a negative voltage; C′3 represents the capacitance value of capacitor C9, and C′4 represents the capacitance value of capacitor C10. It should be noted that the second control signal output terminal SWEEP outputs a control signal of a second level to ensure that the voltage of the control terminal 17 of the second transistor T2 remains unchanged after reaching the first driving voltage.

[0218] In the light-emitting stage, corresponding to stage (6) in Figure 48, the EM signal and the Date_PWM signal are low-level signals, the S8 signal, the S9 signal, the S10 signal, the S11 signal, the S12 signal, and the Date_PAM signal are high-level signals, and the level of the SWEEP signal gradually changes from a high level to a low level.

[0219] Based on FIG. 47 , FIG. 55 is a first schematic diagram of a pixel circuit during the light-emitting phase according to yet another embodiment of the present application. As shown in FIG. 55 , a switch unit marked with a cross indicates disconnection, while an unmarked unit indicates conduction. Because the EM signal is a low-level signal, the twentieth transistor T20 is turned on; while the S8, S9, S10, S11, and S12 signals are high-level signals, the sixteenth transistor T16, the seventeenth transistor T17, the third transistor T3, the eighteenth transistor T18, and the nineteenth transistor T19 are turned off. The reference power supply output terminal VDD outputs current that sequentially passes through the first transistor T1 and the twentieth transistor T20 to reach a light-emitting element, such as a micro-LED, driving the micro-LED to emit light.

[0220] Based on Figure 47, Figure 56 is a second schematic diagram of a pixel circuit in the light-emitting stage according to some further embodiments of the present application. As shown in Figure 56, a cross in the switch unit in the figure indicates disconnection, and an uncrossed one indicates conduction. Because the level of the SWEEP signal gradually changes from a high level to a low level, the voltage at the control terminal 17 of the second transistor T2 gradually changes to the first drive voltage, and the second transistor T2 is turned on. The reference power supply output terminal VDD applies a voltage to the control terminal 18 of the first transistor T1 through the second transistor T2 to the second compensation voltage, and charges the ninth capacitor C9 and the tenth capacitor C10. The voltage at the control terminal 18 of the first transistor T1 is the second compensation voltage, the first transistor T1 is disconnected, and the micro-light-emitting diode Micro-LED stops emitting light.

[0221] Thus, by connecting the first electrode of the seventeenth transistor to the gate of the second transistor and the second electrode to the second electrode of the second transistor, the seventeenth transistor causes the voltage at the gate (i.e., the control terminal) of the second transistor to reach the first compensation voltage during the first compensation phase, thereby completing threshold voltage compensation. By connecting the first electrode of the nineteenth transistor to the gate (i.e., the control terminal) of the first transistor and the second electrode to the second electrode of the first transistor, the nineteenth transistor causes the voltage at the gate (i.e., the control terminal) of the first transistor to reach the second compensation voltage during the second compensation phase, thereby completing threshold voltage compensation. Performing threshold voltage compensation on the PWM drive circuit through the seventeenth transistor, and on the PAM drive circuit through the nineteenth transistor, ensures that threshold voltage drift does not occur in the TFTs in the PWM drive circuit and the PAM drive circuit, thereby stabilizing the current flowing through light-emitting elements, such as micro-LEDs, and maintaining the micro-LED's light emission duration and wavelength, thereby improving display quality.

[0222] In the above embodiments, all the switch circuits are P-type TFTs. In some cases, at least one of the switch circuits included in the pixel circuit may be an N-type TFT. The following describes the case where the switch circuit included in the pixel circuit is an N-type TFT.

[0223] Based on Figure 47 , Figure 57 is a second schematic diagram of the structure of a pixel circuit according to further embodiments of the present application. As shown in Figure 57 , the switch circuit in the figure is an N-type TFT. In the figure, the first power supply terminal is the ground terminal VSS, and the second power supply terminal is the reference power supply output terminal VDD. The light-emitting element is a micro-LED, with a first terminal being a cathode and a second terminal being an anode. The first level is a high level, and the second level is a low level. Figure 58 is a second timing diagram of control signals according to further embodiments of the present application, which is used to control the pixel circuit shown in Figure 57 .

[0224] In the first reset stage, corresponding to stage (1) in Figure 58, the S9 signal, S10 signal, and Date_PWM signal are high-level signals, the S8 signal, S11 signal, S12 signal, EM signal, and Date_PAM signal are low-level signals, and the SWEEP signal remains high-level for a preset period of time and then turns to a low level.

[0225] In the first compensation phase, corresponding to phase (2) in FIG. 58 , the S9 signal and the Date_PWM signal are high-level signals, while the S8 signal, the S10 signal, the S11 signal, the S12 signal, the EM signal, the Date_PAM signal, and the SWEEP signal are low-level signals. The reference power supply output terminal VDD applies a voltage to the control terminal 17 of the second transistor T2 through the second transistor T2 and the seventeenth transistor T17, so that the voltage at the control terminal 17 of the second transistor T2 reaches the first compensation voltage.

[0226] In the first data writing stage, corresponding to stage (3) in Figure 58, the S8 signal is a high-level signal, the S9 signal, S10 signal, S11 signal, S12 signal, EM signal, Date_PAM signal, and SWEEP signal are low-level signals, and the Date_PWM signal remains a high-level signal for a preset period of time and then turns to a low level.

[0227] In the second reset stage, corresponding to stage (4) in Figure 58, the S10 signal and the Date_PWM signal are high-level signals, and the S8 signal, the S9 signal, the S11 signal, the S12 signal, the EM signal, the Date_PAM signal, and the SWEEP signal are low-level signals.

[0228] In the second compensation phase, corresponding to phase (5-1) in FIG. 58 , the S12 and Date_PWM signals are high-level signals, while the S8, S9, S10, S11, EM, Date_PAM, and SWEEP signals are low-level signals. The reference power supply output terminal VDD applies a voltage to the control terminal 18 of the first transistor T1 through the first transistor T1 and the nineteenth transistor T19, causing the voltage at the control terminal 18 of the first transistor T1 to reach the second compensation voltage.

[0229] In the second data writing stage, corresponding to the (5-2) stage in Figure 58, the S11 signal and the Date_PWM signal are high-level signals, the S8 signal, the S9 signal, the S10 signal, the S12 signal, the EM signal, and the SWEEP signal are low-level signals, and the Date_PAM signal remains at a low level for a preset period of time and then turns to a high level.

[0230] In the light-emitting stage, corresponding to stage (6) in Figure 58, the EM signal and the Date_PWM signal are high-level signals, the S8 signal, the S9 signal, the S10 signal, the S11 signal, the S12 signal, and the Date_PAM signal are low-level signals, and the level of the SWEEP signal gradually changes from a low level to a high level.

[0231] It should be noted that the implementation process and technical effects in each stage can be found in the above embodiments and will not be repeated here.

[0232] Based on the same inventive concept, a display device as shown in Figure 1 according to some embodiments of the present application may include a data driving circuit 500, a scan driving circuit 700, a data line DL, a scan line SL, and a pixel array unit 100. The pixel array unit 100 may include the corresponding pixel circuit in any of the aforementioned embodiments.

[0233] For ease of explanation, the above description has been presented in conjunction with specific embodiments. However, the above discussion of some embodiments is not intended to be exhaustive or to limit the embodiments to the specific forms disclosed above. Various modifications and variations are possible based on the above teachings. The above embodiments have been selected and described to better explain the principles and practical applications, thereby enabling those skilled in the art to better utilize the embodiments and various variations of the embodiments as appropriate for specific applications.

Claims

1. A pixel circuit, comprising a first transistor, a second transistor, a third transistor and a light-emitting element, wherein: The first electrode of the first transistor and the first electrode of the second transistor are used to receive a power supply signal, the second electrode of the first transistor is connected to the light emitting element, and the second electrode of the second transistor is connected to the gate of the first transistor; The second electrode of the third transistor is connected to the gate of the first transistor and the gate of the second transistor, the first electrode of the third transistor is used to receive a reset signal, and the gate of the third transistor is used to receive a reset control signal; The first transistor is used to provide a driving signal for the light-emitting element, the second transistor is used to provide a control signal to the first transistor to control the light-emitting duration of the light-emitting element, and the third transistor is used to provide the reset signal to the second transistor and the first transistor in response to the reset control signal received by the gate. 2 . The pixel circuit according to claim 1 , further comprising a first capacitor, a first electrode of the first capacitor being connected to the gate of the first transistor, and a second electrode of the first capacitor being used to receive the power signal.

3. The pixel circuit according to claim 1, further comprising a fourth transistor, a first electrode of the fourth transistor being connected to the gate of the first transistor, a second electrode of the fourth transistor being connected to the second electrode of the first transistor, and a gate of the fourth transistor being used to receive a first compensation control signal; The fourth transistor is configured to provide threshold compensation for the first transistor in response to the first compensation control signal received by the gate.

4. The pixel circuit according to claim 1, further comprising a fifth transistor, a first electrode of the fifth transistor being connected to a gate of the second transistor, a second electrode of the fifth transistor being connected to a second electrode of the second transistor and a second electrode of the third transistor, and a gate of the fifth transistor being used to receive a second compensation and reset control signal; The fifth transistor is used to provide the reset signal provided by the third transistor received at the second pole to the gate of the second transistor through the first pole in response to the second compensation and reset control signal received through the gate; and, in response to the second compensation and reset control signal received through the gate, provide threshold compensation for the second transistor.

5. The pixel circuit according to claim 1, further comprising a sixth transistor and a seventh transistor, wherein a first electrode of the sixth transistor is used to receive a first data signal, a second electrode of the sixth transistor is connected to a first electrode of the first transistor, a gate of the sixth transistor is used to receive a first data write control signal, a first electrode of the seventh transistor is used to receive a second data signal, a second electrode of the seventh transistor is connected to a gate of the second transistor, and a gate of the seventh transistor is used to receive a second data write control signal; The sixth transistor is used to write the first data signal into the first electrode of the first transistor in response to the first data write control signal received by the gate, and the seventh transistor is used to write the second data signal into the gate of the second transistor in response to the second data write control signal received by the gate.

6. The pixel circuit according to claim 1, further comprising a tenth transistor, wherein: The first electrode of the tenth transistor is used to receive the first data signal, the second electrode of the tenth transistor is connected to the gate of the first transistor, and the gate of the tenth transistor is used to receive the third data writing control signal; The third transistor is used for providing the reset signal to the gate of the first transistor and the gate of the second transistor in response to the reset control signal received at the gate; The tenth transistor is configured to write the third data signal into the gate of the first transistor in response to the third data writing control signal received by the gate.

7. The pixel circuit according to claim 6, further comprising an eleventh transistor, a first electrode of the eleventh transistor being connected to the gate of the second transistor, a second electrode of the eleventh transistor being connected to the second electrode of the second transistor and the second electrode of the third transistor, and a gate of the eleventh transistor being used to receive a second compensation and reset control signal; The eleventh transistor is used to provide the reset signal provided by the third transistor to the gate of the second transistor in response to the second compensation and reset control signal received through the gate. The eleventh transistor is also used to The method provides threshold compensation for the second transistor in response to the second compensation and reset control signal received through a gate.

8. The pixel circuit according to claim 7, further comprising a twelfth transistor, a first electrode of the twelfth transistor being connected to the first electrode of the second transistor, a second electrode of the twelfth transistor being used to receive a second data signal, and a gate of the twelfth transistor being used to receive a fourth data write control signal; The twelfth transistor is used to write the second data signal into the first electrode of the second transistor in response to the fourth data writing control signal received by the gate, and the second transistor is also used to transfer the second data signal received by the first electrode to the second electrode after being turned on; The eleventh transistor is further configured to provide the second data signal to the gate of the second transistor in response to the second compensation and reset control signal received through the gate, and provide threshold compensation for the second transistor.

9. The pixel circuit according to claim 6, further comprising a thirteenth transistor, a first electrode of the thirteenth transistor being connected to a gate of the first transistor, a second electrode of the thirteenth transistor being connected to a second electrode of the first transistor, and a gate of the thirteenth transistor being used to receive a third compensation control signal; The thirteenth transistor is configured to provide threshold compensation for the first transistor in response to the third compensation control signal received by the gate.

10. The pixel circuit according to claim 6 further includes a fourth capacitor, a first electrode of the fourth capacitor is connected to the gate of the second transistor, a second electrode of the fourth capacitor is used to receive a light-emitting duration control signal, and the fourth capacitor is used to couple the light-emitting duration control signal to the gate of the second transistor.

11. The pixel circuit according to claim 1, further comprising: Pulse width modulation PWM driving circuit, first compensation circuit, pulse amplitude modulation PAM driving circuit, second compensation circuit, reset circuit, light emitting circuit; The PWM driving circuit includes a sixteenth transistor, a seventh capacitor, an eighth capacitor, and the second transistor; The first electrode of the sixteenth transistor is connected to the PWM drive signal output terminal, the second electrode of the sixteenth transistor is respectively connected to the first end of the seventh capacitor and the first end of the eighth capacitor, and the gate of the sixteenth transistor is connected to the first control signal output terminal; The second end of the eighth capacitor is connected to the second control signal output terminal, the second end of the seventh capacitor is connected to the gate of the second transistor, and the first electrode of the second transistor is connected to the first power supply terminal; The reset circuit is connected to the gate of the second transistor through the first compensation circuit, and the second electrode of the second transistor is connected to the first compensation circuit; The control end of the PAM driving circuit is connected to the reset circuit, the second compensation circuit, and the second end of the second switch circuit respectively, and the light emitting circuit is connected to the PAM driving circuit.

12. The pixel circuit according to claim 11, wherein the first compensation circuit comprises a seventeenth transistor, and the reset circuit comprises a third transistor; The first electrode of the seventeenth transistor is connected to the control terminal of the second transistor, the second electrode of the seventeenth transistor is connected to the second electrode of the second transistor, and the control terminal of the seventeenth transistor is connected to the third control signal output terminal; The gate of the third transistor is connected to the fourth control signal output terminal, the first electrode of the third transistor is connected to the second electrode of the seventeenth transistor, and the second electrode of the third transistor is connected to the reset signal output terminal.

13. The pixel circuit according to claim 12, wherein the PAM driving circuit comprises an eighteenth transistor, a ninth capacitor, a tenth capacitor, and the first transistor; The second compensation circuit includes a nineteenth transistor; The light emitting circuit comprises a twentieth transistor and the light emitting element; The first electrode of the eighteenth transistor is connected to the first end of the tenth capacitor, the second electrode of the eighteenth transistor is connected to the PAM drive signal output terminal, and the gate of the eighteenth transistor is connected to the fifth control signal output terminal; The second end of the tenth capacitor is connected to the first end of the ninth capacitor and the gate of the first transistor respectively, and the first power supply end is connected to the second end of the ninth capacitor and the first electrode of the first transistor respectively; A first electrode of the third transistor is connected to a gate of the first transistor; A first electrode of the nineteenth transistor is connected to a gate of the first transistor, a second electrode of the nineteenth transistor is connected to a second electrode of the first transistor, and a gate of the nineteenth transistor is connected to a sixth control signal output terminal; The gate of the 20th transistor is connected to the switch signal output terminal, the first electrode of the 20th transistor is connected to the second electrode of the first transistor, and the second electrode of the 20th transistor is connected to the first end of the light emitting element; The second end of the light emitting element is connected to the second power supply end.

14. The pixel circuit according to claim 13, wherein in a first reset phase, the third control signal output terminal outputs a control signal of a first level to turn on the seventeenth transistor; The fourth control signal output terminal outputs a control signal of a first level to turn on the third transistor; The control signal outputted by the second control signal output terminal maintains the first level for a preset period of time and then changes to the second level; The reset signal output terminal outputs a reset signal of a reset voltage, and the reset signal passes through the third transistor and the seventeenth transistor in sequence and reaches the gate of the second transistor, so that the voltage of the gate of the second transistor is the reset voltage and the second transistor is turned on.

15. The pixel circuit according to claim 14, wherein in a first compensation phase after the first reset phase, the third control signal output terminal outputs a control signal of a first level to turn on the seventeenth transistor; The first power supply terminal applies a voltage to the gate of the second transistor through the second transistor and the seventeenth transistor. When the voltage of the gate of the second transistor reaches the first compensation voltage, the second transistor is disconnected.

16. The pixel circuit according to claim 15, wherein in a first data writing phase after the first compensation phase, the first control signal output terminal outputs a control signal of a first level to turn on the sixteenth transistor; The control signal outputted by the PWM drive signal output terminal is maintained at the first level for a preset period of time and then changes to the second level; The PWM driving signal output terminal applies a voltage to the gate of the second transistor to a first driving voltage through the sixteenth transistor and the seventh capacitor; In a second reset phase after the first data writing phase, the fourth control signal output terminal outputs a control signal of a first level to turn on the third transistor; The reset signal output terminal outputs a reset signal of the reset voltage; The reset signal passes through the third transistor in sequence and reaches the gate of the first transistor, so that the voltage of the gate of the first transistor is the reset voltage and the first transistor is turned on.

17. The pixel circuit according to claim 16, wherein in a second compensation phase after the second reset phase, the sixth control signal output terminal outputs a control signal of a first level to turn on the nineteenth transistor; The first power supply terminal applies a voltage to the gate of the first transistor through the first transistor and the nineteenth transistor. When the voltage of the gate of the first transistor reaches a second compensation voltage, the first transistor is disconnected.

18. The pixel circuit according to claim 17, wherein in a second data writing phase after the second compensation phase, the fifth control signal output terminal outputs a control signal of a first level to turn on the eighteenth transistor; The control signal output by the PAM drive signal output terminal is to maintain the second level for a preset time and then change to the first level, and the PAM drive signal output terminal applies a voltage to the gate of the first transistor through the eighteenth transistor and the tenth capacitor to the second drive voltage, and the first transistor is turned on; In the light emitting stage after the second data writing stage, the switch signal output terminal outputs a control signal of a first level to turn on the twentieth transistor; The first power supply end or the second power supply end outputs a current which passes through the light emitting element to drive the light emitting element to emit light; The level of the control signal output by the second control signal output terminal gradually changes from the second level to the first level, so that the voltage of the gate of the second transistor gradually changes to the first driving voltage, and the second transistor is turned on; The first power supply terminal applies a voltage to the second compensation voltage to the gate of the first transistor through the second transistor, the first transistor is turned off, and the light-emitting element stops emitting light.

19. The pixel circuit according to claim 13, wherein the third control signal output terminal outputs a control signal of a first level in a first reset phase and a first compensation phase, and outputs a control signal of a second level in a first data writing phase, a second reset phase, a second compensation phase, a second data writing phase, and a light emitting phase.

20. The pixel circuit according to claim 13, wherein the sixth control signal output terminal outputs a control signal of a first level in the second compensation stage, and outputs a control signal of a second level in the first reset stage, the first compensation stage, the first data writing stage, the second reset stage, the second data writing stage, and the light emitting stage.

21. A pixel circuit, comprising a first transistor, a second transistor, a third transistor, a fifth transistor and a light emitting element, wherein the first electrode of the first transistor and the first electrode of the second transistor are used to receive a power supply signal, the second electrode of the first transistor is connected to the light emitting element, the second electrode of the second transistor is connected to the gate of the first transistor, the first electrode of the fifth transistor is connected to the gate of the second transistor, the second electrode of the fifth transistor is connected to the second electrode of the second transistor, the gate of the fifth transistor is used to receive a second compensation and reset control signal, the second electrode of the third transistor is connected to the gate of the first transistor and the second electrode of the fifth transistor, the first electrode of the third transistor is used to receive a reset signal, and the gate of the third transistor is used to receive a reset control signal; The driving phase of the pixel circuit includes a first resetting phase, a first compensation phase, a first data writing phase, a second resetting phase, a second compensation phase, a second data writing phase and a light emitting phase, wherein: The reset control signal is at a valid level in the first reset stage and the second reset stage, and is at an invalid level in the first compensation stage, the first data writing stage, the second compensation stage, the second data writing stage and the light emitting stage; The second compensation and reset control signal is at a valid level in the first reset stage and the first compensation stage, and the second compensation and reset control signal is at an invalid level in the first data writing stage, the second reset stage, the second compensation stage, the second data writing stage and the light emitting stage.

22. The pixel circuit according to claim 21, further comprising a fourth transistor, a first electrode of the fourth transistor being connected to a gate of the first transistor, a second electrode of the fourth transistor being connected to a second electrode of the first transistor, and a gate of the fourth transistor being used to receive a first compensation control signal, wherein: The first compensation control signal is at a valid level in the second compensation stage and the second data writing stage, and the first compensation control signal is at an invalid level in the first reset stage, the first compensation stage, the first data writing stage, the second reset stage and the light emitting stage.

23. The pixel circuit according to claim 21, further comprising a sixth transistor, a first electrode of the sixth transistor being used to receive a first data signal, a second electrode of the sixth transistor being connected to the first electrode of the first transistor, and a gate of the sixth transistor being used to receive a first data write control signal, wherein: The first data write control signal is at a valid level in the second compensation stage and the second data write stage, and the first data write control signal is at an invalid level in the first reset stage, the first compensation stage, the first data write stage, the second reset stage and the light emitting stage.

24. The pixel circuit according to claim 21, further comprising a seventh transistor, a first electrode of the seventh transistor being used to receive a second data signal, a second electrode of the seventh transistor being connected to a gate of the second transistor, and a gate of the seventh transistor being used to receive a second data write control signal, wherein: The second data write control signal is at a valid level in the first data write phase, and the second data write control signal is at an invalid level in the first reset phase, the first compensation phase, the second reset phase, the second compensation phase, the second data write phase, and the light emitting phase.

25. A pixel circuit, comprising a first transistor, a second transistor, a third transistor, a tenth transistor and a light emitting element; the second electrode of the first transistor is connected to the light emitting element, the second electrode of the second transistor is connected to the gate of the first transistor; the second electrode of the third transistor is connected to the gate of the first transistor and the gate of the second transistor, the gate of the third transistor is used to receive a reset control signal; the second electrode of the tenth transistor is connected to the gate of the first transistor, the gate of the tenth transistor is used to receive a third data write control signal; The driving phase of the pixel circuit includes a first resetting phase, a first compensation phase, a first data writing phase, a second resetting phase, a second compensation phase, a second data writing phase and a light emitting phase, wherein: The reset control signal is at a valid level in the first reset stage and the second reset stage; The third data writing control signal is at a valid level in the second data writing phase.

26. The pixel circuit according to claim 25, further comprising an eleventh transistor, a first electrode of the eleventh transistor being connected to the gate of the second transistor, a second electrode of the eleventh transistor being connected to the second electrode of the second transistor and the second electrode of the third transistor, and a gate of the eleventh transistor being used to receive a second compensation and reset control signal, wherein: The second compensation and reset control signal and the reset control signal have the same level state in the first reset stage, the second compensation stage, the second data writing stage and the light emitting stage.

27. The pixel circuit according to claim 26, further comprising a twelfth transistor, a first electrode of the twelfth transistor being connected to the first electrode of the second transistor, and a gate of the twelfth transistor being used to receive a fourth data writing control signal, wherein: The fourth data writing control signal and the second compensation and reset control signal have different level states in the first reset phase; The level states of the fourth data writing control signal and the reset control signal in the first reset phase, the first compensation phase, the first data writing phase and the second reset phase are different.

28. The pixel circuit according to claim 25, wherein: In the second data writing phase, the starting time of the effective level of the first data signal lags behind the starting time of the effective level of the third data writing control signal by a first preset time; In the light emitting stage, the end time of the effective level of the first data signal lags behind the end time of the effective level of the third data writing control signal by a second preset time.

29. The pixel circuit according to claim 25, further comprising a fourth capacitor, a first end of the fourth capacitor being connected to the gate of the second transistor, a second end of the fourth capacitor being used to receive a light emission duration control signal, and the fourth capacitor being used to couple the light emission duration control signal to the gate of the second transistor; The light-emitting duration control signal is at an invalid level in the first reset phase, and the light-emitting duration control signal transitions from the invalid level to the valid level in the light-emitting phase, wherein: In the first resetting stage, a starting time of the inactive level of the light-emitting duration control signal lags behind a starting time of the active level of the reset control signal by a third preset time.

30. A display device comprising a data driving circuit, a scanning driving circuit, a data line, a scanning line, and the pixel circuit according to any one of claims 1 to 29.

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