Layout generation method, device and equipment for chip wire winding scheme test and medium

Abstract

The application provides a layout generation method, device and equipment for chip winding scheme test and a medium. The method comprises the following steps: obtaining a winding area in a chip design process, a total number of winding schemes to be tested and a test area width; if the number of winding areas is one, a center fold line of the winding area is determined, a region expansion process is performed on the center fold line on an initial test layout based on the number of a single group of winding schemes to be tested accommodated by the test area and the test area width, and an initial test area is generated; a plurality of identical initial test areas are generated by performing a replication process and a translation process on the initial test area on the initial test layout based on the total number; and a target test layout is integrated based on the plurality of identical initial test areas on the initial test layout. Through the center line expansion and region translation replication mode, a plurality of winding schemes can be tested simultaneously in the same test layout, thereby significantly improving the test efficiency and resource utilization.

Description

Technical Field

[0001] This application relates to the field of analog chip technology, and in particular to a layout generation method, apparatus, equipment and medium for testing chip wiring schemes. Background Technology

[0002] In chip design, it's necessary to connect and wind several known pins within a defined area. The goal of the winding algorithm is to minimize circuit delay and save area while meeting certain physical constraints. Currently, to test different winding schemes, a separate virtual chip layout is generated for each scheme, but this approach is time-consuming and labor-intensive, requiring a new layout for each scheme. Furthermore, generating layouts multiple times consumes significant computational resources. Summary of the Invention

[0003] In view of this, the purpose of this application is to provide a layout generation method, apparatus, equipment and medium for chip winding scheme testing. By using centerline expansion and region translation and replication, multiple winding schemes can be tested simultaneously in the same test layout, thereby significantly improving testing efficiency and resource utilization.

[0004] This application provides a layout generation method for chip winding scheme testing, the layout generation method including:

[0005] Obtain the winding area in the chip design process, the total number of winding schemes to be tested, and the width of the test area corresponding to the winding scheme to be tested;

[0006] If the number of the winding regions is one, the center broken line of the winding region is determined. Based on the number of single-group winding schemes to be tested that can be accommodated in the test region and the width of the test region, the center broken line is expanded on the initial test layout to generate the initial test region.

[0007] Based on the total number, the initial test area is copied and translated on the initial test layout to generate multiple identical initial test areas. Based on the multiple identical initial test areas on the initial test layout, a target test layout is integrated so that each winding scheme to be tested can be simultaneously tested on the target test layout.

[0008] In one possible implementation, determining the center line of the winding region, and expanding the center line on the initial test layout based on the number of single-group winding schemes accommodated by the test region and the width of the test region to generate an initial test region, includes:

[0009] The central polyline is segmented based on its line segment points to determine multiple line segments;

[0010] The width of the rectangle is determined by multiplying the number of single-group winding schemes to be tested within the test area by the width of the test area.

[0011] Based on the width of the rectangle, each line segment is expanded to generate a rectangular test area corresponding to each line segment. All rectangular test areas corresponding to all line segments are sequentially spliced ​​together to form an initial test area. The initial test area is then divided to generate sub-test areas for testing individual winding schemes to be tested.

[0012] In one possible implementation, the step of dividing the initial test area to generate sub-test areas for testing individual winding schemes under test includes:

[0013] Based on the width of the test area and the length of the initial test area, the initial test area is divided horizontally and vertically to determine multiple horizontal rectangular test areas and multiple vertical rectangular test areas.

[0014] The multiple horizontal rectangular test areas and the multiple vertical rectangular test areas are combined based on the central polygonal line to determine multiple sub-test areas in the initial test area; wherein each sub-test area corresponds to a winding scheme to be tested.

[0015] In one possible implementation, the step of copying and translating the initial test regions on the initial test layout based on the total number to generate multiple identical initial test regions includes:

[0016] Based on the total number and the number of single-group winding schemes to be tested that can be accommodated in the test area, the number of the initial test areas is determined.

[0017] Subtract the number of initial test areas from the target value to determine the number of copies;

[0018] Based on the number of copies and the width of the initial test area, the initial test area is copied and translated in the translation direction to generate multiple identical initial test areas, so that each initial test area can independently accommodate a single set of winding schemes to be tested.

[0019] In one possible implementation, after sequentially piecing together the rectangular test areas corresponding to all line segments to form the initial test area, the layout generation method further includes:

[0020] Based on a preset boundary width, rule-checking boundaries are added to both sides of the initial test area.

[0021] In one possible implementation, after obtaining the winding regions in the chip design process, the total number of winding schemes to be tested, and the width of the test region corresponding to the winding scheme to be tested, the layout generation method further includes:

[0022] Receive at least two center lines of the winding regions, and generate an initial test region based on each center line that can accommodate multiple winding schemes to be tested;

[0023] On the initial test layout, multiple initial test areas corresponding to each of the central broken lines are integrated into the target test layout.

[0024] In one possible implementation, the number of single-group winding schemes to be tested that can be accommodated in the test area is determined by the following steps:

[0025] The complexity index of each winding scheme under test is determined based on the physical characteristics of each winding scheme under test; wherein, the physical characteristics include one or more of the following: wire length, number of inflection points, number of intersection points, and wiring density;

[0026] Based on the complexity index, the resource usage information required for each of the winding schemes to be tested in the test area is determined;

[0027] The number of test winding schemes that can be supported in each test area is dynamically adjusted based on the resource occupancy information.

[0028] This application embodiment also provides a layout generation apparatus for testing chip winding schemes, the layout generation apparatus comprising:

[0029] The acquisition module is used to acquire the winding area, the total number of winding schemes to be tested, and the width of the test area corresponding to the winding scheme to be tested during the chip design process.

[0030] The region expansion module is used to determine the center line of the winding region if the number of winding regions is one, and to perform region expansion processing on the center line on the initial test layout based on the number of single-group winding schemes to be tested accommodated by the test region and the width of the test region, so as to generate the initial test region.

[0031] The copy and translation module is used to copy and translate the initial test area on the initial test layout based on the total number to generate multiple identical initial test areas. Based on the multiple identical initial test areas on the initial test layout, a target test layout is integrated to enable simultaneous winding tests on each winding scheme to be tested on the target test layout.

[0032] This application also provides an electronic device, including: a processor, a memory, and a bus. The memory stores machine-readable instructions executable by the processor. When the electronic device is running, the processor communicates with the memory via the bus. When the machine-readable instructions are executed by the processor, the steps of the layout generation method for chip winding scheme testing as described above are performed.

[0033] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, performs the steps of the xx method described above.

[0034] This application provides a layout generation method, apparatus, device, and medium for testing chip wiring schemes. The layout generation method includes: acquiring wiring regions in the chip design process, the total number of wiring schemes to be tested, and the width of the test region corresponding to each wiring scheme; if the number of wiring regions is one, determining the center line of the wiring region; expanding the center line on an initial test layout based on the number of wiring schemes to be tested in a single group and the width of the test region to generate an initial test region; copying and translating the initial test region on the initial test layout based on the total number to generate multiple identical initial test regions; and integrating the multiple identical initial test regions on the initial test layout to form a target test layout, so that each wiring scheme to be tested can be simultaneously tested on the target test layout. By using center line expansion and region translation and copying, multiple wiring schemes can be tested simultaneously on the same test layout, thereby significantly improving testing efficiency and resource utilization.

[0035] To make the above-mentioned objectives, features and advantages of this application more apparent and understandable, preferred embodiments are described below in detail with reference to the accompanying drawings. Attached Figure Description

[0036] To more clearly illustrate the technical solutions of the embodiments of this application, the accompanying drawings used in the embodiments will be briefly introduced below. It should be understood that the following drawings only show some embodiments of this application and should not be regarded as a limitation of the scope. For those skilled in the art, other related drawings can be obtained based on these drawings without creative effort.

[0037] Figure 1 A flowchart illustrating a layout generation method for chip winding scheme testing provided in an embodiment of this application;

[0038] Figure 2 This is a schematic diagram illustrating the copying and translation of the initial test area as provided in an embodiment of this application;

[0039] Figure 3 This is one of the structural schematic diagrams of a layout generation apparatus for testing a chip winding scheme provided in an embodiment of this application;

[0040] Figure 4 A second schematic diagram of a layout generation apparatus for testing a chip winding scheme provided in an embodiment of this application;

[0041] Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Detailed Implementation

[0042] To make the objectives, technical solutions, and advantages of the embodiments of this application clearer, the technical solutions of the embodiments of this application will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this application, and not all embodiments. The components of the embodiments of this application described and shown in the accompanying drawings can generally be arranged and designed in various different configurations. Therefore, the following detailed description of the embodiments of this application provided in the accompanying drawings is not intended to limit the scope of the claimed application, but merely represents selected embodiments of this application. Based on the embodiments of this application, every other embodiment obtained by those skilled in the art without inventive effort falls within the scope of protection of this application.

[0043] First, the applicable scenarios for this application will be introduced. This application can be applied to the field of analog chip technology.

[0044] Research has revealed that chip design involves connecting and winding several known pins within a defined area. The goal of the winding algorithm is to minimize circuit delay and conserve area while meeting certain physical constraints. Currently, different winding schemes are tested by generating a separate virtual chip layout for each scheme. However, this approach is time-consuming and labor-intensive, requiring a new layout for each scheme and consuming significant computational resources.

[0045] Based on this, this application provides a layout generation method for testing chip winding schemes. By expanding the center line and copying the region, multiple winding schemes can be tested simultaneously in the same test layout, thereby significantly improving testing efficiency and resource utilization.

[0046] Please see Figure 1 , Figure 1 This is a flowchart illustrating a layout generation method for testing a chip winding scheme, provided in an embodiment of this application. Figure 1 As shown in the embodiments of this application, the layout generation method includes:

[0047] S101: Obtain the winding area in the chip design process, the total number of winding schemes to be tested, and the width of the test area corresponding to the winding scheme to be tested.

[0048] It should be noted that the winding region refers to the area corresponding to the circuit connection route between two circuit modules during chip design. The total number of winding schemes to be tested is the total number of winding schemes to be tested between these two circuit modules, and the width of the test area corresponding to each winding scheme to be tested needs to be set.

[0049] S102: If the number of winding regions is one, determine the center broken line of the winding region, and perform region expansion processing on the center broken line on the initial test layout based on the number of single-group winding schemes to be tested accommodated by the test area and the width of the test area to generate the initial test area.

[0050] In this step, if there is only one winding area to be tested, the center line of the winding area is determined. Based on the number of single winding schemes to be tested that the test area can accommodate and the width of the test area, the center line is expanded on the initial test layout to generate the initial test area.

[0051] Specifically, the coordinates of the line segment points of the center broken line of the winding region are stored.

[0052] Here, the number of single-group test winding schemes accommodated in the test area is the same as the number of a single-group test winding schemes accommodated in the generated initial test area.

[0053] In one possible implementation, determining the center line of the winding region, and expanding the center line on the initial test layout based on the number of single-group winding schemes accommodated by the test region and the width of the test region to generate an initial test region, includes:

[0054] A: Based on the line segment points of the central polyline, the central polyline is segmented to determine multiple line segments.

[0055] Here, the central broken line is segmented based on the line segment points to determine multiple line segments.

[0056] B: Multiply the number of single-group winding schemes to be tested within the test area by the width of the test area to determine the width of the rectangle.

[0057] Here, the width of the rectangle is determined by multiplying the number of single-group winding schemes to be tested within the test area by the width of the test area.

[0058] Wherein, the width of the rectangle = the width required for each group of winding schemes × the number of single-group winding schemes to be tested that can be accommodated in the current test area. For example: if the test area width required for each group of winding schemes is W, and the user sets each area to test 3 winding schemes, then the width of each extended rectangle will be 3W.

[0059] C: Based on the width of the rectangle, perform region expansion processing on each line segment to generate a rectangular test area corresponding to each line segment. Then, sequentially splice the rectangular test areas corresponding to all line segments to form an initial test area. Finally, divide the initial test area to generate sub-test areas for testing individual winding schemes to be tested.

[0060] Here, each line segment is expanded according to the width of the rectangle to generate a rectangular test area corresponding to each line segment. The rectangular test areas corresponding to all line segments are sequentially spliced ​​together to form an initial test area. The initial test area is then divided to generate sub-test areas for testing individual winding schemes to be tested.

[0061] It should be noted that region expansion refers to: based on the center line of the original winding region, expanding it into a rectangular region by segmentation to construct an initial test area capable of accommodating multiple samples. Specifically, the original center line (composed of a series of points) is divided into segments, and each segment is expanded into a rectangle. The length of the rectangle is the length of the center line segment, and the width is the width required for each winding scheme multiplied by the number of samples it can accommodate.

[0062] Here, by expanding the area, the area that could originally only be used to test a single winding scheme is structurally divided into multiple sub-test areas. Each sub-test area can independently support a winding scheme, thereby improving the utilization rate of the layout space.

[0063] In one possible implementation, the step of dividing the initial test area to generate sub-test areas for testing individual winding schemes under test includes:

[0064] a: Based on the width of the test area and the length of the initial test area, the initial test area is divided horizontally and vertically to determine multiple horizontal rectangular test areas and multiple vertical rectangular test areas.

[0065] Here, the initial test area is divided horizontally according to the width of the test area to obtain multiple horizontal rectangular test areas, and the initial test area is divided vertically according to the length of the initial test area to determine multiple vertical rectangular test areas.

[0066] b: Based on the central polyline, the multiple horizontal rectangular test areas and the multiple vertical rectangular test areas are combined to determine multiple sub-test areas in the initial test area; wherein, each sub-test area corresponds to a winding scheme to be tested.

[0067] Here, multiple horizontal rectangular test areas and multiple vertical rectangular test areas are combined according to the direction of the central broken line to determine multiple sub-test areas in the initial test area.

[0068] Each of the sub-test areas corresponds to a winding scheme to be tested.

[0069] In one possible implementation, after sequentially splicing together the rectangular test areas corresponding to all line segments to form an initial test area, the layout generation method further includes: adding rule-checked boundaries to both sides of the initial test area based on a preset boundary width.

[0070] In actual business needs, there is often a need to eliminate boundary effects, which requires adding boundary regions to the boundaries of each segment of the area. This can be achieved by doubling the width of the boundary.

[0071] In one possible implementation, the number of single-group winding schemes to be tested that can be accommodated in the test area is determined by the following steps:

[0072] i: Determine the complexity index of each winding scheme under test based on the physical characteristics of each winding scheme under test; wherein, the physical characteristics include one or more of the following: wire length, number of inflection points, number of intersection points, and wiring density.

[0073] ii: Determine the resource usage information required for each of the winding schemes to be tested in the test area based on the complexity index.

[0074] Here, multiple complexity indicators can be merged into resource occupancy information using methods such as weighted linear combination or nonlinear regression models. The formula for weighted linear combination is as follows: Resource occupancy information = ,in: L For line length, B For the number of inflection points, C For the number of intersections, D For wiring density, w1, w2, w3 as well as w4 These are the weighting coefficients for each feature, which are configured by the user.

[0075] iii: Dynamically adjust the number of test winding schemes that can be supported in each test area based on the resource occupancy information.

[0076] Here, the number of test winding schemes that can be supported in each test area is dynamically adjusted based on resource usage information.

[0077] S103: Based on the total number, the initial test area is copied and translated on the initial test layout to generate multiple identical initial test areas. Based on the multiple identical initial test areas on the initial test layout, a target test layout is integrated so that each winding scheme to be tested can be tested simultaneously on the target test layout.

[0078] In this step, multiple identical initial test areas are generated by copying and translating the initial test areas on the initial test layout according to the total number. The target test layout is then formed by integrating the multiple identical initial test areas on the initial test layout, so that each winding scheme to be tested can be tested simultaneously on the target test layout.

[0079] In one possible implementation, the step of copying and translating the initial test regions on the initial test layout based on the total number to generate multiple identical initial test regions includes:

[0080] (1) The number of initial test areas is determined based on the total number and the number of single-group winding schemes to be tested contained in the test area.

[0081] Here, the number of initial test areas is determined based on the total number and the number of single-group winding schemes to be tested that can be accommodated in the test area.

[0082] The number of single-group winding schemes to be tested in each test area may be the same or different, and the number of single-group winding schemes to be tested in each test area is determined according to the complexity of the winding schemes to be tested.

[0083] Here, if the number of single-group winding schemes to be tested accommodated in each test area is the same, the total number is divided by the number of single-group winding schemes to be tested accommodated in each test area to determine the initial number of test areas. If the number of single-group winding schemes to be tested accommodated in each test area is different, the initial number of test areas is determined according to the actual situation.

[0084] (2): Subtract the number of initial test areas from the target value to determine the number of copies.

[0085] The target value is 1, which represents an initial test area generated at this time.

[0086] (3): Based on the number of copies and the width of the initial test area, the initial test area is copied and translated in the translation direction to generate multiple identical initial test areas, so that each initial test area can independently accommodate a single set of winding schemes to be tested.

[0087] Here, the initial test area is copied and translated in the translation direction according to the number of copies and the width of the initial test area, generating multiple identical initial test areas, so that each initial test area can independently accommodate a single set of winding schemes to be tested.

[0088] It should be noted that the translation direction is predetermined. If the direction of the central broken line is to the right and upward, then translating in the same direction to the upper left will not result in overlapping areas.

[0089] Here, to further increase the number of testable winding schemes on the test layout, the initial test area is copied and shifted to generate multiple identical initial test areas, which can multiply the load capacity of the winding schemes. The shift distance is equal to the width of each segment of the initial test area, ensuring that the shifted area aligns with the original area.

[0090] For further details, please refer to Figure 2 , Figure 2This is a schematic diagram illustrating the copying and translation of the initial test area as provided in an embodiment of this application. Figure 2 As shown, the initial test area includes three sub-test areas. The translation direction is to the upper left. The initial test area is copied and translated three times, resulting in a total of four initial test areas. These four initial test areas can accommodate 12 winding schemes.

[0091] In one possible implementation, after obtaining the winding regions in the chip design process, the total number of winding schemes to be tested, and the width of the test region corresponding to the winding scheme to be tested, the layout generation method further includes:

[0092] Receive at least two center lines of the winding regions, and generate an initial test region based on each center line, each center line accommodating multiple winding schemes to be tested; integrate the multiple initial test regions corresponding to each center line on the initial test layout into the target test layout.

[0093] Here, for at least two center lines of the winding regions, initial test areas are generated based on each center line, each capable of accommodating multiple winding schemes to be tested. These initial test areas are then integrated into a target test layout on the initial test layout. This allows for the simultaneous testing of multiple winding schemes corresponding to different winding regions on the same target test layout, improving testing efficiency.

[0094] It should be noted that if the size of the target test layout cannot accommodate multiple initial test areas, the number of initial test areas generated in the target test layout will be reduced.

[0095] This application enables the testing of winding scheme samples to be separated from the original layout through a series of processing of the original winding area, making the testing process easier to control; by shifting the initial area as a whole, the number of samples that a test layout can accommodate is greatly increased, which greatly improves the efficiency of the testing process.

[0096] This application provides a layout generation method for testing chip wiring schemes. The layout generation method includes: obtaining the wiring regions in the chip design process, the total number of wiring schemes to be tested, and the width of the test region corresponding to each wiring scheme to be tested; if the number of wiring regions is one, determining the center line of the wiring region; expanding the center line on an initial test layout based on the number of wiring schemes to be tested in a single group and the width of the test region to generate an initial test region; copying and translating the initial test region on the initial test layout based on the total number to generate multiple identical initial test regions; integrating the multiple identical initial test regions on the initial test layout to form a target test layout, so that each wiring scheme to be tested can be tested simultaneously on the target test layout. By expanding the center line and translating and copying the region, multiple wiring schemes can be tested simultaneously on the same test layout, thereby significantly improving testing efficiency and resource utilization.

[0097] Please see Figure 3 , Figure 4 , Figure 3 This is one of the structural schematic diagrams of a layout generation apparatus for testing a chip winding scheme provided in an embodiment of this application; Figure 4 This is a second schematic diagram of a layout generation apparatus for testing a chip winding scheme, provided in an embodiment of this application. Figure 3 As shown, the layout generation apparatus 300 for testing the chip winding scheme includes:

[0098] The acquisition module 310 is used to acquire the winding area, the total number of winding schemes to be tested, and the width of the test area corresponding to the winding scheme to be tested during the chip design process.

[0099] The region expansion module 320 is used to determine the center line of the winding region if the number of the winding regions is one, and to perform region expansion processing on the center line on the initial test layout based on the number of single-group winding schemes to be tested accommodated by the test region and the width of the test region to generate the initial test region.

[0100] The copy and translation module 330 is used to copy and translate the initial test area on the initial test layout based on the total number to generate multiple identical initial test areas, and integrate the multiple identical initial test areas on the initial test layout to form a target test layout, so that each winding scheme to be tested can be simultaneously tested on the target test layout.

[0101] Furthermore, the region expansion module 320 is used to determine the center line of the winding region, and based on the number of single-group winding schemes to be tested accommodated by the test region and the width of the test region, perform region expansion processing on the center line on the initial test layout to generate the initial test region:

[0102] The central polyline is segmented based on its line segment points to determine multiple line segments;

[0103] The width of the rectangle is determined by multiplying the number of single-group winding schemes to be tested within the test area by the width of the test area.

[0104] Based on the width of the rectangle, each line segment is expanded to generate a rectangular test area corresponding to each line segment. All rectangular test areas corresponding to all line segments are sequentially spliced ​​together to form an initial test area. The initial test area is then divided to generate sub-test areas for testing individual winding schemes to be tested.

[0105] Furthermore, the region expansion module 320 is used to divide the initial test region to generate sub-test regions for testing individual winding schemes under test:

[0106] Based on the width of the test area and the length of the initial test area, the initial test area is divided horizontally and vertically to determine multiple horizontal rectangular test areas and multiple vertical rectangular test areas.

[0107] The multiple horizontal rectangular test areas and the multiple vertical rectangular test areas are combined based on the central polygonal line to determine multiple sub-test areas in the initial test area; wherein each sub-test area corresponds to a winding scheme to be tested.

[0108] Furthermore, the copy and translation module 330 is used to perform copying and translation processing on the initial test area based on the total number to generate multiple identical initial test areas:

[0109] Based on the total number and the number of single-group winding schemes to be tested that can be accommodated in the test area, the number of the initial test areas is determined.

[0110] Subtract the number of initial test areas from the target value to determine the number of copies;

[0111] Based on the number of copies and the width of the initial test area, the initial test area is copied and translated in the translation direction to generate multiple identical initial test areas, so that each initial test area can independently accommodate a single set of winding schemes to be tested.

[0112] Furthermore, the area extension module 320 is also used for:

[0113] Based on a preset boundary width, rule-checking boundaries are added to both sides of the initial test area.

[0114] Furthermore, the region expansion module 320 is also used to receive at least two center lines of the winding region, and generate an initial test region based on each of the center lines, each of which can accommodate multiple winding schemes to be tested.

[0115] The copy and translation module 330 is also used to integrate multiple initial test areas corresponding to each of the central polylines on the initial test layout into the target test layout.

[0116] Furthermore, such as Figure 4 As shown, the layout generation device 300 for chip winding scheme testing also includes a winding scheme number dynamic adjustment module 340, which is used for:

[0117] The complexity index of each winding scheme under test is determined based on the physical characteristics of each winding scheme under test; wherein, the physical characteristics include one or more of the following: wire length, number of inflection points, number of intersection points, and wiring density;

[0118] Based on the complexity index, the resource usage information required for each of the winding schemes to be tested in the test area is determined;

[0119] The number of test winding schemes that can be supported in each test area is dynamically adjusted based on the resource occupancy information.

[0120] This application provides a layout generation apparatus for testing chip winding schemes. The layout generation apparatus includes: an acquisition module, used to acquire winding regions in the chip design process, the total number of winding schemes to be tested, and the width of the test region corresponding to each winding scheme to be tested; a region expansion module, used to determine the center line of the winding region if the number of winding regions is one, and to perform region expansion processing on the center line on an initial test layout based on the number of single-group winding schemes to be tested accommodated by the test region and the width of the test region to generate an initial test region; and a copy and translation module, used to perform copy and translation processing on the initial test layout based on the total number to generate multiple identical initial test regions, and to integrate the multiple identical initial test regions on the initial test layout to form a target test layout, so that each winding scheme to be tested can be simultaneously tested on the target test layout. By using center line expansion and region translation and copying, multiple winding schemes can be tested simultaneously on the same test layout, thereby significantly improving testing efficiency and resource utilization.

[0121] Please see Figure 5 , Figure 5 This is a schematic diagram of the structure of an electronic device provided in an embodiment of this application. Figure 5 As shown, the electronic device 500 includes a processor 510, a memory 520, and a bus 530.

[0122] The memory 520 stores machine-readable instructions executable by the processor 510. When the electronic device 500 is running, the processor 510 and the memory 520 communicate via the bus 530. When the machine-readable instructions are executed by the processor 510, they can perform the operations described above. Figure 1 The steps of the layout generation method for chip winding scheme testing in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0123] This application also provides a computer-readable storage medium storing a computer program, which, when executed by a processor, can perform the above-described actions. Figure 1 The steps of the layout generation method for chip winding scheme testing in the method embodiment shown are described in detail in the method embodiment, and will not be repeated here.

[0124] Those skilled in the art will understand that, for the sake of convenience and brevity, the specific working processes of the systems, devices, and units described above can be referred to the corresponding processes in the foregoing method embodiments, and will not be repeated here.

[0125] In the several embodiments provided in this application, it should be understood that the disclosed systems, apparatuses, and methods can be implemented in other ways. The apparatus embodiments described above are merely illustrative. For example, the division of units is only a logical functional division, and in actual implementation, there may be other division methods. Furthermore, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Additionally, the shown or discussed mutual couplings, direct couplings, or communication connections may be through some communication interfaces; indirect couplings or communication connections between devices or units may be electrical, mechanical, or other forms.

[0126] The units described as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0127] In addition, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit.

[0128] If the aforementioned functions are implemented as software functional units and sold or used as independent products, they can be stored in a processor-executable, non-volatile, computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or a portion of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes several instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of this application. The aforementioned storage medium includes various media capable of storing program code, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0129] Finally, it should be noted that the above-described embodiments are merely specific implementations of this application, used to illustrate the technical solutions of this application, and not to limit them. The scope of protection of this application is not limited thereto. Although this application has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that any person skilled in the art can still modify or easily conceive of changes to the technical solutions described in the foregoing embodiments, or make equivalent substitutions for some of the technical features, within the scope of the technology disclosed in this application. Such modifications, changes, or substitutions do not cause the essence of the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of this application, and should all be covered within the scope of protection of this application. Therefore, the scope of protection of this application should be determined by the scope of the claims.

Claims

1. A method for layout generation for chip wire-wrapping scheme testing, characterized in that, The layout generation method comprises: Obtaining the number of routing regions in the chip design process, the total number of to-be-tested routing schemes, and the width of the test region corresponding to the to-be-tested routing scheme; If the number of routing regions is one, a center fold line of the routing region is determined, the center fold line is regionally expanded on the initial test layout based on the number of to-be-tested routing schemes in a single group accommodated by the test region and the width of the test region, and an initial test region is generated; Based on the total number, the initial test region is copied and translated on the initial test layout to generate multiple identical initial test regions, and a target test layout is integrated based on the multiple identical initial test regions on the initial test layout, so that each to-be-tested routing scheme is simultaneously tested on the target test layout.

2. The layout generation method of claim 1, wherein, The determination of the center fold line of the routing region, the regionally expanding the center fold line on the initial test layout based on the number of to-be-tested routing schemes in a single group accommodated by the test region and the width of the test region, and the generation of the initial test region, comprise: The center fold line is segmented based on the line segment points of the center fold line, and a plurality of line segments are determined; The number of to-be-tested routing schemes in a single group accommodated by the test region and the width of the test region are multiplied to determine the width of a rectangle; Based on the width of the rectangle, each line segment is regionally expanded to generate a rectangular test region corresponding to each line segment, and all rectangular test regions corresponding to the line segments are sequentially spliced to form an initial test region, and the initial test region is divided to generate a sub-test region for testing a single to-be-tested routing scheme.

3. The layout generation method according to claim 2, wherein The division of the initial test region to generate a sub-test region for testing a single to-be-tested routing scheme comprises: Based on the width of the test region and the length of the initial test region, the initial test region is divided horizontally and vertically to determine a plurality of horizontal rectangular test regions and a plurality of vertical rectangular test regions; Based on the center fold line, the plurality of horizontal rectangular test regions and the plurality of vertical rectangular test regions are regionally combined to determine a plurality of sub-test regions in the initial test region; wherein each sub-test region corresponds to a to-be-tested routing scheme.

4. The method of claim 1, wherein, Based on the total number, the initial test region is copied and translated on the initial test layout to generate multiple identical initial test regions, which comprises: Based on the total number and the number of to-be-tested routing schemes in a single group accommodated by the test region, the number of initial test regions is determined; The number of initial test regions is subtracted from a target value to determine the number of copies; Based on the number of copies and the width of the initial test region, the initial test region is copied and translated in the translation direction to generate multiple identical initial test regions, so that each initial test region independently accommodates a single group of to-be-tested routing schemes.

5. The method of claim 2, wherein, After the rectangular test regions corresponding to all the line segments are sequentially spliced to form an initial test region, the layout generation method further comprises: Adding a regular inspection boundary to both sides of the initial test region based on a preset boundary width.

6. The method of claim 1, wherein, After the number of routing regions in the chip design process, the total number of routing schemes to be tested, and the test region width corresponding to the routing schemes to be tested are obtained, the layout generation method further comprises: Receiving at least two center fold lines of the routing regions, and generating an initial test region that can accommodate a plurality of routing schemes to be tested based on each center fold line; Integrating the plurality of initial test regions corresponding to each center fold line on the initial test layout into the target test layout.

7. The method of claim 1, wherein, The number of routing schemes to be tested in a single group accommodated by the test region is determined by the following steps: Determining the complexity index of each routing scheme to be tested based on the physical characteristics of each routing scheme to be tested; wherein the physical characteristics include one or more of line length, number of inflection points, number of intersection points, and wiring density; According to the complexity index, the resource occupation information required by each routing scheme to be tested in the test region is determined; Based on the resource occupation information, the number of routing schemes to be tested that can be carried in each test region is dynamically adjusted.

8. A layout generation apparatus for testing chip winding schemes, characterized in that, The layout generation device comprises: An acquisition module for acquiring the number of routing regions in the chip design process, the total number of routing schemes to be tested, and the test region width corresponding to the routing schemes to be tested; A region expansion module for determining the center fold line of the routing region if the number of routing regions is one, performing region expansion processing on the center fold line on the initial test layout based on the number of routing schemes to be tested in a single group accommodated by the test region and the test region width, and generating an initial test region; A copy and translation module for performing copy processing and translation processing on the initial test region on the initial test layout based on the total number to generate a plurality of identical initial test regions, and integrating a target test layout based on the plurality of identical initial test regions on the initial test layout, so that each routing scheme to be tested is simultaneously tested for routing on the target test layout.

9. An electronic device, comprising: It comprises: A processor, a memory, and a bus, the memory stores machine readable instructions executable by the processor, when the electronic device is running, the processor and the memory communicate through the bus, and the machine readable instructions are executed by the processor to perform the steps of the chip routing scheme test layout generation method according to any one of claims 1 to 7.

10. A computer-readable storage medium, characterized in that, The computer readable storage medium stores a computer program, which is executed by the processor to perform the steps of the chip routing scheme test layout generation method according to any one of claims 1 to 7.

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