Storage device, access request processing method, storage system and computer equipment

Abstract

The invention discloses a storage device, an access request processing method, a storage system and computer equipment, and belongs to the technical field of storage. The storage device comprises an identification element, a generation element, a processing element and a storage plate which are connected in sequence. The recognition element recognizes access requests sent by a plurality of access sources respectively to obtain a first bit sequence, and when bits in the first bit sequence have a first value, the first value is used for indicating the corresponding access source to request to access the storage plate. The generating element generates a second bit sequence, one bit in the second bit sequence has a second value, and the bit with the second value is used for indicating that the corresponding access source is authorized to access the storage plate. And the processing element processes an access request sent by an access source corresponding to the bit with the second value based on the storage plate. The storage device can avoid storage plate conflicts in the process of processing the access request, does not need to depend on a program, is relatively flexible and has relatively good performance. The storage device is suitable for an AI processor.

Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of storage, and in particular, to a storage device, a method for processing access requests, a storage system, and a computer device. BACKGROUND

[0002] In the technical field of storage, a storage device includes storage banks for storing data. An access source can access a storage bank to read data or write data. If different access sources access the same storage bank in a same clock cycle, a storage bank conflict occurs. Since the storage bank conflict increases the access latency of the storage device, it is necessary to avoid the storage bank conflict.

[0003] In the related art, an allocator is added in the storage device. The allocator can run an allocation program, which is manually written by a programmer. In a same clock cycle, if the allocator receives access requests respectively sent by different access sources, and the access requests all request to access the same storage bank, the allocator determines, according to the allocation program run, which access source can access the storage bank to read data or write data in the clock cycle, that is, determines which access request sent by which access source needs to be processed in the clock cycle.

[0004] However, this approach depends on the allocation program manually written by the programmer, and is relatively limited. Moreover, the allocator needs a relatively long time to run the allocation program, which affects the performance of the storage device. SUMMARY

[0005] Embodiments of the present application provide a storage device, a method for processing access requests, a storage system, and a computer device, which can be used to improve the problem that the storage device provided by the related art needs to depend on an allocation program, is relatively limited, and has poor performance. The technical solution provided by embodiments of the present application includes the following aspects.

[0006] In one aspect, a storage device is provided, which includes, in sequence, an identification element, a generation element, a processing element, and a storage bank.

[0007] The identification element is configured to identify access requests respectively sent by a plurality of access sources, to obtain a first bit sequence, each bit in the first bit sequence corresponding to one of the plurality of access sources, and a bit having a first value being used to indicate that the corresponding access source requests to access the storage bank.

[0008] The generating element is configured to generate a second bit sequence in a case where at least one bit in the first bit sequence has the first value, each bit in the second bit sequence corresponds to one of the plurality of access sources, and one bit in the second bit sequence has a second value, the bit having the second value is used to indicate that the corresponding access source is authorized to access the storage board.

[0009] The processing element is configured to process an access request sent by the access source corresponding to the bit having the second value based on the storage board.

[0010] In another aspect, an embodiment of the present application provides a method for processing an access request, the method is applied to a storage device, the storage device comprises an identifying element, a generating element, a processing element and a storage board connected in sequence, and the method comprises the following steps.

[0011] The identifying element is configured to identify access requests respectively sent by a plurality of access sources to obtain a first bit sequence, each bit in the first bit sequence corresponds to one of the plurality of access sources, and a bit having a first value is used to indicate that the corresponding access source requests to access the storage board.

[0012] The generating element is configured to generate a second bit sequence in a case where at least one bit in the first bit sequence has the first value, each bit in the second bit sequence corresponds to one of the plurality of access sources, and one bit in the second bit sequence has a second value, the bit having the second value is used to indicate that the corresponding access source is authorized to access the storage board.

[0013] The processing element is configured to process an access request sent by the access source corresponding to the bit having the second value based on the storage board.

[0014] In another aspect, an embodiment of the present application provides a storage system, the storage system comprises a plurality of storage devices provided by the embodiments of the present application.

[0015] In another aspect, an embodiment of the present application provides a processor, the processor comprises a plurality of access sources and at least one storage device provided by the embodiments of the present application. For example, the access source is a processing core.

[0016] In another aspect, an embodiment of the present application further provides a computer device, the computer device comprises a memory and a processor, wherein the memory comprises at least one storage device provided by the embodiments of the present application, or the processor is a processor provided by the embodiments of the present application.

[0017] The technical solutions provided by the embodiments of the present application at least have the following beneficial effects:

[0018] The storage device provided by the embodiment of the present application comprises an identification element, a generation element, a processing element and a storage block connected in sequence. After a plurality of access sources respectively send access requests, the identification of the access requests by the identification element can obtain a first bit sequence. According to each bit in the first bit sequence, whether the corresponding access source requests to access the current storage block can be determined. Then, the generation element can generate a second bit sequence according to the first bit sequence, so that which access source is authorized to access the current storage block can be determined according to each bit in the second bit sequence, and in the case that at least one access source in the plurality of access sources requests to access the current storage block, an access source authorized to access the current storage block is determined. Then, the processing element processes the access request based on the storage block, and the processed access request is sent by the access source authorized to access the current storage block, so that the access of the storage block by the access source authorized to access the current storage block is realized. Thus, the different access sources are prevented from simultaneously accessing the current storage block, so that the storage block conflict is avoided.

[0019] The process can be realized based on each element comprised by the storage device, each element is hardware, for example, a circuit, and does not need to rely on the allocation program manually written by the programmer to realize, which not only reduces the burden of the programmer and is more flexible, but also is not affected by the error of the programmer, and ensures the correctness of the storage device in processing the access request. In addition, the storage device only needs a short time to complete the processing of the access request sent by the access source, the access delay is short, the performance of the storage device is improved, and the access request can be quickly processed based on the storage device. BRIEF DESCRIPTION OF DRAWINGS

[0020] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings needed in the embodiment description will be briefly introduced. Obviously, the drawings in the following description are only some embodiments of the present application, and other drawings can be obtained by those skilled in the art without creative labor.

[0021] Figure 1 is a structure schematic diagram of a storage device in a related technology provided by the embodiment of the present application;

[0022] Figure 2 is a structure schematic diagram of a storage device provided by the embodiment of the present application;

[0023] Figure 3 is a structure schematic diagram of another storage device provided by the embodiment of the present application;

[0024] Figure 4 is a structure schematic diagram of another storage device provided by the embodiment of the present application;

[0025] Figure 5 is a structural schematic diagram of a storage board provided by an embodiment of the application;

[0026] Figure 6 is a structural schematic diagram of another storage board provided by an embodiment of the application;

[0027] Figure 7 is a structural schematic diagram of still another storage device provided by an embodiment of the application;

[0028] Figure 8 is a structural schematic diagram of still another storage device provided by an embodiment of the application;

[0029] Figure 9 is a schematic diagram of a bit sequence provided by an embodiment of the application;

[0030] Figure 10 is a structural schematic diagram of still another storage device provided by an embodiment of the application;

[0031] Figure 11 is a structural schematic diagram of still another storage device provided by an embodiment of the application;

[0032] Figure 12 is a structural schematic diagram of still another storage device provided by an embodiment of the application;

[0033] Figure 13 is a structural schematic diagram of still another storage device provided by an embodiment of the application;

[0034] Figure 14 is a schematic diagram of a plurality of clock cycles provided by an embodiment of the application;

[0035] Figure 15 is a flowchart of a method for processing an access request provided by an embodiment of the application;

[0036] Figure 16 is a structural schematic diagram of a computer device provided by an embodiment of the application.

[0037] Reference signs:

[0038] 1-identification element, 2-generation element, 21-first moving sub-element, 22-generation sub-element, 23-second moving sub-element, 3-processing element, 4-storage board, 5-register element, 6-determination element, 61-third moving sub-element, 62-conversion sub-element. DETAILED DESCRIPTION

[0039] To make the purpose, technical solutions and advantages of the application clearer, the embodiments of the application will be further described in detail below with reference to the drawings.

[0040] In a storage device, there are storage tiles for storing data. An access source can access a storage tile to implement at least one data processing process in data reading or data writing. If different access sources access the same storage tile in the same clock cycle, a storage tile conflict occurs.

[0041] As shown in Figure 1 To avoid the storage tile conflict, in the related art, a distributor is added in the storage device. Multiple access sources (for example, access source 0, access source 1, and access source 2 as shown in Figure 1 ) are connected to the distributor, and the distributor is also connected to multiple storage tiles (for example, storage tile 0, storage tile 1, and storage tile 2 as shown in Figure 1 ). The distributor runs a distribution program manually written by a programmer. In the same clock cycle, if the distributor receives access requests respectively sent by different access sources, and the access requests all request to access the same storage tile, the distributor determines which access source can access the storage tile to process data in the clock cycle according to the distribution program it runs, that is, determines which access request sent by an access source needs to be processed in the clock cycle.

[0042] However, this approach relies on the distribution program manually written by the programmer, which is not only relatively limited, but also places a heavy burden on the programmer to write the distribution program, and the more the number of access sources, the heavier the burden on the programmer. In addition, the distributor needs a long time to run the distribution program, which results in a long time for the access requests sent by the access sources to be processed, that is, a long access latency of the storage device, thereby affecting the performance of the storage device. In addition, the distribution program manually written by the programmer may have errors, and the distributor running the erroneous distribution program may still cause a storage tile conflict, with a high error rate. For example, when a storage tile conflict occurs, two different access sources access the same storage tile in the same clock cycle, and one access request sent by an access source needs to be processed in the clock cycle, and another access request sent by another access source needs to be processed in the next clock cycle, which doubles the access latency of the storage device and reduces the performance of the storage device by half.

[0043] Therefore, it is necessary to provide a storage device that can avoid storage tile conflicts without relying on a distribution program and has strong performance. Such a storage device is suitable for various scenarios, including but not limited to artificial intelligence (AI) scenarios. In the following, the AI and the terms involved in the embodiments of the present application are introduced.

[0044] AI is the theory, method, technology and application system of simulating, extending and expanding human intelligence by using digital computers or machines controlled by digital computers to perceive the environment, acquire knowledge and use knowledge to obtain the best results. In other words, artificial intelligence is a comprehensive technology of computer science, which attempts to understand the essence of intelligence and produce a new intelligent machine that can react in a similar way to human intelligence. Artificial intelligence is to study the design principles and implementation methods of various intelligent machines, so that machines have the functions of perception, reasoning and decision-making.

[0045] Artificial intelligence technology is a comprehensive discipline, involving a wide range of fields, both hardware and software technologies. Artificial intelligence basic technologies generally include sensors, special artificial intelligence chips, cloud computing, distributed storage, big data processing technology, pre-training model technology, operation / interaction system, mechatronics, etc. Among them, the pre-training model is also called large model or basic model, which can be widely applied to downstream tasks in various directions of artificial intelligence after fine tuning. Artificial intelligence software technology mainly includes computer vision technology, speech processing technology, natural language processing technology and machine learning / deep learning, etc.

[0046] Computer vision (CV) is a science that studies how to make machines "see". Further, it refers to using cameras and computers to replace human eyes to identify and measure targets, and further to do image processing, so that the computer processing becomes more suitable for human eye observation or image transmission to instrument detection. As a scientific discipline, computer vision researches related theories and technologies, trying to establish an artificial intelligence system that can obtain information from images or multidimensional data. Large model technology brings important changes to the development of computer vision technology. Shifted window transformer (swin-transformer), vision transformer (ViT), vision mixture of experts (V-MOE) model, masked auto-encoders (MAE) and other pre-training models in the field of vision can be quickly and widely applied to downstream specific tasks after fine tuning. Computer vision technology usually includes image processing, image recognition, image semantic understanding, image retrieval, optical character recognition (OCR), video processing, video semantic understanding, video content / behavior recognition, three-dimensional (3D) object reconstruction, 3D technology, virtual reality, augmented reality, simultaneous localization and mapping, etc. It also includes common face recognition, fingerprint recognition and other biometric identification technologies.

[0047] Key technologies of speech technology include automatic speech recognition (ASR) technology, text to speech (TTS) technology, and voiceprint recognition technology. Enabling computers to hear, see, speak, and feel is the future direction of human-computer interaction, and voice is one of the promising human-computer interaction methods in the future. Large model technology brings changes to the development of speech technology. Pre-training models such as WavLM (a model name) and unified speech (UniSpeech) using transformer architecture have strong generalization and universality, and can perform various speech processing tasks excellently.

[0048] Nature Language processing (NLP) is an important direction in the field of computer science and artificial intelligence. It studies various theories and methods that can enable effective communication between people and computers using natural language. Natural language processing involves natural language, i.e., the language used in daily life, and is closely related to linguistics, involving computer science and mathematics. Pre-training models, an important technology in the field of artificial intelligence model training, are developed from large language models in the NLP field. After fine-tuning, large language models can be widely applied to downstream tasks. Natural language processing technology usually includes text processing, semantic understanding, machine translation, robot question answering, knowledge graph, and other technologies.

[0049] Machine learning (ML) is a multi-disciplinary subject that involves probability theory, statistics, approximation theory, convex analysis, algorithm complexity theory, and other disciplines. It is a specialized study of how computers simulate or implement human learning behavior to acquire new knowledge or skills, reorganize existing knowledge structures, and continuously improve their performance. Machine learning is the core of artificial intelligence and the fundamental approach to enabling computers to have intelligence, and its applications are widespread in various fields of artificial intelligence. Machine learning and deep learning usually include artificial neural networks, belief networks, reinforcement learning, transfer learning, inductive learning, and rule-based learning. Pre-training models are the latest development in deep learning, integrating the above technologies.

[0050] Autonomous driving technology refers to the technology that enables vehicles to drive autonomously without human intervention. It typically includes technologies such as high-precision maps, environmental perception, computer vision, behavior decision-making, path planning, and motion control. Autonomous driving includes single-vehicle intelligence, vehicle-road coordination, and networked cloud control, among other development paths. Autonomous driving technology has broad application prospects, and while it is currently used in areas such as logistics, public transportation, and taxi services, it will continue to develop in the future.

[0051] Distributed training refers to splitting and sharing the workload of training a model among multiple microprocessors. Large models have a large number of parameters and require large amounts of training data, which exceeds the capacity of a single machine. Therefore, distributed parallel processing is needed to speed up training. Parallel mechanisms include data parallelism (DP), model parallelism (MP), pipeline parallelism (PP), and hybrid parallelism (HP). Structural designs include parameter server-based, reduce-based, and message passing interface (MPI)-based structures.

[0052] Model compression and quantization refer to techniques that help reduce model size and speed up model inference, thereby reducing the cost of model storage and computation. Model compression typically includes pruning, low-rank decomposition, and knowledge distillation, while model quantization involves converting floating-point parameters in the model to fixed-point or integer parameters, thereby reducing model size and speeding up model inference.

[0053] Adaptive computing refers to automatically adjusting the computational load and precision of a model based on different input data to achieve the goal of improving computational efficiency while maintaining model accuracy. Adaptive computing can flexibly adjust the computational load and precision of a model on different input data, thereby better balancing the computational efficiency and accuracy of the model.

[0054] Model parallel computing refers to distributing the computational tasks of a model to multiple computing devices for simultaneous computation, thereby speeding up the training and inference of the model. Computing devices include central processing units (CPUs), graphics processing units (GPUs), and tensor processing units (TPUs), among others. Model parallel computing can effectively utilize computing resources, improving the computational efficiency and training speed of the model.

[0055] With the research and progress of artificial intelligence technology, artificial intelligence technology is researched and applied in many fields, such as common smart home, smart wearable device, virtual assistant, smart speaker, smart marketing, unmanned driving, autonomous driving, unmanned aerial vehicle, digital twin, virtual human, robot, artificial intelligence generated content (AIGC), dialogue interaction, intelligent medical treatment, intelligent customer service, game AI, etc. It is believed that with the development of technology, artificial intelligence technology will be applied in more fields and play an increasingly important role.

[0056] Cyclic shift is used to perform shift on a bit sequence according to a shift amount. Cyclic shift includes right rotate and left rotate. For right rotate, one right shift means moving the rightmost bit in the bit sequence to the leftmost bit, and the number of right shifts is equal to the shift amount. For example, if the shift amount is 1, one right shift is performed, and if the shift amount is 2, two right shifts are performed. For example, the bit sequence is 0110, 0, 1, 1 and 0 are four different bits, one right shift is performed to obtain 0011, and two right shifts are performed to obtain 1001. For left rotate, one left shift means moving the leftmost bit in the bit sequence to the rightmost bit, and the number of left shifts is equal to the shift amount. For example, if the shift amount is 1, one left shift is performed, and if the shift amount is 2, two left shifts are performed. Still taking the bit sequence 0110 as an example, one left shift is performed to obtain 1100, and two left shifts are performed to obtain 1001.

[0057] The embodiment of the present application provides a storage device, as shown in the figure, which comprises identification element 1, generation element 2, processing element 3 and storage board 4 connected in sequence. Exemplarily, identification element 1, generation element 2 and processing element 3 are all in the form of circuit, which is not limited in the embodiment of the present application. Each element and storage board 4 are described as follows. Figure 2

[0058] Identification element 1 is used to identify access requests respectively sent by a plurality of access sources to obtain a first bit sequence, each bit in the first bit sequence corresponds to one access source in the plurality of access sources, and the bit with the first value is used to indicate that the corresponding access source requests to access storage board 4.

[0059] Among them, identification element 1 is connected with a plurality of access sources to receive access requests respectively sent by the plurality of access sources. Exemplarily, see Figure 2 ​The storage device includes a plurality of interfaces, each of the plurality of access sources is connected to the identification element 1 through an interface, respectively, to send an access request to the identification element 1, so that the identification element 1 can receive the access request sent by the plurality of access sources respectively, that is, the identification element 1 receives a plurality of access requests.

[0060] For example, the plurality of access sources includes access source 0 to access source N, that is, the number of access sources is N+1, and N is greater than or equal to 1. The storage device can include N+1 interfaces, and each access source is connected to the identification element 1 through an interface. Alternatively, the storage device can include N+2 interfaces or more. Among these interfaces, N+1 interfaces are working interfaces, and the remaining interfaces are standby interfaces. Each access source is connected to the identification element 1 through a working interface. If a working interface fails, the access source connected to the working interface can be connected to the identification element 1 through a standby interface.

[0061] After the identification element 1 receives a plurality of access requests, it can identify the plurality of access requests. For any one access request, identifying the access request is used to determine whether the access request corresponding to the access source requests to access the storage board 4, and the access request corresponding to the access source refers to the access source sending the access request. Through the identification process, the identification element 1 can obtain a first bit sequence, and each bit in the first bit sequence corresponds to one of the plurality of access sources. Alternatively, the first bit sequence includes a plurality of bits, and the plurality of bits correspond to the plurality of access sources one by one. Wherein, each bit is used to indicate whether the corresponding access source requests to access the storage board 4. The storage board 4 refers to the storage board connected to the identification element 1 through the generation element 2 and the processing element 3, and the storage board 4 is referred to as the current storage board in the following.

[0062] For example, for any bit in the first bit sequence, when the bit has a first value, it indicates that the access source corresponding to the bit requests to access the current storage board. When the bit does not have the first value, for example, when the bit has a fifth value (different from the first value), it indicates that the corresponding access source does not request to access the current storage board, but requests to access other storage boards other than the current storage board. In the embodiments of the present application, the first value and the fifth value are not limited, as long as the first value and the fifth value are different values. For example, the first value and the fifth value are opposite values. Alternatively, the bits in the first bit sequence have Boolean values. For example, the first value is 1 and the fifth value is 0. For example, the first value is 0 and the fifth value is 1.

[0063] For example, the identification element 1 stores an address range corresponding to the current storage board block, and the access request carries an address requested to be accessed by the access source. If the address carried by the access request is within the address range corresponding to the current storage board block, the identification element 1 can determine that the access request corresponds to an access source requesting to access the current storage board block, and thus determine that the bit corresponding to the access source has the first value. If the address carried by the access request is outside the address range corresponding to the current storage board block, the identification element 1 can determine that the access request corresponds to an access source not requesting to access the current storage board block, and thus determine that the bit corresponding to the access source has the fifth value.

[0064] In an exemplary embodiment, referring to Figure 3 The identification element 1 includes a plurality of identification sub-elements, which correspond to a plurality of interfaces included in the storage device in a one-to-one manner, and each access source is connected to an identification sub-element through an interface. For example, the identification sub-element is in the form of a circuit, which is not limited in the embodiments of the present application. For any access request, the access request is sent by the corresponding access source and reaches the identification sub-element corresponding to the interface through the interface corresponding to the access source, so that the identification sub-element can identify the access request. The identification sub-element stores an address range corresponding to the current storage board block, and the access request received by the identification sub-element carries an address. If the address carried by the access request is within the address range corresponding to the current storage board block, the identification sub-element determines that the bit corresponding to the access source has the first value. If the address carried by the access request is outside the address range corresponding to the current storage board block, the identification sub-element determines that the bit corresponding to the access source has the fifth value. Each identification sub-element can determine one bit in this way, and the plurality of identification sub-elements can determine a plurality of bits corresponding to the plurality of access sources to obtain the first bit sequence.

[0065] In some embodiments, the plurality of bits corresponding to the plurality of access sources are sequentially arranged, and each element included in the storage device can correctly identify the access source corresponding to each bit. For example, in the first bit sequence, the first bit on the right end corresponds to the access source 0, the second bit on the right end corresponds to the access source 1, and so on, and the first bit on the left end corresponds to the access source N. For another example, in the first bit sequence, the first bit on the left end corresponds to the access source 0, the second bit on the left end corresponds to the access source 1, and so on, and the first bit on the right end corresponds to the access source N. In other embodiments, the plurality of bits corresponding to the plurality of access sources are arranged in disorder. The embodiments of the present application do not limit how to arrange in disorder, as long as each element included in the storage device can correctly identify the access source corresponding to each bit.

[0066] After the identification element 1 obtains the first bit sequence, since the identification element 1 is connected with the generation element 2, the identification element 1 can send the first bit sequence to the generation element 2. Exemplarily, the identification element 1 can send the first bit sequence in the form of a vector to the generation element 2, and the form of the first bit sequence is not limited in the embodiments of the present application.

[0067] The generation element 2 is configured to generate a second bit sequence in the case that at least one bit in the first bit sequence has the first value, each bit in the second bit sequence corresponds to one of the plurality of access sources, and one bit in the second bit sequence has a second value, the bit with the second value is used to indicate that the corresponding access source is authorized to access the current storage block.

[0068] The generation element 2 can receive the first bit sequence sent by the identification element 1. Since each bit in the first bit sequence is used to indicate whether the corresponding access source requests to access the current storage block, and the first value is used to indicate that the corresponding access source requests to access the current storage block, in the case that at least one bit in the first bit sequence has the first value, that is, in the case that at least one of the plurality of access sources requests to access the current storage block. In this case, the generation element 2 needs to determine and only determine one access source from the at least one access source that can access the current storage block, or only the access source has the permission to access the current storage block, so as to avoid the case that different access sources access the current storage block at the same time and cause the storage block conflict. For example, simultaneously refers to within the same clock cycle.

[0069] Therefore, the generation element 2 needs to generate a second bit sequence, each bit in the second bit sequence corresponds to one of the plurality of access sources. Or, the second bit sequence includes a plurality of bits, and the plurality of bits correspond to the plurality of access sources one by one. And, the plurality of bits included in the second bit sequence also correspond to the plurality of bits included in the first bit sequence one by one. Wherein, each bit in the second bit sequence is used to indicate whether the corresponding access source requests to access the current storage block, so that only one bit in the second bit sequence has the second value. Since the bit with the second value is used to indicate that the corresponding access source is authorized to access the current storage block, the access source corresponding to the bit with the second value is the access source determined by the generation element 2 that is authorized to access the current storage block.

[0070] Exemplarily, in the process of generating the second bit sequence, due to the fact that there is at least one bit having the first value in the first bit sequence, the generating element 2 selects a bit having the first value from the first bit sequence, so that the selected bit in the first bit sequence has the second value in the corresponding bit in the second bit sequence, and the bits other than the selected bit in the first bit sequence have the sixth value (different from the second value) in the corresponding bits in the second bit sequence, when the bits having the sixth value in the second bit sequence, it indicates that the corresponding access source is not authorized to access the current storage board, that is, it does not have the permission to access the current storage board. Thus, the second bit sequence can be obtained, and only one bit in the second bit sequence has the second value.

[0071] Exemplarily, the second value and the first value described above can be the same or different. In the embodiments of the present application, the second value and the sixth value are not limited, as long as the second value and the sixth value are different values. For example, the second value and the sixth value are opposite values. Alternatively, the bits in the second bit sequence have Boolean values. For example, the second value is 1 and the sixth value is 0. For another example, the second value is 0 and the sixth value is 1.

[0072] In addition, according to the above description, no matter whether the first bit sequence is sequentially arranged or randomly arranged, each element included in the storage device can correctly identify the corresponding access source of each bit in the first bit sequence. Based on this, since the plurality of bits included in the second bit sequence also correspond to the plurality of bits included in the first bit sequence one by one, each element included in the storage device can also correctly identify the corresponding access source of each bit in the second bit sequence.

[0073] In the embodiments of the present application, after the generating element 2 receives the first bit sequence sent by the identifying element 1, it does not need to judge or perceive whether the at least one bit in the first bit sequence has the first value, but directly executes the process of generating the second bit sequence described above, so that the second bit sequence can be generated in the case that the at least one bit in the first bit sequence has the first value.

[0074] After the generating element 2 generates the second bit sequence, since the generating element 2 is connected with the processing element 3, the generating element 2 can send the second bit sequence to the processing element 3. The second bit sequence is, for example, in the form of a vector, which is not limited in the embodiments of the present application.

[0075] The processing element 3 is configured to process an access request sent by an access source corresponding to a bit having the second value based on the storage board 4.

[0076] The processing element 3 can receive the second bit sequence sent by the generating element 2. According to the foregoing description, each element included in the storage device can correctly identify the access source corresponding to each bit in the second bit sequence, and thus the processing element 3 can correctly identify the access source corresponding to each bit in the second bit sequence. Therefore, the processing element 3 can determine the access source corresponding to the bit with the second value in the second bit sequence, and the access source is the access source authorized to access the current storage block.

[0077] In addition, the processing element 3 can receive access requests sent by multiple access sources. For example, the storage device in the embodiment of the present application includes multiple interfaces, and each access source in the multiple access sources is connected to the processing element 3 through an interface to send an access request to the processing element 3, so that the processing element 3 can receive multiple access requests.

[0078] Since the processing element 3 determines the access source that can access the current storage block and receives multiple access requests, the processing element 3 can determine the access request sent by the access source authorized to access the current storage block from the multiple access requests and process the determined access request based on the current storage block.

[0079] Alternatively, since only one bit in the second bit sequence has the second value and the other bits have the sixth value, the second bit sequence belongs to one hot (OH). Accordingly, the processing element 3 can be a multiplexer (MUX) based on one hot, which can be represented as MUX OH, and the MUX OH is in the form of a circuit.

[0080] For example, the process of processing the determined access request based on the current storage block includes but is not limited to reading data from the current storage block according to the access request, or writing data into the current storage block according to the access request. For example, the determined access request carries an address, and the address is within the address range of the current storage block. When the determined access request indicates that data needs to be read from the current storage block, the processing element 3 reads data from the address carried by the access request in the current storage block and returns the read data to the access source sending the access request. When the access request indicates that data needs to be written into the current storage block, the processing element 3 also receives data sent by the access source sending the access request, and writes the received data into the address carried by the access request in the current storage block.

[0081] Alternatively, the access request carries an identifier in addition to the address, and the identifier is used to indicate reading data or writing data. Therefore, the processor can determine whether the data needs to be read from the current storage block or the data needs to be written into the current storage block through the identifier carried by the access request.

[0082] According to the foregoing description, the plurality of access sources and the processing element 3 need to interact with access requests and data (data read from the current storage block or data written to the current storage block). Exemplarily, for any one access source, there is a first line and a second line between the access source and the processing element 3, the first line is used to interact with the access request, and the second line is used to interact with the data, so that the access request and the data can interact through different lines, which is more flexible.

[0083] The foregoing description of the generation element 2 and the processing element 3 is for the case that at least one bit in the first bit sequence has the first value, that is, at least one access source in the plurality of access sources requests to access the current storage block. In addition, there is also a case that any bit in the first bit sequence is the fifth value, or in other words, there is no bit with the first value in the first bit sequence, that is, no access source in the plurality of access sources requests to access the current storage block. In this case, the generation element 2 does not generate the second bit sequence and the second bit sequence only includes one bit with the second value, but generates a sixth bit sequence, the sixth bit sequence includes a plurality of bits corresponding to the plurality of access sources, and each bit is the sixth value, representing that each access source in the plurality of access sources is not authorized to access the current storage block. Correspondingly, after the processing element 3 receives the sixth bit sequence sent by the generation element 2, it does not need to process any access request in the plurality of access requests sent by the plurality of access sources.

[0084] As described above, the storage device includes the identification element 1, the generation element 2, the processing element 3 and the storage block 4 connected in sequence. Among them, the identification element 1, the generation element 2 and the processing element 3 constitute the control circuit corresponding to the storage block 4. Exemplarily, the storage device can include a plurality of storage blocks 4, the plurality of storage blocks 4 can form a storage block group, each storage block 4 corresponds to a control circuit, then there are a plurality of control circuits, and at least one control circuit in the plurality of control circuits is the control circuit provided in the embodiment of the application. For example, each control circuit in the plurality of control circuits is the control circuit provided in the embodiment of the application. In the case that the storage device includes a plurality of storage blocks 4, for each access source in the plurality of access sources, the access source sends an access request to the control circuit corresponding to each storage block 4 respectively, that is, the access source broadcasts the access request, so that the control circuit corresponding to each storage block 4 can receive the access request sent by the access source. Correspondingly, each control circuit processes the access request based on the corresponding storage block 4 respectively.

[0085] As Figure 4As shown, the plurality of storage tiles 4 includes storage tile 0 to storage tile M, that is, the number of storage tiles 4 is M+1, and M is greater than or equal to 1. Exemplarily, M is greater than or equal to the number of access sources, that is, the number of storage tiles 4 is greater than or equal to the number of access sources, which facilitates the plurality of access sources to access the plurality of storage tiles 4 in parallel. Wherein, parallel access refers to that each access source can access at least one storage tile 4 in the same clock cycle, and the storage tiles 4 accessed by different access sources are different, and parallel access facilitates to improve the performance of the storage device.

[0086] Each of the plurality of storage tiles 4 corresponds to a certain address range, and each storage tile 4 has a certain width, for example, the width of a storage tile 4 is 4 bytes. Figure 5 As shown, in the storage tile 0, the address increases from the low bit, and after increasing the width of the storage tile 0, it jumps to the next storage tile of the storage tile 0, and so on, until it jumps to the storage tile M, and after increasing the width of the storage tile M, it jumps back to the storage tile 0 and increases. This address organization form between different storage tiles 4 is called low bit address interleaving.

[0087] Referring to Figure 6 Taking the number of storage tiles 4 as 3 and the width of each storage tile 4 as 4 bytes as an example, addresses 0 to 3 are located in the storage tile 0 (0 is the low bit address), addresses 4 to 7 are located in the storage tile 1, addresses 8 to 11 are located in the storage tile 2, the address returns to the storage tile 0 and continues to increase, addresses 12 to 15 are located in the storage tile 0, addresses 16 to 19 are located in the storage tile 1, addresses 20 to 23 are located in the storage tile 2, the address returns to the storage tile 0 and continues to increase, addresses 24 to 27 are located in the storage tile 0, addresses 28 to 31 are located in the storage tile 1, and addresses 32 to 25 are located in the storage tile 2.

[0088] In combination with Figure 7 , the process of processing access requests by the storage device is exemplarily illustrated. Wherein, the address ranges corresponding to the storage tile 0 to the storage tile 2 can be referred to Figure 6 For example, the access request 0 broadcast by the access source 0 carries the address 0 (located in the storage tile 0), the access request 1 broadcast by the access source 1 carries the address 13 (located in the storage tile 0), and the access request 2 broadcast by the access source 2 carries the address 6 (located in the storage tile 1). And the first value and the second value are 1, and the fifth value and the sixth value are 0.

[0089] In the control circuit 0, the three identification sub-elements identify the access request 1, the access request 2 and the access request 3 respectively, and obtain a first bit sequence 110, 1, 1 and 0 being three different bits. In the first bit sequence 110, the left 1 indicates that the access source 0 requests to access the current storage board 0, the middle 1 indicates that the access source 1 requests to access the current storage board 0, and the right 0 indicates that the access source 2 does not request to access the current storage board 0. After the generation element receives the first bit sequence 110, a second bit sequence 100 is generated, 1, 0 and 0 being three different bits. The second bit sequence 100 represents that the access source 0 is authorized to access the current storage board 0. After the processing element receives the second bit sequence 100, the access request 0 corresponding to the access source 0 is processed based on the storage board 0, and the access of the access source 0 to the storage board 0 is realized.

[0090] In the control circuit 1, the three identification sub-elements identify the access request 1, the access request 2 and the access request 3 respectively, and obtain a first bit sequence 001, 0, 0 and 1 being three different bits. In the first bit sequence 001, the left 0 indicates that the access source 0 does not request to access the current storage board 1, the middle 0 indicates that the access source 1 does not request to access the current storage board 1, and the right 1 indicates that the access source 2 requests to access the current storage board 1. After the generation element receives the first bit sequence 001, a second bit sequence 001 is generated, 0, 0 and 1 being three different bits. The second bit sequence 001 represents that the access source 2 is authorized to access the current storage board 1. After the processing element receives the second bit sequence 001, the access request 2 corresponding to the access source 2 is processed based on the storage board 1, and the access of the access source 2 to the storage board 1 is realized.

[0091] In the control circuit 2, the three identification sub-elements identify the access request 1, the access request 2 and the access request 3 respectively, and obtain a first bit sequence 000, 0, 0 and 0 being three different bits, representing that the access source 0, the access source 1 and the access source 2 all do not request to access the current storage board 2. After the generation element receives the first bit sequence 000, a sixth bit sequence 000 is generated, 0, 0 and 0 being three different bits. After the processing element receives the sixth bit sequence 000, any access request does not need to be processed.

[0092] In the embodiments of the present application, since the storage device includes the identification element, the generation element, the processing element and the storage block connected in sequence, after the plurality of access sources respectively send access requests, the first bit sequence can be obtained through the identification of the access request by the identification element, and whether the corresponding access source requests to access the current storage block can be determined according to each bit in the first bit sequence. The second bit sequence can be generated by the generation element according to the first bit sequence, so that it can be determined which access source is authorized to access the current storage block according to each bit in the second bit sequence. Thus, in the case that at least one access source in the plurality of access sources requests to access the current storage block, an access source authorized to access the current storage block is determined. Then, the processing element processes the access request based on the storage block, and the processed access request is sent by the access source authorized to access the current storage block, so that the access of the storage block by the access source authorized to access the current storage block is realized. Thus, the different access sources are avoided from accessing the current storage block at the same time, so that the storage block conflict is avoided.

[0093] The process can be realized based on each element included in the storage device, each element is hardware, and does not need to depend on the allocation program manually written by the programmer, which not only reduces the burden of the programmer and is more flexible, but also only needs a short time to complete the processing of the access request sent by the access source, so that the access time delay of the storage device is short, the performance of the storage device is improved, and the access request can be quickly processed based on the storage device. Moreover, the volume of each element provided in the embodiments of the present application is small, each element and the storage block are integrated into a chip, and the chip also has a small volume, so that the application range of the chip is wide, and the product competitiveness of the chip is improved.

[0094] The storage device provided in the embodiments of the present application is a storage device with good performance and being conducive to parallel access, which can provide data storage function (for persistent storage of data, or non-persistent storage of data) and access request processing function. Exemplarily, the storage device can be independently applied, or applied in a processor or the like. Since the storage device itself has high performance, the overall performance of the processor or the like can be improved.

[0095] Exemplarily, the processor includes but is not limited to CPU or AI processor and the like. Optionally, the AI processor includes but is not limited to graphics processing unit (GPU), TPU, field programmable gate array (FPGA), application specific integrated circuit (ASIC) and the like.

[0096] For example, the AI processor for model training includes a plurality of processing cores and the storage device, the plurality of processing cores are used as a plurality of access sources. In the process of model training, the plurality of processing cores respectively generate access requests according to the model training requirements. The plurality of processing cores respectively send the access requests to the identification element 1 in the storage device, the identification element 1 identifies the access requests respectively sent by the plurality of processing cores, obtains a first bit sequence corresponding to the plurality of processing cores one by one, and each bit in the first bit sequence is used to indicate whether the corresponding processing core requests to access the current storage block, and the bit with the first value is used to indicate that the corresponding processing core requests to access the current storage block.

[0097] The identification element 1 sends the first bit sequence to the generation element 2, and the generation element 2 generates a second bit sequence according to the first bit sequence, and each bit in the second bit sequence has a second value, and each bit is used to indicate whether the corresponding processing core is authorized to access the current storage block, and the bit with the second value is used to indicate that the corresponding processing core is authorized to access the current storage block.

[0098] The generation element 2 sends the second bit sequence to the processing element 3, and the processing element 3 processes the access request sent by the processing core corresponding to the bit with the second value based on the current storage block. For example, data is read from the current storage block according to the access request, and the read data is returned to the processing core corresponding to the bit with the second value, so as to complete the processing of the access request. After receiving the data sent by the processing element 3, the processing core corresponding to the bit with the second value implements the training of the model according to the received data.

[0099] Next, the structure of the storage device provided by the embodiments of the present application is further illustrated by taking examples.

[0100] In the exemplary embodiments, the embodiments of the present application at least provide the following two kinds of generation element 2.

[0101] The first generation element 2 is used to query the bit with the first value in the first bit sequence in the case that at least one bit in the first bit sequence has the first value, and generate the second bit sequence according to the queried bit, and the bit corresponding to the queried bit in the second bit sequence has the second value. Correspondingly, the bits other than the bit with the second value in the second bit sequence have the sixth value.

[0102] When querying in the first bit sequence, the generating element 2 can start querying from the leftmost end of the first bit sequence, or start querying from the rightmost end of the first bit sequence. Regardless of the direction in which the generating element 2 starts querying, the generating element 2 can take the first bit with the first value as the query result (in this case, the generating element 2 is a find first bit (FFB) element), or take the last bit with the first value as the query result. The query result is the queried bit, and thus the generating element 2 causes the corresponding bit in the second bit sequence to have the second value, and causes the other bits in the second bit sequence to have the sixth value.

[0103] If the generating element 2 starts querying from the leftmost end of the first bit sequence and takes the first bit with the first value as the query result, or starts querying from the rightmost end of the first bit sequence and takes the last bit with the first value as the query result, it means that the generating element 2 defaults to taking the access source corresponding to the leftmost bit in the first bit sequence as the access source with the highest priority in the plurality of access sources. For any bit in the first bit sequence, the farther the bit is from the leftmost end of the first bit sequence, the lower the priority of the access source corresponding to the bit in the plurality of access sources.

[0104] If the generating element 2 starts querying from the rightmost end of the first bit sequence and takes the first bit with the first value as the query result, or starts querying from the leftmost end of the first bit sequence and takes the last bit with the first value as the query result, it means that the generating element 2 defaults to taking the access source corresponding to the rightmost bit in the first bit sequence as the access source with the highest priority in the plurality of access sources. Correspondingly, for any bit in the first bit sequence, the farther the bit is from the rightmost end of the first bit sequence, the lower the priority of the access source corresponding to the bit in the plurality of access sources.

[0105] The second generating element 2, referring to Figure 8 The generating element 2 includes a first moving sub-element 21, a generating sub-element 22, and a second moving sub-element 23 connected in sequence, the first moving sub-element 21 is connected to the identifying element 1, and the second moving sub-element 23 is connected to the processing element 3. Exemplarily, the first moving sub-element 21, the generating sub-element 22, and the second moving sub-element 23 are all in the form of a circuit, and the embodiments of the present application do not limit this.

[0106] The first moving sub-element 21 is configured to perform a first cyclic shift on the first bit sequence according to a third value, so that the bit corresponding to the reference access source is at the first end of the first bit sequence, and the third value is used to indicate the reference access source with the highest priority in the plurality of access sources.

[0107] Since the first mobile sub-element 21 is connected with the identification element 1, the identification element 1 can send a first bit sequence to the first mobile sub-element 21, and after the first mobile sub-element 21 receives the first bit sequence, the first mobile sub-element 21 performs the first cyclic shift on the first bit sequence according to a third value. In the case where the plurality of access sources include the access source 0 to the access source N, the third value ranges from 0 to N+1. The third value is used to indicate a reference access source with the highest priority in the plurality of access sources, and then the first cyclic shift is performed on the first bit sequence according to the third value, so that the bit corresponding to the reference access source is located at a first end of the first bit sequence, thereby facilitating the subsequent query of the sub-element 22 based on the first end. The first end is one end in the moving direction of the first cyclic shift. For example, the moving direction of the first cyclic shift is to the right, that is, the first cyclic shift is a cyclic right shift, and the first end is the rightmost end in the first bit sequence. For another example, the moving direction of the first cyclic shift is to the left, that is, the first cyclic shift is a cyclic left shift, and the first end is the leftmost end in the first bit sequence.

[0108] In the embodiment of the present application, the first cyclic shift is performed on the first bit sequence according to the third value, that is, the first bit sequence is cyclically shifted by the third value in the moving direction of the first cyclic shift, that is, the shift amount of the first cyclic shift is equal to the third value. For example, the third value is 0, and the reference access source with the highest priority in the plurality of access sources is the access source 0, so the first bit sequence is cyclically shifted by 0 in the moving direction of the first cyclic shift, and the first bit sequence before and after the first cyclic shift is the same. For another example, the third value is 1, which represents that the reference access source with the highest priority in the plurality of access sources is the access source 1, so the first bit sequence is cyclically shifted by 1 in the moving direction of the first cyclic shift, and the first bit sequence before and after the first cyclic shift is different.

[0109] For example, referring to Figure 9 In the case where the third value is 1 (that is, the reference access source with the highest priority in the plurality of access sources is the access source 1) and the first cyclic shift is a cyclic right shift, the first bit sequence before the first cyclic shift is 101, and the first bit sequence after the first cyclic shift is 110, and the bit (with a value of 0) corresponding to the access source 1 is located at the rightmost end in the first bit sequence 110.

[0110] Still taking the first bit sequence 101 and the first bit sequence 110 in the above example as an example, referring to Figure 8After the first mobile sub-element 21 receives the first bit sequence 101 (i.e. the first bit sequence before the first cyclic shift) sent by the identification element 1, it performs a cyclic right shift with a shift amount of 1. During the cyclic right shift, the first mobile sub-element 21 moves each bit in the first bit sequence 101 one bit to the right, obtaining (0)10(1), where (0) represents the empty positions after the shift, and (1) represents the overflowed bits after the shift. By filling the overflowed bits into the empty positions, the first bit sequence 110 (i.e. the first bit sequence after the first cyclic shift) can be obtained. The first mobile sub-element 21 can subsequently send the first bit sequence 110 to the generating sub-element 22.

[0111] It should be noted that before the first cyclic shift is performed, the plurality of access sources and the plurality of bits included in the first bit sequence are one-to-one corresponding, and are corresponding by bit. Wherein, the corresponding by bit means that the order of an access source in the plurality of access sources is equal to the order of the bit corresponding to the access source in the first bit sequence. For example, in the first bit sequence before the first cyclic shift shown in FIG. 1A, the access source 0 corresponds to the right bit (equivalent to the 0th bit from the right), the access source 1 corresponds to the middle bit (equivalent to the 1th bit from the right), and the access source 2 corresponds to the left bit (equivalent to the 2th bit from the right). Figure 9 However, after the first cyclic shift is performed, the plurality of access sources and the plurality of bits included in the first bit sequence are still one-to-one corresponding, but can not be corresponding by bit. For example, in the first bit sequence after the first cyclic shift shown in FIG. 1B, the access source 0 corresponds to the left bit, the access source 1 corresponds to the right bit, and the access source 2 corresponds to the middle bit. Figure 9

[0112] Since the first mobile sub-element 21 is connected to the generating sub-element 22, after the first mobile sub-element 21 performs the first cyclic shift on the first bit sequence, it sends the first bit sequence after the first cyclic shift to the generating sub-element 22. The first bit sequence after the first cyclic shift can be in the form of a vector, which is not limited in the embodiments of the present application.

[0113] The generating sub-element 22 is configured to, in a case where at least one bit in the first bit sequence has a first value, query a bit having the first value in the first bit sequence based on the first end, and generate a third bit sequence according to the queried bit, wherein a bit corresponding to the queried bit in the third bit sequence has a second value. Correspondingly, in the third bit sequence, each bit other than the bit having the second value has a sixth value.

[0114] ​As mentioned above, the case that at least one bit in the first bit sequence has the first value, that is, the case that at least one access source in the plurality of access sources requests to access the current storage tile. In this case, after the generating sub-element 22 receives the first bit sequence sent by the first moving sub-element 21, it is necessary to generate a third bit sequence (for generating the second bit sequence subsequently), the third bit sequence includes a plurality of bits, each bit corresponds to an access source in the plurality of access sources, and each bit is used to indicate whether the corresponding access source is authorized to access the current storage tile, and only one bit in the third bit sequence has the second value, and the access source corresponding to the bit having the second value is the access source authorized to access the current storage tile. Thus, the storage tile conflict caused by different access sources accessing the current storage tile at the same time is avoided.

[0115] In some embodiments, the direction of the query is from the first end to the second end of the first bit sequence, and since the bit corresponding to the reference access source with the highest priority in the plurality of access sources is at the first end, the query is performed in the direction from the first end to the second end, that is, in the direction of decreasing priority. Therefore, it is necessary to make the bit obtained by the query be the first bit having the first value in the first bit sequence, and the generating sub-element 22 is an FFB element. Thus, it can be ensured that the access source corresponding to the bit obtained by the query is the access source with the highest priority among all the access sources included in the plurality of access sources and requesting to access the current storage tile.

[0116] In other embodiments, the direction of the query is from the second end to the first end, and since the bit corresponding to the reference access source with the highest priority in the plurality of access sources is at the first end, the query is performed in the direction from the second end to the first end, that is, in the direction of increasing priority. Therefore, it is necessary to make the bit obtained by the query be the last bit having the first value in the first bit sequence. Thus, it can also be ensured that the access source corresponding to the bit obtained by the query is the access source with the highest priority among all the access sources included in the plurality of access sources and requesting to access the current storage tile.

[0117] As can be seen, no matter which embodiment is used to complete the query, it can be ensured that the access source corresponding to the bit obtained by the query is the access source with the highest priority among all the access sources included in the plurality of access sources and requesting to access the current storage tile, and the priority access of the access source to the current storage tile is realized. For example, the priorities of the access source 0, the access source 1 and the access source 2 are sequentially decreased. In a clock cycle, if the access source 0 requests to access the current storage tile, the access source 0 is authorized to have the priority access to the current storage tile. If the access source 0 does not request to access the current storage tile, and the access source 1 requests to access the current storage tile, the access source 1 is authorized to access the current storage tile. If the access source 0 and the access source 1 both do not request to access the current storage tile, and the access source 2 requests to access the current storage tile, the access source 2 is authorized to access the current storage tile.

[0118] For example, referring to Figure 9 In the case that the first value and the second value are 1, the fifth value and the sixth value are 0, the third value is 1 (i.e., the reference access source with the highest priority among the plurality of access sources is the access source 1), the first end is the rightmost end, and the direction of the query is from the first end to the second end, in the first bit sequence 110 after the first cyclic shift, the first value of the first bit sequence 110 is 1, that is, the bit in the middle of the first bit sequence 110 (the value of which is 1), the value of the corresponding bit in the third bit sequence is 1, and the values of the other bits (the bit on the right side with the value of 0 and the bit on the left side with the value of 1) are 0. Thus, the third bit sequence is 010, and 0, 1 and 0 are different bits.

[0119] Still taking the first bit sequence 110 and the third bit sequence 010 in the above example as an example, referring to Figure 8 After the generating sub-element 22 receives the first bit sequence 110 sent by the first moving sub-element 21, the generating sub-element 22 starts to query from the rightmost end of the first bit sequence 110. In the query process, the value of the first bit is 0, so the value of the corresponding bit in the third bit sequence is 0. The value of the second bit is 1, and the second bit is the first bit with the value of 1 in the query process, so the value of the corresponding bit in the third bit sequence is 1. The value of the third bit is 1, but the third bit is not the first bit with the value of 1 in the query process, so the value of the corresponding bit in the third bit sequence is 0. Thus, the third bit sequence 010 can be obtained. The generating sub-element 22 can subsequently send the third bit sequence 010 to the second moving sub-element 23.

[0120] It should be noted that, since the generating sub-element 22 does not perform any cyclic shift in the process of generating the third bit sequence from the first bit sequence, if the plurality of access sources are not in one-to-one correspondence with the bits included in the first bit sequence, the plurality of access sources can also not be in one-to-one correspondence with the bits included in the third bit sequence.

[0121] Since the generating sub-element 22 is connected to the second moving sub-element 23, after the generating sub-element 22 generates the third bit sequence, the generating sub-element 22 sends the third bit sequence to the second moving sub-element 23. The third bit sequence can be in the form of a vector, which is not limited in the embodiments of the present application.

[0122] The second moving sub-element 23 is configured to perform a second cyclic shift on the third bit sequence according to the third value, to obtain a second bit sequence, and the moving direction of the second cyclic shift is opposite to that of the first cyclic shift.

[0123] After receiving the third bit sequence sent by the generating sub-element 22, the second moving sub-element 23 performs the second cyclic shift on the third bit sequence according to the third value. That is, the third bit sequence is cyclically shifted by the third value according to the moving direction of the second cyclic shift, that is, the shift amount of the second cyclic shift is equal to the third value. The second cyclic shift is inverse to the first cyclic shift, that is, the shift amount of the second cyclic shift is the same as that of the first cyclic shift (both are the third value), and the moving direction of the second cyclic shift is opposite to that of the first cyclic shift. For example, the moving direction of the first cyclic shift is right, and the moving direction of the second cyclic shift is left, that is, the second cyclic shift is a cyclic left shift. For another example, the moving direction of the first cyclic shift is left, and the moving direction of the second cyclic shift is right, that is, the second cyclic shift is a cyclic right shift.

[0124] As described above, since the first moving sub-element 21 performs the first cyclic shift, the plurality of access sources and the bits included in the first bit sequence may not correspond to each other in a one-to-one manner, resulting in that the plurality of access sources and the bits included in the third bit sequence may not correspond to each other in a one-to-one manner. Therefore, the second moving sub-element 23 needs to perform the second cyclic shift inverse to the first cyclic shift on the third bit sequence to obtain the second bit sequence, so that the plurality of access sources and the bits included in the second bit sequence correspond to each other in a one-to-one manner, facilitating the subsequent processing element 3 to correctly identify which one of the plurality of access sources the bit with the second value corresponds to according to the second bit sequence, thereby processing the access request sent by the access source.

[0125] For example, referring to Figure 9 , in the case that the third value is 1 (that is, the reference access source with the highest priority in the plurality of access sources is the access source 1) and the second cyclic shift is a cyclic left shift, the third bit sequence before the second cyclic shift is 010, and the second bit sequence after the second cyclic shift is 100.

[0126] Still taking the third bit sequence 010 and the second bit sequence 100 in the above example as an example, referring to Figure 8 , after receiving the third bit sequence 010 sent by the generating sub-element 22, the second moving sub-element 23 performs a cyclic left shift, and the shift amount of the cyclic left shift is 1. In the process of the cyclic left shift, the second moving sub-element 23 moves each bit in the third bit sequence 010 by 1 bit to the left to obtain (0)10(), where () represents the empty position obtained after the shift, and (0) represents the overflow bit after the shift. By filling the overflow bit into the empty position obtained after the shift, the second bit sequence 100 can be obtained. The second moving sub-element 23 can subsequently send the second bit sequence 100 to the processing element 3.

[0127] And, the multiple access sources correspond to the bits included in the second bit sequence in a bit-by-bit manner, access source 0 corresponds to the bit with a value of 0 on the right (equivalent to the 0th bit from the right), access source 1 corresponds to the bit with a value of 0 in the middle (equivalent to the 1st bit from the right), and access source 2 corresponds to the bit with a value of 1 on the left (equivalent to the 2nd bit from the right).

[0128] In the embodiment of the present application, the first mobile sub-element 21 performs the first cyclic shift on the first bit sequence, so that the bit corresponding to the reference access source with the highest priority among the multiple access sources is moved to the first end of the first bit sequence, facilitating the generation of the query of the generation sub-element 22 based on the first end, improving the query efficiency of the generation sub-element 22, thereby improving the overall efficiency of the generation sub-element 22 in generating the third bit sequence, and further improving the efficiency of processing the access request, thereby ensuring the performance of the storage device. The second mobile sub-element 22 performs the second cyclic shift on the third bit sequence to obtain the second bit sequence. Since the moving direction of the second cyclic shift is opposite to that of the first cyclic shift, the execution of the second cyclic shift can eliminate the influence caused by the first cyclic shift, thereby ensuring that the processing element 3 can correctly identify the access source corresponding to each of the second bit sequences, and thus ensuring the accuracy of processing the access request.

[0129] Since the second mobile sub-element 23 is connected to the processing element 3, after the second mobile sub-element 23 performs the second cyclic shift on the third bit sequence to obtain the second bit sequence, the second mobile sub-element 23 sends the second bit sequence to the processing element 3, so that the processing element 3 processes the access request according to the above description, which will not be described here.

[0130] In addition, according to the above description, it can be known that the first mobile sub-element 21 needs to use the third value when performing the first cyclic shift, and the second mobile sub-element 23 also needs to use the third value when performing the second cyclic shift. Therefore, the first mobile sub-element 21 and the second mobile sub-element 23 both need to obtain the third value for use. Exemplarily, the third value obtaining method provided by the embodiment of the present application includes but is not limited to the following two kinds.

[0131] The first obtaining method is that the first mobile sub-element 21 and the second mobile sub-element 23 respectively store the third value. The first mobile sub-element 21 can store the third value in the local storage of the first mobile sub-element 21, and when the first mobile sub-element 21 needs to use the third value to perform the first cyclic shift, the first mobile sub-element 21 can read the third value stored in the local storage and use it. The second mobile sub-element 23 can store the third value in the local storage of the second mobile sub-element 23, and when the second mobile sub-element 23 needs to use the third value to perform the second cyclic shift, the second mobile sub-element 23 can read the third value stored in the local storage and use it.

[0132] The second obtaining method is that the first mobile sub-element 21 and the second mobile sub-element 23 respectively obtain the third value from the processing element 3. The first mobile sub-element 21 can obtain the third value from the processing element 3 when the first mobile sub-element 21 needs to use the third value to perform the first cyclic shift, and the second mobile sub-element 23 can obtain the third value from the processing element 3 when the second mobile sub-element 23 needs to use the third value to perform the second cyclic shift. Figure 10The storage device further includes a register element 5 (also known as a register), which is connected to the first moving sub-element 21 and the second moving sub-element 23. For example, the register element 5 is in the form of a circuit, which is not limited in the present embodiment. The register element 5 is used to store a third value, which is used by the first moving sub-element 21 to perform the first circular shift and the second moving sub-element 23 to perform the second circular shift.

[0133] When the first moving sub-element 21 needs to use the third value to perform the first cyclic shift, it can read and use the stored third value from the register element 5. When the second moving sub-element 23 needs to use the third value to perform the second cyclic shift, it can read and use the stored third value from the register element 5. In this second acquisition method, since the register element 5 can be used to store the third value, the first moving sub-element 21 and the second moving sub-element 23 do not need to locally store the third value. This reduces the storage capacity requirements for the first moving sub-element 21 and the second moving sub-element 23, and provides greater universality.

[0134] In some embodiments, the value stored in register element 5 does not need to change, indicating that the highest-priority access source among the multiple access sources is not updated. In this embodiment, one of the multiple access sources is defaulted to the highest-priority access source, allowing access requests from that access source to be processed preferentially. In other embodiments, the value stored in register element 5 can change, indicating that the highest-priority access source among the multiple access sources is updated. In this way, multiple access sources can alternately serve as the highest-priority access source, allowing access requests from multiple access sources to be processed preferentially, achieving balanced processing of access requests from different access sources.

[0135] In the exemplary embodiment, for the case where the value stored in the register element 5 can be changed, see Figure 11 The storage device further includes a determining element 6, which is connected to the second moving sub-element 23 and the registering element 5 respectively.

[0136] Determining element 6 is configured to determine a third value based on a fourth bit sequence. The fourth bit sequence is generated by first moving sub-element 21, generating sub-element 22, and second moving sub-element 23. The fourth bit sequence is generated earlier than the second bit sequence. Exemplarily, determining element 6 is in the form of a circuit, which is not limited in this embodiment of the present application.

[0137] That is, in a previous clock cycle, the plurality of access sources respectively send access requests, the identification element 1, the first mobile sub-element 21, the generating sub-element 22 and the second mobile sub-element 23 generate a fourth bit sequence based on the access requests, and the processing element 3 can process the access requests based on the current storage board block and the fourth bit sequence. In a subsequent clock cycle, the plurality of access sources again respectively send access requests, the identification element 1, the first mobile sub-element 21, the generating sub-element 22 and the second mobile sub-element 23 generate a second bit sequence based on the access requests, and the processing element 3 can process the access requests based on the current storage board block and the second bit sequence. Thus, the generation time of the fourth bit sequence is earlier than the generation time of the second bit sequence. Exemplarily, the previous clock cycle can be the last clock cycle of the subsequent clock cycle, and the embodiments of the present application do not limit this. Alternatively, the manner of generating the fourth bit sequence can refer to the manner of generating the second bit sequence as described above, and the embodiments of the present application also do not limit this.

[0138] Since the determining element 6 is connected with the second mobile sub-element 23, the determining element 6 can receive the fourth bit sequence sent by the second mobile sub-element 23, and after determining the third value according to the fourth bit sequence, since the determining element 6 is connected with the register element 5, the determining element 6 can send the third value to the register element 5, so that the register element 5 stores the third value, and then the first mobile sub-element 21 and the second mobile sub-element 23 can subsequently read the third value from the register element 5 and use the third value according to the above description.

[0139] In some embodiments, after the determining element 6 sends the third value to the register element 5, the register element 5 can replace the originally stored value (used by the first mobile sub-element 21 and the second mobile sub-element 23 in the process of generating the fourth bit sequence) with the third value, that is, the register element 5 only stores the third value, so as to facilitate the first mobile sub-element 21 and the second mobile sub-element 23 to read and use the third value subsequently. Alternatively, in other embodiments, after the determining element 6 sends the third value to the register element 5, the register element 5 can store the third value after the originally stored value, that is, the storage address of the third value is located after the storage address of the originally stored value, and then among all the used storage addresses included in the register element 5, the storage address of the third value is located in the last segment of storage addresses among all the used storage addresses, so as to facilitate the first mobile sub-element 21 and the second mobile sub-element 23 to read and use the third value from the last segment of storage addresses subsequently.

[0140] Of course, after the second bit sequence, the determining element 6 can also generate the seventh value according to the second bit sequence, and send the seventh value to the register element 5, so that the register element 5 can store the seventh value, and then the first moving sub-element 21 and the second moving sub-element 23 can read the seventh value from the register element 5 and use it. As can be seen, the value stored in the register element 5 can be updated continuously, and the access source with the highest priority in the plurality of access sources is also updated continuously, thereby realizing balanced processing of the access requests sent by different access sources.

[0141] In the embodiment of the application, the determining element 6 determines the third value according to the fourth bit sequence generated, and the second value can be used in the subsequent process of generating the second bit sequence, thereby realizing dynamic determination of the third value, so that the third value can be dynamically changed. Since the third value is used to indicate the reference access source with the highest priority in the plurality of access sources, the third value is dynamically changed, that is, the reference access source with the highest priority is dynamically updated, and then the plurality of access sources can alternately serve as the reference access source with the highest priority, so that the access requests sent by the plurality of access sources can be alternately processed preferentially, thereby realizing balanced processing of the access requests sent by different access sources.

[0142] In the exemplary embodiment, the determining element 6 includes but is not limited to the following two kinds.

[0143] The first determining element 6, as shown in Figure 12 The determining element 6 includes a third moving sub-element 61 and a conversion sub-element 62 connected in sequence, the third moving sub-element 61 is connected with the second moving sub-element 23, and the conversion sub-element 62 is connected with the register element 5. The third moving sub-element 61 is used to perform third cyclic shift on the fourth bit sequence according to the fourth value to obtain a fifth bit sequence. The conversion sub-element 62 is used to perform format conversion on the fifth bit sequence to obtain the third value. Exemplarily, the third moving sub-element 61 and the conversion sub-element 62 are both in the form of a circuit, and the embodiment of the application does not limit this.

[0144] Since the third moving sub-element 61 is connected with the second moving sub-element 23, the third moving sub-element 61 can receive the fourth bit sequence sent by the second moving sub-element 23, and then perform third cyclic shift on the fourth bit sequence according to the fourth value to obtain the fifth bit sequence. The fourth value can be stored in the third moving sub-element 61 locally. The embodiment of the application does not limit the moving direction of the third cyclic shift and the execution of the fourth value, which can be set according to actual needs.

[0145] Since the third moving sub-element 61 is connected with the conversion sub-element 62, the third moving sub-element 61 can send a fifth bit sequence to the conversion sub-element 62, so that the conversion sub-element 62 performs format conversion on the fifth bit sequence, thereby obtaining a third value. Optionally, the fifth bit sequence is one-hot code, and the third value is binary code, and the format conversion performed by the conversion sub-element 62 includes one-hot code to binary code (oh2bin).

[0146] For example, the fourth value is 1, the third cyclic shift is a cyclic left shift (i.e., the moving direction is left), and the fourth bit sequence is 010, 0, 1 and 0 are three different bits. In the fourth bit sequence 010, the rightmost 0 represents that the access source 0 is not authorized to access the current storage board, the middle 1 represents that the access source 1 is authorized to access the current storage board, and the leftmost 0 represents that the access source 2 cannot access the current storage board. After the fourth bit sequence 010 is cyclically left shifted by 1 bit, the obtained fifth bit sequence is 100, 1, 0 and 0 are three different bits. The process in which the third moving sub-element 61 cyclically left shifts the fourth bit sequence 010 to obtain the fifth bit sequence 100 can be referred to the process in which the second moving sub-element 23 cyclically left shifts the third bit sequence 010 to obtain the second bit sequence 100, which is described above, and will not be repeated here. The third moving sub-element 61 can send the fifth bit sequence 100 to the conversion sub-element 62.

[0147] After the conversion sub-element 62 receives the fifth bit sequence 100 sent by the third moving sub-element 61, the conversion sub-element 62 performs format conversion on the fifth bit sequence 100 to obtain a binary code (i.e., the third value) of 10, which is 2 in decimal, representing that the reference access source with the highest priority in the subsequent (for example, the next clock cycle) multiple access sources is the access source 2. Therefore, the next access source (i.e., the access source 2) of the access source (i.e., the access source 1) currently authorized to access the storage board is taken as the reference access source with the highest priority in the subsequent, and different access sources can take turns as the reference access source with the highest priority, so that different access sources can take turns to access the current storage board. Wherein, the access source currently authorized to access the storage board is represented as access source i, and the reference access source with the highest priority in the subsequent is represented as (i+1)%(N+1), % represents the modulus operator, and N+1 represents the total number of multiple access sources.

[0148] In the embodiments of the present application, the determination of the third value is realized through the cooperation of the third moving sub-element 61 and the conversion sub-element 62, and this implementation method is simple, fast, easy to hardware implementation, and has strong universality and practical value.

[0149] The second determining element 6 is a random number generator, which triggers the determination of the third value in the case of receiving the fourth bit sequence. In the case of multiple access sources including the access source 0 to the access source N, the value range of the random number generator is 0 to N. The random number generator can randomly select a value in 0 to N as the third value and send the third value to the register element 5.

[0150] In combination Figure 13 Taking the control circuit 0 and the storage block 0 in the storage device as an example, the process of processing the access request by the storage device is illustrated. Wherein, the first value and the second value are 1, the fifth value and the sixth value are 0, the first moving sub-element is used to perform the cyclic right shift, and the second moving sub-element is used to perform the cyclic left shift. In the current clock cycle, the third value stored in the register element is 1, which represents that the reference access source with the highest priority in the multiple access sources is the access source 1, and the priorities of the access source 1, the access source 2 and the access source 0 are successively reduced.

[0151] In the control circuit 0, the three identification sub-elements identify the access request 1, the access request 2 and the access request 3 respectively, and obtain the first bit sequence 101. In the first bit sequence 101, the right 1 indicates that the access source 0 requests to access the current storage block 0, the middle 0 indicates that the access source 1 does not request to access the current storage block 0, and the left 1 indicates that the access source 2 requests to access the current storage block 0.

[0152] The first moving sub-element performs the cyclic right shift on the first bit sequence 101 with a shift amount of 1, and obtains the first bit sequence 110 after the cyclic right shift, so that the value 0 corresponding to the access source 1 with the highest priority is at the rightmost end of the first bit sequence 110. The generating sub-element starts to query from the rightmost end, and obtains the first value 1, that is, the value 1 in the middle of 110, thereby generating the third bit sequence 010. The second moving sub-element performs the cyclic left shift on the third bit sequence 010 with a shift number of 1, and obtains the second bit sequence 100, which represents that the access source 2 is authorized to access the current storage block 0. Therefore, the processing element processes the access request sent by the access source 2 according to the second bit sequence 100.

[0153] In addition, the third moving sub-element performs the cyclic left shift on the second bit sequence 100 with a shift amount of 1, and obtains the bit sequence 001. The conversion sub-element performs the format conversion on the bit sequence 001, and obtains the binary code 0. The value stored in the register element is updated from 1 to 0, which represents that the reference access source with the highest priority in the multiple access sources is updated from the access source 1 to the access source 0 in the next clock cycle. The access source 0 is the next access source of the access source 2 which is currently authorized to access the current storage block 0.

[0154] For example, embodiments of the present application are applicable to scenarios where an access source requires linearly incremental access. For an access source, linearly incremental access means that the access source requests access to storage block 0 in the first clock cycle, requests access to storage block 1 in the second clock cycle, requests access to storage block 2 in the third clock cycle, requests access to storage block 0 in the fourth clock cycle, and so on.

[0155] based on Figure 6 The address range of the memory block 4 shown is shown in Figure 14 Taking the priority of access source 0, access source 1, and access source 2 as an example, the storage device provided by the embodiment of the present application processes access requests, which can achieve the following:

[0156] In the first clock cycle, access source 0 accesses storage block 0;

[0157] In the second clock cycle, access source 0 accesses storage block 1, and access source 1 accesses storage block 0, which is equivalent to delaying the access request sent by access source 1 to access storage block 0 by one clock cycle;

[0158] In the third clock cycle, access source 0 accesses storage block 2, access source 1 accesses storage block 1, and access source 2 accesses storage block 0. This is equivalent to delaying the access request sent by access source 2 to access storage block 0 by two clock cycles.

[0159] In the fourth clock cycle, access source 0 accesses storage block 0, access source 1 accesses storage block 2, and access source 2 accesses storage block 1;

[0160] In the fifth clock cycle, access source 1 accesses storage block 0, and access source 2 accesses storage block 2;

[0161] In the sixth clock cycle, access source 2 accesses storage block 0.

[0162] According to the access situation in the above six clock cycles, it can be seen that in the first clock cycle to the third clock cycle, the access requests of access source 0, access source 1 and access source 2 to storage block 0 are staggered, and then in the subsequent clock cycles, different access sources access different storage blocks in parallel, so that the storage device has better performance.

[0163] In summary, the storage device provided by the embodiment of the present application comprises the identification element, the generating element, the processing element and the storage block connected in sequence. After the access requests are sent by the plurality of access sources respectively, the first bit sequence can be obtained by identifying the access requests through the identification element. Whether the corresponding access source requests to access the current storage block can be determined according to each bit in the first bit sequence. Then, the second bit sequence can be generated according to the first bit sequence through the generating element, so that which access source is authorized to access the current storage block can be determined according to each bit in the second bit sequence, and the access source authorized to access the current storage block is determined in the case that at least one access source of the plurality of access sources requests to access the current storage block. Then, the access request is processed based on the storage block through the processing element, and the processed access request is sent by the access source authorized to access the current storage block, so that the access of the storage block by the access source authorized to access the current storage block is realized. Therefore, the different access sources are prevented from accessing the current storage block at the same time, so that the storage block conflict is avoided.

[0164] The process can be realized based on the elements included in the storage device, and each element is hardware, for example, a circuit, without relying on the allocation program manually written by the programmer, so that the burden of the programmer is reduced, and the process is more flexible and is not affected by the error of the programmer, and the accuracy of processing the access request is ensured. In addition, the process only needs a short time to complete the processing of the access request sent by the access source, so that the access time delay of the storage device is short, the performance of the storage device is improved, and the access request can be quickly processed based on the storage device. In addition, the volume of each element provided by the embodiment of the present application is small, and each element and the storage block are integrated into a chip, and the chip also has a small volume, so that the application range of the chip is wide, and the product competitiveness of the chip is improved.

[0165] The embodiment of the present application can also indicate the access source with the highest priority in the plurality of access sources through the value stored by the register element, and the value stored by the register element can be changed through the determining element, so that the access source with the highest priority in the plurality of access sources is updated. The plurality of access sources can be alternately used as the access source with the highest priority, so that the access requests sent by the plurality of access sources can be alternately processed preferentially, and the balanced processing of the access requests sent by different access sources is realized.

[0166] The embodiment of the present application also provides a method for processing an access request, which can be applied to the storage device described above, and the storage device comprises the identification element, the generating element, the processing element and the storage block connected in sequence. As shown in the method, the method comprises the following steps 1501 to 1503. Figure 15

[0167] ​Step 1501, the access requests respectively sent by the plurality of access sources are identified by the identifying element to obtain a first bit sequence, each bit in the first bit sequence corresponds to one of the plurality of access sources, and a bit with a first value is used to indicate that the corresponding access source requests to access the storage board.

[0168] Step 1502, in a case where at least one bit in the first bit sequence has the first value, a second bit sequence is generated by the generating element, each bit in the second bit sequence corresponds to one of the plurality of access sources, one bit in the second bit sequence has a second value, and the bit with the second value is used to indicate that the corresponding access source is authorized to access the storage board.

[0169] In an exemplary embodiment, the generating element comprises a first moving sub-element, a generating sub-element and a second moving sub-element connected in sequence, the first moving sub-element is connected with the identifying element, and the second moving sub-element is connected with the processing element. Accordingly, the implementation of the step 1502 comprises: performing, by the first moving sub-element, a first cyclic shift on the first bit sequence according to a third value, so that the bit corresponding to a reference access source with the highest priority in the plurality of access sources is at a first end of the first bit sequence, and the third value is used to indicate the reference access source; in a case where at least one bit in the first bit sequence has the first value, the generating sub-element queries the bit with the first value in the first bit sequence based on the first end, and generates a third bit sequence according to the queried bit, and a bit in the third bit sequence corresponding to the queried bit has the second value; and performing, by the second moving sub-element, a second cyclic shift on the third bit sequence according to the third value to obtain the second bit sequence, and the moving direction of the second cyclic shift is opposite to that of the first cyclic shift.

[0170] Optionally, the querying direction is from the first end to a second end of the first bit sequence, and the queried bit is a first bit with the first value in the first bit sequence; and the querying direction is from the second end to the first end, and the queried bit is a last bit with the first value in the first bit sequence.

[0171] Exemplarily, the storage device further comprises a register element connected with the first moving sub-element and the second moving sub-element respectively. The method provided by the embodiments of the present application further comprises: storing, by the register element, the third value, and the third value is used for the first moving sub-element to perform the first cyclic shift, and the third value is also used for the second moving sub-element to perform the second cyclic shift.

[0172] In an example embodiment, the storage device further includes a determining element connected to the second moving sub-element and the register element respectively. The method provided in the embodiments of the present application further includes: generating, by the first moving sub-element, the generating sub-element and the second moving sub-element, a fourth bit sequence, the generation time of the fourth bit sequence being earlier than the generation time of the second bit sequence; and determining, by the determining element, the third value according to the fourth bit sequence.

[0173] For example, the determining element includes a third moving sub-element and a conversion sub-element connected in sequence, the third moving sub-element being connected to the second moving sub-element, and the conversion sub-element being connected to the register element. The determining, by the determining element, of the third value according to the fourth bit sequence includes: performing, by the third moving sub-element, third cyclic shifting on the fourth bit sequence according to a fourth value to obtain a fifth bit sequence; and performing, by the conversion sub-element, format conversion on the fifth bit sequence to obtain the third value.

[0174] At step 1503, the processing element processes, based on the storage board, an access request sent by an access source corresponding to the bit with the second value.

[0175] The implementation manners and technical effects of steps 1501, 1502 and 1503 can be referred to the foregoing description Figures 2 to 14 For the corresponding description, details are not described herein.

[0176] In an example embodiment, the embodiments of the present application provide a storage system, which includes a plurality of storage devices provided in the embodiments of the present application. The storage system has good performance and is conducive to parallel access. The storage system can provide data storage function (for persistent storage of data, or non-persistent storage of data) and access request processing function. For example, the storage system can be independently applied, or can be applied in a processor (for example, an AI processor) or the like. In the case where the storage system is applied in a processor or the like, since the storage system itself has high performance, the overall performance of the processor or the like can also be improved.

[0177] For example, the embodiments of the present application provide a processor, which includes a plurality of access sources and at least one storage device provided in the embodiments of the present application. For example, the access source is a processing core. The processor belongs to a chip.

[0178] In an example embodiment, as Figure 16 shown in the figure, the embodiments of the present application further provide a computer device 1600, which includes a processor 1601 and a memory 1602, wherein the processor 1601 is a processor provided in the embodiments of the present application, or the memory 1602 includes at least one storage device provided in the embodiments of the present application. For example, the computer device can be a terminal or a server.

[0179] It should be noted that the information (including but not limited to user equipment information, user personal information, etc.), data (including but not limited to data for analysis, stored data, displayed data, etc.) and signals involved in the present application are all authorized by the user or fully authorized by all parties, and the collection, use and processing of related data need to comply with relevant laws, regulations and standards of relevant countries and regions. For example, the access request and the bit sequence involved in the present application are obtained under sufficient authorization. It should be understood that "multiple" mentioned in the present application refers to two or more. The character " / " generally represents that the associated objects before and after it are in an "or" relationship. The above-mentioned serial numbers of the embodiments of the present application are only for description, and do not represent the advantages and disadvantages of the embodiments.

[0180] The above only describes exemplary embodiments of the present application and does not limit the present application. Any modification, equivalent replacement, improvement, etc. made within the principles of the present application shall be included in the protection scope of the present application.

Claims

1. A memory device, comprising: The storage device comprises identification element (1), generating element (2), processing element (3) and storage board (4) connected in sequence; The identification element (1) is used for identifying access requests sent by a plurality of access sources respectively, obtaining a first bit sequence, each bit in the first bit sequence corresponds to one of the plurality of access sources, and the bit with a first value is used to indicate that the corresponding access source requests to access the storage board (4); The generating element (2) is used for generating a second bit sequence in the case that at least one bit in the first bit sequence has the first value, each bit in the second bit sequence corresponds to one of the plurality of access sources, and one bit in the second bit sequence has a second value, and the bit with the second value is used to indicate that the corresponding access source is authorized to access the storage board (4); The processing element (3) is used for processing access requests sent by the access source corresponding to the bit with the second value based on the storage board (4).

2. The memory device of claim 1, wherein, The generating element (2) comprises first moving sub-element (21), generating sub-element (22) and second moving sub-element (23) connected in sequence, the first moving sub-element (21) is connected with the identification element (1), and the second moving sub-element (23) is connected with the processing element (3); The first moving sub-element (21) is used for performing first circular movement on the first bit sequence according to a third value, so that the bit corresponding to the reference access source is at the first end of the first bit sequence, and the third value is used to indicate that the reference access source with the highest priority in the plurality of access sources; The generating sub-element (22) is used for obtaining a bit with the first value based on the first end in the first bit sequence in the case that at least one bit in the first bit sequence has the first value, generating a third bit sequence according to the obtained bit, and one bit in the third bit sequence corresponding to the obtained bit has the second value; The second moving sub-element (23) is used for performing second circular movement on the third bit sequence according to the third value, to obtain the second bit sequence, and the moving direction of the second circular movement is opposite to that of the first circular movement.

3. The memory device of claim 2, wherein, The storage device further comprises register element (5), and the register element (5) is connected with the first moving sub-element (21) and the second moving sub-element (23) respectively; The register element (5) is used for storing the third value, and the third value is used for the first moving sub-element (21) to perform the first circular movement, and the third value is also used for the second moving sub-element (23) to perform the second circular movement.

4. The memory device of claim 3, wherein, The storage device further comprises determination element (6), and the determination element (6) is connected with the second moving sub-element (23) and the register element (5) respectively; The determining element (6) is configured to determine the third value according to a fourth bit sequence, the fourth bit sequence being generated by the first moving sub-element (21), the generating sub-element (22) and the second moving sub-element (23), and the generation time of the fourth bit sequence being earlier than the generation time of the second bit sequence.

5. The memory device of claim 4, wherein, The determining element (6) comprises a third moving sub-element (61) and a conversion sub-element (62) connected in sequence, the third moving sub-element (61) being connected with the second moving sub-element (23), and the conversion sub-element (62) being connected with the register element (5). The third moving sub-element (61) is configured to perform third cyclic shift on the fourth bit sequence according to a fourth value to obtain a fifth bit sequence. The conversion sub-element (62) is configured to perform format conversion on the fifth bit sequence to obtain the third value.

6. The storage device according to any one of claims 2-5, wherein: the direction of the query is from the first end to the second end of the first bit sequence, and the bit obtained by the query is the first bit having the first value in the first bit sequence; the direction of the query is from the second end to the first end, and the bit obtained by the query is the last bit having the first value in the first bit sequence.

7. A method of processing an access request, characterized by, The method is applied to a storage device comprising an identification element, a generating element, a processing element and a storage board connected in sequence, and the method comprises: identifying access requests respectively sent by a plurality of access sources through the identification element to obtain a first bit sequence, each bit in the first bit sequence corresponding to one of the plurality of access sources, and a bit having a first value being used to indicate that the corresponding access source requests to access the storage board; generating a second bit sequence by the generating element in the case that at least one bit in the first bit sequence has the first value, each bit in the second bit sequence corresponding to one of the plurality of access sources, and a bit having a second value in the second bit sequence being used to indicate that the corresponding access source is authorized to access the storage board; processing, by the processing element, an access request sent by the access source corresponding to the bit having the second value based on the storage board.

8. The method of claim 7, wherein, The generating element comprises a first moving sub-element, a generating sub-element and a second moving sub-element connected in sequence, the first moving sub-element being connected with the identification element, and the second moving sub-element being connected with the processing element; The generating, by the generating element, of the second bit sequence in the case that at least one bit in the first bit sequence has the first value comprises: performing, by the first moving sub-element, first cyclic shift on the first bit sequence according to a third value, so that a bit corresponding to a reference access source is at a first end of the first bit sequence, the third value being used to indicate the reference access source having the highest priority among the plurality of access sources. the third bit sequence is generated according to the obtained bit, the bit in the third bit sequence corresponding to the obtained bit has the second value, by the generating sub-element, under the condition that at least one bit in the first bit sequence has the first value, the first end inquires the first bit sequence to obtain a bit having the first value, and the third bit sequence is generated according to the obtained bit; the second bit sequence is obtained by the second moving sub-element performing a second cyclic shift on the third bit sequence according to the third value, the moving direction of the second cyclic shift being opposite to the moving direction of the first cyclic shift.

9. The method of claim 8, wherein, The storage device further comprises a register element connected to the first moving sub-element and the second moving sub-element respectively. The method further comprises: the third value is stored by the register element, the third value being used for the first moving sub-element to perform the first cyclic shift, and the third value being used for the second moving sub-element to perform the second cyclic shift.

10. The method of claim 9, wherein, The storage device further comprises a determining element connected to the second moving sub-element and the register element respectively. The method further comprises: a fourth bit sequence is generated by the first moving sub-element, the generating sub-element and the second moving sub-element, the generation time of the fourth bit sequence being earlier than the generation time of the second bit sequence; the third value is determined by the determining element according to the fourth bit sequence.

11. The method of claim 10, wherein, The determining element comprises a third moving sub-element and a conversion sub-element connected in sequence, the third moving sub-element being connected to the second moving sub-element, and the conversion sub-element being connected to the register element. The third value is determined by the determining element according to the fourth bit sequence, comprising: a fifth bit sequence is obtained by the third moving sub-element performing a third cyclic shift on the fourth bit sequence according to a fourth value; the third value is obtained by the conversion sub-element performing format conversion on the fifth bit sequence.

12. The method according to any one of claims 7-11, wherein the direction of the inquiry is from the first end to a second end of the first bit sequence, and the obtained bit is the first bit having the first value in the first bit sequence; the direction of the inquiry is from the second end to the first end, and the obtained bit is the last bit having the first value in the first bit sequence.

13. A storage system, characterized by The storage system comprises a plurality of storage devices according to any one of claims 1-6.

14. A processor, comprising: The processor comprises a plurality of access sources and at least one storage device according to any one of claims 1-6.

15. A computer device, comprising: The computer device comprises a memory and a processor, wherein the memory comprises at least one storage device according to any one of claims 1-6, or the processor is the processor according to claim 14.

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