Arithmetic logic unit parallel processing system, method, and electronic device

Abstract

The application provides an arithmetic logic unit parallel processing system, method and electronic equipment, and relates to the chip architecture processing field.The arithmetic logic unit parallel processing system comprises an instruction emission unit, a write-back unit and a plurality of ALU groups comprising a plurality of arithmetic logic units.The instruction emission unit is connected with the input end of each ALU group.The output end of each ALU group is connected with the write-back unit.The input end of each ALU group is connected with the input end of all arithmetic logic units in the current ALU group.The output end of each ALU group is connected with the output end of all arithmetic logic units in the current ALU group.The scheme can use the same arithmetic logic operation component to realize reduction instructions and vector arithmetic logic operations, reduces the number and area of the vector arithmetic logic operation component and improves the utilization rate of the vector arithmetic logic operation component.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of chip architecture processing, in particular to an arithmetic logic unit parallel processing system, method and electronic equipment. BACKGROUND

[0002] Vector arithmetic logic operation components usually contain a plurality of scalar operation components with the same number of elements in the vector operand, so that one arithmetic logic operation instruction can be sent to the operation component for operation every clock cycle. On this basis, there are two common schemes for vector reduction instructions:

[0003] 1. Add one or several scalar logic operation components to perform reduction calculation;

[0004] 2. Hardware converts the reduction instruction into a plurality of vector arithmetic logic instructions to reuse the arithmetic logic operation component.

[0005] However, in actual scenarios, scheme 1 increases the number of the same operation components, reducing the utilization rate of the operation components; and scheme 2 cannot fully utilize the computing power of the operation components due to the natural data dependency of the reduction instruction, and increases the number of instructions in the pipeline, causing the utilization rate of other operation components to also decrease. SUMMARY

[0006] Therefore, the purpose of the present application is to provide an arithmetic logic unit parallel processing system, method and electronic equipment, which can use the same arithmetic logic operation component to implement reduction instructions and vector arithmetic logic operations, reduce the number and area of vector arithmetic logic operation components, and improve the utilization rate of vector arithmetic logic operation components.

[0007] In a first aspect, an embodiment of the present application provides an arithmetic logic unit parallel processing system, which comprises an instruction sending unit, a write-back unit and a plurality of ALU groups comprising a plurality of arithmetic logic units;

[0008] The input end of each ALU group is connected to the input end of each ALU group, and the output end of each ALU group is connected to the write-back unit.

[0009] The input end of each ALU group is connected to the input end of each arithmetic logic unit in the current ALU group, and the output end of each ALU group is connected to the output end of each arithmetic logic unit in the current ALU group.

[0010] The instruction sending unit is configured to send a vector processing instruction to the corresponding ALU group.

[0011] The ALU group is configured to call the corresponding arithmetic logic unit according to the corresponding operand of the received vector processing instruction to process the vector processing instruction.

[0012] The write-back unit is configured to aggregate the processing results output by each ALU group and return the aggregated results to the target unit corresponding to the vector processing instruction.

[0013] Optionally, the arithmetic logic unit parallel processing system further comprises an intra-group register, which is arranged in each ALU group.

[0014] The input end of the intra-group register is connected to the output end of each arithmetic logic unit in the current ALU group.

[0015] The input end of the intra-group register is also connected to the input end of the ALU group.

[0016] The output end of the intra-group register is connected to the input end of each arithmetic logic unit in the current ALU group.

[0017] The intra-group register is configured to store the calculation results of the arithmetic logic units in the ALU group.

[0018] Optionally, the arithmetic logic unit parallel processing system further comprises an intra-group multiplexer, which is arranged in each ALU group and connected to the corresponding arithmetic logic unit.

[0019] The output end of each intra-group multiplexer is connected to the input end of the corresponding arithmetic logic unit, and the input end of each intra-group multiplexer is connected to the output end of the intra-group register.

[0020] The intra-group multiplexer is configured to determine the arithmetic logic unit to be called in the current ALU group according to the calculation results stored in the intra-group register.

[0021] Optionally, the arithmetic logic unit parallel processing system further comprises an inter-group multiplexer, which is arranged between the write-back unit and the ALU group.

[0022] The input end of the inter-group multiplexer is connected to the output end of each ALU group, and the output end of the inter-group multiplexer is connected to the input end of the write-back unit.

[0023] The inter-group multiplexer is configured to aggregate the processing results output by each ALU group and determine the target unit corresponding to the aggregated results.

[0024] Optionally, the arithmetic logic unit parallel processing system further comprises an inter-group register, which is arranged between the instruction issuing unit and the ALU group.

[0025] The input end of the inter-group register is connected to the output end of the instruction issuing unit, and the output end of the inter-group register is connected to the input end of each ALU group.

[0026] The out-of-group register is used to determine corresponding operands according to the received vector processing instruction.

[0027] Optionally, the instruction emission unit is provided with a delay emission module.

[0028] The output end of the delay emission module is connected with the input end of the out-of-group register, and the delay emission module is used to send the vector processing instruction to the out-of-group register according to the delay strategy determined according to the type of the vector processing instruction; wherein the vector processing instruction at least includes vector arithmetic logic instruction and vector reduction instruction.

[0029] In the second aspect, the present application provides an arithmetic logic unit parallel processing method, which is applied to the arithmetic logic unit parallel processing system mentioned in the first aspect; the arithmetic logic unit parallel processing system at least includes: an instruction emission unit, a write-back unit and a plurality of ALU groups containing a plurality of arithmetic logic units.

[0030] The method includes:

[0031] Obtaining the type parameter of the corresponding vector processing instruction in the instruction emission unit, and determining the delay processing strategy corresponding to the vector processing instruction based on the type parameter;

[0032] Using the delay processing strategy to control the instruction emission unit to send the vector processing instruction to the corresponding ALU group, and control the arithmetic logic unit in the ALU group to respond to the vector processing instruction;

[0033] Controlling the write-back unit to summarize the processing results output by each ALU group, and calling back the summarized results to the target unit corresponding to the vector processing instruction.

[0034] Optionally, determining the delay processing strategy corresponding to the vector processing instruction based on the type parameter includes:

[0035] If the type parameter corresponds to the vector arithmetic logic instruction, the delay time of the arithmetic logic unit is calculated according to the element number s of the corresponding operand of the vector arithmetic logic instruction, the number m of the arithmetic logic unit in each ALU group and the total number n of the arithmetic logic unit; wherein the delay time is ceil(s / m) / (n / m); ceil is the upward rounding calculation;

[0036] Determining the delay processing strategy corresponding to the vector processing instruction based on the delay time.

[0037] Optionally, determining the delay processing strategy corresponding to the vector processing instruction based on the type parameter includes:

[0038] If the type parameter corresponds to a vector reduction instruction, a delay time of the arithmetic logic unit is calculated according to the element number s of the operand corresponding to the vector reduction instruction and the total number n of the arithmetic logic units; wherein the delay time is ceil(s / n); and ceil is a ceiling calculation;

[0039] A delay processing strategy corresponding to the vector processing instruction is determined based on the delay time.

[0040] In a third aspect, an electronic device is provided, which includes a processor and a memory. The memory stores computer executable instructions that are executable by the processor. The processor executes the computer executable instructions to implement the steps of the arithmetic logic unit parallel processing method of the second aspect.

[0041] In a fourth aspect, a storage medium is provided, which stores computer executable instructions. When the computer executable instructions are invoked and executed by a processor, the computer executable instructions cause the processor to implement the steps of the arithmetic logic unit parallel processing method of the second aspect.

[0042] The arithmetic logic unit parallel processing system, method and electronic device provided by the embodiments of the present application can use the same arithmetic logic operation component to implement the reduction instruction and the vector arithmetic logic operation, reduce the number and area of the vector arithmetic logic operation component, and improve the utilization rate of the vector arithmetic logic operation component.

[0043] Other features and advantages of the present application will be further apparent from the following detailed description, and to some extent, will be apparent from the drawings. The purposes and other advantages of the present application can be realized and obtained by the structure particularly pointed out in the description, claims and drawings.

[0044] In order to make the above objectives, features and advantages of the present application more apparent, the following will specifically describe preferred embodiments of the present application with reference to the accompanying drawings. Attached Figure Description

[0045] To more clearly illustrate the specific embodiments of the present invention or the technical solutions in the prior art, the drawings used in the description of the specific embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained from these drawings without creative effort.

[0046] Figure 1 This is a schematic diagram illustrating the interaction between reduction instructions and arithmetic logic instructions in the prior art, provided as an embodiment of the present invention.

[0047] Figure 2 A schematic diagram of the structure of a parallel processing system for arithmetic logic units provided in an embodiment of the present invention;

[0048] Figure 3 A schematic diagram of another parallel processing system for arithmetic logic units provided in an embodiment of the present invention;

[0049] Figure 4 A flowchart of a parallel processing method for arithmetic logic units provided in an embodiment of the present invention;

[0050] Figure 5 A flowchart illustrating the delay processing strategy for determining vector processing instructions based on type parameters in a parallel processing method for arithmetic logic units provided in this embodiment of the invention;

[0051] Figure 6 A flowchart illustrating the delay processing strategy for determining vector processing instructions based on type parameters in another parallel processing method for arithmetic logic units provided in an embodiment of the present invention.

[0052] Figure 7 This is a schematic diagram of the structure of an electronic device provided in an embodiment of the present invention.

[0053] icon:

[0054] 100 - Command issue unit; 200 - Write-back unit; 300 - ALU group; 400 - Intra-group register; 500 - Intra-group multiplexer; 600 - Out-of-group multiplexer; 700 - Out-of-group register; 800 - Delayed issue module;

[0055] 101 - Processor; 102 - Memory; 103 - Bus; 104 - Communication interface. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the present invention will be clearly and completely described below in conjunction with the embodiments. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0057] Vector arithmetic logic unit (ALU) typically contains multiple scalar arithmetic units, the same number of elements as the vector operands. This allows the pipeline to issue one arithmetic logic instruction to the ALU for computation per cycle. Based on this, there are generally two schemes for vector reduction instructions:

[0058] 1. Add one or more scalar logic units specifically for reduction calculations;

[0059] 2. The hardware converts the reduction instructions into multiple vector arithmetic logic instructions, reusing the arithmetic logic operation unit.

[0060] However, in real-world scenarios, Option 1 would increase the number of the same computing units, reducing their utilization rate. Option 2, due to the inherent data dependency of the reduction instructions, would also fail to fully utilize the computing power of the computing units and would increase the number of instructions on the pipeline, causing the utilization rate of other computing units to decrease as well.

[0061] The RISC-V V Extension includes a reduction instruction that reduces the elements 0 of source operand 1 and all elements of source operand 2 through arithmetic and logical operations, ultimately resulting in a single element written to element 0 of the destination operand. Specifically... Figure 1 As shown, assuming each source operand of an instruction has four elements, the pipeline includes an arithmetic logic unit (ALU) for calculating ordinary vector arithmetic logic instructions. Converting the reduction instruction for addition into a vector arithmetic logic instruction results in three instructions. Due to dependencies between operands, the first instruction can only calculate the partial sums psum0 and psum1, meaning it can only utilize two of the four ALUs. The second and third instructions calculate the partial sum psum2 and the final result sum, respectively, each utilizing only one ALU. psum is short for path sum, a node counting process in a binary tree data structure.

[0062] Based on this, the present invention provides a parallel processing system, method and electronic device for arithmetic logic units. This solution can use the same arithmetic logic operation unit to implement reduction instructions and vector arithmetic logic operations, reduce the number and area of ​​vector arithmetic logic operation units, and improve the utilization rate of vector arithmetic logic operation units.

[0063] To facilitate the understanding of the present embodiment, first of all, a kind of arithmetic logic unit parallel processing system disclosed in the embodiment of the application is introduced in detail, as shown in Figure 2 The arithmetic logic unit parallel processing system includes instruction transmitting unit 100, write-back unit 200 and multiple ALU groups 300 containing several arithmetic logic units.

[0064] Wherein, instruction transmitting unit 100 is connected with the input end of each ALU group 300 respectively;The output end of each ALU group 300 is connected with write-back unit;The input end of each ALU group 300 is connected with the input end of all arithmetic logic units in the current ALU group 300 respectively;The output end of each ALU group 300 is connected with the output end of all arithmetic logic units in the current ALU group 300 respectively.

[0065] Instruction transmitting unit 100 is used to send vector processing instruction to corresponding ALU group 300;ALU group 300 is used to call corresponding arithmetic logic unit to process vector processing instruction according to the corresponding operand of received vector processing instruction;Write-back unit 200 is used to summarize the processing result output by each ALU group 300, and call the summary result back to the target unit corresponding to vector processing instruction.

[0066] Specifically, the arithmetic logic unit parallel processing system is a kind of hardware architecture for efficient vector operation, and the core design is through modular grouping and parallel cooperation mechanism, which greatly improves the execution efficiency of vector processing instruction. The system is mainly composed of three key modules: instruction transmitting unit 100, write-back unit 200 and multiple ALU groups 300 containing several arithmetic logic units (ALU), and each module forms a closed loop of collaborative work through a specific connection relationship.

[0067] From the hardware connection relationship, instruction transmitting unit 100 as the instruction center of the system is directly connected with the input end of each ALU group 300, which ensures that the instruction can be accurately and efficiently distributed to the target processing unit. At the same time, the output end of each ALU group 300 is connected with write-back unit 200, which provides a channel for the summary and return of processing result. While in ALU group 300, its input end is connected with the input end of all arithmetic logic units in the group, and the output end also collects the output signals of all ALUs in the group. This internal interconnection design makes a single ALU group can be used as a collaborative processing unit, and flexibly schedules the resources in the group to respond to instructions.

[0068] In terms of functionality, each module has a clear division of labor and works closely together. The core function of the instruction issuing unit 100 is instruction distribution and scheduling. It receives vector processing instructions from the upper-layer system (these instructions usually require performing the same or similar operations on a set of data, such as vector addition and multiplication), and determines which ALU group should process the instruction based on information such as the operation type and data size. Then, it accurately sends the instruction to the corresponding ALU group 300. In this process, it may also be responsible for the initial decoding of the instruction, clarifying key information such as the operation type and operand source, providing a basis for the ALU group's processing.

[0069] The ALU group 300 serves as the system's computational core, undertaking specific vector operation processing tasks. Upon receiving a vector processing instruction, it schedules the corresponding arithmetic logic unit within the group to participate in the operation based on the operands specified in the instruction (which may come from registers, memory, or other storage units). For example, if the instruction requires addition to a vector containing 8 elements, all 8 ALUs in the group can start simultaneously, processing one element of the vector respectively, achieving data-level parallelism. This parallel processing mode can significantly shorten the total time of vector operations and improve system throughput.

[0070] Write-back unit 200 plays the role of summarizing and returning results. It collects the operation results output by each ALU group 300 (these results may be the processed values ​​of each element of the vector), summarizes and integrates them according to the format required by the instruction (such as reorganizing them into a complete vector result), and finally returns the summarized results to the target unit specified by the vector processing instruction (which may be a register group, main memory, or other operation unit that needs the result), ensuring that the operation results are correctly reused.

[0071] like Figure 3 The diagram shows the structure of another parallel processing system for arithmetic logic units. Figure 3 The ALU in the text corresponds to the arithmetic and logic unit (ALU). Figure 3 The system divides n scalar arithmetic units into n / m groups (s, n, m are usually powers of 2), and each group can independently compute a vector reduction instruction or a vector arithmetic logic instruction. Registers are added to the vector arithmetic logic unit to store uncomputed source operands and partial results.

[0072] Optionally, the arithmetic logic unit parallel processing system further comprises: an intra-group register 400; the intra-group register 400 is arranged in each ALU group 300; wherein, the input end of the intra-group register 400 is connected with the output end of all arithmetic logic units ALU in the current ALU group 300 respectively; the input end of the intra-group register 400 is also connected with the input end of the ALU group 300; the output end of the intra-group register 400 is connected with the input end of all arithmetic logic units ALU in the current ALU group 300 respectively; and the intra-group register 400 is used for storing the calculation results corresponding to the arithmetic logic units ALU in the ALU group 300.

[0073] The intra-group register 400 is a key storage component inside each ALU group 300, and its connection relationship embodies the data closed-loop design: on the one hand, its input end is directly connected with the output end of all arithmetic logic units (ALU) in the group, and can store the calculation results of each ALU in real time; on the other hand, its input end is also connected with the total input end of the ALU group 300, and can receive the initial data or intermediate parameters transmitted from outside; at the same time, its output end is connected with the input end of all ALU in the group, and provides data support for subsequent operation. The core value of this design lies in reducing data access delay and repeated calculation. In multi-step vector operation (such as vector multiplication followed by addition), the intermediate results of the ALU do not need to be transmitted back and forth through external storage (such as main memory), but can be directly reused through the intra-group register 400, greatly shortening the data flow path. For example, when the ALU group executes a composite instruction of vector multiplication followed by addition, the result of the multiplication ALU can be temporarily stored in the intra-group register, and the addition ALU directly reads data from the register for operation, avoiding the bandwidth occupation of the external bus, and improving the continuity of the intra-group operation.

[0074] Optionally, the arithmetic logic unit parallel processing system further comprises: an intra-group multiplexer 500; the intra-group multiplexer 500 is arranged in each ALU group; and each intra-group multiplexer 500 is connected with the corresponding arithmetic logic unit ALU. Wherein, the output end of each intra-group multiplexer 500 is connected with the input end of the corresponding arithmetic logic unit ALU respectively; the input end of each intra-group multiplexer 500 is connected with the output end of the intra-group register 400; and the intra-group multiplexer 500 is used for determining the arithmetic logic unit to be called in the current ALU group according to the calculation results stored in the intra-group register 400.

[0075] The intra-group multiplexer 500 provides precise resource switching for each ALU in the ALU group 300, with its input end connected to the output end of the intra-group register 400 and its output end connected to the input end of the corresponding ALU. Its core function is to dynamically select the ALU to be called according to the calculation result stored in the intra-group register 400. In actual operation, the processing of a vector instruction can involve multiple iterations or conditional branching (such as selecting addition or subtraction operation according to the intermediate result). For example, when a certain intermediate result stored in the intra-group register is negative, the intra-group multiplexer can trigger the ALU for taking absolute value according to this result, while other elements with positive results continue to use the regular addition ALU. This dynamic scheduling mechanism based on data enables the ALU group 300 to flexibly allocate resources according to real-time calculation state, avoiding resource waste caused by fixed ALU allocation and significantly improving the adaptability of intra-group parallel processing.

[0076] Optionally, the arithmetic logic unit parallel processing system further comprises an inter-group multiplexer 600; the inter-group multiplexer 600 is arranged between the write-back unit 200 and the ALU group 300. The input end of the inter-group multiplexer 600 is connected to the output end of each ALU group 300; the output end of the inter-group multiplexer 600 is connected to the input end of the write-back unit 200; and the inter-group multiplexer 600 is used for aggregating the processing results output by each ALU group 300 and determining the target unit corresponding to the aggregated results.

[0077] The inter-group multiplexer 600 is arranged between the write-back unit 200 and the ALU groups 300, and is a result coordination hub connecting the outputs of multiple ALU groups and the write-back unit. Its input end aggregates the output results of all ALU groups 300, and its output end is connected to the input end of the write-back unit 200. Its core role is to solve the conflict and orientation problems of the results of multiple ALU groups. When multiple ALU groups process different vector instructions in parallel, the output time of the results may overlap, and the target units may be different (for example, the results of one ALU group need to be written to register R1, and the results of another ALU group need to be written to memory address 0x100). The inter-group multiplexer first classifies and aggregates all the results, and then according to the target information (such as register number, memory address) preset in the instruction, accurately directs the corresponding results to the specified channel of the write-back unit 200, ensuring that the results are not out of line and misaligned, and improving the result return efficiency when multiple groups are processed in parallel.

[0078] Optionally, the arithmetic logic unit parallel processing system further comprises: an out-of-group register 700; the out-of-group register 700 is arranged between the instruction issuing unit 100 and the ALU group 300; wherein, an input end of the out-of-group register 700 is connected with an output end of the instruction issuing unit 100; output ends of the out-of-group register 700 are respectively connected with input ends of each ALU group 300; the out-of-group register 700 is used for determining corresponding operands according to the received vector processing instruction.

[0079] The out-of-group register 700 is arranged between the instruction issuing unit 100 and the ALU group 300, forming a transition buffer of instruction-operand: its input end receives the vector processing instruction sent by the instruction issuing unit 100, and its output end distributes the processed operands to the ALU group 300. Its core function is to analyze the instruction in advance and prepare the operands, breaking the waiting barrier between instruction issuing and ALU execution. For example, when the instruction issuing unit sends a vector addition instruction, the out-of-group register will first analyze the operand source in the instruction (such as reading from the register group or the memory), load each element of the vector into the internal cache in advance, and group them according to the parallel processing requirements of the ALU group (such as 8 ALUs corresponding to 8 elements), and then provide the operands when the ALU group is ready. This process reduces the idle time of the ALU group due to waiting for operands, making the instruction execution pipeline smoother.

[0080] Optionally, the instruction issuing unit 100 is provided with a delay issuing module 800; an output end of the delay issuing module 800 is connected with an input end of the out-of-group register 700, and the delay issuing module 800 is used for sending the vector processing instruction to the out-of-group register 700 according to the delay strategy determined according to the type of the vector processing instruction; wherein, the vector processing instruction at least includes vector arithmetic logic instructions and vector reduction instructions.

[0081] The delay issuing module 800 is integrated in the instruction issuing unit 100, its output end is connected with the out-of-group register 700, and it is responsible for dynamically adjusting the issuing time according to the type of the vector processing instruction, and the core target is to avoid data conflict and resource competition. The vector processing instruction is mainly divided into two categories:

[0082] Vector arithmetic logic instructions (such as vector addition, subtraction, multiplication and division): usually can be directly parallel processed, each element operation is independent, and there is no dependency relationship;

[0083] Vector reduction instructions (such as vector sum and maximum value): need to gradually summarize the intermediate results (such as first summing the first two elements, and then adding the third element), and there is a strong dependency relationship.

[0084] The delay emission module formulates delay strategies for different instruction types: for example, for reduction instructions, the subsequent instructions are delayed according to the completion time of the previous operation to avoid the ALU group idling due to the lack of data; for arithmetic logic instructions, the maximum parallelism is used for fast emission to fully utilize the ALU resources. This on-demand delay mechanism optimizes the timing of instruction emission, ensures that each ALU group obtains the correct instruction and data at the correct time, and greatly reduces the probability of pipeline blocking.

[0085] These optional components are designed in multiple layers of in-group optimization (registers + multiplexer) - inter-group coordination (external registers + multiplexer) - instruction regulation (delay emission module), which makes the system more refined in data multiplexing, resource scheduling, timing control, etc. They work with the core modules (instruction emission, ALU group, write-back unit) to make the system not only efficient in processing independent and parallel vector operations, but also flexible in dealing with complex instructions with dependencies, significantly improving the adaptability and overall performance of parallel processing.

[0086] From the arithmetic logic unit parallel processing system in the above embodiment, it can be known that the system can use the same arithmetic logic operation component to implement the reduction instruction and the vector arithmetic logic operation, reduce the number and area of the vector arithmetic logic operation component, and improve the utilization rate of the vector arithmetic logic operation component.

[0087] The embodiment of the present application also provides an arithmetic logic unit parallel processing method, which is applied to the arithmetic logic unit parallel processing system mentioned in the above embodiment; the arithmetic logic unit parallel processing system at least comprises an instruction emission unit, a write-back unit and a plurality of ALU groups comprising a plurality of arithmetic logic units.

[0088] As shown in the above embodiment, the method comprises: Figure 4

[0089] Step S401: Obtain the type parameter of the corresponding vector processing instruction in the instruction emission unit, and determine the delay processing strategy corresponding to the vector processing instruction based on the type parameter.

[0090] Firstly, the system extracts the type parameter of the vector processing instruction to be processed from the instruction emission unit (for example, whether the instruction belongs to a vector arithmetic logic instruction or a vector reduction instruction, or other specific types). These type parameters directly determine the operation characteristics of the instruction. For example, an arithmetic logic instruction may support complete parallel processing, while a reduction instruction may have data dependency. Based on these characteristics, the system determines the corresponding delay processing strategy: for example, for an arithmetic logic instruction without dependency, an immediate emission strategy is adopted, and for a reduction instruction with dependency, a delay rule of waiting for the previous result is set to avoid operation conflicts.

[0091] ​Step S402: The instruction emission unit sends the vector processing instruction to the corresponding ALU group according to the delay processing strategy control instruction, and controls the arithmetic logic unit in the ALU group to respond to the vector processing instruction.

[0092] According to the delay processing strategy determined in step S401, the instruction emission unit will accurately send the vector processing instruction to the corresponding ALU group at the appropriate time (such as after meeting the delay condition). The ALU group receiving the instruction will immediately respond: according to the required operands of the instruction (possibly from the internal register or external storage), the corresponding arithmetic logic unit (ALU) in the group is scheduled to start parallel processing. For example, for a vector instruction containing 8 elements, 8 ALUs in the group can simultaneously perform the same operation on different elements to achieve data-level parallelism.

[0093] Step S403: Control the write-back unit to aggregate the processing results output by each ALU group, and call back the aggregated results to the target unit corresponding to the vector processing instruction.

[0094] After each ALU group completes the operation, it will output the processing result to the write-back unit. The write-back unit will integrate the output results of all ALU groups (such as reorganizing into complete vector results, sorting processing results, etc.), and according to the target information (such as target register number, memory address, etc.) preset in the vector processing instruction, accurately call back the final result after aggregation to the corresponding target unit, ensuring that the operation result is correctly reused or stored.

[0095] Optionally, the delay processing strategy corresponding to the vector processing instruction is determined based on the type parameter, such as Figure 5 As shown in the figure, it includes:

[0096] Step S501: If the type parameter corresponds to a vector arithmetic logic instruction, calculate the delay time of the arithmetic logic unit according to the number of elements s of the operand corresponding to the vector arithmetic logic instruction, the number m of arithmetic logic units in each ALU group, and the total number n of arithmetic logic units; wherein the delay time is ceil(s / m) / (n / m); ceil is the ceiling calculation;

[0097] Step S502: Determine the delay processing strategy corresponding to the vector processing instruction based on the delay time.

[0098] For a vector arithmetic logic instruction, if the number of elements of the operand is s, then each arithmetic logic operation group can receive a new vector arithmetic logic instruction after ceil(s / m) times; there are n / m groups in total, and if all the instructions emitted are vector arithmetic logic instructions, then the vector arithmetic logic operation component as a whole can receive a new vector arithmetic logic instruction every ceil(s / m) / (n / m) times. When s, n, and m are powers of 2, the throughput is consistent with that of non-grouping, both of which are ceil(s / n).

[0099] Optionally, the delay processing strategy corresponding to the vector processing instruction is determined based on the type parameter, as shown in the following formula: Figure 6

[0100] Step S601: If the type parameter corresponds to a vector reduction instruction, the delay time of the arithmetic logic unit is calculated according to the element number s of the operation number corresponding to the vector reduction instruction and the total number n of the arithmetic logic units; wherein the delay time is ceil(s / n); ceil is the upward rounding calculation;

[0101] Step S602: The delay processing strategy corresponding to the vector processing instruction is determined based on the delay time.

[0102] For the vector reduction instruction, each arithmetic logic operation group will be different according to the number of m and the type of instruction, and it is assumed that each group t can emit a new vector reduction instruction; there are n / m groups in total, and if the emitted instructions are all vector reduction instructions, then the vector arithmetic logic operation component can receive a new vector reduction instruction every ceil(s / n).

[0103] From the arithmetic logic unit parallel processing method in the above embodiment, it can be known that the method can use the same arithmetic logic operation component to implement the reduction instruction and the vector arithmetic logic operation, reduce the number and area of the vector arithmetic logic operation component, and improve the utilization rate of the vector arithmetic logic operation component.

[0104] The arithmetic logic unit parallel processing method provided by the embodiment of the present application has the same implementation principle and technical effects as the arithmetic logic unit parallel processing system embodiment, and for brevity of description, the part not mentioned in the system embodiment can refer to the corresponding content in the above arithmetic logic unit parallel processing method embodiment.

[0105] The embodiment also provides an electronic device, and a structure diagram of the electronic device is shown in the following figure: Figure 7 The device includes a processor 101 and a memory 102; wherein the memory 102 is used to store one or more computer instructions, and the one or more computer instructions are executed by the processor to implement the steps of the above arithmetic logic unit parallel processing method.

[0106] Figure 7 The electronic device shown in the figure also includes a bus 103 and a communication interface 104, and the processor 101, the communication interface 104 and the memory 102 are connected through the bus 103.

[0107] ​The memory 102 can include a high-speed random access memory (RAM), and can also include a non-volatile memory, such as at least one disk memory. The bus 103 can be an ISA bus, a PCI bus, or an EISA bus, etc. The bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 7 Only one bidirectional arrow is used to represent the bus in the figure, but it does not mean that there is only one bus or only one type of bus.

[0108] The communication interface 104 is used to connect with at least one user terminal and other network units through a network interface, and to send the encapsulated IPv4 packet or IPv4 packet to the user terminal through the network interface.

[0109] The processor 101 can be an integrated circuit chip with signal processing capability. In the implementation process, each step of the above method can be completed by the integrated logic circuit of hardware in the processor 101 or the instruction in the form of software. The above processor 101 can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components. Each method, step and logic block disclosed in the embodiment of the present disclosure can be implemented or executed. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor. The steps of the method disclosed in combination with the embodiment of the present disclosure can be directly embodied as a hardware code processor for execution, or a combination of hardware and software modules in the code processor for execution. The software module can be located in a random access memory, a flash memory, a read-only memory, a programmable read-only memory, an electrically erasable programmable memory, a register, or other mature storage media in the art. The storage medium is located in the memory 102, and the processor 101 reads the information in the memory 102 and combines the hardware to complete the steps of the method of the above embodiment.

[0110] The embodiment of the present application also provides a storage medium, which stores a computer program, and the computer program is executed by a processor to perform the steps of the arithmetic logic unit parallel processing method in the above embodiment.

[0111] In several embodiments provided in the present application, it should be understood that the disclosed system, device, apparatus and method can be implemented in other manners. The above described system embodiments are merely illustrative. For example, the division of the units is only a logical function division. There can be another division manner for the actual implementation, or a plurality of units or components can be combined or integrated into another system, or some features can be ignored or not executed. In addition, the displayed or discussed mutual couplings or direct couplings or communication connections between different units, can be indirect couplings or communication connections through some interfaces, devices or units, and can be in electrical, mechanical or other forms.

[0112] The units described as separated components can or can not be physically separated, and the components displayed as units can or can not be physical units, i.e., can be located in one place, or can be distributed on a plurality of network units. In actual implementation, some or all of the units can be selected according to the actual needs to achieve the purposes of the embodiments of the present application.

[0113] In addition, each functional unit in the various embodiments of the present application can be integrated in one processing unit, or each unit can exist physically as a separate unit, or two or more units can be integrated in one unit.

[0114] If the functions are implemented in the form of software function units and sold or used as independent products, they can be stored in a non-volatile computer readable storage medium executable by a processor. Based on this understanding, the technical solutions of the present application essentially or the part that contributes to the prior art, or part of the technical solutions can be embodied in the form of a software product. The computer software product is stored in a storage medium, and includes a plurality of instructions for causing a computer device (which can be a personal computer, an electronic device, or a network device, etc.) to execute all or part of the steps of the methods described in the various embodiments of the present application. The foregoing storage medium includes: a U disk, a mobile hard disk, a read-only memory (ROM, Read-Only Memory), a random access memory (RAM, Random Access Memory), a magnetic disk or an optical disk, and various program code storage media.

[0115] Finally, it should be noted that the above-described embodiments are merely specific embodiments of the present application, which are used to illustrate the technical solutions of the present application, but not to limit the same. The protection scope of the present application is not limited thereto. Although the present application has been described in detail with reference to the foregoing embodiments, it should be understood by those skilled in the art that any person skilled in the art can still modify or easily think of changes to the technical solutions recorded in the foregoing embodiments, or make equivalent replacements to some of the technical features, within the technical scope disclosed by the present application. The modifications, changes or replacements do not cause the corresponding technical solutions to deviate from the spirit and scope of the technical solutions of the embodiments of the present application, and should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. An arithmetic logic unit parallel processing system, characterized by, The arithmetic logic unit parallel processing system comprises an instruction emission unit, a write-back unit and a plurality of ALU groups comprising a plurality of arithmetic logic units; The instruction emission unit is connected with the input end of each ALU group; the output end of each ALU group is connected with the write-back unit; The input end of each ALU group is connected with the input end of all arithmetic logic units in the current ALU group; the output end of each ALU group is connected with the output end of all arithmetic logic units in the current ALU group; The instruction emission unit is used to obtain the type parameter of a vector processing instruction, determine the delay processing strategy corresponding to the vector processing instruction based on the type parameter, and send the vector processing instruction to the corresponding ALU group by using the delay processing strategy; The ALU group is used to call the corresponding arithmetic logic unit to process the vector processing instruction according to the operand corresponding to the received vector processing instruction; The write-back unit is used to aggregate the processing results output by each ALU group and call back the aggregation result to the target unit corresponding to the vector processing instruction.

2. The system of claim 1, wherein, The arithmetic logic unit parallel processing system further comprises an intra-group register; the intra-group register is arranged in each ALU group; The input end of the intra-group register is connected with the output end of all arithmetic logic units in the current ALU group; The input end of the intra-group register is also connected with the input end of the ALU group; The output end of the intra-group register is connected with the input end of all arithmetic logic units in the current ALU group; The intra-group register is used to store the calculation result corresponding to the arithmetic logic unit in the ALU group.

3. The system of claim 2, wherein, The arithmetic logic unit parallel processing system further comprises an intra-group multiplexer; the intra-group multiplexer is arranged in each ALU group; each intra-group multiplexer is connected with the corresponding arithmetic logic unit; The output end of each intra-group multiplexer is connected with the input end of the corresponding arithmetic logic unit; the input end of each intra-group multiplexer is connected with the output end of the intra-group register; The intra-group multiplexer is used to determine the arithmetic logic unit to be called in the current ALU group according to the calculation result stored in the intra-group register.

4. The system of claim 1, wherein, The arithmetic logic unit parallel processing system further comprises an inter-group multiplexer; the inter-group multiplexer is arranged between the write-back unit and the ALU group; The input end of the inter-group multiplexer is connected with the output end of each ALU group; the output end of the inter-group multiplexer is connected with the input end of the write-back unit; The inter-group multiplexer is used to aggregate the processing results output by each ALU group and determine the target unit corresponding to the aggregation result.

5. The system of claim 1, wherein, The arithmetic logic unit parallel processing system further comprises an inter-group register; the inter-group register is arranged between the instruction emission unit and the ALU group; The input end of the out-group register is connected with the output end of the instruction emission unit; the output end of the out-group register is connected with the input end of each ALU group respectively; The out-group register is used for determining the corresponding operation number according to the received vector processing instruction.

6. The system of claim 5, wherein, The instruction emission unit is provided with a delay emission module; The output end of the delay emission module is connected with the input end of the out-group register, and the delay emission module is used for sending the vector processing instruction to the out-group register according to the delay strategy determined according to the type of the vector processing instruction; wherein the vector processing instruction at least includes vector arithmetic logic instruction and vector reduction instruction above-mentioned two types.

7. An arithmetic logic unit parallel processing method, characterized by, The method is applied to the arithmetic logic unit parallel processing system in any one of claims 1 to 6; The arithmetic logic unit parallel processing system at least includes an instruction emission unit, a write-back unit and a plurality of ALU groups containing a plurality of arithmetic logic units; The method includes: acquiring the type parameter of the corresponding vector processing instruction in the instruction emission unit, and determining the delay processing strategy corresponding to the vector processing instruction based on the type parameter; controlling the instruction emission unit to send the vector processing instruction to the corresponding ALU group by using the delay processing strategy, and controlling the arithmetic logic unit in the ALU group to respond to the vector processing instruction; controlling the write-back unit to summarize the processing results output by each ALU group, and calling back the summarized results to the target unit corresponding to the vector processing instruction.

8. The arithmetic logic unit parallel processing method of claim 7, wherein, determining the delay processing strategy corresponding to the vector processing instruction based on the type parameter, including: if the type parameter corresponds to vector arithmetic logic instruction, calculating the delay time of the arithmetic logic unit according to the element number s of the corresponding operation number of the vector arithmetic logic instruction, the number m of the arithmetic logic unit in each ALU group and the total number n of the arithmetic logic unit; wherein the delay time is ceil(s / m) / (n / m); ceil is the upward rounding calculation; determining the delay processing strategy corresponding to the vector processing instruction based on the delay time.

9. The arithmetic logic unit parallel processing method of claim 7, wherein, determining the delay processing strategy corresponding to the vector processing instruction based on the type parameter, including: if the type parameter corresponds to vector reduction instruction, calculating the delay time of the arithmetic logic unit according to the element number s of the corresponding operation number of the vector reduction instruction and the total number n of the arithmetic logic unit; wherein the delay time is ceil(s / n); ceil is the upward rounding calculation; determining the delay processing strategy corresponding to the vector processing instruction based on the delay time.

10. An electronic device, comprising: The processor and the memory, the memory stores computer executable instructions capable of being executed by the processor, the processor executes the computer executable instructions to realize the steps of the arithmetic logic unit parallel processing method in any one of claims 7 to 9.

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