Vector compression system and method

Abstract

The application discloses a kind of vector compression system and method, it relates to computer technical field, the system includes: delay chain module, for generating a series of continuous pulses according to input pulse and output to pulse elimination module;Pulse elimination module, for eliminating part of pulse in continuous pulse according to input mask vector, obtain effective pulse;Pulse merging and separation module, for merging all effective pulse into a signal, and separating into multiple sampling pulses which are spatially continuous and temporally separated;Data serial module, for converting the parallel multiple vector elements in input source vector into single vector element changing with time according to effective pulse, obtain serial data;Destination vector sampling module, for simultaneously sampling serial data using multiple sampling pulses, obtain destination vector.The application can perform vector compression based on time domain calculation method, and can reduce the hardware overhead and power consumption required for vector compression.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of computer, and in particular, to a vector compression system and method. BACKGROUND

[0002] Vector compression is an indispensable type of instruction in the instruction set of a processor. For example, the AVX512 instruction set of Intel Corporation has a VPCOMPRESSD instruction, the openPower instruction set of IBM Corporation has XXGENPCVBM and XXPERM instructions, and the vector extension instruction set of RISC-V also has a VCOMPRESS instruction. Vector compression instructions can not only be used in traditional text conversion to improve the efficiency of program execution, but also be used in neural networks to reduce the bandwidth demand for memory access and significantly improve the performance of matrix operations by utilizing the natural sparsity of data. Therefore, an efficient vector compression method is crucial for the performance improvement of a processor.

[0003] Reference Figure 1 , Figure 1 A vector compression principle diagram is provided for an example. In the accompanying Figure 1 , the source vector and the destination vector each contain 8 8-bit elements, and the mask vector contains 8 1-bit elements. A bit of 1 in the mask vector means that the corresponding element in the source vector needs to be compressed into the destination vector, and a bit of 0 in the mask vector means that the corresponding element in the source vector needs to be discarded. Figure 1 In the accompanying , the value of the mask vector is “01001101”. Since the lowest bit is 1, the first element a in the source vector is placed into the first element in the destination vector. Since the second bit is 0, the second element b in the source vector is discarded. In this way, the elements in the source vector are sequentially compressed into the destination vector. In the process of vector compression, each element in the destination vector can come from any element in the source vector.

[0004] Figure 2 Reference Figure 2 A vector compression principle diagram of an existing vector compression method is provided for an example. When performing vector compression, the existing vector compression method first calculates the prefix sum of the mask vector, then calculates the index of each position in the destination vector using the prefix sum, and finally performs a gather operation on the index vector and the source vector to obtain the destination vector.

[0005] However, the above-mentioned vector compression method needs to use a large number of selector trees, and the number of selectors increases quadratically with the bit width of the vector. At the same time, since the control signals for generating these selector trees need to be calculated from the mask vector, a super-long accumulation circuit or a first-1 finding circuit needs to be used, and a large amount of combinational logic is also needed.

[0006] Compared with digital domain computation, time domain computation is a computation method using signal time domain coding and delay manipulation. In recent years, time domain computation has been applied in shortest path solving, multiply-accumulate operations and the like to reduce circuit overhead and improve energy efficiency. Meanwhile, since time domain computation does not need signal strength to carry information, it can be seamlessly compatible with existing data storage methods such as registers or static random access memory.

[0007] Therefore, it is necessary to develop a vector compression system and method based on time domain computation to reduce hardware overhead and power consumption required for vector compression. SUMMARY

[0008] To solve the above-mentioned problems in the prior art, the present application provides a vector compression system and method.

[0009] The technical solutions of the present application are as follows:

[0010] In a first aspect, a vector compression system is provided, which comprises:

[0011] A delay chain module is connected to the input end of the pulse elimination module, and is configured to generate a series of continuous pulses from the input pulse and output the continuous pulses to the pulse elimination module;

[0012] The pulse elimination module is connected to the input end of the data serial module and the input end of the pulse merging and separating module, and is configured to eliminate part of the continuous pulses received according to the input mask vector, obtain effective pulses, and output the effective pulses to the data serial module and the pulse merging and separating module, respectively;

[0013] The pulse merging and separating module is connected to the input end of the destination vector sampling module, and is configured to merge all the effective pulses received into a signal, separate the merged signal into a plurality of sampling pulses which are continuous in space and separated in time, and output the plurality of sampling pulses to the destination vector sampling module;

[0014] The data serial module is connected to the input end of the destination vector sampling module, and is configured to convert a plurality of vector elements in parallel in the input source vector into a single vector element changing over time according to the effective pulses received, obtain serial data, and output the serial data to the destination vector sampling module;

[0015] The destination vector sampling module is configured to sample the serial data received simultaneously using the plurality of sampling pulses received, and obtain a destination vector.

[0016] In some embodiments, the delay chain module comprises a plurality of buffers connected in sequence, the input of a first buffer is configured to receive an input pulse, and the outputs of the plurality of buffers collectively constitute the output of the delay chain module.

[0017] In some embodiments, the pulse elimination module comprises a plurality of first AND gates, one input of each of the first AND gates is connected to an output of the buffer, another input of each of the first AND gates is used to receive an element of the mask vector, and outputs of the first AND gates together form an output of the pulse elimination module.

[0018] In some embodiments, the pulse merging and separating module comprises a pulse merging circuit and a pulse separating circuit, an input of the pulse merging circuit is connected to an output of the pulse elimination module, an output of the pulse merging circuit is connected to an input of the pulse separating circuit, and an output of the pulse separating circuit is connected to an input of the destination vector sampling module, the pulse merging circuit is used to merge all valid pulses into one signal and output the merged signal to the pulse separating circuit, and the pulse separating circuit is used to separate the merged signal into a plurality of sampling pulses which are spatially continuous and temporally separated and output the sampling pulses to the destination vector sampling module.

[0019] In some embodiments, the pulse merging circuit comprises a first OR gate tree, a plurality of inputs of the first OR gate tree are connected to outputs of the first AND gates, and the first OR gate tree is used to merge the valid pulses output by the first AND gates into one signal and output the merged signal to the pulse separating circuit.

[0020] In some embodiments, the pulse separating circuit comprises a plurality of registers, a plurality of NOT gates and a positive power supply voltage.

[0021] A data input of a first register is connected to the positive power supply voltage, a data output of the first register is connected to a data input of a second register through a NOT gate, data inputs and data outputs of the second register to a last register are connected in sequence, a data output of the second register is also connected to a clock input of the first register, a data output of a previous register of the second register to the last register is also connected to a reset input of a next register through a NOT gate, data outputs of the second register to the last register are also connected to the destination vector sampling module respectively, clock inputs of the second register to the last register are connected to outputs of the first OR gate tree respectively, and the second register to the last register output sampling pulses respectively.

[0022] In some embodiments, the data serial module comprises a plurality of second AND gates and a second OR gate tree.

[0023] An input end of each of the plurality of second AND gates is connected to an output end of each of the plurality of first AND gates, another input end of each of the plurality of second AND gates is configured to receive a plurality of elements of the source vector, and an output end of each of the plurality of second AND gates is connected to a plurality of input ends of the second OR gate tree, and an output end of the second OR gate tree is connected to the destination vector sampling module.

[0024] In some embodiments, the destination vector sampling module comprises a plurality of multi-bit registers, a data input end of each of the plurality of multi-bit registers is connected to an output end of the second OR gate tree in the data serial module, and a clock input end of each of the plurality of multi-bit registers is connected to a data output end of a second register to a last register in the pulse merging and separating module.

[0025] In a second aspect, a vector compression method is also provided, and the method comprises:

[0026] generating a series of continuous pulses, wherein the number of the continuous pulses is the same as the number of elements contained in the compressed vector;

[0027] eliminating part of the pulses in the continuous pulses according to the mask vector to obtain effective pulses;

[0028] merging all the effective pulses into one signal, and separating the merged signal into a plurality of sampling pulses which are spatially continuous and temporally separated;

[0029] converting a plurality of vector elements in the source vector which are in parallel into a single vector element which changes over time according to the effective pulses to obtain serial data;

[0030] sampling the serial data simultaneously by using the plurality of sampling pulses to obtain the destination vector.

[0031] The main advantages of the technical scheme of the present application are as follows:

[0032] The vector compression system and method of the present application can perform vector compression based on a time domain calculation mode, and no prefix and suffix of the mask vector is required when performing vector compression, which can reduce delay overhead, no aggregation operation is required for the source vector, which can simplify the operation process, reduce the required selector tree and control logic circuit, reduce hardware overhead, reduce power consumption, and improve the energy efficiency of vector compression. At the same time, by removing the invalid pulses instead of removing the invalid elements, the required multi-bit parallel circuit can be reduced, the circuit size can be further reduced, the hardware overhead can be reduced, and the energy efficiency can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0033] The accompanying drawings, which are included to provide a further understanding of embodiments of the invention and constitute a part of this invention, illustrate exemplary embodiments of the invention and, together with their description, serve to explain the invention and do not constitute an undue limitation thereof. In the drawings:

[0034] Figure 1 A schematic diagram illustrating the principle of vector compression is provided as an example.

[0035] Figure 2 A schematic diagram illustrating the principle of an existing vector compression method is provided as an example.

[0036] Figure 3 A schematic diagram of a vector compression system provided in an embodiment of the present invention;

[0037] Figure 4 A schematic diagram of another vector compression system provided in an embodiment of the present invention;

[0038] Figure 5 This is a schematic diagram illustrating the working principle of the vector compression system provided in an embodiment of the present invention;

[0039] Figure 6 This is a flowchart illustrating a vector compression method provided in an embodiment of the present invention. Detailed Implementation

[0040] To make the objectives, technical solutions, and advantages of this invention clearer, the technical solutions of this invention will be clearly and completely described below in conjunction with specific embodiments and corresponding drawings. Obviously, the described embodiments are only a part of the embodiments of this invention, and not all of them. All other embodiments obtained by those skilled in the art based on the embodiments of this invention without creative effort are within the scope of protection of this invention.

[0041] The technical solutions provided by the embodiments of the present invention will be described in detail below with reference to the accompanying drawings.

[0042] refer to Figure 3 In a first aspect, embodiments of the present invention provide a vector compression system, the system comprising:

[0043] The delay chain module is connected to the input terminal of the pulse rejection module and is used to generate a series of continuous pulses based on the input pulse and output them to the pulse rejection module.

[0044] The pulse rejection module is connected to the input terminals of the data serialization module and the pulse combining and separating module, respectively. It is used to reject part of the pulses in the received continuous pulses according to the input mask vector, obtain the effective pulses, and output them to the data serialization module and the pulse combining and separating module, respectively.

[0045] The pulse merging and separating module is connected with the input end of the destination vector sampling module, and is used for merging all the received effective pulses into one signal, separating the merged signal into a plurality of sampling pulses which are continuous in space and separated in time, and outputting the plurality of sampling pulses to the destination vector sampling module;

[0046] The data serial module is connected with the input end of the destination vector sampling module, and is used for converting a plurality of vector elements in parallel in the input source vector into a single vector element which changes over time according to the received effective pulse, obtaining serial data, and outputting the serial data to the destination vector sampling module.

[0047] The destination vector sampling module is used for sampling the received serial data simultaneously by using the plurality of received sampling pulses, and obtaining a destination vector.

[0048] The vector compression system provided by the embodiment of the present application can realize vector compression by using time domain calculation. When performing vector compression, one pulse is input to the delay chain module, a mask vector used for vector compression is input to the pulse elimination module, and a source vector used for vector compression is input to the data serial module. The delay chain module generates a series of continuous pulses according to the input pulse and outputs the series of continuous pulses to the pulse elimination module. The pulse elimination module eliminates part of the received continuous pulses, i.e., eliminates invalid pulses, according to the mask vector, obtains effective pulses, and respectively outputs the effective pulses to the data serial module and the pulse merging and separating module. The pulse merging and separating module merges all the received effective pulses into one signal, separates the merged signal into a plurality of sampling pulses which are continuous in space and separated in time, and outputs the plurality of sampling pulses to the destination vector sampling module. The data serial module converts a plurality of vector elements in parallel in the input source vector into a single vector element which changes over time according to the received effective pulse, obtains serial data, and outputs the serial data to the destination vector sampling module. The destination vector sampling module samples the received serial data simultaneously by using the plurality of received sampling pulses, and obtains a destination vector, thereby realizing vector compression.

[0049] The vector compression system provided by the embodiment of the present application can realize vector compression based on a time domain calculation mode. When performing vector compression, there is no need to prefix the mask vector, the delay overhead can be reduced, there is no need to perform a gather operation on the source vector, the operation process can be simplified, the required selector tree and control logic circuit are reduced, the hardware overhead is reduced, the power consumption is reduced, and the energy efficiency of vector compression is improved. At the same time, the invalid elements are removed by removing the invalid pulses, the required multi-bit parallel circuit is reduced, the circuit scale is further reduced, the hardware overhead is reduced, and the energy efficiency is improved.

[0050] Further, refer to Figure 4In order to achieve the function of the delay chain module as defined above, in this embodiment of the invention, the delay chain module includes: a plurality of buffers connected in sequence, wherein the input of the first buffer is used to receive the input pulse, and the outputs of the plurality of buffers together constitute the output of the delay chain module.

[0051] The number of buffers in the delay chain module is specifically determined based on the number of elements contained in the actual compressed vector, and the number of buffers is the same as the number of elements contained in the vector.

[0052] In this embodiment of the invention, based on the aforementioned defined delay chain module structure, after a pulse is input into the first buffer, the output of each buffer can obtain a delayed pulse. The multiple pulses obtained through multiple buffers do not overlap in time and have equal time intervals.

[0053] Assuming the compressed vector has N elements, then the number of buffers is set to N. Through the delay chain module, N consecutive pulses can be obtained, i.e., appended... Figure 4 The pulses shown are pulse 1 to pulse N.

[0054] Further, refer to Figure 4 In order to achieve the function of the pulse rejection module as defined above, in this embodiment of the invention, the pulse rejection module includes: a plurality of first AND gates, one input of the plurality of first AND gates is connected to the output of a plurality of buffers respectively, the other input of the plurality of first AND gates is used to receive a plurality of elements of the mask vector respectively, and the output of the plurality of first AND gates together constitutes the output of the pulse rejection module.

[0055] The number of first AND gates in the pulse rejection module is specifically determined based on the number of elements contained in the actual compressed vector, and the number of first AND gates is the same as the number of elements contained in the vector.

[0056] In this embodiment of the invention, based on the pulse elimination module structure defined above, one end of each first AND gate is input with a pulse from a continuous pulse, and the other end is input with an element from a mask vector. If the element of the input mask vector is 0, the pulse signal output by the corresponding first AND gate will be 0. If the element of the input mask vector is 1, the pulse signal output by the corresponding first AND gate will remain unchanged. The pulse signal with a pulse signal of 0 is an invalid pulse, and the pulse signal with a pulse signal that remains unchanged is a valid pulse.

[0057] Assuming the number of elements of the compressed vector is N, the number of first AND gates is set to N, one end of the N first AND gates respectively inputs the pulses output by the N buffers, that is, pulse 1-pulse N, the other end of the N first AND gates respectively inputs the N elements in the mask vector, that is, mask vector element 1-mask vector element N, and the input of the Nth first AND gate is the pulse output by the Nth buffer and the Nth element in the mask vector.

[0058] Further, referring to Figure 4 , in order to realize the function of the pulse merging and separating module defined above, in the embodiment of the present application, the pulse merging and separating module comprises: a pulse merging circuit and a pulse separating circuit, the input end of the pulse merging circuit is connected with the output end of the pulse rejection module, the output end of the pulse merging circuit is connected with the input end of the pulse separating circuit, and the output end of the pulse separating circuit is connected with the input end of the destination vector sampling module, the pulse merging circuit is used for merging all the valid pulses received into a signal, and outputs the merged signal to the pulse separating circuit, and the pulse separating circuit is used for separating the merged signal into a plurality of sampling pulses which are continuous in space and separated in time, and outputs the plurality of sampling pulses to the destination vector sampling module.

[0059] Further, referring to Figure 4 , in the embodiment of the present application, the pulse merging circuit comprises: a first OR gate tree, a plurality of input ends of the first OR gate tree are respectively connected with the output ends of a plurality of first AND gates, and the first OR gate tree is used for merging the valid pulses output by the plurality of first AND gates into a signal, and outputs the merged signal to the pulse separating circuit.

[0060] In the embodiment of the present application, the first OR gate tree merges the input valid pulses into a signal, and the signal has all the valid pulses which are not overlapped in time.

[0061] Further, referring to Figure 4 , in the embodiment of the present application, the pulse separating circuit comprises: a plurality of registers, a plurality of NOT gates and a positive power supply voltage;

[0062] The data input end of the first register is connected with the positive power supply voltage, the data output end of the first register is connected with the data input end of the second register through a NOT gate, the data input end and the data output end of the second register to the last register are connected in sequence, the data output end of the second register is further connected with the clock input end of the first register, the data output end of the last register is further connected with the reset input end of the previous register through a NOT gate, the data output end of the second register to the last register is further respectively connected with the destination vector sampling module, the clock input end of the second register to the last register is respectively connected with the output end of the first OR gate tree, and the second register to the last register respectively outputs a sampling pulse.

[0063] The number of registers in the pulse separation circuit is determined according to the number of elements in the actually compressed vector, and the number of registers is one more than the number of elements in the vector.

[0064] In the embodiment of the application, based on the pulse separation circuit structure defined above, the clock signal of the register in the pulse separation circuit comes from the output signal of the first OR gate tree, when the next register outputs a rising edge, the previous register is reset, and the output of the previous register is pulled low, thus generating a sampling pulse; through the pulse separation circuit defined above, the merging signal output by the pulse merging circuit is split into multiple sampling pulses in the pulse separation circuit, and the multiple sampling pulses are continuous in space and separated in time.

[0065] Further, referring to Figure 4 , in order to realize the function of the data serial module defined above, in the embodiment of the application, the data serial module comprises: a plurality of second AND gates and a second OR gate tree.

[0066] One input end of each of the plurality of second AND gates is connected with the output end of each of the plurality of first AND gates, the other input end of each of the plurality of second AND gates is used for receiving a plurality of elements of the source vector, and the output end of each of the plurality of second AND gates is connected with a plurality of input ends of the second OR gate tree, and the output end of the second OR gate tree is connected with the destination vector sampling module.

[0067] The number of second AND gates in the data serial module is determined according to the number of elements in the actually compressed vector, and the number of second AND gates is the same as the number of elements in the vector.

[0068] In the embodiment of the application, based on the data serial module structure defined above, the valid pulses output by the plurality of first AND gates in the pulse elimination module can be ANDed with the corresponding elements in the source vector through the second AND gates to obtain the mask source vector elements, the second OR gate tree converts the plurality of mask source vector elements into a single vector element that changes over time to obtain serial data and output.

[0069] Further, referring to Figure 4 , in order to realize the function of the destination vector sampling module defined above, in the embodiment of the application, the destination vector sampling module comprises: a plurality of multi-bit registers, the data input ends of the plurality of multi-bit registers are connected with the output end of the second OR gate tree in the data serial module, and the clock input ends of the plurality of multi-bit registers are connected with the data output ends of the second register to the last register in the pulse merging and separation module.

[0070] The number of the multi-bit registers in the destination vector sampling module is determined according to the number of the elements contained in the actually compressed vector, and the number of the multi-bit registers is the same as the number of the elements contained in the vector.

[0071] In the embodiment of the present application, based on the above defined structure of the destination vector sampling module, the multi-bit registers of each element are driven by the same sampling clock, the serial data is connected to all the elements, and the sampling pulse aligned with the serial data can sample the correct value, so as to obtain the destination vector and complete the vector compression process.

[0072] It should be noted that, in the attached Figure 5 , "D" on the register represents a data input terminal, "Q" represents a data output terminal, the triangle symbol represents a clock input terminal, and "RST" represents a reset input terminal.

[0073] Further, referring to Figure 6 , for example, the working principle of the vector compression system provided by the embodiment of the present application is exemplarily explained for the vector compression containing 8 eight-bit elements, and the source vector is "hgfedcba" and the mask vector is "01001101".

[0074] Firstly, the delay chain module generates 8 continuous pulses which are not overlapped in time and have equal time intervals according to an input pulse; since the mask vector is "01001101", after the pulse elimination module, the 2nd, 5th, 6th and 8th pulses of the 8 continuous pulses are invalid pulses (dashed part), and the 1st, 3rd, 4th and 7th pulses are valid pulses (solid part); since the 1st, 3rd, 4th and 7th pulses are valid pulses, in the data serial module, a, c, d and g become serial data; at the same time, since the 1st, 3rd, 4th and 7th pulses are valid pulses, in the pulse merging and separating module, the 1st, 3rd, 4th and 7th pulses are respectively put into the sampling pulses 1, 2, 3 and 4, and the falling edge of the previous pulse is aligned with the rising edge of the next pulse; in the destination vector sampling module, the sampling pulse 1 samples the element a, the sampling pulse 2 samples the element c, the sampling pulse 3 samples the element d, and the sampling pulse 4 samples the element g, so as to complete the whole vector compression process.

[0075] Referring to ​ , in a second aspect, the embodiment of the present application further provides a vector compression method, which comprises the following steps 1-5.

[0076] Step 1, generating a series of continuous pulses;

[0077] In the embodiment of the present application, the number of the continuous pulses is the same as the number of the elements contained in the compressed vector.

[0078] Step 2, according to the mask vector, part of the pulses in the continuous pulses are removed to obtain effective pulses;

[0079] In the embodiment of the application, the pulse corresponding to the position where the element of the mask vector is 0 is removed.

[0080] Step 3, all effective pulses are combined into a signal, and the combined signal is separated into a plurality of sampling pulses which are continuous in space and separated in time;

[0081] Step 4, according to the effective pulses, a plurality of vector elements in the source vector in parallel are converted into a single vector element changing over time to obtain serial data;

[0082] Step 5, the serial data is sampled by using the plurality of sampling pulses to obtain a destination vector.

[0083] The vector compression method provided by the embodiment of the application can perform vector compression based on a time domain calculation mode, without requiring a prefix of the mask vector when performing vector compression, so as to reduce delay overhead, without requiring a gathering operation on the source vector, so as to simplify an operation process, reduce a required selector tree and control logic circuit, reduce hardware overhead, reduce power consumption, and improve energy efficiency of vector compression. Meanwhile, by removing invalid pulses to replace removing invalid elements, a plurality of multi-bit parallel circuits required can be reduced, so as to further reduce circuit scale, reduce hardware overhead, and improve energy efficiency.

[0084] It should be noted that, in the present document, relational terms such as“first” and“second”, and the like, are used solely to distinguish one entity or action from another entity or action, without necessarily requiring or implying any actual such relationship or order between such entities or actions. Moreover, the terms“comprises”,“comprising”, or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can include other elements not expressly listed or inherent to such process, method, article, or apparatus. Furthermore, the terms“front”,“rear”,“left”,“right”,“up”, and“down”, and the like, are used in relation to the placement of the described elements in the drawings, as indicated by the reference numerals in the drawings.

[0085] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present application, and not to limit them; although the foregoing embodiments of the present application have been described in detail, those skilled in the art should understand that: it can still modify the technical solutions recorded in the foregoing embodiments, or make equivalent replacement for part of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present application.

Claims

1. A vector compression system characterized in that, The application relates to a pulse processing method and device. The delay chain module is connected with the input end of the pulse elimination module, and is used for generating a series of continuous pulses according to the input pulse and outputting the pulses to the pulse elimination module; The pulse elimination module is connected with the input end of the data series module and the input end of the pulse merging and separating module respectively, and is used for eliminating part of the received continuous pulses according to the input mask vector, obtaining effective pulses and outputting the effective pulses to the data series module and the pulse merging and separating module respectively; The pulse merging and separating module is connected with the input end of the target vector sampling module, and is used for merging all the received effective pulses into a signal, separating the merged signal into a plurality of sampling pulses which are continuous in space and separated in time, and outputting the plurality of sampling pulses to the target vector sampling module; The data series module is connected with the input end of the target vector sampling module, and is used for converting a plurality of parallel vector elements in the input source vector into a single vector element which changes with time according to the received effective pulses, obtaining serial data and outputting the serial data to the target vector sampling module; The target vector sampling module is used for sampling the received serial data simultaneously by using the received plurality of sampling pulses, and obtaining a target vector.

2. The vector compression system of claim 1, wherein, The delay chain module comprises a plurality of buffers which are connected in sequence, the input of a first buffer is used for receiving the input pulse, and the outputs of the plurality of buffers jointly constitute the output of the delay chain module.

3. The vector compression system of claim 2, wherein, The pulse elimination module comprises a plurality of first AND gates, one input end of each of the plurality of first AND gates is connected with the output end of a corresponding buffer, the other input end of each of the plurality of first AND gates is used for receiving an element of the mask vector, and the output ends of the plurality of first AND gates jointly constitute the output end of the pulse elimination module.

4. The vector compression system of claim 3, wherein, The pulse merging and separating module comprises a pulse merging circuit and a pulse separating circuit, the input end of the pulse merging circuit is connected with the output end of the pulse elimination module, the output end of the pulse merging circuit is connected with the input end of the pulse separating circuit, the output end of the pulse separating circuit is connected with the input end of the target vector sampling module, the pulse merging circuit is used for merging all the received effective pulses into a signal and outputting the merged signal to the pulse separating circuit, and the pulse separating circuit is used for separating the merged signal into a plurality of sampling pulses which are continuous in space and separated in time, and outputting the plurality of sampling pulses to the target vector sampling module.

5. The vector compression system of claim 4, wherein, The pulse merging circuit comprises a first OR gate tree, a plurality of input ends of the first OR gate tree are connected with the output ends of the plurality of first AND gates respectively, and the first OR gate tree is used for merging the effective pulses output by the plurality of first AND gates into a signal and outputting the merged signal to the pulse separating circuit.

6. The vector compression system of claim 5, wherein, The pulse separating circuit comprises a plurality of registers, a plurality of NOT gates and a positive power supply voltage. The data input end of the first register is connected with the positive power voltage, the data output end of the first register is connected with the data input end of the second register through a NOT gate, the data input end and the data output end of the second register to the last register are connected in sequence, the data output end of the second register is also connected with the clock input end of the first register, the data output end of the second register to the last register is also connected with the reset input end of the previous register through a NOT gate, the data output end of the second register to the last register is also connected with the destination vector sampling module, the clock input end of the second register to the last register is connected with the output end of the first OR gate tree, and the second register to the last register outputs a sampling pulse.

7. The vector compression system of claim 6, wherein, The data serial module comprises a plurality of second AND gates and a second OR gate tree. One input end of each of the plurality of second AND gates is connected with the output end of each of the plurality of first AND gates, the other input end of each of the plurality of second AND gates is used for receiving a plurality of elements of a source vector, and the output end of each of the plurality of second AND gates is connected with a plurality of input ends of the second OR gate tree.

8. The vector compression system of claim 7, wherein, The destination vector sampling module comprises a plurality of multi-bit registers, the data input end of each of the plurality of multi-bit registers is connected with the output end of the second OR gate tree in the data serial module, and the clock input end of each of the plurality of multi-bit registers is connected with the data output end of the second register to the last register in the pulse merging and separating module.

9. A vector compression method, characterized by, The method comprises: generating a series of continuous pulses, wherein the number of pulses of the continuous pulses is the same as the number of elements contained in the compressed vector; eliminating part of the pulses in the continuous pulses according to the mask vector to obtain effective pulses; merging all the effective pulses into a signal, and separating the merged signal into a plurality of sampling pulses which are continuous in space and separated in time; converting a plurality of vector elements in the source vector which are parallel in time into a single vector element which changes over time according to the effective pulses to obtain serial data; sampling the serial data simultaneously by using the plurality of sampling pulses to obtain a destination vector.

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