PC value log unit and control unit

Abstract

The embodiment of the invention provides a PC value log unit and component, and relates to the technical field of storage. The PC value log unit comprises an acquisition subunit, a compression subunit and a combination subunit; the acquisition subunit is coupled with the central processing unit core and acquires a program counter value output by the central processing unit core; the compression subunit is coupled with the acquisition subunit, compresses the program counter values acquired by the acquisition subunit, and generates program counter value log data packets with specified formats corresponding to the program counter values; the combination subunit is coupled with the compression subunit and combines the one or more program counter value log data packets generated by the compression subunit to obtain a combined data packet. According to the program counter value log unit, the program counter value sequence collected by the collection subunit is compressed, the size of the program counter value sequence is reduced, and then the bandwidth for transmitting a program counter value log data packet is reduced.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of storage, and in particular to a PC value log unit and a control component. BACKGROUND

[0002] The control component of an electronic device includes one or more CPUs (Central Processing Units), and each CPU includes one or more CPU cores. The CPU cores are real physical processing units, and each CPU core can work independently and in parallel. For example, the CPU cores execute a firmware program during work, and output a PC value of each instruction of the firmware program. The PC value is the value of the program counter of the CPU core, and represents the address of the instruction submitted by the CPU core. The instruction submitted by the CPU core is the instruction that is completed by the CPU core and makes the execution result take effect in the CPU core. The sequence of PC values represents the order of execution of each instruction of the CPU core, so that the process of the CPU core executing the firmware program can be restored by analyzing the PC values, and the firmware program and the correctness of the control component can be identified. For this purpose, as shown in the prior art, the control component provides a program counter value log unit (referred to as a PC value log unit). During work of the control component, the PC value log unit collects the PC values output by each CPU core, generates a PC value log in chronological order, and writes the PC value log into a memory such as a DRAM (Dynamic Random Access Memory) so that a host can obtain the PC value log. The PC value log can be used to analyze the work process of the control component, debug the firmware, repair defects of the control component, and simulate behaviors of the control component. Figure 1

[0003] However, the CPU core works at a high frequency, for example, 1 GHz. Each CPU core can submit multiple instructions per clock cycle, so that a high bandwidth is required to output the PC value log during work of the CPU core. Taking a control component including two CPU cores, a work frequency of 1 GHz, and a length of each PC value of 48 bits as an example, the two CPU cores generate PC values of 10^9*2*6 bytes per second, and at least 12 GB of bandwidth is required to record the PC values. When the number of CPU cores increases, the bandwidth required to record the PC values further increases. The bandwidth of the control component is a limited resource, and is mainly used to implement functions of the control component itself. Therefore, it is necessary to reduce the bandwidth required to record the PC value log and reduce competition for the bandwidth resource of the control component. SUMMARY

[0004] ​To solve the above technical problems or at least partially solve the above technical problems, an embodiment of the present application provides a program counter value log unit and a control component.

[0005] In a first aspect, an embodiment of the present application provides a program counter value log unit, which is coupled with a central processor core, and includes an acquisition subunit, a compression subunit and a combination subunit. The acquisition subunit is coupled with the central processor core and acquires program counter values output by the central processor core. The compression subunit is coupled with the acquisition subunit and compresses the program counter values acquired by the acquisition subunit to generate program counter value log data packets of a specified format corresponding to the program counter values. The combination subunit is coupled with the compression subunit and combines one or more program counter value log data packets generated by the compression subunit to obtain a combination data packet.

[0006] In an optional embodiment, the specified format of the program counter value log data packet includes a packet format symbol bit and a data bit.

[0007] The packet format symbol bit represents the type of the program counter value log data packet, and the data bit records the numerical value related to the program counter value.

[0008] In an optional embodiment, the compression subunit records the numerical value of all bits of the program counter value or the numerical value of specified bits in the program counter value as the numerical value recorded by the data bit.

[0009] In an optional embodiment, the compression subunit records the difference between two adjacent program counter values or the numerical value of specified bits in the difference as the numerical value recorded by the data bit of the program counter value log data packet corresponding to the latter program counter value of the two adjacent program counter values.

[0010] In an optional embodiment, the compression subunit records the numerical value of all bits of the first program counter value acquired by the acquisition subunit each time the acquisition subunit is powered on and started as the numerical value recorded by the data bit of the program counter value log data packet corresponding to the first program counter value.

[0011] In an optional embodiment, the compression subunit determines the type of the program counter value log data packet corresponding to the latter program counter value of two adjacent program counter values according to the comparison result of the two adjacent program counter values.

[0012] In an optional embodiment, the compression subunit determines a bit range in which there is a change between two adjacent program counter values, and determines a type of the program counter value log data packet corresponding to the latter one of the two adjacent program counter values according to the bit range in which there is a change.

[0013] In an optional embodiment, the compression subunit generates a program counter value log data packet corresponding to one of the two adjacent program counter values in response to the two adjacent program counter values being the same.

[0014] In an optional embodiment, the program counter value log data packet comprises one or more of the following types: a first data packet, a second data packet, and a third data packet; wherein the first data packet has a size of 16 bits, the second data packet has a size of 32 bits, and the third data packet has a size of 64 bits.

[0015] In an optional embodiment, the compression subunit generates the third data packet for a first program counter value collected by the collection subunit each time the collection subunit is powered on.

[0016] In an optional embodiment, if a bit range in which there is a change between two adjacent program counter values is within a bit range recordable by data bits of the first data packet, the compression subunit generates the first data packet for the latter one of the two adjacent program counter values; or, if a bit range in which there is a change between two adjacent program counter values is beyond the bit range recordable by data bits of the first data packet and within a bit range recordable by data bits of the second data packet, the compression subunit generates the second data packet for the latter one of the two adjacent program counter values; or, if a bit range in which there is a change between two adjacent program counter values is beyond the bit range recordable by data bits of the second data packet, the compression subunit generates the third data packet for the latter one of the two adjacent program counter values.

[0017] In an optional embodiment, a size of the combined data packet is consistent with a bus width coupled to the program counter value log unit.

[0018] In an optional embodiment, the combination subunit combines a plurality of program counter value log data packets received successively to obtain a combined data packet.

[0019] In an optional embodiment, if a total size of N program counter value log data packets received successively is consistent with a size of the combined data packet, the combination subunit combines the N program counter value log data packets received successively to obtain a combined data packet; wherein N is a positive integer not less than 1.

[0020] If the total size of N continuous received program counter value log data packets is less than the size of the combined data packet, and the total size of N+1 continuous received program counter value log data packets is greater than the size of the combined data packet, the combining subunit combines the N continuous received program counter value log data packets and fills invalid data to obtain the combined data packet.

[0021] In an optional embodiment, the size of the combined data packet is 64 bits; if the combining subunit continuously receives one third data packet, two second data packets and four first data packets, the combining subunit takes the third data packet as the combined data packet, combines the two second data packets as the combined data packet, and combines the four first data packets as the combined data packet; or, if the combining subunit continuously receives one second data packet, one first data packet and one third data packet, the combining subunit combines the second data packet, the first data packet and 16 bits of invalid data as the combined data packet, and takes the third data packet as the combined data packet; or, if the combining subunit continuously receives two first data packets and one third data packet, the combining subunit combines the two first data packets and 32 bits of invalid data as the combined data packet, and takes the third data packet as the combined data packet.

[0022] In an optional embodiment, the collecting subunit comprises a mode selection module, a continuous mode collecting module, an interval trigger mode collecting module and a threshold trigger mode collecting module.

[0023] The mode selection module delivers the program counter value output by the central processor core to one of the continuous mode collecting module, the interval trigger mode collecting module and the threshold trigger mode collecting module according to an enable signal, so that one of the continuous mode collecting module, the interval trigger mode collecting module and the threshold trigger mode collecting module works.

[0024] When the continuous mode collecting module works, it continuously collects the program counter value output by the central processor core.

[0025] When the interval trigger mode collecting module works, it collects the program counter value output by the central processor core within a preset program counter value interval.

[0026] When the threshold trigger mode collecting module works, it continuously or periodically collects the program counter value output by the central processor core in response to detecting that the program counter value output by the central processor core is greater than a preset threshold.

[0027] In an optional embodiment, the program counter value log unit further comprises a multiplexer.

[0028] The multiplexer is coupled with the continuous mode acquisition module, the interval trigger mode acquisition module and the threshold trigger mode acquisition module, and delivers the program counter value acquired by one of the continuous mode acquisition module, the interval trigger mode acquisition module and the threshold trigger mode acquisition module to the compression subunit.

[0029] In an optional embodiment, the compression subunit comprises a current program counter value register, a last program counter value register, a data packet selection module and a data packet generation module.

[0030] The current program counter value register records a first program counter value received currently, and the last program counter value register records a second program counter value received last time.

[0031] The data packet selection module compares the first program counter value with the second program counter value, and selects the type of the program counter value log data packet corresponding to the first program counter value according to the comparison result.

[0032] The data packet generation module generates the program counter value log data packet corresponding to the first program counter value according to the determined type of the program counter value log data packet.

[0033] In an optional embodiment, the program counter value log unit is coupled with a queue, and the queue buffers the combined data packet output by the program counter value log unit.

[0034] The program counter value log unit further comprises an overflow detection subunit, which is coupled with the acquisition subunit and the queue, and detects whether the queue is overflowed; and the acquisition subunit stops acquiring the program counter value output by the central processing unit core in response to the overflow detection subunit detecting that the queue is overflowed.

[0035] In an optional embodiment, the program counter value log unit further comprises a data packet generation subunit; and the data packet generation subunit generates the relevant data packet with a specified format in response to detecting that the relevant data packet generation condition is met.

[0036] In an optional embodiment, the relevant data packet comprises one or more of the following: a synchronization data packet, a timestamp data packet, an overflow data packet and a timeout data packet.

[0037] The data packet generating sub-unit generates at least one relevant data packet in response to detecting that at least one relevant data packet generating condition is met: a synchronization data packet is generated in response to detecting that the program counter value log unit is powered on to start; a time stamp data packet is generated in response to a specified time interval or the collection sub-unit collecting a specified number of program counter values; an overflow data packet is generated in response to the overflow detection sub-unit detecting that the queue is overflowing; and a timeout data packet is generated in response to the compression sub-unit not generating a program counter value log data packet for a specified length of time.

[0038] In an optional embodiment, the synchronization data packet includes a packet format symbol bit, an ID bit, a channel bit, and a data bit; the time stamp data packet includes a packet format symbol bit, an ID bit, and a data bit; the overflow data packet includes a packet format symbol bit, an ID bit, a specified value bit, and a data bit; and the timeout data packet includes one of the time stamp data packet and one of the first data packet.

[0039] The data bits of the synchronization data packet, the time stamp data packet, and the overflow data packet respectively record time information of generating the synchronization data packet, the time stamp data packet, and the overflow data packet.

[0040] In an optional embodiment, the data packet generating sub-unit is coupled with the queue, and the relevant data packet with the specified format generated by the data packet generating sub-unit is cached into the queue.

[0041] In a second aspect, an embodiment of the present application provides a control component, which includes at least one central processor core and at least one program counter value log unit as shown in any embodiment of the present application, and the central processor core and the program counter value log unit are in one-to-one correspondence.

[0042] The program counter value log unit is coupled with the corresponding central processor core, collects a sequence of program counter values output by the central processor core, compresses the sequence of program counter values, generates corresponding program counter value log data packets with a specified format for each program counter value in the sequence of program counter values, and combines one or more program counter value log data packets to obtain a combined data packet.

[0043] In an optional embodiment, the control component includes at least one central processor cluster, each of the central processor clusters includes at least one central processor core, each of the central processor cores is coupled with a program counter value log unit, and the number of program counter value log units is the same as the total number of central processor cores included in the plurality of central processor clusters.

[0044] In an optional embodiment, each of the central processor clusters corresponds to a first multiplexer, and each of the program counter value log units in each of the central processor clusters is coupled to the first multiplexer corresponding to the central processor cluster; and the first multiplexer transmits the combined data packet or the related data packet output by one of the program counter value log units coupled thereto to the memory in each clock cycle.

[0045] In an optional embodiment, the control component further comprises at least one data packet merging unit, and each of the data packet merging units corresponds to one of the program counter value log units.

[0046] The data packet merging unit is coupled to the program counter value log unit, receives the combined data packet and / or the related data packet output by the program counter value log unit, and merges the combined data packet and / or the related data packet output by the program counter value log unit successively to obtain a merged data packet, wherein the size of the merged data packet is consistent with the bus width of the control component.

[0047] In an optional embodiment, if the total size of the M combined data packets and / or related data packets received successively is consistent with the size of the merged data packet, the data packet merging unit merges the M combined data packets and / or related data packets received successively to obtain the merged data packet, wherein M is a positive integer not less than 1; if the total size of the M combined data packets and / or related data packets received successively is smaller than the merged data packet, and the total size of the M+1 combined data packets and / or related data packets received successively is larger than the merged data packet, the data packet merging unit merges the M combined data packets and / or related data packets and fills invalid data in the merged data packet after the M combined data packets and / or related data packets are merged.

[0048] In an optional embodiment, the control component further comprises at least one second multiplexer, at least one queue, and an arbitrator.

[0049] Each of the second multiplexers is coupled to one or more data packet merging units and one queue, and selects the merged data packet output by one of the one or more data packet merging units to send to the queue coupled thereto in each clock cycle.

[0050] The arbitrator is coupled to the at least one queue, and selects the merged data packet from one of the at least one queue to send to the memory coupled thereto in each clock cycle.

[0051] In an optional embodiment, all or part of the central processor cores in the control component are working normally, and each of the second multiplexers periodically selects the merged data packet output by the data packet merging unit corresponding to each normally working central processor core and transmits the merged data packet to the arbitrator; the arbitrator periodically selects the merged data packet output by each second multiplexer coupled thereto and transmits the merged data packet to the memory through a bus, so that all or part of the normally working central processor cores share the bandwidth of the bus coupled thereto.

[0052] In an optional embodiment, the control component comprises a third multiplexer; the third multiplexer is coupled to at least one program counter value log unit comprised in the control component and selects the combined data packet or the related data packet output by one of the at least one program counter value log unit and transmits the combined data packet or the related data packet to the memory in each clock cycle.

[0053] The program counter value log unit and the control component provided by the embodiments of the present application compress the program counter values output by the central processor cores, generate program counter value log data packets with a specified format corresponding to each program counter value, and then combine various program counter value log data packets with the specified format, which can compress the program counter values in some scenarios, reduce the size of the program counter value sequence, and further reduce the bandwidth of transmitting the program counter value log data packets. BRIEF DESCRIPTION OF DRAWINGS

[0054] In order to more clearly illustrate the technical solutions of the embodiments of the present application or the prior art, the drawings needed in the embodiments or the prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments described in the present application, and other drawings can also be obtained by those skilled in the art according to these drawings.

[0055] Figure 1 A structural schematic diagram of a control component in the prior art is shown;

[0056] Figure 2 A structural schematic diagram of a PC value log unit of an embodiment of the present application is shown;

[0057] Figure 3A A schematic diagram of the data format of an S packet of an embodiment of the present application is shown;

[0058] Figure 3B A schematic diagram of the data format of an L packet of an embodiment of the present application is shown;

[0059] Figure 3C A schematic diagram of the data format of an A packet of an embodiment of the present application is shown;

[0060] Figure 4A flowchart of the PC value log unit processing PC value of an embodiment of the present application is shown.

[0061] Figure 5 A structural diagram of the control component of an embodiment of the present application is shown.

[0062] Figure 6 A structural diagram of the control component of another embodiment of the present application is shown.

[0063] Figure 7 A structural diagram of the PC value log unit of yet another embodiment of the present application is shown.

[0064] Figure 8 A flowchart of the PC value log unit processing PC value of an embodiment of the present application is shown.

[0065] Figure 9 A structural diagram of the PC value log unit of an embodiment of the present application is shown.

[0066] Figure 10 A structural diagram of the PC value log unit of yet another embodiment of the present application is shown.

[0067] Figure 11A A diagram of the synchronization data packet in an embodiment of the present application is shown.

[0068] Figure 11B A diagram of the time stamp data packet in an embodiment of the present application is shown.

[0069] Figure 11C A diagram of the overflow data packet in an embodiment of the present application is shown.

[0070] Figures 12-16 A flowchart of the PC value log unit processing PC value of an embodiment of the present application is shown.

[0071] Figure 17 A flowchart of the PC value log unit processing PC value of an embodiment of the present application is shown.

[0072] Figure 18 A structural diagram of the control component of an embodiment of the present application is shown.

[0073] Figure 19 A flowchart of the control component processing PC value of an embodiment of the present application is shown. DETAILED DESCRIPTION

[0074] With reference to the drawings and the embodiments of the present application, the technical solutions in the embodiments of the present application are clearly and completely described. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative work are within the scope of protection of the present application.

[0075] Figure 2 The structural schematic diagram of the PC value log unit in an embodiment of the present application is shown. As shown in the figure, Figure 2 the PC value log unit 200 includes a collection subunit 201, a compression subunit 202 and a combination subunit 203.

[0076] The collection subunit 201 is coupled with the CPU core to collect the PC value output by the CPU core.

[0077] The CPU core outputs the PC value of the instruction submitted in the current clock cycle in each clock cycle. According to the micro-architecture adopted by the CPU core, the maximum number of instructions submitted by the CPU core in each clock cycle can be different, for example, the maximum number of instructions submitted by the CPU core can be 1, 2, 3 or 4. Correspondingly, the number of PC values output by the CPU core in each clock cycle can also be different, and the number of PC values collected by the collection subunit 201 in each clock cycle is also different.

[0078] In an optional embodiment, the PC log channel is used to distinguish the PC values of different instructions submitted by the CPU core in the same clock cycle. For example, the CPU core handles at most two instructions in each clock cycle, and correspondingly outputs at most two PC values, and the PC log channels corresponding to the two PC values are CH0 and CH1 respectively. The number of PC log channels represents the maximum number of instructions submitted by the CPU core in each clock cycle, but in a certain clock cycle, the actual number of instructions submitted by the CPU core can be less than the number of PC log channels. For example, the number of PC log channels of the CPU core is 4, which indicates that the CPU core submits at most four instructions in each clock cycle, the CPU core outputs at most four PC values, and the CPU core outputs 0, 1, 2, 3 or 4 PC values in a certain clock cycle, and the collection subunit 201 collects at most 4 PC values, and collects 0, 1, 2, 3 or 4 PC values in a certain clock cycle.

[0079] The compression subunit 202 is coupled to the collection subunit 201 and compresses the PC value sequence formed by one or more PC values collected by the collection subunit 201 to generate a program counter value log data packet (hereinafter referred to as PC value log data packet) having a specified format for each PC value. Optionally, the specified format of the PC value log data packet generated by the compression subunit 202 is defined by a tool processing the PC value log, so that the tool processing the PC value log can obtain the correct PC value sequence from the data packet having the specified format.

[0080] In an optional embodiment, the specified format of the PC value log data packet generated by the compression subunit 202 includes a packet format symbol bit, an ID bit, a channel bit, and a data bit. The packet format symbol bit represents the type of the program counter value log data packet, the ID bit represents the ID of the central processing unit core outputting the program counter value, the channel bit represents the program counter value log channel of the central processing unit core outputting the program counter value, and the data bit records the numerical value related to the program counter value. Optionally, the data bit is used to record the numerical value of all bits of the program counter value or the numerical value of specified bits. Still optionally, the data bit is used to record the difference between two adjacent program counter values or the numerical value of specified bits in the difference, and the data bit is the data bit of the program counter value log data packet of the later program counter value of the two adjacent program counter values.

[0081] As an optional example, the PC value log data packet having the specified format generated by the compression subunit 202 includes an S data packet (hereinafter referred to as S packet), an L data packet (hereinafter referred to as L packet), and an A data packet (hereinafter referred to as A packet).

[0082] Figure 3A A schematic diagram showing the data format of the S packet of an embodiment of the present application is shown.

[0083] As shown in Figure 3A , the size of the S packet is 16 bits (as shown in Figure 3AThe S packet shown includes bits 0 to 15. Bits 0 to 2 are packet format specifier bits, used to identify the type of data packet. For example, if a data packet is 16 bits and bits 0 to 2 are 010, then the data packet is an S packet. Bits 3 to 5 are ID bits, representing the ID (Core ID) of the CPU core that submitted the PC value corresponding to the data packet. Bit 6 is the channel bit, representing the PC log channel that submitted the PC value corresponding to the data packet. Bits 7 to 15 are data bits, used to record data about the PC value itself, such as the values ​​of all bits of the PC value or the values ​​of specific bits within the PC value. For example, the values ​​recorded by bits 7 to 15 are recorded as Addr[a:b], where a represents the ath bit of the PC value and b represents the bth bit of the PC value. For example, bits 7 to 15 in the S packet record the values ​​of bits 1 to 9 in the PC value sequence. Optionally, the values ​​of the first to ninth bits in the PC value sequence can be recorded as Addr[9:1]( Figure 3A In the example, Addr[1] and Addr[9:2] are combined to get Addr[9:1]).

[0084] In an optional embodiment, the 7th to 15th bits in the S packet are used to record data calculated by the PC value, such as recording the difference between two adjacent PC values ​​or the numerical value of a specified bit in the difference. The S packet generated in this case represents a PC value log data packet corresponding to the latter PC value of the two adjacent PC values. As an optional example, the 7th to 15th bits in the S packet are used to record the numerical values ​​of the 1st to 9th bits in the difference between PC2 (the latter PC value) and PC1 (the previous PC value).

[0085] Figure 3B A schematic diagram showing the data format of an L packet according to an embodiment of the present application is shown.

[0086] like Figure 3B As shown, the size of the L packet is 32 bits (as Figure 3BThe L packet includes 0-31 bits as shown. The 0th bit-2nd bit in the L packet is a packet format symbol bit, which is used to represent the type of the data packet. For example, if a data packet is 32 bits, and the 0th bit-2nd bit is 001, the data packet is an L packet. The 3rd bit-5th bit is an ID bit, which represents the ID of the CPU core that submits the PC value corresponding to the data packet. The 6th bit is a channel bit, which represents the PC log channel of the PC value corresponding to the data packet. The 7th bit-31st bit is a data bit, which is used to record data of the PC value itself, for example, the value of all bits of the PC value or the value of a specified bit in the PC value. For example, the 7th bit-31st bit in the L packet records the value of the 1st bit to the 25th bit of the PC value. Alternatively, the value of the 1st bit to the 25th bit in the PC value sequence can be recorded as Addr[25:1].

[0087] For another example, the 7th bit-31st bit in the L packet is used to record data calculated from the PC value, such as the difference between two adjacent PC values or the value of a specified bit in the difference. In this case, the generated L packet represents the PC value log data packet corresponding to the latter PC value of the two adjacent PC values. As an optional example, the 7th bit-31st bit in the L packet is used to record the value of the 1st bit to the 25th bit in the difference between PC2 (the latter PC value) and PC1 (the former PC value).

[0088] Figure 3C A diagram showing the data format of the A packet of the embodiment of the application is shown.

[0089] As shown in Figure 3C The size of the A packet is 64 bits as shown in Figure 3B The A packet includes 0-63 bits as shown. The 0th bit-2nd bit in the A packet is a packet format symbol bit, which is used to represent the type of the data packet. For example, if a data packet is 64 bits, and the 0th bit-2nd bit is 100, the data packet is an A packet. The 3rd bit-5th bit is an ID bit, which represents the ID of the CPU core that submits the PC value corresponding to the data packet. The 6th bit is a channel bit, which represents the PC log channel of the PC value corresponding to the data packet. The 7th bit-53rd bit is a data bit, which is used to record data of the PC value itself, for example, the value of all bits of the PC value or the value of a specified bit in the PC value. For example, the 7th bit-53rd bit in the A packet records the value of the 1st bit to the 47th bit of the PC value. Alternatively, the value of the 1st bit to the 47th bit of the PC value can be recorded as Addr[47:1].

[0090] For example, the 7th bit to the 53rd bit of the A packet is used to record data calculated by the PC value, such as recording the difference between two adjacent PC values or the value of a specified bit in the difference. In this case, the A packet generated represents the PC value log data packet corresponding to the latter PC value of the two adjacent PC values. As an optional example, the 7th bit to the 53rd bit of the A packet is used to record the value of the 1st bit to the 47th bit in the difference between PC2 (the latter PC value) and PC1 (the former PC value). The 54th bit to the 53rd bit of the A packet is not used and can be a default value such as 0.

[0091] It should be understood that, in the process of generating the PC value log data packet corresponding to each PC value by the compression subunit 202 for each PC value collected by the collection subunit 201, the PC value log data packet generated for the first PC value collected by the collection subunit 201 each time the collection subunit 201 is powered on to start collection should record the value of all bits of the PC value. For example, the A packet can record the value of all bits of a PC value, and the compression subunit 202 processes the PC value sequence. The PC value log data packet generated for the first PC value should be an A packet (the A packet records the value of all bits of the first PC value), and the PC value log data packet corresponding to other PC values can be one of an S packet, an L packet, and an A packet.

[0092] As an optional example, the PC value output by the CPU core is 48 bits, and the PC value sequence generated by the CPU core in a certain period of time is [10000, 10002, 10004, 10006, 10008, 10010]. The PC value log data packet corresponding to each PC value is generated by processing each PC value in the PC value sequence. The first PC value log data packet needs to carry the complete PC value, so the first PC value 10000 in the PC value sequence [10000, 10002, 10004, 10006, 10008, 10010] generates an A packet. The difference between the subsequent PC value and the previous PC value is 2, and the bit that changes between the two adjacent PC values is within the bit range that can be recorded by the data bit of an S packet. The S packet can carry the difference, so the PC value log data packet corresponding to the subsequent PC value is an S packet. Therefore, the PC value log data packets corresponding to the PC value sequence [10000, 10002, 10004, 10006, 10008, 10010] are generated in turn as follows:

[0093] PC value log data packet 1: A packet (carrying PC value = 10000, the PC value is 48 bits); PC value log data packet 2: S packet (carrying PC difference = 2); PC value log data packet 3: S packet (carrying PC difference = 2); PC value log data packet 4: S packet (carrying PC difference = 2); PC value log data packet 5: S packet (carrying PC difference = 2); PC value log data packet 6: S packet (carrying PC difference = 2).

[0094] The size of the PC value sequence [10000, 10002, 10004, 10006, 10008, 10010] is 36 bytes, the total size of the generated PC value log data packet sequence (PC value log data packet 1-PC value log data packet 6) is 18 bytes, and the size of the PC value log data packet sequence generated by the PC value log unit is smaller than the size of the PC value sequence. Therefore, the PC value log unit realizes compression of the PC value sequence by combined use of A packets, S packets and L packets in the process of processing PC values in the PC value sequence.

[0095] In order to recover the correct PC value sequence from the PC value log data packets 1-6, for the received A packet, the PC value carried by the A packet is taken as the current PC value, and for the received S packet, the PC difference value carried by the S packet is added to the previous current PC value to obtain a new current PC value.

[0096] For example, the PC value sequence generated by the CPU core in a certain period of time is [10000, 10002, 11004, 11006, 11008, 12010]. Compression of the PC value sequence is realized by combined use of A packets, S packets and L packets to generate PC value log data packets. The data bits in the A packets, S packets and L packets record the difference between adjacent two PC values. The first PC value log data packet needs to carry a complete PC value, so the first PC value 10000 generates an A packet. The difference between the third PC value 11004 and the second PC value 10002 is 1002, the changed bit positions exceed the bit position range that can be recorded by the data bit of the S packet, but do not exceed the bit position range that can be recorded by the data bit of the L packet, the 16-bit S packet cannot carry the difference value, and the 32-bit L packet can carry the difference value, so the format of the PC value log data packet corresponding to the third PC value is L packet, and the formats of the PC value log data packets corresponding to the second PC value, the fourth PC value, the fifth PC value and the sixth PC value are S packets.

[0097] The PC value sequence [10000, 10002, 11004, 11006, 11008, 12010] corresponds to a plurality of PC value log data packets generated in turn as follows: PC value log data packet 1: A packet (carrying PC value = 10000, PC value size is 48 bits); PC value log data packet 2: S packet (carrying PC difference value = 2); PC value log data packet 3: L packet (carrying PC difference value = 1002); PC value log data packet 4: S packet (carrying PC difference value = 2); PC value log data packet 5: S packet (carrying PC difference value = 2); PC value log data packet 6: S packet (carrying PC difference value = 2).

[0098] The size of the PC value sequence [10000, 10002, 11004, 11006, 11008, 12010] is 36 bytes, and the total size of the generated PC value log data packet sequence (PC value log data packet 1-PC value log data packet 6) is 20 bytes.

[0099] In the embodiment of the present application, the PC value sequence is compressed by generating PC value log packets with a specified format for each PC value in the collected PC value sequence, and the A packet, the S packet and the L packet are used in combination, and a tool for processing the PC log can recover the correct PC value sequence from the PC value log data packet.

[0100] In an optional embodiment, before the compression subunit 202 generates the PC value log data packet with a specified format for the PC value sequence, the PC value sequence is further subjected to a deduplication process. For example, in the case where there are N identical PC values in the PC value sequence (N is a positive integer greater than 1), the compression subunit 202 deletes (N-1) identical PC values in the PC value sequence, and only one PC value is retained in the PC value sequence. The PC value log data packet with a specified format corresponding to each PC value in the deduplicated PC value sequence is generated.

[0101] In an optional embodiment, the compression subunit 202 further compresses the PC value sequence using a compression algorithm (such as the Huffman compression algorithm) to generate the PC value log data packet with a specified format corresponding to each PC value.

[0102] Continuing to refer to Figure 2 After the PC value log unit 200 collects the PC value output by the CPU core (such as the PC value log data packet corresponding to the PC value), the collected PC value needs to be stored in the memory (such as the DRAM). The PC value log unit 200 and the memory transmit data through a bus. In different application scenarios, the bus bit width between the PC value log unit 200 and the memory can be different, for example, the bus bit width is 128 bits or 64 bits. However, the size of the PC value log data packet generated by the PC value log unit 200 may not be consistent with the bus bit width. For example, the size of the PC value log data packet with a specified format generated by the PC value log unit 200 is, for example, 32 bits, 16 bits or 64 bits. However, when transmitting data through the bus, the size of the transmitted data packet needs to be consistent with the bus bit width. Therefore, the PC value log unit 200 is further provided with a combination subunit 203.

[0103] The combination subunit 203 is coupled with the compression subunit 202, and combines the plurality of PC value log data packets generated by the compression subunit 202 to obtain a combination data packet with a specified size. The size of the combination data packet is consistent with the bus bit width of the coupled PC value log unit.

[0104] For example, the size of a PC value log data packet is inconsistent with the bus width coupled with the PC value log unit, the combination sub-unit 203 combines multiple PC value log data packets into a combination data packet consistent with the bus width, so as to write the PC value log data packet into a storage such as a DRAM through a bus. As an optional example, the size of a PC value log data packet is 16 bits, while the bus width is 256 bits, the combination sub-unit 203 needs to combine 16 PC value log data packets into one combination data packet.

[0105] The PC value log unit provided by the embodiment of the application generates the PC value log data packet corresponding to each PC value by compressing the PC value sequence collected by the collection sub-unit through the compression sub-unit, realizes the compression of the PC value in some scenarios by combining multiple PC value log data packets (such as S packets, L packets and A packets), reduces the size of the PC value sequence, and further reduces the bandwidth of the transmission of the PC value log data packet. In addition, the combination sub-unit combines the PC value log data packet into a combination data packet consistent with the bus width, so as to facilitate the storage of the combination data packet into the storage through the bus.

[0106] As an example, the collection sub-unit 201, the compression sub-unit 202 and the combination sub-unit 203 in the PC value log unit 200 provided by the embodiment of the application are hardware circuit units composed of hardware circuits. As long as the hardware circuit units can realize the corresponding functions, the composition of the hardware circuit units such as the collection sub-unit 201, the compression sub-unit 202 and the combination sub-unit 203 is not limited herein.

[0107] Figure 4 A flowchart of the process of the PC value log unit processing PC values in an embodiment of the application is shown. As shown in the figure, the process of the PC value log unit processing PC values includes: Figure 4

[0108] Step S401: The collection sub-unit collects the PC value output by the CPU core.

[0109] Step S402: The compression sub-unit compresses the PC value sequence formed by one or more PC values collected by the collection sub-unit, and generates the PC value log data packet corresponding to each PC value.

[0110] Step S403: The combination sub-unit combines one or more PC value log data packets to obtain a combination data packet. The combination data packet has a specified size, and the size is consistent with the bus width, for example, 64 bits, 128 bits or 256 bits.

[0111] Step S404: The combination sub-unit stores the combination data packet into a storage such as a DRAM through a bus.

[0112] ​For step S403, if the bus width is 64 bits, the PC value log data packets received by the combination subunit are A packet (such as A1 packet), L packet, S packet (such as S1 packet), A packet (such as A2 packet), S packet (such as S2 packet), S packet (such as S3 packet), and S packet (such as S4 packet) respectively. Then, the combination subunit separately takes A1 packet as combination data packet 1; combines L packet and S1 packet as combination data packet 2, and the combination data packet 2 further includes 16 bits of invalid data because L packet and S packet are 48 bits in total; separately takes A2 packet as combination data packet 3; combines S2 packet, S3 packet, and S4 packet as combination data packet 4, and the combination data packet 4 further includes 16 bits of invalid data because S2 packet, S3 packet, and S4 packet are 48 bits in total. As an example, the invalid data in the combination data packet is located at the low bit of the combination data packet, for example, the 16 bits of invalid data in combination data packet 4 are located at 0-15 bits of combination data packet 4.

[0113] In an optional embodiment, multiple CPU cores are adopted in the control component of the electronic device, and a corresponding PC value log unit is set for each CPU core to collect, compress, and generate combination data packets of the PC value sequence output by the CPU core. Wherein, the CPU cores in the control component are independent of each other, and one CPU core is working while the other CPU cores can be working or not working. The PC value log units are also independent of each other, and independently collect the PC values output by the corresponding CPU core and generate combination data packets.

[0114] In the case that the control component includes multiple CPU cores, the combination data packet generated by one of the PC value log units is transmitted to the DRAM through a multiplexer or an arbitrator.

[0115] As an optional example, as shown in Figure 5 , the control component of the electronic device includes four CPU cores, namely CPU core 0, CPU core 1, CPU core 2, and CPU core 3. A corresponding PC value log unit is set for each CPU core (the PC value log unit can be a PC value log unit 1, a PC value log unit 2, a PC value log unit 3, and a PC value log unit 4 respectively). Figure 2 , Figure 7 , Figure 9 or Figure 10There are four PC value logging units (see PC value logging unit shown): PC value logging unit 0, PC value logging unit 1, PC value logging unit 2, and PC value logging unit 3. CPU core 0, CPU core 1, CPU core 2, and CPU core 3 operate independently of each other. PC value logging units 0, 1, 2, and 3 also independently collect the PC values ​​output by their coupled CPU cores. PC value logging unit 0 collects and compresses the PC values ​​output by CPU core 0 and generates a combined data packet. PC value logging unit 1 collects and compresses the PC values ​​output by CPU core 1 and generates a combined data packet. PC value logging unit 2 collects and compresses the PC values ​​output by CPU core 2 and generates a combined data packet. PC value logging unit 3 collects and compresses the PC values ​​output by CPU core 3 and generates a combined data packet.

[0116] like Figure 5 As shown, the control component further includes a multiplexer coupled to PC value log unit 0, PC value log unit 1, PC value log unit 2, and PC value log unit 3, and selects and stores the combined data packet generated by one of PC value log unit 0, PC value log unit 1, PC value log unit 2, and PC value log unit 3 in a memory, such as a DRAM. For example, the multiplexer stores the combined data packet generated by PC value log unit 0 in the memory during cycle T1, stores the combined data packet generated by PC value log unit 1 in the memory during cycle T2, stores the combined data packet generated by PC value log unit 2 in the memory during cycle T3, and stores the combined data packet generated by PC value log unit 3 in the memory during cycle T4.

[0117] In an optional embodiment, the control component of the electronic device includes multiple CPU clusters, and each CPU cluster includes one or more CPU cores. The CPU clusters are independent of each other, and the operation of the CPU core in one CPU cluster does not affect the operation of the CPU core in another CPU cluster. The CPU cores in each CPU cluster are independent of each other. A corresponding PC value log unit is set for each CPU core in each CPU cluster to collect and compress the PC value output by the corresponding CPU core and generate a combined data packet. The PC value log units are also independent of each other, independently collecting the PC value of the corresponding CPU core and generating a combined data packet. Each CPU cluster corresponds to a multiplexer, and the multiplexer corresponding to each CPU cluster is used to transmit the combined data packet generated by one of the PC value log units corresponding to the CPU cluster to the DRAM. The multiplexers corresponding to each CPU cluster are independent of each other.

[0118] As an optional example, Figure 6As shown, the control component of the electronic device includes two CPU clusters: CPU Cluster 0 and CPU Cluster 1. CPU Cluster 0 includes four CPU cores: CPU Core 0, CPU Core 1, CPU Core 2, and CPU Core 3. CPU Cluster 1 includes two CPU cores: CPU Core 4 and CPU Core 5. CPU Cluster 0 and CPU Cluster 1 are independent of each other. CPU Core 0, CPU Core 1, CPU Core 2, and CPU Core 3 in CPU Cluster 0 are independent of each other. CPU Core 4 and CPU Core 5 in CPU Cluster 1 are independent of each other.

[0119] like Figure 6 As shown, the control component also includes 6 PC value log units (the PC value log unit can be Figure 2 、 Figure 7 、 Figure 9 or Figure 10 The six PC value log units shown are PC value log unit 0, PC value log unit 1, PC value log unit 2, PC value log unit 3, PC value log unit 4, and PC value log unit 5. The six PC value log units are coupled to CPU core 0, CPU core 1, CPU core 2, CPU core 3, CPU core 4, and CPU core 5, respectively. PC value log unit 0 processes the PC value output by CPU core 0, PC value log unit 1 processes the PC value output by CPU core 1, PC value log unit 2 processes the PC value output by CPU core 2, PC value log unit 3 processes the PC value output by CPU core 3, PC value log unit 4 processes the PC value output by CPU core 4, and PC value log unit 5 processes the PC value output by CPU core 5.

[0120] like Figure 6 As shown, the control component also includes multiplexers 1 and 2. Multiplexer 1 corresponds to CPU cluster 0, and multiplexer 2 corresponds to CPU cluster 1. Multiplexer 0 and multiplexer 1 are independent of each other, and the operation of multiplexer 1 is not affected by multiplexer 0. Multiplexer 1 stores the combined data packet generated from one of PC value log units 0, 1, 2, and 3 in DRAM. Multiplexer 2 stores the combined data packet generated from one of PC value log units 4 and 5 in DRAM.

[0121] Figure 7 FIG. 1 shows a structural diagram of a PC value log unit according to another embodiment of the present application. Figure 7 As shown, the PC value log unit 700 includes a collection subunit 701, a multiplexer 702, a compression subunit 703, and a combination subunit 704. The input of the multiplexer is coupled to the output of the collection subunit 701, and the output of the multiplexer is coupled to the input of the compression subunit 703. The output of the compression subunit 703 is coupled to the input of the combination subunit 704.

[0122] The collection subunit 701 collects the PC value output by the CPU core. The collection subunit 701 includes a mode selection module 7011, a continuous mode collection module 7012, an interval trigger mode collection module 7013, and a threshold trigger mode collection module 7014.

[0123] The mode selection module 7011 delivers the PC value from the CPU core to one of the continuous mode collection module 7012, the interval trigger mode collection module 7013, and the threshold trigger mode collection module 7014 according to whether the enable signal is valid. One of the continuous mode collection module 7012, the interval trigger mode collection module 7013, and the threshold trigger mode collection module 7014 collects the PC value output by the CPU core according to its corresponding collection mode. For example, the enable signal corresponding to the continuous mode collection module is valid, and the mode selection module 7011 delivers the PC value output by the CPU core to the continuous mode collection module 7012, which collects the PC value by its corresponding collection mode. For another example, the enable signal corresponding to the interval trigger mode collection module 7013 is valid, and the mode selection module 7011 delivers the PC value output by the CPU core to the interval trigger mode collection module 7013, which collects the PC value by its corresponding collection mode.

[0124] By way of example, the collection mode of the continuous mode collection module 7012 is to continuously collect the PC value output by the CPU core, for example, to continuously collect the PC value at each clock cycle. The collection mode of the interval trigger mode collection module 7013 is to collect the PC value within a preconfigured PC value interval, for example, the preconfigured PC value interval is [0, 10], and the interval trigger mode collection module 7013 is triggered to collect the PC value when the PC value output by the CPU core is between 0 and 10. The collection mode of the threshold trigger mode collection module 7014 is to continuously collect the PC value and deliver the collected PC value to the multiplexer 702 when the PC value output by the CPU core is greater than a preset threshold. Alternatively, the threshold trigger mode collection module 7014 continuously collects the PC value in response to detecting that the PC value output by the CPU core is greater than the preset threshold. For example, if the threshold trigger mode collection module 7014 detects that the PC value output by the CPU core is greater than the preset threshold, the PC value output by the CPU core is collected at each clock cycle in the following. Still alternatively, the threshold trigger mode collection module 7014 periodically collects the PC value in response to detecting that the PC value output by the CPU core is greater than the preset threshold. For example, if the threshold trigger mode collection module 7014 detects that the PC value output by the CPU core is greater than the preset threshold, the PC value is periodically collected according to a configured collection interval, for example, the PC value is collected once every N clock cycles.

[0125] One of the continuous mode acquisition module 7012, the interval triggered mode acquisition module 7013 and the threshold triggered mode acquisition module 7014 transmits the acquired PC value to the multiplexer 702. For example, the multiplexer 702 includes three input ends coupled with the output ends of the continuous mode acquisition module 7012, the interval triggered mode acquisition module 7013 and the threshold triggered mode acquisition module 7014 respectively, and an output end coupled with the input end of the compression sub-module 703, and transmits the PC value acquired by one of the continuous mode acquisition module 7012, the interval triggered mode acquisition module 7013 and the threshold triggered mode acquisition module 7014 to the compression sub-module 703.

[0126] The compression sub-module 703 generates the PC value log data packet with a specified format according to the received PC value. For example, according to the comparison result of the current received PC value and the last PC value, the format of the PC value log data packet corresponding to the current PC value is determined, and the PC value log data packet corresponding to the current PC value is generated according to the format of the PC value log data packet. As shown in FIG. 7, the compression sub-module 703 includes a current PC value register 7031, a last PC value register 7032, a data packet selection module 7033 and a data packet generation module 7034. Figure 7

[0127] The current PC value register 7031 records the current PC value received from the multiplexer 702. The last PC value register 7032 records the last PC value received from the multiplexer 702.

[0128] The data packet selection module 7033 compares the current PC value recorded by the current PC value register (denoted as PC value 2) with the last PC value recorded by the last PC value register (denoted as PC value 1), and selects the format of the PC value log data packet corresponding to the PC value 2 according to the comparison result. For example, the data packet selection module 7033 compares the PC value 2 with the PC value 1 bit by bit, determines the format of the data packet corresponding to the PC value 2 according to the comparison result of the PC value 2 and the PC value 1, generates the PC value log data packet corresponding to the PC value 2 according to the determined format of the PC value log data packet, for example, the PC value log data packet corresponding to the PC value 2 is one of the S packet, the L packet and the A packet.

[0129] The data packet generation module 7034 generates the PC value log data packet corresponding to the current PC value according to the determined format of the PC value log data packet. The specific process of determining the format of the PC value log data packet corresponding to the PC value by the data packet selection module 7033 and generating the PC value log data packet corresponding to the current PC value is described below, which is not repeated here. Figure 8

[0130] ​​The combination sub-unit 704 combines one or more PC value log data packets output by the data packet generation module 7034, generates a combination data packet, and stores the combination data packet into a memory such as a DRAM through a bus. The size of the combination data packet is consistent with the bus bit width used for transmitting the combination data packet.

[0131] The PC value log unit of the embodiments of the present application provides various PC value collection modes, and can provide diversified PC value collection modes for different scenarios and meet different requirements.

[0132] By way of example, the collection sub-unit 701, the multiplexer 702, the compression sub-unit 703, and the combination sub-unit 704 in the PC value log unit 700 are hardware circuit units composed of hardware circuits. As long as the hardware circuit units can realize the corresponding functions, any hardware circuit units can be used, which are not limited herein.

[0133] Figure 8 A flowchart of the PC value log unit of the embodiments of the present application is shown. As shown in the flowchart, Figure 8 the flowchart includes:

[0134] Step S801: The mode selection module 7011 transmits the PC value from the CPU core to one of the continuous mode collection module 7012, the interval trigger mode collection module 7013, and the threshold trigger mode collection module 7014 according to whether the enable signal is valid (such as the process (1) shown in Figure 7 ).

[0135] Step S802: One of the continuous mode collection module 7012, the interval trigger mode collection module 7013, and the threshold trigger mode collection module 7014 collects the PC value output by the CPU core, and transmits the collected PC value to the multiplexer 702.

[0136] The mode selection module 7011 transmits the PC value from the CPU core to the continuous mode collection module 7012 in response to the enable signal of the continuous mode collection module being valid (such as the process (2a) shown in Figure 7 ).

[0137] The mode selection module 7011 transmits the PC value from the CPU core to the interval trigger mode collection module 7013 in response to the enable signal of the interval trigger mode collection module being valid (such as the process (2b) shown in Figure 7 ).

[0138] The mode selection module 7011 transmits the PC value from the CPU core to the threshold trigger mode collection module 7014 in response to the enable signal of the threshold trigger mode collection module being valid (such as the process (2c) shown inFigure 7 The process (2c) shown.

[0139] The continuous mode acquisition module 7012 continuously acquires the PC value output by the CPU core and delivers the acquired PC value to the multiplexer 702 (as shown in Figure 7 The process (3a) shown.

[0140] The interval trigger mode acquisition module 7013 acquires the PC value and delivers the acquired PC value to the multiplexer 702 (as shown in Figure 7 The process (3b) shown.

[0141] The threshold trigger mode acquisition module 7013 continuously acquires the PC value and delivers the acquired PC value to the multiplexer 702 (as shown in Figure 7 The process (3c) shown.

[0142] Step S803: The multiplexer 702 delivers the currently received PC value to the compression subunit 703.

[0143] The compression subunit 703 stores the current PC value delivered by the multiplexer into the current PC value register (as shown in Figure 7 The process (4a) shown.

[0144] Step S804: The compression subunit 703 determines the PC value log data packet format corresponding to the current PC value and generates the PC value log data packet corresponding to the current PC value based on the PC value log data packet format.

[0145] The compression subunit 703 stores the last PC value stored in the current PC value register into the last PC value register (as shown in Figure 7 The process (4b) shown.

[0146] The data packet selection module 7033 compares the current PC value stored in the current PC value register with the last PC value stored in the last PC value register and selects the format of the PC value log data packet corresponding to the current PC value according to the comparison result (as shown in Figure 7 The process (5a) shown. If the current PC value is the same as the last PC value, the last PC value is discarded (as shown in Figure 7 The process (5b) shown.

[0147] For example, if the current PC value is different from the previous PC value, the current received PC value is compared with the previous PC value to determine the range of bit positions in which there is a change between the two adjacent PC values, and the format of the PC value log data packet corresponding to the current PC value is determined according to the range. For example, if the PC value is 48 bits, and the range of changed bit positions between the two adjacent PC values is N+8 and below (N represents the starting bit position of the valid bits recorded in the PC value log data packet), the format of the PC value log data packet is selected to be an S packet; if the range of changed bit positions between the two adjacent PC values is 25 and below, the format of the PC value log data packet is selected to be an L packet; and if the range of changed bit positions between the two adjacent PC values is 47 and below, the format of the PC value log data packet is selected to be an A packet. As an example, the first PC value received by the compression subunit 703 corresponds to a PC value log data packet in the format of an A packet.

[0148] For another example, the current received PC value and the previous PC value are each divided into three parts (47-26 bits, 25-N+9 bits, and N+8-N bits, where N represents the starting bit position of the valid bits recorded in the PC value log data packet). The 26-47 bits are compared to determine whether they are the same. If the 26-47 bits are the same, the A packet is not selected, and the 25-N+9 bits are compared. If the 26-47 bits are different, the format of the PC value log data packet is selected to be an A packet. If the 25-N+9 bits are the same, the N+8-N bits are compared. If the 25-N+9 bits are different, the format of the PC value log data packet is selected to be an L packet. If the N+8-N bits are different, the format of the PC value log data packet is selected to be an S packet.

[0149] The data packet generation module generates a PC value log data packet corresponding to the selected format of the PC value log data packet for the current PC value (as shown in process (6) of FIG. 8), and delivers the PC value log data packet to the combination subunit (as shown in process (7) of FIG. 8). Figure 7 Figure 7 The combination subunit combines the PC value log data packets corresponding to the plurality of PC values to generate a combined data packet, and stores the combined data packet to the DRAM through the bus (as shown in process (8) of FIG. 8).

[0150] Step S805: The combination subunit combines the PC value log data packets corresponding to the plurality of PC values to generate a combined data packet, and stores the combined data packet to the DRAM through the bus (as shown in process (8) of FIG. 8). Figure 7

[0151] ​​In an optional embodiment, there is also a queue (e.g., a first-in-first-out queue FIFO) between the PC value logging unit and a memory (e.g., a DRAM), and the combined data packets are buffered to the memory through the queue. The PC value logging unit buffers the generated combined data packets to the queue first, and then stores the combined data packets buffered in the queue to the memory (e.g., a DRAM). However, the input frequency and the output frequency of the queue are not necessarily the same. Due to the limited queue depth (i.e., the limited number of combined data packets that can be stored in the queue), when the input frequency of the queue is greater than the output frequency, the queue will overflow because the speed of the combined data packets input to the queue is greater than the speed of the combined data packets read from the queue. When the queue overflows, all the overflowed data packets are not reliable. To improve the reliability of the data packets, in an optional embodiment of the present application, the PC value logging unit can include an overflow detection subunit to detect whether the queue overflows. When it is detected that the queue overflows, the collection of the PC values is stopped.

[0152] Figure 9 A structure diagram of the PC value logging unit according to an embodiment of the present application is shown. As shown in Figure 9 Based on the PC value logging unit shown in Figure 7 The PC value logging unit 700 further includes an overflow detection subunit 705. The overflow detection subunit 705 is coupled to the mode selection module 7011. In response to detecting that the queue overflows, the overflow detection subunit 705 generates a control signal and sends the control signal to the mode selection module 7011 to control the mode selection module 7011 to invalidate the enable signal, so that the collection subunit stops collecting the PC values.

[0153] Figure 10 A structure diagram of the PC value logging unit according to another embodiment of the present application is shown. As shown in Figure 10 Based on the PC value logging unit shown in Figure 9 The PC value logging unit further includes a data packet generation subunit 706.

[0154] In response to detecting that the generation condition of the related data packet is met, the data packet generation subunit 706 generates the related data packet in a specified format. Optionally, the related data packet generated by the data packet generation subunit 706 can include at least one of the following types: a synchronization data packet, a timestamp data packet, a timeout data packet, and an overflow data packet.

[0155] Optionally, in response to detecting that the PC value logging unit is powered on, the data packet generation subunit 706 generates a synchronization data packet. The synchronization data packet records the time information of generating the synchronization data packet, to represent the time information when the PC value logging unit is powered on and starts to work.

[0156] Optionally, the data packet generating subunit 706 generates a timestamp data packet in response to a specified time interval or a specified number of PC values being collected. The timestamp data packet records time information of generating the timestamp data packet.

[0157] Optionally, the data packet generating subunit 706 generates an overflow data packet in response to the overflow detecting subunit 1004 detecting a buffer queue overflow. The overflow data packet records time information of generating the overflow data packet to represent that the queue has overflowed.

[0158] Optionally, the data packet generating subunit 706 generates a timeout data packet in response to the compression subunit not generating a PC log data packet within a specified time length, to represent that a timeout condition has occurred. As an example, the timeout data packet includes a timestamp data packet and an A packet; wherein the timestamp data packet included in the timeout data packet records time of generating the timestamp data packet, to represent time of the timeout condition occurring.

[0159] As an example, the data packet generating subunit 706 is coupled with the queue, and stores the generated relevant data packets into the queue, and then stores the data packets in the queue into the memory.

[0160] In an optional embodiment, the above-mentioned synchronization data packet, timestamp data packet and overflow data packet are all 64-bit data packets.

[0161] Figure 11A A schematic diagram of the synchronization data packet is shown. As shown in Figure 11A the 0th-2nd bits of the synchronization data packet are packet format symbol bits. If the 0th-2nd bits are 111, it indicates that the data packet is a synchronization data packet. The 3rd-5th bits of the synchronization data packet are ID bits, representing an ID of a CPU core corresponding to the PC value log unit. The 6th bit is a channel bit, representing a PC log channel corresponding to the PC value collected by the PC value log unit. The 7th-63rd bits are data bits, recording time information of generating the synchronization data packet.

[0162] Figure 11B A schematic diagram of the timestamp data packet is shown. As shown in Figure 11B the 0th-2nd bits of the timestamp data packet are packet format symbol bits. If the 0th-2nd bits are 201, it indicates that the data packet is a timestamp data packet. The 3rd-5th bits of the timestamp data packet are ID bits, representing an ID of a CPU core corresponding to the PC value log unit. The 6th-63rd bits are data bits, recording time information of generating the timestamp data packet.

[0163] Figure 11C A schematic diagram of the overflow data packet is shown. As shown in Figure 11CAs shown, bits 0-2 of the overflow packet are the packet formatting bits. If bits 0-2 are 011, the packet is an overflow packet. Bits 3-5 of the overflow packet are the Core bits, which identify the CPU core to which the overflow packet corresponds. Bit 6 is a fixed value of 0, and bits 7-63 are data bits, recording the time when the overflow packet was generated.

[0164] Figures 12-16 Shown respectively Figure 10 The flow chart of processing PC value of PC value log unit is shown in FIG. Figure 12 As shown, the data processing flow of the PC value log unit includes:

[0165] Step S1201: Collect PC values ​​according to the selected designated collection mode.

[0166] Step S1202: compress the collected PC values ​​and generate a corresponding PC value log data packet with a specified format for each PC value.

[0167] Step S1203: Combine the multiple generated PC value log data packets to obtain a combined data packet with a specified size.

[0168] Step S1204: Add the generated combined data packet to a queue.

[0169] Step S1205: Move the combined data packets in the queue to a memory such as a DRAM.

[0170] like Figure 13 As shown, the data processing flow of the PC value log unit also includes:

[0171] Step S1301: In response to detecting a queue overflow, an overflow data packet is generated.

[0172] Step S1302: Stop collecting PC values.

[0173] Step S1303: Add the generated overflow data packet to the queue.

[0174] Optionally, the order of step S1302 and step S1303 can be reversed, for example, first adding the generated overflow data packet to the queue and then stopping collecting the PC value. Still optionally, the PC value logging unit does not execute step S1302, but only executes steps S1301 and S1303.

[0175] like Figure 14 As shown, the data processing flow of the PC value log unit also includes:

[0176] Step S1401: in response to not collecting PC values or not generating PC value log data packets within a specified length of time, generating a timestamp data packet and an A packet, the generated timestamp data packet and A packet as a timeout data packet.

[0177] Step S1402: adding the generated timeout data packet to the queue.

[0178] As shown in Figure 15 , the data processing flow of the PC value logging unit further includes:

[0179] Step S1501: in response to a specified time interval, generating a timestamp data packet; or in response to generating a specified number of PC value log data packets, generating a timestamp data packet.

[0180] Step S1502: adding the generated timestamp data packet to the queue.

[0181] As shown in Figure 16 , the data processing flow of the PC value logging unit further includes:

[0182] Step S1601: in response to the PC value logging unit starting to collect PC values, generating a synchronization data packet.

[0183] Step S1602: adding the generated synchronization data packet to the queue.

[0184] As can be seen from Figures 12-16 , the PC value logging unit generates synchronization data packets, timestamp data packets, timeout data packets, and overflow data packets independently of each other, and do not affect each other. The PC value logging unit detects that the generation condition of a certain related data packet is met, and then generates the related data packet.

[0185] Figure 17 A flowchart of the PC value logging unit processing PC values according to an embodiment of the present application is shown. As shown in Figure 17 , the flowchart includes:

[0186] Step S1701: starting to collect PC values output by the CPU core.

[0187] Step S1702: determining whether to set a collection interval or set a collection threshold.

[0188] Step S1703-1: in the case where the collection interval and the collection threshold are not set, continuously collecting PC values.

[0189] Step S1702-2: in the case where the collection interval is set and the interval trigger collection mode enabling signal is valid, collecting PC values according to the interval trigger collection mode.

[0190] Step S1703-3: In the case of setting the acquisition threshold, determine whether the enable signal of the threshold triggered acquisition mode is valid; in the case of determining that the enable signal of the threshold triggered acquisition mode is valid, acquire the PC value in the threshold triggered acquisition mode. Or in the case of setting the acquisition interval, determine whether the enable signal of the interval triggered acquisition mode is valid; in the case of determining that the enable signal of the interval triggered acquisition mode is valid, acquire the PC value in the interval triggered acquisition mode.

[0191] Step S1704: Compare the current PC value with the last PC value, and determine the comparison result.

[0192] Step S1705: According to the comparison result, determine the format of the PC value log data packet corresponding to the current PC value.

[0193] Step S1706: According to the format of the PC value log data packet corresponding to the current PC value, generate the PC value log data packet corresponding to the current PC value.

[0194] Step S1707-1: Combine one or more PC value log data packets to generate a combined data packet.

[0195] Step S1707-2: In response to starting to acquire the PC value, generate a synchronization data packet.

[0196] Step S1707-3: In response to a specified time interval or a specified number of PC values being acquired, generate a timestamp data packet.

[0197] Step S1707-4: In response to not acquiring a PC value or not generating a PC value log data packet within a specified length of time, generate a timestamp data packet and an A packet, and the generated timestamp data packet and A packet are used as a timeout data packet.

[0198] Step S1707-5: In response to detecting that the queue is overflowed, generate an overflow data packet, and stop acquiring the PC value.

[0199] Step S1708: Store the combined data packet, the synchronization data packet, the timestamp data packet, the timeout data packet and the overflow data packet in the queue.

[0200] Step S1709: Determine whether the queue is overflowed.

[0201] Step S1710: In the case of the queue not being overflowed, move the combined data packet, the synchronization data packet, the timestamp data packet, the timeout data packet and the overflow data packet in the queue to the DRAM.

[0202] In this embodiment, steps S1707-1, S1707-2, S1707-3, S1707-4, and S1707-5 are not executed sequentially, and there is no order in the timing of generating each data packet. These steps are independent of each other.

[0203] Figure 18 FIG. 1 shows a schematic diagram of the structure of the control component of an embodiment of the present application. Figure 18 As shown, the control component includes CPU Cluster 0 and CPU Cluster 1. CPU Cluster 0 includes two CPU cores, CPU Core 0 and CPU Core 1. CPU Cluster 1 includes two CPU cores, CPU Core 2 and CPU Core 3. CPU Cluster 0 and CPU Cluster 1 are independent of each other, CPU Core 0 and CPU Core 1 are independent of each other, and CPU Core 2 and CPU Core 3 are independent of each other.

[0204] like Figure 18 As shown, the control component further includes PC value logging unit 0, PC value logging unit 1, PC value logging unit 2, and PC value logging unit 3. PC value logging unit 0, PC value logging unit 1, PC value logging unit 2, and PC value logging unit 3 are independent of each other. PC value logging unit 0 is coupled to CPU core 0 and processes the PC value output by CPU core 0. PC value logging unit 1 is coupled to CPU core 1 and processes the PC value output by CPU core 1. PC value logging unit 2 is coupled to CPU core 2 and processes the PC value output by CPU core 2. PC value logging unit 3 is coupled to CPU core 3 and processes the PC value output by CPU core 3.

[0205] like Figure 18As shown, the control component further comprises a data packet merging unit 0, a data packet merging unit 1, a data packet merging unit 2 and a data packet merging unit 3. The data packet merging unit 0 is coupled with the PC value log unit 0 and merges one or more data packets outputted by the PC value log unit 0. The data packet merging unit 1 is coupled with the PC value log unit 1 and merges one or more data packets outputted by the PC value log unit 1. The data packet merging unit 2 is coupled with the PC value log unit 2 and merges one or more data packets outputted by the PC value log unit 2. The data packet merging unit 3 is coupled with the PC value log unit 3 and merges one or more data packets outputted by the PC value log unit 3. The data packets outputted by the PC value log units comprise, for example, a combination data packet, an overflow data packet, a synchronization data packet, a time stamp data packet, a timeout data packet, and each data packet merging unit merges the data packets outputted by the corresponding PC value log unit to generate a merged data packet. For example, the data packet merging unit 0 obtains a combination data packet, a synchronization data packet, a time stamp data packet and an overflow data packet from the PC value log unit 0, and the data packet merging unit 0 merges one or more of the combination data packet, the synchronization data packet, the time stamp data packet and the overflow data packet to generate a merged data packet. For example, the size of the merged data packet is 256 bits, and the sizes of the combination data packet, the synchronization data packet, the time stamp data packet and the overflow data packet are 64 bits respectively, and thus the data packet merging unit 0 merges four 64-bit data packets into one merged data packet, such as merging three combination data packets and one synchronization data packet into one merged data packet.

[0206] As Figure 18As shown, the control component further includes multiplexer 0, multiplexer 1, queue 0, queue 1 and arbiter. Multiplexer 0 is coupled with packet merging unit 0 and packet merging unit 1, and stores the merged packet output from one of packet merging unit 0 and packet merging unit 1 into queue 0. Multiplexer 1 is coupled with packet merging unit 2 and packet merging unit 3, and stores the merged packet output from one of packet merging unit 2 and packet merging unit 3 into queue 1. The arbiter is coupled with queue 0 and queue 1, and selects the merged packet from queue 0 or queue 1 to store into DRAM through the arbiter. The CPU core 0, CPU core 1, CPU core 2 and CPU core 3 in the control component share the bandwidth of the bus, and the bus bandwidth is allocated to each CPU core through multiplexer 0, multiplexer 1 and the arbiter. For example, in Tl period, multiplexer 0 selects to store the merged packet generated by packet merging unit 0 into queue 0. In T2 period, multiplexer 0 selects to store the merged packet generated by packet merging unit 1 into queue 0. In T3 period, multiplexer 1 selects to store the merged packet generated by packet merging unit 2 into queue 1. In T4 period, multiplexer 1 selects to store the merged packet generated by packet merging unit 3 into queue 1. Meanwhile, in Tl period and T2 period, the arbiter stores the packet in queue 0 into DRAM. In T3 period and T4 period, the arbiter stores the packet in queue 1 into DRAM.

[0207] In an optional embodiment, if only one or part of the CPU cores are working in a certain period of time, the multiplexer allocates the bus bandwidth to the working CPU cores. For example, in a certain period of time, only CPU core 0 and CPU core 1 are working in the control component, and the bus bandwidth is allocated to CPU core 0 and CPU core 1 through multiplexer 0. For example, in Tl period, multiplexer 0 selects to store the merged packet generated by packet merging unit 0 into queue 0. In T2 period, multiplexer 0 selects to store the merged packet generated by packet merging unit 1 into queue 0. In T3 period, multiplexer 0 selects to store the merged packet generated by packet merging unit 0 into queue 0. In T4 period, multiplexer 0 selects to store the merged packet generated by packet merging unit 1 into queue 0. Meanwhile, in Tl period-T4 period, the arbiter stores the packet in queue 0 into DRAM.

[0208] Figure 19 A flowchart of the control component processing PC values in the embodiment of the present application is shown. As shown, the flowchart includes: Figure 19

[0209] Step S1901: Each PC value log unit collects the PC value output by the CPU core coupled thereto, and generates a combination data packet and a related data packet.

[0210] ​Step S1902: Each PC value log unit passes the generated combined data packet and the associated data packet to the data packet merging unit coupled thereto.

[0211] Step S1903: Each data packet merging unit merges the combined data packet and the associated data packet received thereby to obtain a merged data packet.

[0212] Step S1904: The multiplexer selects the merged data packet generated by one of the data packet merging units coupled thereto from the plurality of data packet merging units coupled thereto and stores the merged data packet into the corresponding queue.

[0213] Step S1905: The arbiter selects the merged data packet stored in one of the queues coupled thereto from the plurality of queues coupled thereto and stores the merged data packet into the DRAM.

[0214] While the preferred embodiments of the application have been described, additional variations and modifications can be made to the preferred embodiments by those skilled in the art once they learn of the basic inventive concepts. Therefore, the appended claims are intended to cover all such variations and modifications as fall within the scope of the application. It should be apparent that the application can be embodied in a variety of forms other than the specific embodiments described and that the "specific embodiments" have been used only for the purposed of exemplification. Accordingly, the application is not limited to the specific embodiments described. Rather, it is intended to cover all modifications and alternatives that fall within the scope of the application as defined by the appended claims and their equivalents.

Claims

1. A program counter value logging unit, characterized by The program counter value log unit is coupled with the central processor core, and the program counter value log unit comprises a collection subunit, a compression subunit and a combination subunit; The collection subunit is coupled with the central processor core and collects the program counter values output by the central processor core; The compression subunit is coupled with the collection subunit and compresses the program counter values collected by the collection subunit to generate program counter value log data packets of a specified format corresponding to each of the program counter values; The combination subunit is coupled with the compression subunit and combines one or more program counter value log data packets generated by the compression subunit to obtain a combination data packet.

2. The program counter value logging unit according to claim 1, characterized in that, The collection subunit comprises a mode selection module, a continuous mode collection module, an interval trigger mode collection module and a threshold trigger mode collection module; The mode selection module transmits the program counter values output by the central processor core to one of the continuous mode collection module, the interval trigger mode collection module and the threshold trigger mode collection module according to an enable signal to enable one of the continuous mode collection module, the interval trigger mode collection module and the threshold trigger mode collection module to work; When the continuous mode collection module works, it continuously collects the program counter values output by the central processor core; When the interval trigger mode collection module works, it collects the program counter values within a preset program counter value interval output by the central processor core; When the threshold trigger mode collection module works, it continuously or periodically collects the program counter values output by the central processor core in response to detecting that the program counter values output by the central processor core are greater than a preset threshold.

3. The program counter value logging unit according to claim 1 or 2, characterized in that, The compression subunit comprises a current program counter value register, a last program counter value register, a data packet selection module and a data packet generation module; The current program counter value register records a first program counter value received currently, and the last program counter value register records a second program counter value received last time; The data packet selection module compares the first program counter value with the second program counter value and selects the type of the program counter value log data packet corresponding to the first program counter value according to the comparison result; The data packet generation module generates the program counter value log data packet corresponding to the first program counter value according to the determined type of the program counter value log data packet.

4. The program counter value logging unit according to any of claims 1-3, characterized by The program counter value log unit is coupled with a queue, and the queue buffers the combination data packet output by the program counter value log unit; The program counter value log unit further comprises an overflow detection subunit, which is coupled with the collection subunit and the queue, and detects whether the queue is overflowed; The collection subunit stops collecting the program counter values output by the central processor core in response to the overflow detection subunit detecting that the queue is overflowed. The program counter value log unit further comprises a data packet generation subunit; 5. The program counter value logging unit according to any one of claims 1 to 4, wherein: ​ The data packet generating subunit generates the relevant data packet with a specified format in response to detecting that a relevant data packet generating condition is met.

6. A control unit, characterized by The control component includes at least one central processor core and at least one program counter value log unit as claimed in claims 1-5, and the central processor core and the program counter value log unit correspond one-to-one. The program counter value log unit is coupled to the corresponding central processor core, collects a sequence of program counter values output by the central processor core, compresses the sequence of program counter values, generates corresponding program counter value log data packets with a specified format for each program counter value in the sequence of program counter values, and combines one or more program counter value log data packets to obtain a combined data packet.

7. The control member of claim 6, wherein The control component includes at least one central processor cluster, each central processor cluster includes at least one central processor core, and each central processor core is coupled to a program counter value log unit, and the number of program counter value log units is the same as the total number of central processor cores included in the plurality of central processor clusters.

8. The control component of claim 7, wherein, Each central processor cluster corresponds to a first multiplexer, and the program counter value log unit corresponding to each central processor core in each central processor cluster is coupled to the first multiplexer corresponding to the central processor cluster; and the first multiplexer selects the combined data packet or the relevant data packet output by one of all the program counter value log units coupled thereto in each clock cycle and transmits the combined data packet or the relevant data packet to the memory.

9. The control unit according to any one of claims 6 to 8, characterized in that The control component further includes at least one data packet merging unit, and the data packet merging unit corresponds one-to-one to the program counter value log unit. The data packet merging unit is coupled to the program counter value log unit, receives the combined data packet and / or the relevant data packet output by the program counter value log unit, merges the combined data packet and / or the relevant data packet continuously output by the program counter value log unit to obtain a merged data packet, and the size of the merged data packet is consistent with the bus bit width coupled to the control component.

10. The control unit according to claim 9, characterized in that The control component further includes at least one second multiplexer, at least one queue, and an arbitrator. Each second multiplexer is coupled to one or more data packet merging units and coupled to one queue, and selects the merged data packet output by one of the one or more data packet merging units and sends the merged data packet to the queue coupled thereto in each clock cycle. The arbitrator is coupled to the at least one queue, and selects the merged data packet from one of the at least one queue and sends the merged data packet to the memory coupled thereto in each clock cycle.

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