Process control method, device and equipment for digital chip back-end design, and medium

Abstract

The application discloses a kind of process control methods, device, equipment and medium of digital chip back-end design, it is related to digital integrated circuit design technical field, the method includes: the each digital back-end design file obtained is parsed, obtains parameter information;According to parameter information, from the static rule in basic rule set, target static rule is matched and screened;According to target static rule, generate basic flow sequence;With the electronic design automation tool as target flow sequence, the execution result of target flow sequence is obtained, by using target flow sequence;According to the design state information monitored, from the dynamic rule in dynamic programming set, target dynamic rule is matched and screened, and target flow sequence is adjusted according to target dynamic rule;The application can dynamically adjust flow sequence, realized the closed-loop feedback control system of support multi-objective joint optimization, improve the rationality of the process of digital chip back-end design.

Description

Technical Field

[0001] This invention relates to the field of digital integrated circuit design technology, and in particular to a process control method, apparatus, equipment and medium for digital chip back-end design. Background Technology

[0002] As semiconductor process nodes continue to shrink to 5 nanometers and below, digital integrated circuit back-end design (i.e., digital chip back-end design) faces increasingly severe challenges in terms of complexity and multiple constraints. Traditional back-end design flows typically follow a fixed sequence of stages (such as placement planning → clock tree synthesis → global routing → physical verification). Their core flaw lies in the fact that the static flow architecture cannot dynamically adapt to real-time changes in the design state. For example, in 7-nanometer and more advanced processes, the nonlinear characteristics of metal layer resistance-capacitance effects and voltage drop (IR Drop) make traditional staged optimization strategies prone to getting trapped in local optima, requiring repeated iterative corrections and resulting in a design cycle extension of more than 30%.

[0003] In related technologies, improved techniques mainly achieve process adjustments for limited scenarios through predefined rule bases, such as a static process control system based on conditional branching. While such solutions can pre-set macro-module layout priorities or clock network optimization strategies for specific process nodes (such as TSMC 7nm), their rule bases are deeply bound to process parameters, making them unable to dynamically respond to sudden congestion and timing violations during the design process. More importantly, this fragmented optimization logic, which prioritizes a single objective, often leads to problems such as excessive power consumption or insufficient area utilization after timing convergence, requiring manual intervention to roll back the process, resulting in high iteration costs.

[0004] Therefore, how to automatically adjust the back-end design process of digital chips, dynamically respond to and handle sudden abnormal states during the design process, and improve the rationality of the back-end design process of digital chips is an urgent problem to be solved. Summary of the Invention

[0005] The purpose of this invention is to provide a process control method, apparatus, device, and computer-readable storage medium for digital chip back-end design, so as to realize automatic adjustment of the digital chip back-end design process, dynamically respond to and handle sudden abnormal states during the design process, and improve the rationality of the digital chip back-end design process.

[0006] To address the aforementioned technical problems, this invention provides a process control method for digital chip back-end design, comprising:

[0007] The acquired digital back-end design files are parsed to obtain parameter information; wherein, the digital back-end design files include physical design data files, timing constraint data files, and power consumption analysis data files, and the parameter information includes at least one of macro module density, clock complexity exponent, power consumption sensitivity, and local congestion rate;

[0008] Based on the parameter information, the target static rule is matched and filtered from the static rules in the basic rule set;

[0009] Based on the target static rules, a basic process sequence is generated; wherein, the basic process sequence includes at least two basic stages;

[0010] The basic process sequence is used as the target process sequence, and the target process sequence is executed using electronic design automation tools to obtain the execution result of the target process sequence;

[0011] When executing the target process sequence using the electronic design automation tool, target dynamic rules are matched and filtered from the dynamic rules in the dynamic programming set based on the monitored design status information, and the target process sequence is adjusted according to the target dynamic rules.

[0012] On the other hand, the macro module density is the ratio of the total area of ​​macro modules to the area of ​​the chip core region; the clock complexity index is the product of the number of clock domains and the average clock tree level; the power consumption sensitivity is the deviation rate between the current power consumption estimate and the design budget; and the local congestion rate is the proportion of areas in the wiring mesh where the resource utilization exceeds the utilization threshold.

[0013] On the other hand, the process of parsing the acquired digital back-end design files to obtain parameter information includes:

[0014] The key fields of each digital back-end design file are parsed to obtain the extraction parameters of each digital back-end design file.

[0015] Based on the extracted parameters, fusion computing parameters are obtained; wherein, the parameter information includes the extracted parameters and the fusion computing parameters, and the fusion computing parameters include at least one of the macro module density, the clock complexity index, the power consumption sensitivity, and the local congestion rate.

[0016] On the other hand, the process of parsing key fields in each of the digital backend design files to obtain extraction parameters for each of the digital backend design files includes:

[0017] Based on the file extension of each digital back-end design file, determine the key field information corresponding to each digital back-end design file.

[0018] Based on the key field information, the key fields of each digital backend design file are parsed to obtain the extraction parameters of each digital backend design file.

[0019] On the other hand, after parsing the key fields of each digital backend design file based on the key field information to obtain the extraction parameters of each digital backend design file, the method further includes:

[0020] Based on the association index between each of the digital back-end design files, generate the associated parameter set corresponding to the extracted parameters;

[0021] Correspondingly, obtaining the fusion calculation parameters based on the extracted parameters includes:

[0022] Based on the extracted parameters from the associated parameter set, the fusion calculation parameters are obtained.

[0023] On the other hand, determining the key field information corresponding to each of the digital back-end design files based on their file extensions includes:

[0024] Verify whether the file header of the current digital back-end design file is the preset file header corresponding to the current file extension; wherein, the current digital back-end design file is any of the aforementioned digital back-end design files, and the current file extension is the file extension of the current digital back-end design file;

[0025] If so, determine the key field information corresponding to the current digital back-end design file based on the current file extension;

[0026] If not, output a data format error message for the current digital back-end design file.

[0027] On the other hand, generating the basic process sequence based on the target static rules includes:

[0028] Based on the priority of the target static rules corresponding to each preset basic stage, the usage static rules corresponding to each preset basic stage are determined; wherein, the usage static rules are the target static rules with the highest priority.

[0029] The basic process sequence is generated based on the static rules described above.

[0030] On the other hand, the preset basic stages are each stage in the preset basic process sequence, and the basic process sequence is the process sequence of all or part of the preset basic stages corresponding to the preset basic process sequence.

[0031] On the other hand, generating the basic process sequence based on the use of static rules includes:

[0032] Based on the static rules corresponding to each preset basic stage in the preset basic process sequence, the order of the steps within each preset basic stage is adjusted to generate the basic process sequence.

[0033] On the other hand, the method also includes:

[0034] Based on the historical frequency of effectiveness of each static rule in the basic rule set, the priority of each static rule in the basic rule set is adjusted.

[0035] On the other hand, the method also includes:

[0036] Based on the obtained project information, the priority of each static rule in the basic rule set is adjusted.

[0037] On the other hand, adjusting the target process sequence according to the target dynamic rules includes:

[0038] Insert the incremental optimization stage corresponding to the target dynamic rule into the target process sequence.

[0039] On the other hand, the execution of the target process sequence using electronic design automation tools includes:

[0040] Send a status transition command to the electronic design automation tool to control the electronic design automation tool to execute the incremental optimization phase.

[0041] On the other hand, adjusting the target process sequence according to the target dynamic rules includes:

[0042] Control jump to execute the target already executed basic stage in the target process sequence; wherein, the target already executed basic stage is any already executed basic stage in the target process sequence.

[0043] On the other hand, matching and filtering target static rules from static rules in the basic rule set based on the parameter information includes:

[0044] Using a decision rule engine, the target static rule is matched and filtered from the static rules in the basic rule set based on the parameter information of the JS key-value pair data format.

[0045] On the other hand, the physical design data file includes .def and .lef files, the timing constraint data file includes .sdc files, and the power consumption analysis data file includes .upf files.

[0046] On the other hand, the step of using electronic design automation tools to execute the target process sequence and obtain the execution result of the target process sequence includes:

[0047] Based on the decision result of the current stage in the target process sequence, obtain the script command corresponding to the electronic design automation tool;

[0048] Control the electronic design automation tool to execute the script commands.

[0049] The present invention also provides a process control device for digital chip back-end design, comprising:

[0050] The feature extraction module is used to parse the acquired digital back-end design files and obtain parameter information; wherein, the digital back-end design files include physical design data files, timing constraint data files and power analysis data files, and the parameter information includes at least one of macro module density, clock complexity exponent, power sensitivity and local congestion rate;

[0051] The static matching module is used to match and filter target static rules from static rules in the basic rule set based on the parameter information.

[0052] The process generation module is used to generate a basic process sequence based on the target static rules; wherein the basic process sequence includes at least two basic stages;

[0053] The process execution module is used to take the basic process sequence as the target process sequence, execute the target process sequence using electronic design automation tools, and obtain the execution result of the target process sequence.

[0054] The dynamic matching module is used to match and filter target dynamic rules from the dynamic rules in the dynamic programming set based on the monitored design status information when executing the target process sequence using the electronic design automation tool at the current stage, and adjust the target process sequence according to the target dynamic rules.

[0055] The present invention also provides a process control device for digital chip back-end design, comprising:

[0056] Memory, used to store computer programs;

[0057] A processor is used to implement the steps of the flow control method for digital chip back-end design as described above when executing the computer program.

[0058] In addition, the present invention provides a computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the flow control method for digital chip back-end design as described above.

[0059] The present invention provides a process control method for digital chip back-end design, comprising: parsing acquired digital back-end design files to obtain parameter information; wherein the digital back-end design files include physical design data files, timing constraint data files, and power consumption analysis data files, and the parameter information includes at least one of macromodule density, clock complexity index, power consumption sensitivity, and local congestion rate; matching and filtering target static rules from static rules in a basic rule set according to the parameter information; generating a basic process sequence according to the target static rules; wherein the basic process sequence includes at least two basic stages; using the basic process sequence as the target process sequence, and executing the target process sequence using electronic design automation tools to obtain the execution result of the target process sequence; while executing the current stage of the target process sequence using electronic design automation tools, matching and filtering target dynamic rules from dynamic rules in a dynamic programming set according to the monitored design status information, and adjusting the target process sequence according to the target dynamic rules.

[0060] As can be seen, this invention generates a basic process sequence based on target static rules. It utilizes parameter information parsed from digital back-end design files to match and generate the basic process sequence, avoiding the problem of deep binding between the rule base and specific process nodes. This facilitates adaptation to the design constraints and device characteristics of new process nodes. Furthermore, by matching and filtering target dynamic rules from the dynamic rules in the dynamic programming set based on monitored design status information during the current stage of executing the target process sequence using electronic design automation tools, and adjusting the target process sequence according to these dynamic rules, the invention dynamically adjusts the process sequence, avoiding redundant calculations in traditional processes. This achieves a closed-loop feedback control system supporting multi-objective joint optimization, improving the rationality of the digital chip back-end design process. In addition, this invention also provides a process control device, equipment, and computer-readable storage medium for digital chip back-end design, which also possess the aforementioned beneficial effects. Attached Figure Description

[0061] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on the provided drawings without creative effort.

[0062] Figure 1 A flowchart illustrating a process control method for digital chip back-end design provided in an embodiment of the present invention;

[0063] Figure 2 This is a flowchart illustrating a parameter extraction method provided in an embodiment of the present invention;

[0064] Figure 3 This is a schematic diagram of the system architecture of a process control method for digital chip back-end design provided in an embodiment of the present invention;

[0065] Figure 4 This is a schematic diagram of the processing flow of a decision rule engine provided in an embodiment of the present invention;

[0066] Figure 5 This is a schematic diagram of the processing flow of an execution controller provided in an embodiment of the present invention;

[0067] Figure 6 This is a structural block diagram of a process control device for digital chip back-end design provided in an embodiment of the present invention;

[0068] Figure 7 This is a schematic diagram of the structure of a process control device for digital chip back-end design provided in an embodiment of the present invention. Detailed Implementation

[0069] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0070] Please refer to Figure 1 , Figure 1 A flowchart illustrating a process control method for digital chip back-end design provided in an embodiment of the present invention. The method may include:

[0071] Step 101: Parse the acquired digital back-end design files to obtain parameter information.

[0072] The digital back-end design files include physical design data files, timing constraint data files, and power analysis data files. The parameter information includes at least one of macro module density, clock complexity index, power sensitivity, and local congestion rate.

[0073] It is understood that the digital back-end design file in this embodiment can be any file required for digital chip back-end design. The digital chip back-end design is a crucial stage in converting the RTL (register-transfer level) code of the logic design into a physical layout. EDA (Electronic Design Automation) tools are used to complete the physical implementation of timing convergence, power optimization, and area constraints, ultimately generating a manufacturable chip layout.

[0074] Correspondingly, the specific number and type of digital back-end design files in this step can be set by the designer according to the usage scenario and user needs. For example, digital back-end design files can include physical design data files, timing constraint data files, and power analysis data files. Physical design data files can be used to store physical design data (such as layout information and process constraints). For instance, physical design data files can include layout information files for storing layout information, such as DEF (Design Exchange Format) files (i.e., .def files), and process constraint files for storing process constraints, such as LEF (Library Exchange Format) files (i.e., .lef files). Timing constraint data files can be used to store timing constraint data (such as clock definitions and design objectives); timing constraint data files can be SDC (Synopsys Design Constraint) files (i.e., .sdc files). Power analysis data files are used to store power analysis data (such as voltage domain partitioning and current density distribution); power analysis data files can be UPF (Unified Power Format) files (i.e., .upf files).

[0075] It should be noted that the parameter information in this embodiment can be parameters obtained by parsing each digital backend design file, used for subsequent static rule matching. The specific content of the parameter information in this embodiment can be set by the designer according to the practical scenario and user needs. For example, the parameter information can include parameters that can be directly extracted from each digital backend design file (i.e., extracted parameters) and parameters that need to be obtained by fusing and calculating the extracted parameters from multiple digital backend design files (i.e., fused calculation parameters). For example, the extraction parameters in a layout information file (such as a .def file) may include any one or more of the following: macro module coordinates, standard cell distribution, metal layer utilization, and clock tree layout coordinates; the extraction parameters in a process constraint file (such as a .lef file) may include any one or more of the following: metal layer stacking rules, minimum linewidth spacing, and via density limits; the extraction parameters in a timing constraint data file (such as a .sdc file) may include any one or more of the following: clock definition-related main frequency, clock domain partitioning and clock tree hierarchy, and design target-related maximum frequency, power budget, and signal slope constraints; the extraction parameters in a timing constraint data file (such as a .sdc file) may include any one or more of the following: clock definition-related main frequency, clock domain partitioning and clock tree hierarchy, and design target-related maximum frequency, power budget, and signal slope constraints; the extraction parameters in a power analysis data file (such as a .upf file) may include any one or more of the following: voltage domain partitioning-related power network structure and shutdown domain configuration, and current density distribution-related peak current and average current of each functional module.

[0076] Accordingly, the aforementioned fusion computing parameters may include at least one of macromodule density, clock complexity index, power sensitivity, and local congestion rate, to improve the accuracy of the generated basic process sequence through the setting of fusion computing parameters. For example, fusion computing parameters may include macromodule density, clock complexity index, power sensitivity, and local congestion rate. Among them, the ratio of the total area of ​​macromodules to the area of ​​the chip core region is used to identify macro-intensive design scenarios; the clock complexity index is the product of the number of clock domains and the average clock tree level, used to quantify the difficulty of clock network optimization; power sensitivity is the deviation rate between the current power consumption estimate and the design budget, used to guide the triggering of low-power processes; and the local congestion rate is the proportion of areas in the routing mesh where resource utilization exceeds the utilization threshold, used to provide early warning of routing bottlenecks.

[0077] In this step, the specific method for parsing the acquired digital backend design files and obtaining parameter information can be set by the designer according to the practical scenario and user needs. For example, if the parameter information includes extracted parameters and fusion calculation parameters, this step can parse the key fields of each digital backend design file to obtain the extracted parameters; based on the extracted parameters, the fusion calculation parameters can be obtained, such as... Figure 2 As shown, the extracted parameters are calculated and fused using a feature extraction engine to obtain fused calculation parameters; among them, the fused calculation parameters include at least one of macro module density, clock complexity exponent, power consumption sensitivity and local congestion rate.

[0078] Correspondingly, to facilitate the parsing and extraction of the aforementioned parameters, since the file extensions of each digital back-end design file are different (i.e., different file types), the process of parsing key fields of each digital back-end design file to obtain the extraction parameters may include: determining the key field information corresponding to each digital back-end design file based on its file extension; and parsing the key fields of each digital back-end design file based on the key field information to obtain the extraction parameters. In other words, in this embodiment, the key field information corresponding to the file extensions of each digital back-end design file can be pre-set, such as automatically classifying data types like physical design, timing constraints, and power planning based on the file extension (e.g., .def, .lef, .sdc, or .upf); and utilizing the key field information corresponding to each data type to perform corresponding key field parsing to obtain the extraction parameters of each digital back-end design file.

[0079] Furthermore, the method provided in this embodiment may also include a verification process for digital back-end design files to avoid parsing anomalies caused by data format errors in the digital back-end design files. For example, the process of determining the key field information corresponding to each digital back-end design file based on its file extension may include: verifying whether the file header of the current digital back-end design file is a preset file header corresponding to the current file extension (such as the VERSION field in the first line of a .def file); if so, determining the key field information corresponding to the current digital back-end design file based on the current file extension; if not, outputting a data format error message for the current digital back-end design file; wherein, the current digital back-end design file is any digital back-end design file, and the current file extension is the file extension of the current digital back-end design file.

[0080] For example, the parsing process of each digital back-end design file in step 101 may include the following steps: a) File format identification: Based on the file extensions of each digital back-end design file (such as .def, .lef, .sdc, and .upf, etc.), classify data types such as physical design, timing constraints, and power planning; verify the file header of each digital back-end design file (such as the VERSION field in the first line of the .def file) to prevent parsing anomalies caused by data format errors. b) Key field parsing: For physical design, key fields such as COMPONENTS (component coordinates) and TRACKS (routing tracks) can be extracted from the .def file; for timing constraints, instructions from key fields such as create_clock (clock definition) and set_input_delay (input delay) can be extracted from the .sdc file; for power planning, key fields such as create_power_domain (voltage domain division) and create_supply_net (power supply network) can be extracted from the .upf file. c) Data Association Mapping: Establish cross-file association indexes (e.g., associate clock definitions in a .sdc file with clock tree layout coordinates in a .def file); generate a unified set of association parameters to support subsequent comprehensive calculations of extracted parameters, resulting in fused calculation parameters. Then, as follows... Figure 2 As shown, the feature information containing the fusion calculation parameters and the extracted parameters is used as a structured feature vector and output in JSON (JavaScript Object Notation, JS key-value pair data format) format to facilitate the use of parameter information in step 102.

[0081] Accordingly, after parsing the key fields of each digital backend design file based on the key field information to obtain the extraction parameters of each digital backend design file, the process may further include: generating a set of associated parameters corresponding to the extraction parameters based on the association index between the digital backend design files. Correspondingly, obtaining the fusion calculation parameters based on the extraction parameters may include: obtaining the fusion calculation parameters based on the extraction parameters in the set of associated parameters. This embodiment does not limit the specific storage format of the associated parameter set; for example, the associated parameter set may be a table file.

[0082] like Figure 3As shown, this step utilizes a feature extraction module to collect and calculate parameter information corresponding to each digital backend design file in real time. This information is then output to the decision rule engine in the form of structured feature vectors (such as JSON format) for subsequent static rule matching. For example, the output format of macro-density, clock complexity, power sensitivity, and local congestion in the parameter information (design_features) can be as follows:

[0083] {

[0084] "design_features": {

[0085] "macro_density": 0.35,

[0086] "clock_complexity": 4.2,

[0087] "power_sensitivity": 0.18,

[0088] "local_congestion": 0.12

[0089] }

[0090] }

[0091] Step 102: Based on the parameter information, match and filter the target static rules from the static rules in the basic rule set.

[0092] In this embodiment, the basic rule set can be a set of pre-set static rules; the static rules can be rules used to adjust the process of digital chip back-end design (i.e., digital back-end design process) based on the parameter information of digital back-end design files.

[0093] Correspondingly, the specific number and content of static rules in the basic rule set of this embodiment can be set by the designer according to the practical scenario and user needs. For example, the strategies recommended by the Design Rule Manuals (DRM) of various foundries can be integrated to configure static rules; for example, for the extraction parameters in the digital back-end design file, the 4LPP (a 4-nanometer process) specification requires that the clock-first process be used for designs with multiple clock domains (e.g., ≥4), that is, the static rules can include rules that adopt the clock-first process when the number of clock domains is greater than or equal to the clock domain threshold (e.g., 4); for fused calculation parameters Static rules can include rules that prioritize macro-layout when the macro module density is greater than a density threshold (e.g., 25%) to avoid routing congestion caused by later shifts; rules that relax timing constraints and use "useful skew" to help timing convergence when the clock complexity exponent exceeds a complexity threshold to reduce clock tree depth and complexity; rules that batch replace ordinary threshold voltage cells with high threshold voltage cells on paths with sufficient timing margin (Slack) when the power sensitivity exceeds a sensitivity threshold (e.g., 15%); and rules that directly enable congestion optimization options when running the placement tool when the local congestion rate exceeds a congestion rate threshold (e.g., 5%).

[0094] Accordingly, the target static rule in this step can be a static rule matched with the parameter information in the basic rule set. For example, if the local congestion rate in the parameter information exceeds the congestion rate threshold, the rule that directly enables the congestion optimization option when running the layout tool can be matched.

[0095] Correspondingly, the specific method for matching and filtering target static rules from the static rules in the basic rule set based on parameter information in this step can be set by the designer according to the practical scenario and user needs. For example, the parameter information can be directly used to match and filter target static rules from the static rules in the basic rule set. In some embodiments, the static rules in the basic rule set can be stored in categories according to process nodes (such as 7nm, 5nm, and 3nm nodes). In this step, the target static rules can be matched and filtered from the static rules of the target process node in the basic rule set based on the parameter information; wherein, the target process node can be the process node used in the digital back-end design file. This embodiment does not impose any restrictions on this.

[0096] Step 103: Generate the basic process sequence according to the target static rules; wherein the basic process sequence includes at least two basic stages.

[0097] It is understandable that the basic process sequence in this embodiment can be the initial digital backend design process generated using the target static rules matched by parameter information. The specific method for generating the basic process sequence based on the target static rules in this step can be set by the designer according to the practical scenario and user needs. For example, the static rules to be used can be determined based on the priority of each target static rule; and the basic process sequence can be generated based on the static rules to be used. In other words, the static rules to be used (i.e., the target static rules) matched by parameter information can be used to determine the static rules to be used (i.e., the static rules to be used), thereby completing the generation of the basic process sequence. The static rules to be used can be the first preset number of target static rules sorted from high to low priority; or they can be the highest priority target static rule among conflicting target static rules and non-conflicting target static rules. Figure 4 As shown, the decision rule engine can use the main rule engine to determine the target static rule by comparing the parameter information with the conditions of the static rule; then, it can generate the basic process sequence by prioritizing the target static rule.

[0098] Correspondingly, this step can also determine the corresponding static rule for each preset basic stage based on the priority of the target static rule corresponding to each preset basic stage; among which, the static rule used is the target static rule with the highest priority; and the basic process sequence is generated based on the static rule used. In other words, the correspondence between each preset basic stage and its corresponding static rule can be pre-set. Based on the priority of the static rule (i.e., the target static rule) corresponding to each preset basic stage matched with the parameter information, the highest priority target static rule (i.e., the static rule used) corresponding to each preset basic stage is determined, thereby generating the basic process sequence using the static rule used. The preset basic stages can include at least one of Floorplan, Placement, Clock Tree Synthesis (CTS), Routing, and Signoff.

[0099] Accordingly, the aforementioned preset basic stages refer to the stages in the preset basic process sequence, and the aforementioned basic process sequence refers to the process sequence of all or part of the preset basic stages corresponding to the preset basic process sequence. In other words, this step can determine the usage static rules corresponding to each preset basic stage based on the priority of the target static rules corresponding to each preset basic stage in the preset basic process sequence; among which, the usage static rules are the target static rules with the highest priority; based on the usage static rules, the preset basic process sequence is adjusted to generate a basic process sequence. For example, based on the usage static rules corresponding to each preset basic stage in the preset basic process sequence, the sequence of steps within each preset basic stage can be adjusted to generate a basic process sequence, that is, the sequence of steps within a preset basic stage is adjusted using the usage static rules corresponding to a certain preset basic stage.

[0100] Furthermore, the method provided in this embodiment may also include a priority adjustment process for each static rule in the basic rule set to improve the accuracy of the generated basic process sequence. For example, the priority of each static rule in the basic rule set can be adjusted according to the historical effectiveness frequency of each static rule in the basic rule set; that is, in this embodiment, the confidence level of static rules can be evaluated, and their priority can be dynamically adjusted according to the historical effectiveness frequency of static rules (such as rule A being effective in 90% of scenarios).

[0101] In other embodiments, the priority of each static rule in the basic rule set can be adjusted based on the acquired project information. The project information may include the process node (i.e., the target process node) used in the digital back-end design file. If the effect of some static rules is reduced under advanced processes, their priority can be automatically reduced.

[0102] For example, static rules can include the following two rules (rule_macro_priority and rule_clock_first):

[0103] rule_macro_priority = {

[0104] "condition": "macro_density > 0.3",

[0105] "action": ["Floorplan", "PowerPlan", "PlaceMacro", "CTS"],

[0106] "priority": 1

[0107] };

[0108] rule_clock_first = {

[0109] "condition": "clock_complexity >= 5",

[0110] "action": ["CTS", "Placement", "Routing"],

[0111] "priority": 2

[0112] }

[0113] The `rule_macro_priority` rule is triggered when the macro density in the design exceeds 30%, indicating that the chip is a macro-module-intensive design. The success of such designs depends on the proper placement of macro modules. The sequence of actions to be executed is: placement planning -> power planning -> macro module placement and standard cell placement -> clock tree synthesis. A priority of 1 indicates that this is the highest priority rule. Once a design is identified as macro-module-intensive, this process path must be prioritized. This is because if macro modules are not placed properly, all subsequent processes (standard cell placement and routing) will fail.

[0114] The `rule_clock_first` rule is triggered when the clock complexity index (`clock_complexity`) is greater than or equal to 5. This indicates that the design has a certain level of clock complexity, and the clock network will affect the success or failure of the design to some extent. The sequence of actions to be executed is: clock tree synthesis -> standard cell placement -> routing. This is an unconventional but effective process for specific scenarios, often referred to as the "clock-first" or "early clock" process. This rule has lower priority than the previous rule. The system will first determine whether it is a macro-module-intensive design; if not, it will then determine whether the clock is complex to decide whether to adopt the "clock-first" process.

[0115] Step 104: Use the basic process sequence as the target process sequence, and use electronic design automation tools to execute the target process sequence to obtain the execution results of the target process sequence.

[0116] It is understood that the target flow sequence in this embodiment can be the digital back-end design flow that needs to be executed currently. In this step, EDA (Electronic Design Automation) tools can be used to execute the target flow sequence and obtain the execution results, such as netlist files, layout GDSII (Graphic DesignSystem, a database file format) files, or some report files. The EDA tools can be core software suites that automate integrated circuit design, verification, simulation, and manufacturing preparation.

[0117] Correspondingly, the specific method for using electronic design automation (EDA) tools to execute the target workflow sequence and obtain the execution results in this step can be set by the designer according to the practical scenario and user needs. For example, in this step, the decision results in each stage of the target workflow sequence can be converted into script commands supported by the EDA tool, so that the EDA tool can execute the script commands to complete the target workflow sequence and obtain the execution results of the target workflow sequence returned by the EDA tool. In other words, this step may include obtaining the script commands corresponding to the EDA tool based on the decision results of the current stage in the target workflow sequence; and controlling the EDA tool to execute the script commands; wherein, the current stage can be any stage in the target workflow sequence.

[0118] like Figure 3 As shown, in this step, the execution controller can be used to process the decision results (such as...). Figure 5 Decision instructions in the code are converted into script commands supported by EDA tools (such as...). Figure 5 Electronic Design Automation (EDA) commands, such as Tcl (Tool Command Language, a scripting language) or Python (a programming language), are used to schedule the various stages in the target workflow sequence. Correspondingly, the execution controller can communicate with various EDA tools (such as...) through a standardized interface layer. Figure 3 Interacting with the electronic design automation toolchain in China.

[0119] Step 105: When executing the target process sequence using electronic design automation tools at the current stage, based on the monitored design status information, match and filter the target dynamic rules from the dynamic rules in the dynamic programming set, and adjust the target process sequence according to the target dynamic rules.

[0120] It is understood that in this embodiment, when using EDA tools to execute each stage of the target process sequence, the current design status information (such as wiring congestion rate and timing violation number) can be monitored to achieve real-time monitoring of design status information. For example, the execution controller can be used to receive design status information sent by the EDA tool. The execution controller can transmit design status information and script commands to the EDA tool through the OpenAccess database, support cross-tool data synchronization, and realize intermediate database driving.

[0121] Accordingly, the dynamic programming set in this embodiment can be a set of pre-set dynamic rules; dynamic rules can be rules used to adjust the digital backend design process by matching design state information. Correspondingly, the specific number and content of dynamic rules in the dynamic programming set in this embodiment can be set by the designer according to practical scenarios and user needs. For example, historical projects can be summarized and learned to obtain various dynamic rules; for example, common patterns can be extracted from more than 100 successfully taped-out projects to obtain various dynamic rules, forming an experience rule base (i.e., the dynamic programming set). For example, dynamic rules may include rules that trigger the metal density optimization stage in advance when the metal layer utilization rate is detected to be greater than the metal layer utilization rate threshold (e.g., 80%) during the layout stage; they may also include rules that insert an incremental timing fix stage if the number of timing path violations exceeds 5% of the total number of paths.

[0122] Furthermore, each dynamic rule can also be set with its own priority. When the monitored design status information matches multiple dynamic rules (i.e. target dynamic rules) at the same time, the target process order can be adjusted according to the target dynamic rules and their priorities; for example, the target process order can be adjusted using the target dynamic rule with the highest priority.

[0123] It should be noted that the specific method for adjusting the target process sequence according to the target dynamic rules in this step can be set by the designer. For example, an incremental optimization stage corresponding to the target dynamic rule can be inserted into the target process sequence, such as inserting an adjacent stage (i.e., an incremental optimization stage) after the current stage, inserting an incremental optimization stage at the end of the target process sequence, or inserting an incremental optimization stage before the current stage. Correspondingly, during the execution of the target process sequence using the electronic design automation (EDA) tool, a status jump command can be sent to the EDA tool to control the execution of the incremental optimization stage, thereby realizing the jump of the inserted incremental optimization stage. For example, the execution controller can be used to send the status jump command based on XML (Extensible Markup Language) or JSON protocol to trigger the EDA tool to execute a specified operation. In some other embodiments, the jump can also be controlled to execute the target already executed basic stage in the target process sequence; wherein, the target already executed basic stage is any already executed basic stage in the target process sequence, i.e., the basic stage corresponding to the target dynamic rule. This embodiment does not impose any restrictions on this.

[0124] like Figure 3 As shown, the execution controller can monitor the execution status information of the EDA tool in real time and feed it back to the feature extraction module, enabling the feature extraction module to adjust the target process sequence according to dynamic rules, forming a continuous iterative mechanism of "data acquisition → intelligent decision-making → precise execution → status closed-loop feedback".

[0125] For example, the basic process sequence is Floorplan→Placement→CTS→Routing; the target process sequence, dynamically adjusted using target dynamic rules, can be Floorplan→[Insert PowerPlan]→Placement→[Insert PartialRouting (Pre-routing)]→CTS→Routing.

[0126] In this embodiment, the present invention generates a basic process sequence based on target static rules. This can utilize parameter information parsed from digital back-end design files to match and generate a basic process sequence, avoiding the problem of deep binding between the rule base and specific process nodes. This facilitates adaptation to the design constraints and device characteristics of new process nodes. By matching and filtering target dynamic rules from dynamic rules in the dynamic programming set based on the monitored design status information when executing the target process sequence using electronic design automation tools, and adjusting the target process sequence according to the target dynamic rules, the process sequence can be dynamically adjusted. This avoids redundant calculations in traditional processes, realizes a closed-loop feedback control system that supports multi-objective joint optimization, and improves the rationality of the digital chip back-end design process.

[0127] Corresponding to the above method embodiments, this invention also provides a process control device for digital chip back-end design. The process control device for digital chip back-end design described below and the process control method for digital chip back-end design described above can be referred to in correspondence.

[0128] Please refer to Figure 6 , Figure 6 This is a structural block diagram of a process control device for digital chip back-end design provided in an embodiment of the present invention. The device may include:

[0129] The feature extraction module 10 is used to parse the acquired digital back-end design files and obtain parameter information. The digital back-end design files include physical design data files, timing constraint data files, and power analysis data files. The parameter information includes at least one of macro module density, clock complexity exponent, power sensitivity, and local congestion rate.

[0130] The static matching module 20 is used to match the target static rule from the static rules in the basic rule set according to the parameter information.

[0131] The process generation module 30 is used to generate a basic process sequence based on the target static rules; wherein the basic process sequence includes at least two basic stages;

[0132] The process execution module 40 is used to take the basic process sequence as the target process sequence, and use electronic design automation tools to execute the target process sequence to obtain the execution result of the target process sequence.

[0133] The dynamic matching module 50 is used to match and filter target dynamic rules from the dynamic rules in the dynamic programming set based on the monitored design status information when executing the target process sequence using electronic design automation tools at the current stage, and adjust the target process sequence according to the target dynamic rules.

[0134] On the other hand, macro module density is the ratio of the total area of ​​macro modules to the area of ​​the chip core region; clock complexity index is the product of the number of clock domains and the average clock tree level; power sensitivity is the deviation rate between the current power consumption estimate and the design budget; local congestion rate is the proportion of areas in the wiring mesh where resource utilization exceeds the utilization threshold.

[0135] On the other hand, the feature extraction module 10 may include:

[0136] The field parsing submodule is used to parse key fields of each digital backend design file and obtain the extraction parameters of each digital backend design file.

[0137] The fusion computing submodule is used to obtain fusion computing parameters based on the extracted parameters; wherein, the parameter information includes the extracted parameters and the fusion computing parameters, and the fusion computing parameters include at least one of macro module density, clock complexity exponent, power consumption sensitivity and local congestion rate.

[0138] On the other hand, the field parsing submodule may include:

[0139] The file extension determination unit is used to determine the key field information corresponding to each digital back-end design file based on the file extension of each digital back-end design file.

[0140] The field parsing unit is used to parse the key fields of each digital backend design file based on the key field information, and obtain the extraction parameters of each digital backend design file.

[0141] On the other hand, the feature extraction module 10 may also include:

[0142] The association generation submodule is used to generate the association parameter set corresponding to the extracted parameters based on the association index between each digital back-end design file;

[0143] Correspondingly, the fusion computing submodule can be specifically used to obtain fusion computing parameters based on the extracted parameters from the associated parameter set.

[0144] On the other hand, the extension determination unit may include:

[0145] The file verification subunit is used to verify whether the file header of the current digital back-end design file is the preset file header corresponding to the current file extension; wherein, the current digital back-end design file is any digital back-end design file, and the current file extension is the file extension of the current digital back-end design file;

[0146] The file extension determination sub-unit is used to determine the key field information corresponding to the current digital back-end design file based on the current file extension if it is a preset file header corresponding to the current file extension.

[0147] The error message subunit is used to output a data format error message for the current digital back-end design file if the file header does not correspond to the preset file header of the current file extension.

[0148] On the other hand, the process generation module 30 may include:

[0149] The priority determination submodule is used to determine the usage static rule corresponding to each preset basic stage based on the priority of the target static rule corresponding to each preset basic stage; among which, the usage static rule is the target static rule with the highest priority;

[0150] The process generation submodule is used to generate a basic process sequence based on static rules.

[0151] On the other hand, the preset basic stages are the stages in the preset basic process sequence, and the basic process sequence is the process sequence of all or part of the preset basic stages corresponding to the preset basic process sequence.

[0152] On the other hand, the process generation submodule can be specifically used to adjust the order of steps within each preset basic stage according to the static rules corresponding to each preset basic stage in the preset basic process sequence, and generate the basic process sequence.

[0153] On the other hand, the device may also include:

[0154] The first priority adjustment module is used to adjust the priority of each static rule in the basic rule set based on the historical frequency of effectiveness of each static rule in the basic rule set.

[0155] On the other hand, the device may also include:

[0156] The second priority adjustment module is used to adjust the priority of each static rule in the basic rule set based on the obtained project information.

[0157] On the other hand, the dynamic matching module 50 may include:

[0158] The stage insertion submodule is used to insert incremental optimization stages corresponding to the target dynamic rules into the target process sequence.

[0159] On the other hand, the process execution module 40 may include:

[0160] The jump rotor module is used to send state jump commands to the electronic design automation tool and control the electronic design automation tool to perform the incremental optimization phase.

[0161] On the other hand, the dynamic matching module 50 may include:

[0162] The stage jump module is used to control the jump to execute the target's already executed basic stage in the target process sequence; wherein, the target's already executed basic stage is any already executed basic stage in the target process sequence.

[0163] On the other hand, the static matching module 20 can be specifically used to utilize the decision rule engine to match and filter target static rules from static rules in the basic rule set based on parameter information of JS key-value pair data format.

[0164] On the other hand, physical design data files include .def and .lef files, timing constraint data files include .sdc files, and power analysis data files include .upf files.

[0165] On the other hand, the process execution module 40 may include:

[0166] The command conversion submodule is used to obtain the script commands corresponding to the electronic design automation tools based on the decision results of the current stage in the target process sequence.

[0167] The control execution submodule is used to control the execution of script commands by electronic design automation tools.

[0168] In this embodiment, the process generation module 30 generates a basic process sequence based on target static rules. This can utilize parameter information parsed from digital back-end design files to match and generate the basic process sequence, avoiding the problem of deep binding between the rule base and specific process nodes, and facilitating adaptation to the design constraints and device characteristics of new process nodes. When the target process sequence is executed using electronic design automation tools, the dynamic matching module 50 matches and filters target dynamic rules from the dynamic rules in the dynamic programming set based on the monitored design status information, and adjusts the target process sequence according to the target dynamic rules. This dynamic adjustment of the process sequence avoids redundant calculations in traditional processes, realizes a closed-loop feedback control system that supports multi-objective joint optimization, and improves the rationality of the digital chip back-end design process.

[0169] Corresponding to the above method embodiments, this invention also provides a process control device for digital chip back-end design. The process control device for digital chip back-end design described below and the process control method for digital chip back-end design described above can be referred to in correspondence.

[0170] Please refer to Figure 7 , Figure 7 This is a schematic diagram of a process control device for digital chip back-end design provided in an embodiment of the present invention. The device may include:

[0171] Memory D1 is used to store computer programs;

[0172] Processor D2 is used to implement the steps of the flow control method for digital chip back-end design provided in the above method embodiments when executing a computer program.

[0173] In this embodiment, the process control device can be specifically a host device or a server.

[0174] Corresponding to the above method embodiments, this invention also provides a computer program product. The computer program product described below and the process control method for digital chip back-end design described above can be referred to and correspond to each other.

[0175] A computer program product includes a computer program / instructions that, when executed by a processor, implement the steps of the flow control method for digital chip back-end design provided in the above-described method embodiments.

[0176] Corresponding to the above method embodiments, this invention also provides a computer-readable storage medium. The computer-readable storage medium described below and the process control method for digital chip back-end design described above can be referred to and correspond to each other.

[0177] A computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps of the flow control method for digital chip back-end design as provided in the above-described method embodiments.

[0178] The computer-readable storage medium can specifically be a USB flash drive, a portable hard drive, a read-only memory (ROM), a random access memory (RAM), a magnetic disk, or an optical disk, or any other readable storage medium capable of storing program code.

[0179] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on its differences from other embodiments. Similar or identical parts between embodiments can be referred to interchangeably. For the apparatuses, devices, computer-readable storage media, and computer program products disclosed in the embodiments, since they correspond to the methods disclosed in the embodiments, the descriptions are relatively simple, and relevant parts can be referred to the method section.

[0180] The foregoing has provided a detailed description of the process control method, apparatus, device, and medium for digital chip back-end design provided by this invention. Specific examples have been used to illustrate the principles and implementation methods of this invention. The descriptions of the embodiments above are merely for the purpose of helping to understand the method and core ideas of this invention. It should be noted that those skilled in the art can make various improvements and modifications to this invention without departing from its principles, and these improvements and modifications also fall within the protection scope of this invention.

Claims

1. A process control method for digital chip back-end design, characterized in that, include: The acquired digital back-end design files are parsed to obtain parameter information; wherein, the digital back-end design files include physical design data files, timing constraint data files, and power consumption analysis data files, and the parameter information includes at least one of macro module density, clock complexity exponent, power consumption sensitivity, and local congestion rate; Based on the parameter information, target static rules are matched and filtered from the static rules in the basic rule set; wherein, the static rules are rules used to adjust the digital backend design process based on the parameter information of the digital backend design file. Based on the target static rules, a basic process sequence is generated; wherein, the basic process sequence includes at least two basic stages; The basic process sequence is used as the target process sequence, and the target process sequence is executed using electronic design automation tools to obtain the execution result of the target process sequence; When executing the target process sequence using the electronic design automation tool at the current stage, target dynamic rules are matched and filtered from the dynamic rules in the dynamic programming set based on the monitored design status information, and the target process sequence is adjusted according to the target dynamic rules; wherein, the dynamic rules are rules matched with the design status information for adjusting the digital back-end design process; The step of generating the basic process sequence based on the target static rules includes: Based on the priority of the target static rules corresponding to each preset basic stage, the usage static rules corresponding to each preset basic stage are determined; wherein, the usage static rules are the target static rules with the highest priority; the preset basic stages are the stages in the preset basic process sequence, and the basic process sequence is the process sequence of all or part of the preset basic stages corresponding to the preset basic process sequence. Based on the static rules corresponding to each preset basic stage in the preset basic process sequence, the order of the steps within each preset basic stage is adjusted to generate the basic process sequence.

2. The process control method for digital chip back-end design according to claim 1, characterized in that, The macro module density is the ratio of the total area of ​​macro modules to the area of ​​the chip core region; the clock complexity index is the product of the number of clock domains and the average clock tree level; the power consumption sensitivity is the deviation rate between the current power consumption estimate and the design budget; and the local congestion rate is the proportion of areas in the wiring mesh where the resource utilization exceeds the utilization threshold.

3. The process control method for digital chip back-end design according to claim 1, characterized in that, The process of parsing the acquired digital backend design files to obtain parameter information includes: The key fields of each digital back-end design file are parsed to obtain the extraction parameters of each digital back-end design file. Based on the extracted parameters, fusion computing parameters are obtained; wherein, the parameter information includes the extracted parameters and the fusion computing parameters, and the fusion computing parameters include at least one of the macro module density, the clock complexity index, the power consumption sensitivity, and the local congestion rate.

4. The process control method for digital chip back-end design according to claim 3, characterized in that, The step of parsing key fields in each of the digital backend design files to obtain extraction parameters for each of the digital backend design files includes: Based on the file extension of each digital back-end design file, determine the key field information corresponding to each digital back-end design file. Based on the key field information, the key fields of each digital backend design file are parsed to obtain the extraction parameters of each digital backend design file.

5. The process control method for digital chip back-end design according to claim 4, characterized in that, After parsing the key fields of each digital backend design file based on the key field information to obtain the extraction parameters of each digital backend design file, the process further includes: Based on the association index between each of the digital back-end design files, generate the associated parameter set corresponding to the extracted parameters; The step of obtaining the fusion calculation parameters based on the extracted parameters includes: Based on the extracted parameters from the associated parameter set, the fusion calculation parameters are obtained.

6. The process control method for digital chip back-end design according to claim 4, characterized in that, The step of determining the key field information corresponding to each of the digital back-end design files based on their file extensions includes: Verify whether the file header of the current digital back-end design file is the preset file header corresponding to the current file extension; wherein, the current digital back-end design file is any of the aforementioned digital back-end design files, and the current file extension is the file extension of the current digital back-end design file; If so, determine the key field information corresponding to the current digital back-end design file based on the current file extension; If not, output a data format error message for the current digital back-end design file.

7. The process control method for digital chip back-end design according to claim 1, characterized in that, Also includes: Based on the historical frequency of effectiveness of each static rule in the basic rule set, the priority of each static rule in the basic rule set is adjusted.

8. The process control method for digital chip back-end design according to claim 1, characterized in that, Also includes: Based on the obtained project information, the priority of each static rule in the basic rule set is adjusted.

9. The process control method for digital chip back-end design according to claim 1, characterized in that, The step of adjusting the target process sequence according to the target dynamic rules includes: Insert the incremental optimization stage corresponding to the target dynamic rule into the target process sequence.

10. The process control method for digital chip back-end design according to claim 9, characterized in that, Executing the target process sequence using electronic design automation tools includes: Send a status transition command to the electronic design automation tool to control the electronic design automation tool to execute the incremental optimization phase.

11. The process control method for digital chip back-end design according to claim 1, characterized in that, The step of adjusting the target process sequence according to the target dynamic rules includes: Control jump to execute the target already executed basic stage in the target process sequence; wherein, the target already executed basic stage is any already executed basic stage in the target process sequence.

12. The process control method for digital chip back-end design according to claim 1, characterized in that, The step of matching and filtering target static rules from static rules in the basic rule set based on the parameter information includes: Using a decision rule engine, the target static rule is matched and filtered from the static rules in the basic rule set based on the parameter information of the JS key-value pair data format.

13. The process control method for digital chip back-end design according to claim 1, characterized in that, The physical design data files include .def and .lef files, the timing constraint data files include .sdc files, and the power consumption analysis data files include .upf files.

14. The process control method for digital chip back-end design according to any one of claims 1 to 13, characterized in that, Executing the target process sequence using electronic design automation tools and obtaining the execution results of the target process sequence includes: Based on the decision result of the current stage in the target process sequence, obtain the script command corresponding to the electronic design automation tool; Control the electronic design automation tool to execute the script commands.

15. A process control device for digital chip back-end design, characterized in that, include: The feature extraction module is used to parse the acquired digital back-end design files and obtain parameter information; wherein, the digital back-end design files include physical design data files, timing constraint data files and power analysis data files, and the parameter information includes at least one of macro module density, clock complexity exponent, power sensitivity and local congestion rate; The static matching module is used to match and filter target static rules from static rules in the basic rule set according to the parameter information; wherein, the static rules are rules for adjusting the digital backend design process based on the parameter information of the digital backend design file. The process generation module is used to generate a basic process sequence based on the target static rules; wherein the basic process sequence includes at least two basic stages; The process execution module is used to take the basic process sequence as the target process sequence, execute the target process sequence using electronic design automation tools, and obtain the execution result of the target process sequence. The dynamic matching module is used to match and filter target dynamic rules from dynamic rules in the dynamic programming set based on the monitored design status information when executing the target process sequence using the electronic design automation tool at the current stage, and adjust the target process sequence according to the target dynamic rules; wherein, the dynamic rules are rules for adjusting the digital back-end design process matched with the design status information. The process generation module includes: The priority determination submodule is used to determine the usage static rule corresponding to each preset basic stage based on the priority of the target static rule corresponding to each preset basic stage; wherein, the usage static rule is the target static rule with the highest priority; the preset basic stage is each stage in the preset basic process sequence, and the basic process sequence is the process sequence of all or part of the preset basic stages corresponding to the preset basic process sequence. The process generation submodule is used to adjust the order of the steps within each preset basic stage according to the static rules corresponding to each preset basic stage in the preset basic process sequence, and generate the basic process sequence.

16. A process control device for digital chip back-end design, characterized in that, include: Memory, used to store computer programs; A processor, configured to implement the steps of the flow control method for a digital chip back-end design as described in any one of claims 1 to 14 when executing the computer program.

17. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program that, when executed by a processor, implements the steps of the flow control method for digital chip back-end design as described in any one of claims 1 to 14.

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