Memory system, operating method thereof, and readable storage medium

Abstract

Some embodiments of the present application provide a memory system. A memory system includes a memory device and a memory controller coupled with the memory device. Wherein the memory device includes a page buffer; the page buffer includes a latch. The memory controller is configured to acquire data in the latch in response to a program state error occurring when the memory device performs a program operation. And obtaining at least part of recovery data by using the obtained data in the latch.

Description

TECHNICAL FIELD

[0001] Embodiments of the present disclosure relate to the technical field of semiconductor technology, and particularly relate to a memory system and an operating method thereof, and a readable storage medium. BACKGROUND

[0002] Semiconductor memories can be roughly divided into two categories depending on whether they retain stored data when power is off. The two categories of semiconductor memories are volatile memories and non-volatile memories, the volatile memories losing stored data when power is off, and the non-volatile memories retaining stored data when power is off.

[0003] In the case of a programming operation error of the non-volatile memory, a redundant array of independent disks (RAID) can be used to recover all error data. SUMMARY

[0004] Therefore, embodiments of the present disclosure provide a memory system and an operating method thereof, and a readable storage medium, which can more quickly implement data recovery in the case of a programming operation state error, and improve the accuracy of the recovered data.

[0005] In one aspect, some embodiments of the present disclosure provide a memory system, comprising: a memory device and a memory controller coupled with the memory device. The memory device comprises a page buffer; the page buffer comprises a latch.

[0006] The memory controller is configured to: in response to a programming state error occurring when the memory device performs a programming operation, obtain data in the latch. At least part of the recovered data is obtained by using the obtained data in the latch.

[0007] In some examples, the memory device further comprises a storage unit storing a plurality of bits; the latch comprises one or more data latches and a cache latch, wherein one of the data latches is configured to cache one-bit data to be written into the storage unit; and the cache latch is configured to cache data exchanged between the memory device and the memory controller.

[0008] The memory controller is configured to: before obtaining the data in the latch, obtain information indicating a programming mode of the memory device; different programming modes correspond to different times at which the latch releases cache data. And according to the programming mode, determine whether to control the memory device to transfer the data in the data latch to the cache latch, and obtain the data transferred to the cache latch. Wherein, before the data in the data latch is transferred to the cache latch, part of the recovery data is obtained by using the cache data in the cache latch.

[0009] In some examples, the memory controller is configured to: based on the programming mode being a first mode, directly obtain the data in the cache latch, and obtain at least part of the recovery data. Based on the programming mode being a second mode, control the memory device to transfer the data in the plurality of data latches to the cache latch respectively, and obtain the data transferred from the plurality of data latches to the cache latch, and obtain part of the recovery data; and before the data in the data latch is transferred to the cache latch, part of the recovery data is obtained by using the cache data in the cache latch.

[0010] In some examples, the duration for which the cache latch stores cache data corresponding to the first mode is greater than the duration for which the cache latch stores cache data corresponding to the second mode.

[0011] In some examples, the programming mode of the memory device is the first mode; when a programming state error occurs in a programming operation of the memory device, the data in the cache latch is data corresponding to the programming operation.

[0012] The memory controller is configured to: based on the data obtained directly from the cache latch, obtain the recovery data of all the storage bits of the memory cell.

[0013] In some examples, the programming mode of the memory device is the second mode.

[0014] The programming operation performed by the memory device includes a multi-pass programming operation on a group of the memory cells. When a programming state error occurs in a programming operation of a group of the memory cells of the memory device, the data in part of the plurality of data latches has been updated to data corresponding to a next pass of a current pass of the multi-pass programming operation.

[0015] The memory controller is configured to obtain recovery data of the data latch corresponding to the storage bit for which data is not updated based on data transmitted from the data buffer into the cache latch, and to recover error data of the data latch corresponding to the storage bit for which data is updated using a redundant array of independent disks.

[0016] In some examples, the second mode includes a first sub-mode and a second sub-mode; a time at which the cache latch corresponding to the first sub-mode releases cache data is later than a time at which the cache latch corresponding to the second sub-mode releases cache data.

[0017] An amount of data recovered using a redundant array of independent disks when the memory device performs a program operation in the first sub-mode is less than an amount of data recovered using a redundant array of independent disks when the memory device performs a program operation in the second sub-mode.

[0018] In some examples, when the memory device performs a program operation in the first mode, the cache latch releases cache data corresponding to the program operation after all program states pass verification.

[0019] When the memory device performs a program operation in the first sub-mode, the cache latch releases cache data corresponding to the program operation after a first portion of program states pass verification, and updates data corresponding to a next program operation into a portion of the data latches.

[0020] When the memory device performs a program operation in the second sub-mode, the cache latch releases cache data corresponding to the program operation after a second portion of program states pass verification, and updates data corresponding to a next program operation into a portion of the data latches.

[0021] The first portion corresponds to a number of program states that is greater than a number of program states corresponding to the second portion.

[0022] In some examples, the memory controller is configured to send a first command based on the program mode being the second mode.

[0023] The memory device is configured to receive and respond to the first command by transmitting data in the plurality of data latches into the cache latch, respectively.

[0024] In some examples, the first command is configured by setting a feature command.

[0025] In some examples, the memory controller is configured to decode the data of the storage bit corresponding to the data latch that is not updated to obtain user data of the storage bit corresponding to the data latch that is not updated.

[0026] The user data of the storage bit corresponding to the data latch that is not updated is used in combination with the independent redundant disk array to recover error data of the storage bit corresponding to the data latch that is updated to obtain user data of the storage bit corresponding to the data latch that is updated.

[0027] The user data of all the storage bits is encoded, and the memory device is controlled to program the encoded data to a position different from the programming position where the programming state error occurs.

[0028] In some examples, the memory controller includes a buffer; the memory controller is configured to send a second command and a third command.

[0029] The memory device is configured to receive and respond to the second command to send the data in the cache latch to the buffer, and to receive and respond to the third command to program the recovered data to a position different from the programming position where the programming state error occurs.

[0030] In some examples, the memory device includes at least one memory chip; the memory chip includes at least one memory plane; the memory plane includes a plurality of memory blocks.

[0031] The memory controller is configured to send a fourth command.

[0032] The memory device is configured to receive and respond to the fourth command to program the error recovery data to other memory blocks in the memory plane where the programming state error occurs.

[0033] In some examples, the memory controller is configured to control the memory device to re-execute a programming operation using the recovered data. After the re-programming operation is completed, a logical-physical mapping table is updated.

[0034] In the above-mentioned memory system, compared with the method of only using the memory controller to control the recovery of erroneous data in the memory device, the present application can use the memory controller to directly recover the erroneous data in the memory device. For example, the memory controller obtains at least part of the recovered data by directly obtaining and using the data in the latch in the memory device, which not only reduces the resource occupation of the memory controller, but also requires less or no use of the disk to rebuild the data, reducing the occupation of other storage space. Moreover, the delay is short, which is conducive to improving the data recovery speed, reducing errors in the data transmission process, and improving the accuracy of the recovered data.

[0035] In another aspect, some embodiments of the present application provide a method for operating a memory system. The method includes: in response to a program state error occurring during a program operation of a memory device of the memory system, obtaining data in a latch of a page buffer of the memory device; and obtaining at least partial recovery data using the obtained data in the latch.

[0036] In some examples, the memory device further includes a storage unit having multiple storage bits; the page buffer further includes one or more data latches and a cache latch; wherein one of the data latches is configured to cache one bit of data to be written to the storage unit respectively, and the cache latch is configured to cache data interacting between the memory device and the memory controller.

[0037] The method further includes: before acquiring the data in the latch, acquiring information indicating a programming mode of the memory device; different programming modes correspond to different times at which the latch releases cached data. Based on the programming mode, determining whether to control the memory device to transfer the data in the plurality of data latches to the cache latch, and acquiring the data transferred to the cache latch. Prior to transferring the data in the data latches to the cache latch, the cache data is used to obtain a portion of the recovered data.

[0038] In some examples, determining whether to control the memory device to transfer the data in the multiple data latches to the cache latch based on the information of the programming mode includes: based on the programming mode being the first mode, directly obtaining the data in the cache latch of the page cache, and obtaining at least part of the recovered data.

[0039] based on the second mode, controlling the memory device to transfer data in the plurality of data latches to the cache latch respectively, and obtaining the recovery data from the data transferred from the plurality of data latches to the cache latch; and obtaining the recovery data from the cache data in the cache latch before the data in the data latches is transferred to the cache latch.

[0040] In some examples, a time duration for which the cache latch stores cache data corresponding to the first mode is greater than a time duration for which the cache latch stores cache data corresponding to the second mode.

[0041] In some examples, the programming mode of the memory device is the first mode; and the data in the cache latch is corresponding to a programming operation of the memory device when a programming state error occurs in the programming operation.

[0042] The method further includes obtaining the recovery data of all the storage bits of the storage unit based on the data obtained directly from the cache latch.

[0043] In some examples, the programming mode of the memory device is the second mode. The programming operation performed by the memory device includes a multi-pass programming operation on a group of the storage units. When a programming state error occurs in the programming operation of the group of the storage units of the memory device, the data in part of the data latches of the plurality of data latches has been updated to data corresponding to a next pass of a current pass of the multi-pass programming operation.

[0044] The method further includes obtaining the recovery data of the storage bits corresponding to the data latches whose data is not updated based on the data transferred from the data latches to the cache latch; and recovering the error data of the storage bits corresponding to the data latches whose data is updated by a redundant array of independent disks.

[0045] In some examples, the second mode includes a first sub-mode and a second sub-mode; and a time at which the cache latch corresponding to the first sub-mode releases cache data is later than a time at which the cache latch corresponding to the second sub-mode releases cache data.

[0046] An amount of data recovered by a redundant array of independent disks when the memory device performs the programming operation in the first sub-mode is less than an amount of data recovered by the redundant array of independent disks when the memory device performs the programming operation in the second sub-mode.

[0047] In some examples, when the memory device performs a programming operation in the first mode, after all of the program states are verified, the cache latch releases the cache data corresponding to the programming operation.

[0048] When the memory device performs a programming operation in the first sub-mode, after the first part of the program states are verified, the cache latch releases the cache data corresponding to the programming operation and updates the data corresponding to the next programming operation into the partial data latch.

[0049] When the memory device performs a programming operation in the second sub-mode, after the second part of the program states are verified, the cache latch releases the cache data corresponding to the programming operation and updates the data corresponding to the next programming operation into the partial data latch; the number of program states corresponding to the first part is greater than the number of program states corresponding to the second part.

[0050] In some examples, the method further includes: based on the programming mode being the second mode, sending a first command; the first command instructs the memory device to transmit the data in the plurality of data latches into the cache latch respectively.

[0051] In some examples, the first command is configured by setting a feature command.

[0052] In some examples, the method further includes: decoding the data of the data latch whose data is not updated to obtain the user data of the storage bit corresponding to the data latch that is not updated.

[0053] Using the user data of the storage bit corresponding to the data latch that is not updated, and in combination with a redundant array of independent disks, the error data of the storage bit corresponding to the data latch that is updated is recovered to obtain the user data of the storage bit corresponding to the data latch that is updated.

[0054] Encoding the user data of all the storage bits, and controlling the memory device to program the data after encoding to a position different from the programming position where the programming state appears an error.

[0055] In some examples, the method further includes: based on the programming mode being the first mode, sending a second command and a third command; the second command instructs the memory device to output the data in the cache latch of the page buffer; the third command instructs the memory device to program the recovered data to a position different from the programming position where the programming state appears an error.

[0056] In some examples, the memory device includes at least one memory chip; the memory chip includes at least one memory plane; the memory plane includes a plurality of memory blocks.

[0057] The method further includes: sending a fourth command based on the programming mode being the first mode; the fourth command instructs the memory device to obtain the recovery data with the data in the buffer and program the recovery data to other memory blocks of the memory plane where the programming state error occurs.

[0058] In some examples, the method further includes: controlling the memory device to re-perform a programming operation with the recovery data. After the re-programming operation is completed, updating a logical-physical mapping table.

[0059] The memory system provided by any of the above examples has the same beneficial effects as the memory system provided by any of the above examples, which will not be repeated here.

[0060] In another aspect, some embodiments of the present application provide a readable storage medium. The readable storage medium stores a computer program which, when executed, implements the operation method of the memory system provided by any of the above examples.

[0061] The readable storage medium has the same beneficial effects as the operation method of the memory system provided by any of the above examples, which will not be repeated here. BRIEF DESCRIPTION OF DRAWINGS

[0062] In the drawings, like reference numerals can be used to describe like parts throughout the several views. Like reference numerals with different letter suffixes can represent different instances of the like parts. The drawings illustrate generally, by way of example, various embodiments discussed in the present document.

[0063] Figure 1 A structural schematic diagram of an electronic device provided by an embodiment of the present application;

[0064] Figure 2 A structural schematic diagram of a storage medium provided by an embodiment of the present application;

[0065] Figure 3 A structural schematic diagram of another storage medium provided by an embodiment of the present application;

[0066] Figure 4 A structural schematic diagram of a memory system provided by an embodiment of the present application Figure 1 ;

[0067] Figure 5 A structural schematic diagram of a peripheral circuit of a memory system provided by an embodiment of the present application;

[0068] Figure 6 A structure diagram of a page buffer set of a memory system according to an embodiment of the present application;

[0069] Figure 7A A structure diagram of a plurality of latches of a page buffer according to an embodiment of the present application;

[0070] Figure 7B Another structure diagram of a plurality of latches of a page buffer according to an embodiment of the present application;

[0071] Figure 8 A structure diagram of a memory system according to an embodiment of the present application; Figure 2 ;

[0072] Figure 9 A structure diagram of a memory system according to an embodiment of the present application; Figure 3 ;

[0073] Figure 10 A structure diagram of a memory system according to an embodiment of the present application; Figure 4 ;

[0074] Figure 11 A structure diagram of a memory block of a memory system according to an embodiment of the present application;

[0075] Figure 12 A flow diagram of an operation method of a memory system according to an embodiment of the present application; Figure 1 ;

[0076] Figure 13 A storage type and a storage state of a storage unit according to an embodiment of the present application;

[0077] Figure 14 A flow diagram of an operation method of a memory system according to an embodiment of the present application; Figure 1 ;

[0078] Figure 15 A sensing latch verification process diagram of a storage unit shown in Figure 13 ;

[0079] Figure 16 A latch data release and storage data diagram of a storage unit shown in Figure 13 ; Figure 1 ;

[0080] Figure 17 A latch data release and storage data diagram of a storage unit shown in Figure 13 ; Figure 2 ;

[0081] Figure 18 A latch data release and storage data diagram of a storage unit shown in Figure 13Schematic diagram of a latch of the storage unit releasing data and storing data Figure 3 ;

[0082] Figure 19 Schematic diagram of a flow of an operation method of a memory system according to an embodiment of the present application Figure 2 ;

[0083] Figure 20A Schematic diagram of a latch of an operation method of a memory system according to an embodiment of the present application

[0084] Figure 20B Schematic diagram of another latch of an operation method of a memory system according to an embodiment of the present application

[0085] Figure 21 Schematic diagram of another flow of an operation method of a memory system according to an embodiment of the present application Figure 1 ;

[0086] Figure 22 Schematic diagram of another flow of an operation method of a memory system according to an embodiment of the present application Figure 2 ;

[0087] Figure 23 Schematic diagram of another flow of an operation method of a memory system according to an embodiment of the present application Figure 3 ;

[0088] Figure 24 Schematic diagram of another flow of an operation method of a memory system according to an embodiment of the present application Figure 4 . DETAILED DESCRIPTION

[0089] The technical solutions of the present application will be further described in detail below in combination with the accompanying drawings and specific embodiments.

[0090] In the embodiments of the present application, the terms “first”, “second”, and the like are used to distinguish similar objects, and are not used to describe a specific order or sequence.

[0091] In the embodiments of the present application, the term “contacting A and B” includes the case where A and B are directly in contact, or the case where A and B are indirectly in contact with each other with other components interposed therebetween.

[0092] It should be understood that the term "some embodiments" or "some examples" as used throughout this specification means that a particular feature, structure, or characteristic described is included in at least one embodiment of the application. Thus, appearances of the phrases "in some embodiments" or "in some examples" in various places throughout this specification are not necessarily intended to refer to the same embodiment. Furthermore, the particular features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. It should be understood that the sequence of the steps in the above-described processes does not mean the order of execution, and the execution order of the steps should be determined according to their functions and inherent logic, and should not constitute any limitation on the implementation process of the embodiments of the application. The sequence of the above-described embodiments of the application is only for description, and does not represent the advantages or disadvantages of the embodiments.

[0093] It should be noted that the terms "comprises", "comprising", or any other variations thereof, are intended to cover a non-exclusive inclusion, such that a process, method, article, or apparatus that comprises a list of elements does not include only those elements but can also include other elements not expressly listed or inherent to such process, method, article, or apparatus. Without more limitations, an element defined by the phrase "comprising a" does not exclude the existence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0094] It can be understood that the meanings of "on", "over", and "above" in the present disclosure should be interpreted in the broadest way, such that "on" not only means the meaning of "on" with no intervening features or layers therebetween (i.e. directly on), but also includes the meaning of "on" with intervening features or layers therebetween.

[0095] It should be noted that although the present specification is described in terms of embodiments, not every embodiment contains only one independent technical solution, and the description manner of the specification is only for the sake of clarity, and those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be properly combined to form other embodiments that those skilled in the art can understand.

[0096] RAID is a data backup technology that can combine multiple independent physical disks in different ways to form a disk array (i.e. a logical disk), thereby providing higher storage performance and higher reliability performance than a single disk. Each disk can be regarded as a collection of continuous, non-overlapping, fixed-size segments. RAID stores data through multiple stripes, and a stripe includes multiple segments (located in different disks), one of which is a parity information block.

[0097] It should be noted that the "disk" refers to a non-volatile memory for persistently storing data, such as a hard-disk drive (HDD), an optical disk drive, a solid-state drive (SSD), or the like.

[0098] In the process of data recovery after a certain disk in the RAID fails, the data in the failed disk is calculated by one or more parity information blocks set to distribute the error data, and the data is reconstructed in the hot idle disk or hot idle segment to recover the data. For example, one disk in the RAID is used as a hot idle disk; when a disk fails, the hot idle disk (any segment for storing data) can be selected for data reconstruction to obtain the recovered data. Alternatively, each disk can reserve some segments as hot idle segments; when a disk fails, a hot idle segment on another disk can be randomly selected for data reconstruction to obtain the recovered data.

[0099] For example, the types of the RAID include RAID 0, RAID 1, RAID 3, RAID 5, or RAID 6, etc.

[0100] However, the reconstruction speed of the RAID is related to the number of disks. The more the number of disks, the faster the reconstruction speed, and accordingly, the failure rate of the RAID increases, which reduces the accuracy of data recovery of the RAID. Meanwhile, in the process of data calculation of the RAID, a large amount of data calculation is occupied, which occupies more processor (such as a memory controller) resources, and thus reduces the memory system.

[0101] To solve the above problems, the present application provides a memory system, an operating method of the memory system, and a readable storage medium, which can more quickly realize data recovery in the case of a programming operation state error, and improve the accuracy of the recovered data.

[0102] As shown in Figure 1 First, an electronic device 10 is shown in the embodiments of the present application. For example, the electronic device 10 can include but is not limited to a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory device 32 therein.

[0103] Please continue to refer to Figure 1 The electronic device 10 can include a host 20 and a memory system 30.

[0104] The host 20 can be a processor (e.g., a Central Processing Unit (CPU) or a System on Chip (SoC) (e.g., an Application Process (AP)) of the electronic device 10. The host 20 can be configured to transmit data to or receive data from the memory system 30.

[0105] The memory system 30 includes a memory controller 31 and one or more memory devices 32, and other integrated circuit structures for signal transmission. Among them, the memory controller 31 and the one or more memory devices 32 can be integrated and packaged in the same storage medium 40 (see Figure 2 and Figure 3 ). In this way, it is beneficial to apply the memory system 30 to different types of terminal electronic products.

[0106] As shown in Figure 2 and Figure 3 , in some embodiments, the present application provides a readable storage medium 40. The readable storage medium 40 includes stored computer programs or instructions; when the computer programs or instructions are executed, the device where the computer readable storage medium is located implements the operation method of the memory system as provided in any of the subsequent examples.

[0107] The readable storage medium 40 integrates the memory controller 31 and the one or more memory devices 32. Examples of the type of readable storage medium 40 include Universal Flash Storage (UFS) or Embedded Multi Media Card (eMMC) and other types of storage devices.

[0108] In addition, there are many ways to integrate the integrated circuits of the readable storage medium 40, for example, it can be a memory card 410 (as shown in Figure 2 ) formed by integrating a single memory device 32 and a memory controller 31 together, or it can be an SSD 420 (as shown in Figure 3 ) formed by integrating a plurality of memory devices 32 and a memory controller 31 together.

[0109] For example, the memory card 410 can include one or more types of storage devices of a Personal Computer Memory Card International Association (PC) card, a CF card, a SmartMedia (SM) card, a memory stick, a Multi-Media Card (MMC), a Reduced-Size MMC (RS-MMC), an MMC micro, an SD card (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), and a UFS.

[0110] Wherein, please refer to Figure 2 , the memory card 410 further includes a memory card connector 41. The memory card connector 41 is configured to couple the memory card 410 with a host (e.g., the host 20 in Figure 1 ). For example, the memory card connector 41 includes a gold finger.

[0111] Or, please refer to Figure 3 , the SSD 420 further includes an SSD connector 41. The SSD connector 41 is configured to couple the SSD 420 with a host (e.g., the host 20 in Figure 1 ). For example, the SSD connector 41 includes a gold finger.

[0112] It can be understood that the storage capacity and / or operating speed of the SSD 420 is greater than that of the memory card 410.

[0113] The above-mentioned memory controller 31 and the memory device 32 (and the host 20) coupled in the same storage device, the memory controller 31 is configured to control the memory device 32.

[0114] Exemplarily, the memory controller 31 can be designed for operation in a low duty cycle environment. For example, for operation in a Secure Digital (SD) card, a Compact Flash (CF) card, a Universal Serial Bus (USB) flash drive, or other media used in electronic devices such as personal computers, digital cameras, mobile telephones, etc. Exemplarily, the memory controller 31 can be designed for operation in a high duty cycle environment, for example, for operation in an SSD or an embedded Multi-Media Card (eMMC). The SSD or eMMC can be used as data storage for mobile devices such as smartphones, tablet computers, laptop computers, etc., as well as enterprise storage arrays.

[0115] Further, the memory controller 31 can manage data in the memory device 32 and communicate with the host 20. The memory controller 31 can be configured to control read, erase, and program operations of the memory device 32; can be further configured to manage various functions regarding data stored in or to be stored in the memory device 32, including but not limited to bad block management, garbage collection, logical to physical address translation, wear leveling, etc.; and can be further configured to handle error checking and correction (ECC) regarding data read from or written to the memory device 32.

[0116] In addition, the memory controller 31 can also perform any other suitable functions, such as formatting the memory device 32, or communicating with external devices (e.g., a host 20) according to a particular communication protocol, Figure 1The memory controller 31 can communicate with the host 20 through at least one of various interface protocols. Among them, the interface protocols include one or more of a USB protocol, an MMC protocol, a Peripheral Component Interconnect (PCI) protocol, a Peripheral Component Interconnect Express (PCI-E) protocol, an Advanced Technology Attachment (ATA) protocol, a Serial ATA protocol, a Parallel ATA protocol, a Small Computer System Interface (SCSI) protocol, an Enhanced Small Disk Interface (ESDI) protocol, an Integrated Development Equipment (IDE) protocol, a Firewire protocol, and the like.

[0117] The memory device 32 described above can include, but is not limited to, one or more of a NAND flash memory, a vertical NAND flash memory, a NOR flash memory, a Dynamic Random Access Memory (DRAM), a Ferroelectric Random Access Memory (FRAM), a Magnetoresistive Random Access Memory (MRAM), a Phase Change Random Access Memory (PCRAM), a Resistive Random Access Memory (RRAM), a Nano Random Access Memory (NRAM), and the like.

[0118] Based on the above description, the present application takes the memory device 32 as a semiconductor memory, for example, a solid-state electronic device (such as a NAND type memory) for storing data information made by a semiconductor integrated circuit process. The subsequent examples of the present application do not limit the specific internal structure of the memory device 32 and the memory controller 31.

[0119] It is understood that, in order to facilitate the distinction between the adaptive adjustment made by the memory device 32 and the memory controller 31 applied to different memory systems 30, for example, based on the foregoing examples of various structures of the memory device 32, and the generation logic of the control instructions output by the memory controller 31 to the memory device 32, the subsequent examples of the present application provide a memory device (for example, a NAND type memory) for storing the memory device 60 and the memory controller 51 applied to the memory system 50.

[0120] Secondly, in order to solve the above problems, as shown in some embodiments, the present application provides a memory system 50, which can realize data recovery more quickly in the case of programming operation state error, and improve the accuracy of the recovered data. Figures 4-11

[0121] As shown in Figure 4 The memory system 50 includes a memory device 60 and a memory controller 51 coupled to the memory device 60.

[0122] The memory device 60 can include a storage cell array 61 and a peripheral circuit 62 coupled to the storage cell array 61 and the like circuit structure.

[0123] The storage cell array 61 is coupled to a plurality of bit lines BL. For example, the storage cell array 61 can be a NAND flash storage cell array. For example, the storage cell array 61 is a circuit structure arranged in the form of an array of NAND storage strings 611. Each NAND storage string 611 extends vertically on a substrate. For example, each NAND storage string 611 can include a plurality of storage cells coupled in series and stacked vertically. Each storage cell transmits a signal in a state that maintains a continuous analog value (for example, voltage or charge), and the analog value of the storage cell depends on the number of electrons captured in the storage cell region.

[0124] For example, each storage cell in the storage cell array 61 can be a floating gate type storage cell including a floating gate transistor, or a charge trapping type storage cell including a charge trapping transistor. The present application does not limit this.

[0125] In some examples, the storage type of the above-mentioned storage cell includes any one of a single level cell (SLC), a multi level cell (MLC), a triple level cell (TLC), and a quad level cell (QLC).

[0126] ​For example, each memory cell of an SLC can store one bit of data and have two possible first and second storage states. The first storage state (e.g., “0”) corresponds to a first threshold voltage range and the second storage state (e.g., “1”) corresponds to a second threshold voltage range. In this way, the second storage state (e.g., “1”) is an erase state and the first storage state (e.g., “0”) is a program state.

[0127] For another example, each memory cell of an MLC can store two bits of data and have four possible first, second, third, and fourth storage states. The first storage state (e.g., “00”) corresponds to a first threshold voltage range, the second storage state (e.g., “01”) corresponds to a second threshold voltage range, the third storage state (e.g., “10”) corresponds to a third threshold voltage range, and the fourth storage state (e.g., “11”) corresponds to a fourth threshold voltage range. In this way, the fourth storage state (e.g., “11”) is an erase state and the first, second, and third storage states (e.g., “00”, “01”, and “10”) are program states.

[0128] Similarly, each memory cell of a TLC can store three bits of data and have eight possible storage states. The eight storage states correspond to eight threshold voltage ranges, respectively, and specific storage states are not described herein. One of the eight threshold voltage ranges is an erase state (e.g., “111”) and the remaining seven threshold voltage ranges are program states. Also, each memory cell of a QLC can store four bits of data and have sixteen possible storage states. The sixteen storage states correspond to sixteen threshold voltage ranges, respectively, and specific storage states are not described herein. One of the sixteen threshold voltage ranges is an erase state (e.g., “1111”) and the remaining fifteen threshold voltage ranges are program states.

[0129] Please refer to Figure 4 The peripheral circuit 62 described above can be coupled to the memory cell array 61 by bit lines (BLs), word lines (WLs), source lines (SLs), source select gates (SSGs), and drain select gates (DSGs). The peripheral circuit 62 is configured to implement logical operations (e.g., program, read, or write operations) of the memory cell array 61 by applying voltage signals and / or current signals to and sensing voltage signals and / or current signals from each target memory cell via the bit lines BLs, the word lines WLs, the source lines SLs, the source select gates SSGs, or the drain select gates DSGs, etc.

[0130] For example, the peripheral circuit 62 includes various types of circuit structures formed using Metal-Oxide-Semiconductor (MOS) transistors. For example, as shown in FIG. 6A, the peripheral circuit 62 can include a row decoder / word line driver 620, a page buffer (PB) / sense amplifier 621, a column decoder / bit line driver 623, a voltage generator 624, a control logic unit 625, a latch circuit 626, an interface 627, and a data bus 628, and the like. Figure 5

[0131] The page buffer 621 is an important bridge for converting binary data (0 / 1) of external logic into analog signals (threshold voltage / electron number) in the memory device 60. Further, as shown in FIG. 6B, the peripheral circuit 62 can include a page buffer group composed of a plurality of page buffers 621. The page buffer group can be coupled with the memory cell array 61 via a plurality of bit lines (BL1 to BLk). For example, as shown in FIG. 6C, the plurality of page buffers 621 can be respectively coupled with the memory cell array 61 via corresponding bit lines BL1 to BLk, and configured to perform data programming and reading in response to a target signal controlling the memory cells on the memory string 611 (see FIG. 6D). Figure 6 Figure 6 Figure 4

[0132] Based on the above, in some embodiments, the page buffer 621 of the peripheral circuit 62 includes a plurality of latches 6210, and the plurality of latches 6210 include a sense latch (S Latch), a low voltage latch (LVT Latch), a data latch (D Latch), and a cache latch (C Latch).

[0133] The sense latch S Latch can be used to store inhibition information and verification information from a verification operation.

[0134] The cache latch (C Latch) is used for data exchange with the outside, for example, data from the outside is first transmitted to the cache latch (C Latch), and then transmitted to the sense latch S Latch through the cache latch (C Latch). For another example, data in the sense latch (S Latch) is transmitted to the cache latch (C Latch), and then transmitted to the outside through the cache latch (C Latch). The outside can be a memory controller 31 or a host 20, etc. For another example, the cache latch (C Latch) can also be used for other functions, for example, used for temporarily storing verification information. ​​​​

[0135] A data latch (D Latch) can be used to latch data of a specified page of a memory cell. For example, the specified page includes one or more of a lower page (LP), a middle page (MP), and an upper page (UP).

[0136] A low voltage latch (LVT Latch) can be used to store disable information and adjusted verify information from a verify operation.

[0137] It can be appreciated that the number of latches 6210 of the page buffer 621 can vary depending on the type of memory cell.

[0138] For example, each memory cell of an SLC can include 3 latches 6210, including a sense latch (S Latch), a low voltage latch (LVT Latch), and a cache latch (C Latch). The cache latch (C Latch) can be used to latch data of the memory cell.

[0139] For example, each memory cell of an MLC can include 4 latches 6210, including a sense latch (S Latch) 6211, a low voltage latch (LVT Latch), a data latch (D Latch), and a cache latch (C Latch). The data latch (D Latch) can be used to latch lower page (LP) data of the memory cell, and the cache latch (C Latch) can be used to latch upper page (UP) data of the memory cell.

[0140] For example, each memory cell of a TLC can include 5 latches 6210, including a sense latch (S Latch) 6211, a low voltage latch (LVT Latch), two data latches (D Latch), and a cache latch (C Latch). One data latch (D Latch) can be used to latch lower page (LP) data of the memory cell, another data latch (D Latch) can be used to latch middle page (MP) data of the memory cell, and the cache latch (C Latch) can be used to latch upper page (UP) data of the memory cell.

[0141] For example, each memory cell of the QLC can include 6 latches 6210, wherein 4 latches 6210 include a sense latch (S Latch) 6211, a low voltage latch (LVT Latch), three data latches (D Latch), and a cache latch (C Latch). One data latch (D Latch) can be used to latch lower page (LP) data of the memory cell, one data latch (D Latch) can be used to latch middle page (MP) data of the memory cell, another data latch (D Latch) can be used to latch upper page (UP) data of the memory cell, and the cache latch (C Latch) can be used to latch another upper page (XP) data of the memory cell.

[0142] In addition, based on the type and number of latches 6210 included in the storage type of the memory cell, the number of latches 6210 can also be increased (for example, the number of D Latch is increased) according to actual needs, and the present application does not make specific limitations thereto. For example, Figure 7A As shown, the following embodiments take the storage type of the memory cell as QLC and include 6 latches 6210 as an example for illustrative description. For example, the page cache 621 includes a sense latch (S Latch) 6211, a low voltage latch (LVT Latch) 6212, a first data latch (D Latch) 6213, a second data latch (D Latch) 6214, and a third data latch (D Latch) 6215, and a cache latch (C Latch) 6216.

[0143] For example, 4-bit data of a memory cell of a QLC is stored in the first data latch (D Latch) 6213, the second data latch (D Latch) 6214, the third data latch (D Latch) 6215, and the cache latch (C Latch) 6216, respectively. The 4-bit data is transmitted to the sense latch 6211 through the low voltage latch 6212 in sequence, and data programming state verification is performed to obtain a verification result. After the programming state of all storage bits is verified, the cache latch 6216 releases the cache data.

[0144] Based on this, as shown in Figure 8 In some examples, the memory device 60 includes a page cache 621. The page cache 621 includes a latch (Latch).

[0145] The memory controller 51 is configured to obtain data in the latch (Latch) in response to a programming state error occurring when the memory device 50 performs a programming operation. Using the obtained data in the latch (Latch), at least part of the recovery data re_Data is obtained.

[0146] It is understood that a "programming state error" includes the state of a memory device in which some data is not written to the cache or is lost during the programming (writing) process. Furthermore, "recovered data" refers to data obtained by reconstructing data not stored in the cache in the event of a programming state error. At least one of the attributes of this data, such as size and type, is the same as the data in which the error occurred and can be used in subsequent operations. In the examples provided herein, "recovered data" is used to represent the difference between the recovered data and the original data, to facilitate a clearer understanding of the state changes of the data during the data storage process of the memory controller 51 in the memory device 60. Furthermore, it is used to distinguish data that is identical to the original data obtained by subsequent encoding using the recovered data.

[0147] Compared to the method of only using the memory controller to control RAID to recover erroneous data in the memory device 60, the present application can use the memory controller 51 to directly recover the erroneous data in the memory device 60. For example, the memory controller 51 obtains at least part of the recovered data by directly obtaining and using the data in the latch in the memory device 60. This not only reduces the resource usage of the memory controller 51, but also requires less or no disk usage to rebuild data, thereby reducing the usage of other storage space. Moreover, the short delay is conducive to improving the data recovery speed, reducing errors in the data transmission process, and improving the accuracy of the recovered data.

[0148] In some examples, such as Figure 9 As shown, the memory device 60 also includes a memory cell (cell) with multiple storage bits. The page buffer 621 also includes one or more data latches (D Latch) and cache latches (C Latch). Among them, a data latch (D Latch) is configured to cache one bit of data to be written to the memory cell. The cache latch (CLatch) is configured to cache data exchanged between the memory device 60 and the memory controller 51.

[0149] For example, a storage unit with multiple storage bits is QLC, such as Figure 7A As shown, the page buffer 621 includes a sense latch (S Latch) 6211, a low voltage latch (LVT Latch) 6212, three data latches (D Latch) 6213, 6214, and 6215, and a cache latch (C Latch) 6216. The three data latches (D Latch) 6213, 6214, and 6215, and the cache latch (C Latch) 6216 each store one bit of data.

[0150] The memory controller 51 is configured to acquire information indicating a programming mode of the memory device 60 before acquiring data in the latch, different programming modes correspond to different time instants at which the latch releases the cached data, and according to the programming mode, determine whether to control the memory device 60 to transfer the data in the data latch (D Latch) into the cache latch (C Latch) and acquire the data transferred into the cache latch (C Latch). Wherein, before the data in the data latch (D Latch) is transferred into the cache latch (C Latch), the partial recovered data re_Data is obtained by using the cached data in the cache latch (C Latch).

[0151] The above-mentioned cache 52 (see Figure 10 ) does not store data corresponding to the programming operation (for example, data to be read in a read operation), and the un-stored data needs to be acquired from the latch 6210 and re-stored in the cache 52. The "programming mode" is determined based on different processes of acquiring the un-stored data from different latches of the memory device 60, for example, a process in which all the un-stored data in the cache 52 can be acquired from the cache latch (C Latch) corresponds to one programming mode. A process in which the un-stored data in the cache 52 can be acquired from the cache latch (C Latch) and the data latch (D Latch) corresponds to another programming mode. Since the data to be recovered in the cache 52 is still in different latches 6210, different operations need to be performed to acquire the data in all the latches 6210 in different programming modes. In this way, for the different location states of the current un-stored data (i.e., the data to be recovered), the memory controller 51 determines different operation steps for data recovery in response to different programming modes. For example, when all the data to be recovered has been cached into the cache latch (C Latch), the memory controller 51 responds to a command of a first mode Model1; or when part of the data to be recovered has been stored into the data latch (D Latch) and another part has been cached into the cache latch (C Latch), the memory controller 51 responds to a command of a second mode Model2. Different programming modes generate different commands, and the memory controller 51 performs corresponding operation steps in response to different commands.

[0152] In this way, by determining different operation modes through different programming modes, a more suitable data recovery mode is selected, which can improve the speed of data recovery and reduce the time consumption of data recovery. Some embodiments are provided below to exemplarily illustrate the processes of two kinds of data recovery in the first mode Model1 and the second mode Model2.

[0153] In some examples, the memory controller 51 is configured to, based on the programming mode being the first mode Model1, directly obtain data in the cache latch (CLatch) and obtain the at least partially recovered data re_Data.

[0154] Exemplarily, as shown in Figure 10 The memory controller 51 includes a buffer 52.

[0155] It should be noted that the buffer 52 can be located in the memory controller 51 or be an external buffer (located in the memory system 30) in communication with the memory controller 51, and can achieve data buffering and data interaction between the memory controller and the memory device, and the examples provided in the present application do not specifically limit the method of driving the buffer 52. The following examples are exemplarily described with the buffer 52 located in the memory controller 51.

[0156] The memory controller 51 is configured to send a second command based on the programming mode being the first mode Model1. The memory device 60 is configured to, in response to the second command, send data in the cache latch (CLatch) to the buffer 52.

[0157] Exemplarily, the programming mode of the memory device 60 is the first mode Model1; when a programming state error occurs in the programming operation of the memory device 60, the data in the cache latch (CLatch) is all data corresponding to the programming operation.

[0158] The memory controller 51 is configured to, based on the data directly obtained from the cache latch (CLatch), obtain the recovery data re_Data of all storage bits of the storage unit.

[0159] Then, based on the memory device 60 performing the programming operation in the first mode Model1, the cache latch (CLatch) releases the buffered data corresponding to the programming operation after all the programming states are verified.

[0160] For example, after all the programming states of the data latches (D Latch) are verified, the cache latch (C Latch) releases the cache data corresponding to the programming operation. The data in the cache latch (C Latch) is transmitted to the sensing latch for programming state verification through the data latch (D Latch). For example, the programming states of the data in the plurality of data latches (D Latch) can be verified in sequence. After the verification is passed, the cache latch (C Latch) releases the cache data, stores the data corresponding to the next programming operation (e.g., fine programming operation or operation of storing the storage bit of the next storage cell), and then transmits the data to some of the data latches (D Latch). In addition, the verified data can be transmitted to the buffer 52.

[0161] If the verification of the programming state of the data in a certain data latch (D Latch) fails, the data in the cache latch (C Latch) that has not been released is retransmitted to the data latch (D Latch) for verification again.

[0162] In some examples, the storage type of the storage cell is QLC, and the storage cell includes 4 storage bits LP, MP, UP, and XP. The page buffer 621 includes a cache latch 6216. The data in the cache latch (C Latch) is all the data corresponding to the programming operation.

[0163] Based on the programming mode being the first mode Model 1, the memory controller 51 is configured to send a second command. The memory device 60 is configured to receive and respond to the second command by sending the data in the cache latch (C Latch) 6216 to the buffer 52. Then, the memory controller 51 obtains the recovery data re_Data corresponding to the storage bit using the obtained data.

[0164] In other examples, based on the programming mode being the second mode Model 2, the memory device 60 is controlled to transmit the data in the plurality of data latches (D Latch) to the cache latch (C Latch) respectively, and obtain the partial recovery data re_Data from the data transmitted from one or more data latches (D Latch) to the cache latch (C Latch). In addition, the partial recovery data re_Data is obtained using the cache data in the cache latch (C Latch) before the data in the data latch (D Latch) is transmitted to the cache latch (C Latch).

[0165] The above memory controller 51 is configured to send a first command based on the programming mode being the second mode Model 2.

[0166] The memory device 60 is configured to transmit the data in the plurality of data latches (D Latch) into the cache latch (C Latch) respectively in response to the first command.

[0167] The first command is configured by a set feature command. For example, the set feature command can include arbitration, power management, logical address range type, temperature threshold, error recovery, volatile write cache, interrupt coalescing, interrupt coalescing configuration, write atomic normal, asynchronous event configuration, automatic power state transition, host memory buffer, command set specific, hang clock time or time stamp corresponding to absolute time, supported protocol version, etc. In some examples provided by the present application, the memory controller 51 sends the first command based on the set feature command for "error recovery".

[0168] In some examples, the memory controller 51 includes a buffer 52. Based on the programming mode being the second mode Model2, the memory controller 51 is configured to send a second command. The memory device 60 is configured to transmit the data in the cache latch (C Latch) to the buffer 52 in response to the second command.

[0169] It can be understood that the "second command" is used to transmit the data in the cache latch (C Latch) to the buffer 52. The "second command" can not be limited to the type of each programming mode, but can apply to instructions of various programming modes, or can be different instructions with the same function under different programming modes. Some examples provided by the present application do not limit this, and can be set according to actual needs.

[0170] In this way, the data in the cache latch (C Latch) can be transmitted to the buffer 52 in response to the "second command" first, and then the data in the plurality of data latches (D Latch) is transmitted into the cache latch (C Latch) in response to the "first command", so that the data exchange with the external electronic element is realized through the cache latch (C Latch).

[0171] Considering that the data in the data latch (D Latch) can represent different storage states of the storage unit, different ways can be used to recover the data in different storage states. The following embodiments exemplarily embody the recovery way of the data in different storage states by the method of using the data in the data latch (D Latch) under the second mode Model2.

[0172] In some examples, the programming mode of the memory device 60 is the second mode Model2. The programming operation performed by the memory device 60 includes a multi-pass programming operation on a set of memory cells; when a programming state error occurs in the programming operation on the set of memory cells of the memory device 60, the data in a portion of the data latches (D Latch) has been updated to data corresponding to a next pass of the current pass of the multi-pass programming operation.

[0173] The memory controller 51 is configured to obtain the recovery data re_Data of the storage bits corresponding to the data latches (D Latch) whose data has not been updated based on the data transferred from the data latches (D Latch) to the cache latches (C Latch); and to recover the error data of the storage bits corresponding to the data latches (D Latch) whose data has been updated using a redundant array of independent disks (RAID).

[0174] In some examples, the programming operation performed by the memory device 60 includes a multi-pass programming operation on a set of memory cells, for example, the multi-pass programming operation includes performing a fine programming operation after performing a coarse programming operation. When a programming state error occurs in the programming operation on the set of memory cells of the memory device 60, the data in a portion of the data latches (D Latch) is data after the coarse programming operation has been performed and before the fine programming operation has been performed (i.e., the storage bits corresponding to the data latches whose data has not been updated), which can be directly transferred from the data latches (D Latch) to the cache latches (C Latch); the memory controller 51 obtains the data in the cache latches (C Latch) and obtains the recovery data re_Data of the corresponding storage bits. The data in another portion of the data latches (D Latch) is data after the fine programming operation has been performed (i.e., the storage bits corresponding to the data latches whose data has been updated), which can be recovered using a RAID to obtain the recovery data re_Data of the corresponding storage bits.

[0175] In this way, the two data recovery steps can be combined to reduce the time consumption of data recovery and reduce the resource occupation of the processor (e.g., the memory controller) when there is a large amount of unrecorded data, compared to the method of recovering data using a RAID only.

[0176] In another example, if the data in the data latches (D Latch) is all data after the fine programming operation has been performed, the data can also be directly transferred from the data latches (D Latch) to the cache latches (C Latch); the memory controller 51 obtains the data in the cache latches (C Latch) and obtains the recovery data re_Data of the corresponding storage bits.

[0177] In this way, data recovery can be performed without using RAID, reducing the resource occupation of a processor (e.g., a memory controller) and other storage space, and improving the data recovery speed and reducing the time consumption of data recovery compared with the data recovery by using RAID.

[0178] Based on this, in some examples, for the data that has been subjected to fine programming in the second mode Model2 described above, the selection of the sub-mode can be performed according to the size of the amount of data in this part, and then the timing of the cache latch (CLatch) releasing the cache data corresponding to the programming operation in different sub-modes is different, that is, according to the size of the amount of data that the cache latch (CLatch) can store, different sub-modes are selected, which can reduce the probability of data loss caused by the cache latch (CLatch) releasing data faster than the rate of storing data, and improve the accuracy and integrity of data recovery.

[0179] Exemplarily, the second mode Model2 includes a first sub-mode Model21 and a second sub-mode Model22.

[0180] When the memory device 60 performs the programming operation in the first sub-mode Model21, after the first part of the programming state verification passes, the cache latch (CLatch) releases the cache data corresponding to the programming operation, and updates the data corresponding to the next programming operation to the partial data latch (DLatch).

[0181] When the memory device 60 performs the programming operation in the second sub-mode Model22, after the second part of the programming state verification passes, the cache latch (CLatch) releases the cache data corresponding to the programming operation, and updates the data corresponding to the next programming operation to the partial data latch (DLatch).

[0182] After all the programming states in the data latch (DLatch) are verified, the cache latch (CLatch) releases the cache data corresponding to the programming operation. The data of the cache latch (CLatch) is transmitted to the sensing latch (SLatch) through the data latch (DLatch) for programming state (i.e., threshold voltage distribution range) verification. For example, the programming states of the data in the plurality of data latches (DLatch) can be verified in sequence, after the verification passes, the cache latch (CLatch) releases the cache data, and stores the data corresponding to the next programming operation (e.g., fine programming operation or operation of storing the next storage bit of the storage unit), and then transmits to the partial data latch (DLatch). In addition, the verified data can be transmitted to the buffer 52.

[0183] If the programming state of the data in the data latch (D Latch) fails the verification, the data in the cache latch (C Latch) that has not been released is retransmitted to the data latch (D Latch) for verification again.

[0184] For example, the number of programming states corresponding to the first part is greater than the number of programming states corresponding to the second part. It can be understood that the number of programming states corresponding to the first part and the number of programming states corresponding to the second part are used to distinguish the executed fine programming data in different sub-modes, and are not used to divide the executed fine programming data into two parts. Different sub-modes can be selected by judging the size of the amount of executed fine programming data.

[0185] In this way, in the case that the number of programming states that are not stored (for example, the programming states of the first part) is large, the first sub-mode Model21 is used for programming operation, which can occupy fewer resources of the processor (for example, the memory controller) and improve the data recovery speed.

[0186] In addition, the time at which the cache latch (C Latch) corresponding to the first sub-mode Model21 releases the cached data is later than the time at which the cache latch (C Latch) corresponding to the second sub-mode Model22 releases the cached data. In this way, based on the number of programming states corresponding to the first part being greater than the number of programming states corresponding to the second part, the cache latch (C Latch) in the first sub-mode Model21 needs to cache data for a longer time, so as to ensure that the data in the cache latch (C Latch) is stored before being released, reduce the probability of data loss, and improve the accuracy of data recovery.

[0187] In some examples, the storage types of the storage units include QLC, including four storage bits of LP, MP, UP, and XP.

[0188] When the first sub-mode Model21 is used for programming operation, the LP storage bit uses RAID for data recovery, and the MP, UP, and XP storage bits (that is, the data of the first part) are obtained from the cache latch (C Latch) by the memory controller 51 and are recovered to obtain the data re_Data.

[0189] When the second sub-mode Model22 is used for programming operation, the LP and MP storage bits use RAID for data recovery, and the UP and XP storage bits (that is, the data of the second part) are obtained from the cache latch (C Latch) by the memory controller 51 and are recovered to obtain the data re_Data.

[0190] Due to the large amount of data in the first part, the first sub-mode Model 21 is used to obtain and recover the data re_Data from the cache latch (CLatch) through the memory controller 51, which is beneficial to improve the speed of obtaining the un-stored data and reduce the overall time consumption of data recovery.

[0191] At the same time, for the same amount of data, more data is obtained and recovered as the data re_Data from the cache latch (CLatch) through the memory controller 51, and the remaining part of the data is recovered by the independent redundant array of inexpensive disks (RAID). In this way, the amount of data recovered by the RAID in the first sub-mode Model 21 is less than that in the second sub-mode Model 22, which reduces the resource occupation of the processor (such as the memory controller) and further reduces the time consumption of all data recovery in the storage unit.

[0192] In some examples, for the part of data corresponding to the data that has been coarsely programmed and not finely programmed, the original user data can be obtained by decoding the recovered data re_Data, and then the recovered data re_Data is re-encoded in combination with the recovered data re_Data obtained by the RAID.

[0193] For example, the memory controller 51 is configured to decode the data of the storage bit corresponding to the data latch (DLatch) that has not been updated to obtain the user data (i.e. the original data in the case where the programming state is not erroneous) of the storage bit corresponding to the data latch (DLatch) that has not been updated. For example, the decoding method includes de-randomization encoding processing and / or error correction decoding processing.

[0194] The user data of the storage bit corresponding to the data latch (DLatch) that has not been updated is used, and in combination with the independent redundant array of inexpensive disks (RAID), the error data of the storage bit corresponding to the data latch (DLatch) that has been updated is recovered to obtain the user data of the storage bit corresponding to the data latch (DLatch) that has been updated.

[0195] The user data of all storage bits is encoded, and the memory device 60 is controlled to program the encoded data to a position different from the programming position where the programming state is erroneous.

[0196] For example, the storage bit corresponding to the data latch (DLatch) that has not been updated is the data that has been coarsely programmed and not finely programmed. The de-randomization encoding processing and error correction decoding processing are performed on these data to obtain the user data (i.e. the original data in the case where the programming state is not erroneous) of the corresponding storage bit. Then, the recovered data re_Data is obtained in combination with the RAID.

[0197] The data re_Data is re-encoded. The memory controller 51 controls the memory device 60 to program the data after encoding to a position different from the programming position where the programming state error occurs.

[0198] In some examples, the amount of data recovered by the redundant array of independent disks (RAID) is less when the memory device 60 performs the programming operation in the first sub-mode Model21 of the second mode Model2 than when the memory device 60 performs the programming operation in the second sub-mode Model22 of the second mode Model2.

[0199] Considering that the storage bit corresponding to the data latch (D Latch) whose data is not updated is the data that has been subjected to coarse programming and has not been subjected to fine programming and needs to be decoded to obtain the original user data, and in combination with the recovery data obtained by the RAID processing, the overall time consumption is relatively long. Therefore, when there is a large amount of data that has been subjected to coarse programming and has not been subjected to fine programming and a small amount of data recovered by the RAID, the first sub-mode Model21 can be used to perform the programming operation, which can further reduce the resources occupied by the processor (such as the memory controller) and improve the speed of data recovery, as compared with the second sub-mode Model22.

[0200] In some examples, based on the data recovery processes of the first mode Model1 and the second mode Model2 described above, the duration for which the cache latch (C Latch) corresponding to the first mode Model1 stores the cache data is greater than the duration for which the cache latch (C Latch) corresponding to the second mode Model2 stores the cache data.

[0201] In the process of performing data recovery on the same memory device 51, for different programming modes, for example, the timing of the cache latch (CLatch) releasing data under the first mode Model 1 is later than the timing of the cache latch (CLatch) releasing data under the second mode Model 2. Considering that the memory controller 51 can directly obtain the data in the cache latch (CLatch) of the page buffer 621 of the memory device 60, and the data in the data latch (DLatch) needs to be first transferred to the cache latch (CLatch) before being obtained by the memory controller 51. In this way, compared to the case where the data stored in the cache latch (CLatch) is all the data to be recovered under the first mode Model 1, the second mode Model 2 releases part of the data in the cache latch (CLatch) after recovery, and then transfers the data in the data latch (DLatch) to the cache latch (CLatch). The memory controller 51 obtains and releases part of the updated data in the cache latch (CLatch), and until all the data in the data latch (DLatch) is stored in the buffer 52 through the cache latch (CLatch) (see Figure 10 ) in the memory controller 51; wherein the second mode Model 2 undergoes a data transfer and release process for several cycles, and the duration of the cache latch (CLatch) storing cache data in each cycle is less than the duration of the cache latch (CLatch) storing cache data corresponding to the first mode Model 1.

[0202] Based on this, in order to reduce the probability of data loss and improve the time of the cache latch (CLatch) storing data under the first mode Model 1, the probability of not being able to effectively utilize the data in the cache latch (CLatch) for data recovery due to the cache latch (CLatch) releasing data too early can be reduced under the case of programming state verification failure.

[0203] It can be understood that under the second mode Model 2, even if the programming state verification fails, part of the data is still stored in other data latches (DLatch) and cache latches (CLatch), and will not cause all the unstored data to be lost.

[0204] In addition, the memory controller 51 provided by the present application can also determine whether the programming mode currently used for data recovery is more appropriate according to the time length of the cache latch (C Latch) storing the cache data. For example, if the time length of the cache latch (C Latch) storing the cache data is longer, the programming mode can be switched. If the time length of the cache latch (C Latch) storing the cache data of the switched programming mode is shorter than that of the previous programming mode, the switched programming mode can be used for data recovery processing.

[0205] In some examples, the memory controller 51 is further configured to send a third command. The memory device 60 is configured to receive and respond to the third command by programming the recovery data re_Data to a location different from the programming location where the programming state error occurs.

[0206] As shown in Figure 11 The memory device 60 includes at least one memory chip 601. For example, the memory chip 601 can include one or more of a Personal Computer Memory Card International Association (PC) card, a CF card, a Smart Media (SM) card, a memory stick, a Multi-Media Card (MMC), a Reduced-Size MMC (RS-MMC), an MMC micro, an SD card (SD, miniSD, microSD, SDHC (Secure Digital High Capacity)), and a UFS.

[0207] The memory chip 601 includes at least one memory plane 610. The memory plane 610 includes a plurality of memory blocks 611. One memory block 611 includes a plurality of memory cells. One memory bit of one memory cell corresponds to one type of page. One data latch (D Latch) of a plurality of data latches (D Latches) in a page buffer 621 is configured to cache data of one type of page of a memory cell.

[0208] The programming location where the programming state error occurs is a certain memory block 611. The memory device 60 responds to the third command by programming the recovery data re_Data to a location different from the programming location where the programming state error occurs.

[0209] As shown in Figure 11 One page buffer 621 is coupled to one memory page. A plurality of memory pages of the memory block 611 are respectively coupled to a plurality of page buffers 621 (for reference Figure 6The page buffers 621 of one memory block 611 can exchange data with each other. In the case where the programming position where the programming state has an error is a certain memory page of one memory block 611, the memory device 60 programs the recovery data re_Data into other memory pages of the memory block 611 in response to the third command.

[0210] In another example, the memory controller 51 is configured to send a fourth command. The memory device 60 is configured to receive and respond to the fourth command to program the recovery data re_Data into other memory blocks 611 of the memory plane 610 where the programming state has an error.

[0211] It can be understood that, although the "fourth command" and the "third command" described above are both commands indicating that the programming position of the recovery data re_Data is different from the programming position where the programming state has an error. However, the "third command" can be provided with instruction information of an initial default storage position, for example, the "third command" can be based on the basic logic principle of data passing through the page buffer 621 to program the recovery data re_Data into different memory pages of the same memory block 611 as the programming position where the programming state has an error. If the initial default storage position is changed, the instruction information of the "fourth command" can be set, for example, the "fourth command" can be based on the coupling connection of the page buffer 621 coupled to different memory blocks, and the error recovery data can be programmed into other memory blocks 611 of the memory plane where the programming state has an error.

[0212] Based on the programming position where the programming state has an error being a certain memory block 611; the data in one memory block 611 can be stored as multiple memory pages by using multiple page buffers 621. And the page buffers coupled to different memory blocks 611 are coupled. For example, the programming state of one of the two memory blocks 611 has an error, and at least one page buffer of the two memory blocks 611 is coupled. After the data in the memory block 611 where the programming state has an error is recovered, the data can be stored in another memory block 611 by using the coupled page buffer 621.

[0213] In this way, the probability that the recovery data re_Data obtained again due to damage of the memory block 611 cannot be read or erased by subsequent programming operations can be reduced, and the effective utilization rate of the recovery data re_Data obtained can be improved.

[0214] In some examples, the memory controller 51 is configured to control the memory device 60 to re-execute the programming operation by using the recovery data re_Data. After the re-programming operation is completed, the logical-physical mapping table is updated.

[0215] For example, the data obtained by the reprogramming operation using the recovery data re_Data is stored in the logical-physical mapping table (e.g., in the buffer 52), and the correct data is stored well, so that even if the recovery data re_Data is released or lost subsequently, the memory system 50 can still perform other programming operations using the data in the logical-physical mapping table.

[0216] In some embodiments, as shown in Figures 12-24 The present application also provides a method for operating the memory system 50. The method comprises S100-S300.

[0217] The memory system 50 comprises a memory device 60 and a memory controller 51. The memory device 60 comprises a plurality of storage units each storing a plurality of bits, and a page buffer 510 in a peripheral circuit. One page buffer 510 can comprise one or more data latches (D Latch), cache latches (C Latch), sense latches (S Latch), and low-voltage latches (LVT Latch). Among them, the plurality of data latches (D Latch) are configured to respectively cache one-bit data to be written into the storage unit; the cache latches (C Latch) are configured to first transmit external data into the cache latches (C Latch), and then transmit the data from the cache latches (C Latch) to the data latches (D Latch), and transmit the data in the data latches (D Latch) to the cache latches (C Latch), and then transmit the data from the cache latches (C Latch) to the outside.

[0218] S100: As shown in Figure 12 In response to the occurrence of a programming state error when the memory device 60 of the memory system 50 performs a programming operation, data in the latches (Latch) of the page buffer 621 of the memory device 60 is obtained.

[0219] For example, the memory device 60 comprises a plurality of storage units each storing a plurality of bits; and the latches (Latch) comprise one or more data latches (D Latch) and cache latches (C Latch), wherein one data latch (D Latch) is configured to respectively cache one-bit data to be written into the storage unit, and the cache latches (C Latch) are configured to cache data exchanged between the memory device 60 and the memory controller 51.

[0220] As shown in Figure 14 S100 comprises S110: before obtaining the data in the latches (C Latch), information indicating a programming mode of the memory device 60 is obtained; different programming modes correspond to different time points at which the latches (Latch) release cached data.

[0221] Data loss or unsuccessful storage in the buffer 52 (see Figure 10 ) in the above programming state error condition requires that the unsuccessfully stored data be retrieved from the latches 6210 and re-stored in the buffer 52. The "programming mode" is determined based on the different processes by which the unsuccessfully stored data in the buffer 52 can be retrieved from different latches of the memory device 60, for example, a process in which the unsuccessfully stored data in the buffer 52 can all be retrieved from the cache latches (C Latch) corresponds to one programming mode. A process in which the unsuccessfully stored data in the buffer 52 can be retrieved from both the cache latches (C Latch) and the data latches (D Latch) corresponds to another programming mode. Since the unsuccessfully stored data is in different latches 6210, different operations need to be performed to retrieve the data in all the latches 6210 in different programming modes. Thus, in response to the different location states of the currently unsuccessfully stored data (i.e., the data to be recovered), the memory controller 51 responds to different programming modes to perform different operation steps for data recovery.

[0222] For example, if all the data to be recovered has been cached to the cache latches (C Latch), the memory controller 51 responds to commands of a first mode Model 1. Or, if part of the data to be stored has been stored to the data latches D Latch and another part has been cached to the cache latches (C Latch), the memory controller 51 responds to commands of a second mode Model 2. Different programming modes generate different commands, and the memory controller 51 performs corresponding operation steps in response to different commands. That is, in the case of a programming state error during the execution of a programming operation by the memory device 60, the requirement for the memory controller 51 to respond to commands of the first mode Model 1 is that all the memory cells in the memory cell array need to complete the programming operation (and pass the program state verification) before the data in the cache latches (C Latch) can be released and stored to the next memory location. The requirement for the memory controller 51 to respond to commands of the second mode Model 2 is that it is not necessary for all the memory cells in the memory cell array to complete the programming operation (and pass the program state verification) before the data in the cache latches (C Latch) can be released and stored to the next memory location, but only when part of the memory cells pass the program state verification. Thus, by determining different operation modes through different programming modes, a more suitable data recovery mode can be selected, which can improve the speed of data recovery and reduce the time consumption of data recovery.

[0223] In some examples, as Figure 7BAs shown, the storage type of the storage unit is TLC, and can include 5 latches 6210. The 5 latches 6210 include a sense latch (S Latch), a low voltage latch (LVT Latch), a first data latch (D Latch1), a second data latch (D Latch2), and a cache latch (C Latch). Also, the storage mode of the storage unit is TLC, including 3 storage bit data of LP, MP, and UP, and, as shown in the table, 8 storage states (threshold voltage distribution states) of L0-L7. Figure 13 As shown, there are 8 storage states (threshold voltage distribution states) of L0-L7.

[0224] Based on this, Figure 15 The first row of the table shown indicates 8 threshold voltage distribution states of the storage unit TLC, and the leftmost first column indicates 7 programming states of L1-L7 that need to be verified (L0 is the erase state, and can not be verified and recovered). In the programming verification process, the data in the latches is first pre-processed (DPP) to determine the data latched in the multiple latches corresponding to L0-L7 and can be used for verification. Then, the multiple data transmitted by the sense latch (S Latch) are sequentially obtained and verified (i.e., verifying whether the threshold voltage distribution states of L0-L7 shown in the first row of the table are within the threshold voltage distribution range of the programming states of L1-L7 shown in the leftmost first column, and the verification code is 1 if the verification is passed). Figure 15 The first row of the table shown indicates 8 threshold voltage distribution states of the storage unit TLC, and the leftmost first column indicates 7 programming states of L1-L7 that need to be verified (L0 is the erase state, and can not be verified and recovered). In the programming verification process, the data in the latches is first pre-processed (DPP) to determine the data latched in the multiple latches corresponding to L0-L7 and can be used for verification. Then, the multiple data transmitted by the sense latch (S Latch) are sequentially obtained and verified (i.e., verifying whether the threshold voltage distribution states of L0-L7 shown in the first row of the table are within the threshold voltage distribution range of the programming states of L1-L7 shown in the leftmost first column, and the verification code is 1 if the verification is passed).

[0225] Specifically, since the cache latch (C Latch) is used to temporarily store data exchanged between the memory device 50 and the outside world, and the data latch (D Latch) is used to latch the data of a specified page of the storage unit, in order to release the cache latch (C Latch) as early as possible, the data stored in the multiple data latches (D Latch) can be set according to the storage mode of the storage unit, and the verification can be implemented only according to the data in the multiple data latches (D Latch) without using the data in the cache latch (C Latch) for verification. As shown in the table, Figure 13As shown, in the case that the 8 storage states of the TLC storage unit correspond to the storage bits in different latches, considering the process of storing the 8 storage states in different latches, the case that the data state of the UP bit stored in the cache latch (CLatch) is "0" can be set in the last four storage states in the verification sequence of the 8 storage states, so that in the case that the data in the cache latch (CLatch) is not used for verification, the earliest time to release the data in the cache latch (CLatch) can be after the L4 verification in the L1-L7 verification sequence is passed. In this way, in the process of sequentially verifying the L5, L6 and L7 storage states, the time to release the data in the cache latch (CLatch) can be set to after the verification of any one of the three storage states is successful.

[0226] For example, the process of releasing the data in the cache latch (CLatch) after the L4 verification is successful belongs to the first sub-mode Model21 in the second mode Model2. For example, the process of releasing the data in the cache latch (CLatch) after the L5 or L6 verification is successful belongs to the second sub-mode Model22.

[0227] For another example, after the L1-L7 storage states are sequentially verified and all of them are verified successfully, it indicates that the cache latch (CLatch) includes all the data that has not been stored, and the data in the cache latch (CLatch) needs to be transferred to the sensing latch (SLatch) through the data latch (DLatch) and verified successfully before being released, that is, the process of releasing the data in the cache latch (CLatch) after the L7 verification is successful belongs to the first mode Model1.

[0228] In some examples, in response to a programming state error occurring when the memory device 60 of the memory system 50 performs a programming operation, the programming mode information is obtained, and the data in the cache latch (CLatch) is obtained. Different programming modes correspond to different times to release the cached data in the cache latch (CLatch).

[0229] Based on this, the duration for which the cache latch (CLatch) corresponding to the first mode Model1 stores the cached data is greater than the duration for which the cache latch (CLatch) corresponding to the second mode Model2 stores the cached data. That is, for the same use state of the same memory device 60, the time to release the cached data in the cache latch (CLatch) corresponding to the first mode Model1 is later than the time to release the cached data in the cache latch (CLatch) corresponding to the second mode Model2.

[0230] For the same use state of the same memory device 60, considering that in the first mode Model 1, the data stored in the cache latch (C Latch) is all unstored data, and in the second mode Model 2, the unstored data is respectively stored in the data latch (D Latch) and the cache latch (C Latch), based on this, in order to reduce the probability of data loss and improve the time of storing data in the cache latch (C Latch) in the first mode Model 1, the probability of being unable to effectively utilize the data in the cache latch (C Latch) for data recovery due to the premature release of data in the cache latch (C Latch) can be reduced in the case of programming state verification failure.

[0231] It can be understood that in the second mode Model 2, even if the programming state verification fails, part of the data is still stored in other data latches (D Latch) and cache latches (C Latch), and it will not cause all unstored data to be lost.

[0232] S200: As shown in Figure 12 , the obtained data in the latch (Latch) is used to obtain at least part of the recovery data re_Data. For example, the data in the obtained cache latch (C Latch) is used to obtain at least part of the recovery data re_Data.

[0233] In some examples, S200 includes S210: determining whether to control the memory device 60 to transfer the data in the plurality of data latches (D Latch) to the cache latch (C Latch) according to the programming mode, and obtaining the data transferred to the cache latch (C Latch). Wherein, before the data in the data latch (D Latch) is transferred to the cache latch (C Latch), part of the recovery data re_Data is obtained by using the cache data.

[0234] It can be understood that in the programming process, the data of one storage bit can be stored in the cache latch (C Latch), and before the data of the next storage bit is stored in the cache latch (C Latch), the data already stored in the cache latch (C Latch) is transferred to the data latch (D Latch), and then the data of the next storage bit is stored in the cache latch (C Latch). In this way, until all data latches (D Latch) in the page buffer 621 store data or the storage of the data to be stored is completed. For example, as Figure 7BAs shown, the storage type of the storage unit is TLC, and the storage unit can include five latches 6210. The five latches 6210 include a sense latch (S Latch), a low voltage latch (LVT Latch), a first data latch (D Latch1), a second data latch (D Latch2), and a cache latch (C Latch). Moreover, the storage type of the storage unit includes TLC, and includes three storage bit data of LP, MP, and UP. The LP data is transmitted to the cache latch (C Latch). Before the MP data is transmitted to the cache latch (C Latch), the LP data in the cache latch (C Latch) is transferred to the second data latch (D Latch2), and then the MP data is stored in the cache latch (C Latch). Before the UP data is transmitted to the cache latch (C Latch), the MP data in the cache latch (C Latch) is transferred to the first data latch (D Latch1), and then the UP data is stored in the cache latch (C Latch). Based on this, in the process of data recovery using the data in the latches (Latch), it is determined according to the programming mode whether to directly and only obtain the data in the cache latch (C Latch) or to obtain the data in the data latch (D Latch) and the cache latch (C Latch). Thus, the data transmission process of different latches (Latch) is controlled in response to the command of different programming modes. The following examples exemplarily illustrate the data transmission process under different programming modes.

[0235] According to different programming modes, S210 includes S211 based on the programming mode being the first mode Model1 (see Figure 14 ), and S212 based on the programming mode being the second mode Model2 (see Figure 21 ).

[0236] S211: Based on the programming mode being the first mode Model1, the data in the cache latch (C Latch) of the page cache 621 is directly obtained, and at least part of the recovered data re_Data is obtained.

[0237] The programming mode is the first mode Model1, and the cache latch (C Latch) stores data. This part of data can be all storage bit data of the storage unit that is not stored when the programming state is erroneous, or can be part of the storage bit data of the storage unit that is not stored when the programming state is erroneous. Based on the functional attribute of the cache latch (C Latch), the data in the cache latch (C Latch) can be directly obtained by the memory controller 51, and at least part of the recovered data re_Data is obtained.

[0238] In the example, asFigure 14 As shown, S211 includes S2111 and S2112.

[0239] S2111: Based on the programming mode being the first mode Model 1, the memory controller 51 sends a second command. The second command instructs the memory device 60 to output the data in the cache latch (C Latch) of the page buffer 621.

[0240] As shown, S211 includes S2111 and S2112. Figure 7B and Figures 15-18 As shown, the threshold voltage distribution states of L0-L7 are shown in the first row of the table, and L1-L7 shown in the leftmost column are the threshold voltage distribution states of the programming states that need to be verified (L0 is the erase state, and verification and recovery can not be performed). Figure 15 As shown, in the process of verifying L0-L4, the verification codes of L0-L4 are all 1 (at this time, the data type in the sensing latch can be referred to as DS), that is, the verification is passed, and the data of L0-L4 has been stored in the cache buffer 52. Then, the data of LP is stored in the cache latch (C Latch) (the data type in the cache latch (C Latch) can be referred to as DC).

[0241] Figure 16 As shown, in the process of verifying L5, the verification code of L5 is obtained as 1, that is, the verification is passed, and the data of LP in the cache latch (C Latch) is transferred to the first data latch (D Latch1) (the data type in the first data latch (D Latch1) can be referred to as D1), and then the LP data is released and the data of MP is stored until the current L5 verification operation ends.

[0242] As shown, in the process of verifying L5, the verification code of L5 is obtained as 1, that is, the verification is passed, and the data of LP in the cache latch (C Latch) is transferred to the first data latch (D Latch1) (the data type in the first data latch (D Latch1) can be referred to as D1), and then the LP data is released and the data of MP is stored until the current L5 verification operation ends. Figure 17 As shown, in the process of verifying L6, the verification code of L6 is obtained as 1, that is, the verification is passed, and the data of MP in the cache latch (C Latch) is transferred to the second data latch (D Latch2) (the data type in the second data latch (D Latch2) can be referred to as D2), and then the MP data is released and the data of UP of the next storage unit is stored until the current L6 verification operation ends.

[0243] Figure 18 As shown, in the process of verifying L6, the verification code of L6 is obtained as 1, that is, the verification is passed, and the data of MP in the cache latch (C Latch) is transferred to the second data latch (D Latch2) (the data type in the second data latch (D Latch2) can be referred to as D2), and then the MP data is released and the data of UP of the next storage unit is stored until the current L6 verification operation ends.

[0244] By analogy, in the process of verifying L7, the data of UP in the cache latch (C Latch) can be transferred to the first data latch (D Latch1) or the second data latch (D Latch2), the verification code of the threshold voltage distribution of L7 is obtained as 1 or 0, and when the verification code is 1, the verification is passed. Then, the MP data in the cache latch (C Latch) is released and the data of LP of the next storage unit is stored.

[0245] ​​Based on this, when the programming state of different storage units occurs error, the data stored in the corresponding cache latch (CLatch) can be different, for example, the data stored in the cache latch (CLatch) can include any one of the storage bit data of LP, UP and MP. Subsequent operations can obtain at least partial recovery data re_Data by using multiple data stored in multiple cache latches (CLatch).

[0246] In some examples, based on the data obtained directly from the cache latch (CLatch), the recovery data of all storage bits of the storage unit is obtained.

[0247] For example, the data in the multiple cache latches (CLatch) is the data of all storage bits of the storage unit that is not stored when the programming state occurs error, and the data obtained directly from the cache latch (CLatch) can obtain the recovery data of all storage bits of the storage unit. For example, the storage type of the storage unit includes QLC, including 4 storage bits of LP, MP, UP and XP. Among them, the data in one data latch (DLatch) is transferred to the cache latch (CLatch) for 77 microseconds, and the data of 4 storage bits is recovered by using the first sub-mode Model21 for 308 microseconds.

[0248] S2112: Based on the programming mode being the first mode Model1, the memory controller 51 sends a third command. The third command instructs the memory device 60 to program the recovery data re_Data to a position different from the position of the programming state that occurs error.

[0249] For example, when the memory device 60 performs the programming operation by using the first mode Model1, after all the programming states are verified, the cache latch (CLatch) releases the cache data corresponding to the programming operation. Among them, as shown in Figure 7A and Figure 7B The data of the cache latch (CLatch) is transmitted to the sensing latch (SLatch) through the data latch (DLatch) for programming state verification; after verification, the data in the sensing latch (SLatch) is output through the cache latch (CLatch). For example, the programming state of the data in multiple data latches (DLatch) can be verified in sequence, after verification, the cache latch (CLatch) releases the cache data, and stores the data corresponding to the next programming operation, and then transmits it to part of the data latch (DLatch). And, the verified data can be transmitted to the buffer 52.

[0250] If the programming state of the data in a data latch (D Latch) fails to be verified, the data in the cache latch (CLatch) that has not been released is re-transmitted to the data latch (D Latch) and verified again.

[0251] In some examples, such as Figure 11 As shown, memory device 60 includes at least one memory chip 601. Memory chip 601 includes at least one memory plane 610; memory plane 610 includes multiple memory blocks 611. Each memory block 611 includes multiple memory cells, where a memory bit of each memory cell corresponds to a type of page. A data latch (D Latch) of multiple data latches (DLatch) in page buffer 621 is configured to cache data of a type of page of memory cells.

[0252] like Figure 19 As shown, S2112 includes S2113: based on the programming mode being the first mode Model1, sending a fourth command. The fourth command instructs the memory device 60 to use the data in the buffer to obtain recovery data re_Data, and program the recovery data re_Data into other memory blocks 611 in the memory plane 610 where the programming state error occurs.

[0253] For example, the data recovery process based on the first mode Model1, and the storage type of the storage unit includes QLC, including LP, MP, UP and XP, which are four storage bits. The page buffer 621 includes three data latches (D Latch) and a cache latch (C Latch). Figure 20AAs shown, the data of the storage bit MP stored in the first data latch 6213 of the sense latch (S Latch), the data of the storage bit UP stored in the second data latch 6214, and the data of the storage bit XP stored in the third data latch 6215 are sequentially transferred to the cache latch 6216. The memory controller 51 obtains the data in the cache latch (C Latch) to obtain the corresponding recovery data re_Data. Then, the memory controller 51 programs the recovery data re_Data to other memory blocks 611 in the storage surface 610 where the programming state error occurs. For example, one storage surface 610 includes a plurality of memory blocks 611, and one page buffer 621 (or page buffer group) coupled to one memory block 611 can exchange data with one page buffer 621 coupled to another memory block 611. In this way, the recovery data re_Data corresponding to the programming state error in one memory block 611 can be programmed to another memory block 611, and the probability that the recovery data re_Data stored in other memory pages of the memory block 611 cannot be effectively utilized due to damage of the memory block 611 can be reduced.

[0254] S212: As Figure 21 shown, based on the programming mode being the second mode Model2, the memory device 60 is controlled to transfer the data in the plurality of data latches (D Latch) to the cache latch (C Latch) respectively, obtain the data transferred from the plurality of data latches (D Latch) to the cache latch (C Latch), and obtain partial recovery data re_Data; and before the data in the data latch (D Latch) is transferred to the cache latch (C Latch), the partial recovery data re_Data is obtained by using the cache data in the cache latch (C Latch).

[0255] For example, the storage type of the storage unit includes TLC, and the data of 3-bit storage bits (requiring 18 programming cycle operations) requires a programming cycle time of 400*3=1200 microseconds for programming completion, and the time of one programming cycle operation (which can write one bit of data) is about 67 microseconds. The time of transmitting 18KB data at a rate of 2400 Gb / s is about 62 microseconds, that is, in the data recovery process, the time of transferring one bit of data to the cache latch (C Latch) is about 62 microseconds. In this way, the time of transferring one bit of data is less than or equal to the time of programming at least one bit of remaining data, so that the recovery can be performed by obtaining the data of the cache latch (C Latch) at the same time of programming one bit of data, without increasing additional time and reducing the time consumption of data recovery.

[0256] Please continue to readFigure 21 S212 includes S2121, S2122, S2123 and S2124.

[0257] S2121: The memory controller 51 includes a buffer 52 (see Figure 20A and Figure 20B ). Based on the programming mode being the second mode Model2, the memory controller 51 is configured to send a second command. The memory device 60 is configured to: receive and respond to the second command, send data in a cache latch (C Latch) to the buffer 52.

[0258] It can be understood that the "second command" is used to send data in the cache latch (C Latch) to the buffer 52. The "second command" can not be limited to the type of each programming mode, but can apply instructions of various programming modes, or can be different instructions with the same function under different programming modes. Some examples provided by the present application do not limit this, and can be set according to actual needs.

[0259] S2122: Based on the programming mode being the second mode Model2, a first command is sent; the first command instructs the memory device 60 to respectively transmit data in a plurality of data latches (D Latch) to the cache latch (C Latch). Wherein, the first command is configured by setting a feature command.

[0260] For example, the setting feature command can include arbitration, power management, logical address range type, temperature threshold, error recovery, volatile write cache, interrupt bonding, interrupt adaptation configuration, write atomic normal, asynchronous event configuration, automatic power state transition, host memory buffer, command set specific, hanging clock time or time stamp corresponding to absolute time, supported protocol version, etc. In some examples provided by the present application, the first command is sent by the memory controller 51 based on the setting feature command being "error recovery".

[0261] It can be understood that based on the programming mode being the second mode Model2, partial recovery data re_Data is obtained by using cache data in the cache latch (C Latch) before transmitting data in the data latch (D Latch) to the cache latch (C Latch). In this way, the existing data in the cache latch (C Latch) of the plurality of storage units can be first sent to the buffer 52 in response to the "second command", and then the data in the plurality of data latches (D Latch) of the plurality of storage units is sequentially transmitted to the cache latch (C Latch) in response to the "first command", and then the data exchange with the external electronic element is realized through the cache latch (C Latch).

[0262] S2123: Based on the programming mode being the second mode Model2, after S2122, the memory controller 51 is configured to send a second command again. The memory device 60 is configured to, in response to the second command, send the data in the cache latch (CLatch) to the buffer 52.

[0263] As shown in FIG. 2, the memory controller 51 is configured to send a first command to the memory device 60. The memory device 60 is configured to, in response to the first command, send the data in the cache latch (CLatch) to the buffer 52. Figures 16-18 and Figure 21 As shown in FIG. 2, the memory controller 51 is configured to send a first command to the memory device 60. The memory device 60 is configured to, in response to the first command, send the data in the cache latch (CLatch) to the buffer 52.

[0264] For example, for the programming operation and the programming verification process of the same memory cell, after the L4 verification is successful, the memory device 60 is configured to, in response to the second command, send the data in the cache latch (CLatch) to the buffer 52 and store the LP data of the next memory cell. Then, in the L5 verification process, the data in the cache latch (CLatch) is stored in the sense latch (SLatch) for verification, and after the L5 verification is successful (the verification code is 1), the LP data in the cache latch (CLatch) is sent to the buffer 52 and stored as the MP data of the next memory cell. Then, in the L6 verification process, the data in the cache latch (CLatch) is stored in the sense latch for verification, and after the L6 verification is successful, the MP data in the cache latch (CLatch) is sent to the buffer 52 and stored as the UP data of the next memory cell. Similarly, the data in the cache latch (CLatch) of multiple memory cells is sent to the buffer 52.

[0265] S2124: Based on the programming mode being the second mode Model2, a third command is sent. The third command instructs the memory device 60 to program the recovery data re_Data to a position different from the programming position where the programming state has an error.

[0266] In some examples, the memory controller 51 encodes the user data of all the storage bits and controls the memory device 60 to program the encoded data to a position different from the programming position where the programming state has an error.

[0267] As shown in FIG. 2, the memory device 60 includes at least one memory chip 601. The memory chip 601 includes at least one memory plane 610, and the memory plane 610 includes a plurality of memory blocks 611. One memory block 611 includes a plurality of memory cells, and one storage bit of one memory cell corresponds to one type of page. One data latch (DLatch) of a plurality of data latches (DLatch) in the page buffer 621 is configured to cache the data of one type of page of the memory cell.

[0268] For example, the programming location where the programming state error occurs is a certain memory block 611; the memory device 60 responds to the third command to program the recovery data re_Data into a different memory page within the same memory block 611 as the programming location where the programming state error occurs.

[0269] For another example, as shown in FIG. 12B, S2124 includes S2125: sending a fourth command based on the programming mode being the second mode Model2. The fourth command instructs the memory device 60 to obtain the recovery data re_Data using the data in the buffer 52 and program the recovery data re_Data into other memory blocks 611 of the memory surface where the programming state error occurs. Figure 22

[0270] It can be understood that although the "fourth command" and the above-mentioned "third command" are both commands instructing the programming location of the recovery data re_Data to be different from the programming location where the programming state error occurs. However, the "third command" can be provided with an initial default storage location instruction information, for example, the "third command" can be based on the basic logic principle of the data in the memory block being programmed into a different memory page within the same memory block 611 as the programming location where the programming state error occurs through the page buffer 621; if the initial default storage location is changed, the instruction information of the "fourth command" can be set, for example, the "fourth command" can be based on the page buffer 621 coupled to the different memory blocks to be coupled to be able to program the error recovery data into other memory blocks 611 of the memory surface where the programming state error occurs.

[0271] The above-mentioned first command, second command, third command and fourth command respectively control the memory device 60 to transfer the data storage location. The subsequent embodiment exemplarily illustrates the recovery mode of the data in different storage states through the method of using the data in the data latch (DLatch) in the second mode Model2. For example, the data in the data latch (DLatch) can represent different storage states of the memory cells, and different recovery modes can be used for the data in different storage states.

[0272] As shown in FIG. 12B, S212 also includes S213 and S214. Figure 23

[0273] S213: based on the data transmitted from the data buffer (DLatch) to the cache latch (CLatch), obtaining the recovery data re_Data of the storage bit corresponding to the data latch (DLatch) where the data is not updated.

[0274] ​​S214: The error data of the corresponding storage bit of the data latch (DLatch) whose data has been updated is recovered by using the independent redundant array of independent disks (RAID).

[0275] For example, the programming operation performed by the memory device 60 includes a multi-pass programming operation on a group of memory cells, i.e., a coarse programming operation followed by a fine programming operation. For example, when a programming state error occurs in the programming operation of a group of memory cells of the memory device 60, the data of the data latch (DLatch) of some storage bits is data after the coarse programming has been performed and before the fine programming has been performed (i.e., the data of the data latch (DLatch) that has not been updated), which can be directly transferred from the data latch (DLatch) to the cache latch (CLatch); the memory controller 51 obtains the data in the cache latch (CLatch) and obtains the recovery data re_Data of the corresponding storage bit. The data in the data latch (DLatch) of another group of storage bits is data after the fine programming has been performed (i.e., the data of the data latch (DLatch) that has been updated), which can be directly recovered by RAID to obtain the recovery data re_Data of the corresponding storage bit. In this way, by combining the two data recovery steps, in the case of a large amount of lost data, compared with the method of recovering data by RAID only, the resource occupation of the processor (such as the memory controller) can be reduced while the time consumption of data recovery is further reduced.

[0276] For another example, if the data in the data latch (DLatch) is all data after the fine programming has been performed, these data can also be directly transferred from the data latch (DLatch) to the cache latch (CLatch); the memory controller 51 obtains the data in the cache latch (CLatch) and obtains the recovery data re_Data of the corresponding storage bit.

[0277] In this way, the data recovery can be performed without using RAID, which reduces the resource occupation of the processor (such as the memory controller) and the occupation of other storage space, and compared with the method of recovering data by RAID, the method of the present example improves the data recovery speed and reduces the time consumption of data recovery.

[0278] Based on this, in some examples, for the data that has been finely programmed in the second mode Model2 described above, the selection of the sub-mode can be performed according to the size of the amount of data in this part, and then the timing of the cache latch (CLatch) releasing the cache data corresponding to the programming operation is different in different sub-modes, that is, according to the size of the amount of data that the cache latch (CLatch) can store, different sub-modes are selected, which can reduce the probability of data loss caused by the cache latch (CLatch) releasing data faster than the rate of storing data, and improve the accuracy and integrity of data recovery.

[0279] For example, the second mode Model2 includes a first sub-mode Model21 and a second sub-mode Model22. As shown in Figure 24 S212 includes S215 and S216.

[0280] S215: When the memory device 60 performs the programming operation in the first sub-mode Model21, after the first part of the programming state verification is passed, the cache latch (CLatch) releases the cache data corresponding to the programming operation, and updates the data corresponding to the next programming operation to the partial data latch (DLatch).

[0281] For example, after all the programming states in the data latch (DLatch) are verified, the cache latch (CLatch) releases the cache data corresponding to the programming operation. The data in the cache latch (CLatch) is transmitted to the sensing latch (SLatch) through the data latch (DLatch) for programming state verification. For example, the programming states of the data in the plurality of data latches (DLatch) can be verified in sequence, after the verification is passed, the cache latch (CLatch) releases the cache data, and stores the data corresponding to the next programming operation (such as fine programming operation or operation of storing the next storage bit of the storage cell), and then transmits it to the partial data latch (DLatch).

[0282] If the verification of the programming state of the data in a certain data latch (DLatch) does not pass, the data in the cache latch (CLatch) that has not been released is retransmitted to the data latch (DLatch) for verification again.

[0283] For example, as shown in Figure 7B and Figures 16-18 During the verification of L0~L4, during the verification of the storage state of L0~L4, the verification code is 1, that is, the verification is passed, and the data of L0~L4 is stored in the cache. Then, the cache latch (CLatch) stores the data of LP.

[0284] As shown in Figure 16As shown, in the process of verifying L0~L4, the verification codes of L0~L4 are all 1 (at this time, the data type in the sensing latch can be referred to as DS), that is, the verification is passed, and the data of L0~L4 is stored in the buffer 52. Then, the buffer latch (CLatch) stores the data of LP (the data type in the buffer latch (CLatch) can be referred to as DC).

[0285] As shown in FIG. 6, in the process of verifying L5, the verification code of L5 is obtained as 1, that is, the verification is passed, and the data of LP in the buffer latch (CLatch) is transferred to the first data latch (DLatch1) (the data type in the first data latch (DLatch1) can be referred to as D1), and then the data of LP is released and the data of MP is stored until the current L5 verification operation ends. Figure 17 As shown in FIG. 7, in the process of verifying L6, the verification code of L6 is obtained as 1, that is, the verification is passed, and the data of MP in the buffer latch (CLatch) is transferred to the second data latch (DLatch2) (the data type in the second data latch (DLatch2) can be referred to as D2), and then the data of MP is released and the data of UP of the next storage unit is stored until the current L6 verification operation ends.

[0286] Figure 18 As shown in FIG. 8, in the process of verifying L7, the data of UP in the buffer latch (CLatch) can be transferred to the first data latch (DLatch1) or the second data latch (DLatch2), the threshold voltage distribution of verifying L7 obtains the verification code as 1 or 0, when the verification code is 1, the verification is passed, and then the data of MP in the buffer latch (CLatch) is released and the data of LP of the next storage unit is stored.

[0287] S216: When the memory device 60 performs the programming operation in the second sub-mode Model22, after the verification of the second part in the programming state is passed, the buffer latch (CLatch) releases the buffer data corresponding to the programming operation, and updates the data corresponding to the next programming operation to the partial data latch (DLatch). The steps of the verification of the second part in the programming state can be the same as the steps of the verification of the first part in the programming state, which will not be described here.

[0288] For example, the number of programming states corresponding to the first part is greater than the number of programming states corresponding to the second part. It can be understood that the "number of programming states corresponding to the first part" and the "number of programming states corresponding to the second part" are used to distinguish the executed fine programming data in different sub-modes, and are not to divide the executed fine programming data into two parts. Different sub-modes can be selected by judging the size of the amount of executed fine programming data.

[0289] For example, the number of programming states corresponding to the first part is greater than the number of programming states corresponding to the second part. It can be understood that the "number of programming states corresponding to the first part" and the "number of programming states corresponding to the second part" are used to distinguish the executed fine programming data in different sub-modes, and are not to divide the executed fine programming data into two parts. Different sub-modes can be selected by judging the size of the amount of executed fine programming data. ​

[0290] In this way, in the case that the number of programming states not stored is large (for example, the first part of programming states), the programming operation is performed in the first sub-mode Model 21, which can occupy fewer resources of the processor (for example, the memory controller) and improve the data recovery speed.

[0291] For example, the time at which the cache latch (CLatch) corresponding to the first sub-mode Model 21 releases the cached data is later than the time at which the cache latch (CLatch) corresponding to the second sub-mode releases the cached data.

[0292] In this way, based on the number of programming states corresponding to the first part being greater than the number of programming states corresponding to the second part, the cache latch (CLatch) under the first sub-mode Model 21 needs to cache data for a longer time, so as to ensure that the data in the cache latch (CLatch) is stored before being released, reduce the probability of data loss, and improve the accuracy of data recovery.

[0293] For example, the storage type of the storage unit includes QLC, including four storage bits of LP, MP, UP, and XP. When the programming operation is performed in the first sub-mode Model 21, the RAID is used for data recovery of the LP storage bit, and the MP, UP, and XP storage bits (that is, the first part of data) stored in the data latch (DLatch) are obtained from the cache latch (CLatch) by the memory controller 51 and recovered data re_Data is obtained.

[0294] For example, the time for transferring the data in the data latch (DLatch) to the cache latch (CLatch) can be 77 microseconds, the time for obtaining the three-bit data of MP, UP, and XP from the cache latch (CLatch) and performing data recovery can be 77*3=231 microseconds, and the time for the RAID to recover the data of one storage bit (LP) can be 150*5=750 microseconds. The time for recovering data in the first sub-mode Model 21 can be 981 microseconds.

[0295] For example, the storage type of the storage unit includes QLC, including four storage bits of LP, MP, UP, and XP. When the programming operation is performed in the second sub-mode Model 22, the RAID is used for data recovery of the LP and MP storage bits, and the UP and XP storage bits (that is, the first part of data) stored in the data latch (DLatch) are obtained from the cache latch (CLatch) by the memory controller 51 and recovered data re_Data is obtained.

[0296] For example, the time consumed for transferring the data in the data latch (D Latch) to the cache latch (C Latch) can be 77 microseconds, the time consumed for obtaining the UP and XP three-bit data through the cache latch (C Latch) and performing data recovery can be 77*2=154 microseconds, and the time consumed for the RAID to recover the data of one storage bit (LP and MP) can be 150*5*2=1500 microseconds. The time consumed for recovering the data by using the second sub-mode Model 22 is 1654 microseconds.

[0297] In this way, since the first part of data has a large amount, the first sub-mode Model 21 is used to obtain and recover the data re_Data from the cache latch (C Latch) through the memory controller 51, which is beneficial to improve the speed of obtaining the non-stored data and reduce the overall time consumed for data recovery.

[0298] Meanwhile, for the same amount of data, more data is obtained and recovered as the data re_Data from the cache latch (C Latch) through the memory controller 51, and the remaining part of data is recovered by the RAID. In this way, the amount of data recovered by the RAID in the first sub-mode Model 21 is less than the amount of data recovered by the RAID in the second sub-mode Model 22, which reduces the occupied resources of the processor (for example, the memory controller) and further reduces the time consumed for recovering all the data in the storage unit.

[0299] In some examples, for the part of data corresponding to the data after the coarse programming is performed and the fine programming is not performed, the original user data can be obtained by decoding the recovered data re_Data, and then the recovered data re_Data is re-encoded in combination with the recovered data re_Data obtained by the RAID.

[0300] For example, the memory controller 51 is configured to perform decoding processing on the data of the storage bit corresponding to the data latch (D Latch) that is not updated, to obtain the user data (i.e., the original data in the case where the programming state is not erroneous) of the storage bit corresponding to the data latch (D Latch) that is not updated. For example, the decoding manner includes randomization encoding processing and / or error correction encoding processing.

[0301] The user data of the storage bit corresponding to the data latch (D Latch) that is not updated is used, and in combination with the error data of the storage bit corresponding to the data latch (D Latch) that is updated being recovered by the RAID, the user data of the storage bit corresponding to the data latch (D Latch) that is updated is obtained.

[0302] The amount of data recovered by the memory device 60 using the RAID when programming in the first sub-mode Model 21 is smaller than the amount of data recovered by the RAID when programming in the second sub-mode Model 22.

[0303] Taking into account the storage bits corresponding to the data latches (D Latch) whose data has not been updated, that is, the data that has been coarsely programmed but not finely programmed needs to be decoded to obtain the original user data, and the recovered data obtained in combination with RAID processing, the overall time consumption is relatively long. In this way, when there is a large amount of data that has been coarsely programmed but not finely programmed, and the amount of data recovered using RAID is small, the first sub-mode Model 21 can be used for programming operations. Compared with the second sub-mode Model 22 for programming operations, it can further reduce the resources occupied by the processor (such as the memory controller) and increase the speed of data recovery.

[0304] S300: Figure 21 As shown, the memory device 60 is controlled to re-execute the programming operation using the recovery data re_Data; after the re-programming operation is completed, the logical-physical mapping table is updated.

[0305] For example, the data obtained by the reprogramming operation using the recovery data re_Data is stored in the logical-physical mapping table (for example, in the cache) to obtain correct data with good storage performance. Even if this part of the recovery data re_Data is released or lost later, the memory system 60 can still use the data in the logical-physical mapping table to perform other programming operations.

[0306] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A memory system, characterized by, The application relates to a memory device and a memory controller coupled with the memory device; wherein, The memory device comprises a page buffer; the page buffer comprises a latch; The memory controller is configured to: acquire data in the latch in response to a program state error occurring when the memory device performs a program operation; obtain at least part of recovery data by using the acquired data in the latch. The memory device further comprises a plurality of storage units each storing a plurality of bits; the latch comprises one or more data latches and a cache latch, wherein one of the data latches is configured to cache one-bit data to be written into the storage units; 2. The memory system of claim 1, wherein, The memory controller is configured to: acquire information indicating a program mode of the memory device before acquiring the data in the latch; different program modes correspond to different time instants at which the cache latch releases cached data; and determine whether to control the memory device to transfer the data in the data latch to the cache latch and acquire the data transferred to the cache latch according to the program mode; wherein, before the data in the data latch is transferred to the cache latch, part of the recovery data is obtained by using cached data in the cache latch. The memory controller is configured to:

3. The memory system of claim 2, wherein, based on the program mode being a first mode, directly acquire the data in the cache latch and obtain at least part of the recovery data; based on the program mode being a second mode, control the memory device to transfer the data in the plurality of data latches to the cache latch respectively, acquire the data transferred from the plurality of data latches to the cache latch, and obtain part of the recovery data; and before the data in the data latch is transferred to the cache latch, part of the recovery data is obtained by using cached data in the cache latch. The time length during which the cache latch stores cached data corresponding to the first mode is greater than the time length during which the cache latch stores cached data corresponding to the second mode.

4. The memory system of claim 3, wherein, The program mode of the memory device is the first mode; when a program state error occurs in a program operation of the memory device, the data in the cache latch is data corresponding to the program operation; 5. The memory system of claim 3, wherein, The memory controller is configured to: based on the data directly acquired from the cache latch, obtain the recovery data of all the storage bits of the storage units. The program mode of the memory device is the second mode; 6. The memory system of claim 3, wherein, The program operation performed by the memory device comprises a multi-pass program operation on a group of the storage units; When a program state error occurs in a program operation of a group of the storage units of the memory device, the data in part of the data latches of the plurality of data latches has been updated to data corresponding to a next pass program operation of a current pass program operation in the multi-pass program operation; The memory controller is configured to: based on the data transferred from the data latches to the cache latch, obtain recovery data of the storage bits corresponding to the data latches whose data has not been updated; and based on the data transferred from the data latches to the cache latch, obtain recovery data of the storage bits corresponding to the data latches whose data has not been updated. and An independent redundant disk array is used to recover erroneous data of the storage bit corresponding to the data latch whose data has been updated.

7. The memory system of claim 6, wherein, The second mode includes a first sub-mode and a second sub-mode; the time when the cache latch corresponding to the first sub-mode releases the cache data is later than the time when the cache latch corresponding to the second sub-mode releases the cache data; The amount of data recovered by the independent redundant array of disks when the memory device is programmed in the first sub-mode is smaller than the amount of data recovered by the independent redundant array of disks when the memory device is programmed in the second sub-mode.

8. The memory system of claim 7, wherein, When the memory device performs a programming operation in the first mode, after all programming states are verified, the cache latch releases cache data corresponding to the programming operation; When the memory device performs a programming operation in the first sub-mode, after a first portion of the programming state verification passes, the cache latch releases cache data corresponding to the programming operation and updates data corresponding to the next programming operation into part of the data latches; When the memory device performs a programming operation in the second sub-mode, after the second portion of the programming state verification passes, the cache latch releases the cache data corresponding to the programming operation and updates the data corresponding to the next programming operation into part of the data latch; The number of programming states corresponding to the first part is greater than the number of programming states corresponding to the second part.

9. The memory system of claim 6, wherein, The memory controller is configured to: send a first command based on the programming mode being the second mode; The memory device is configured to receive and, in response to the first command, transfer the data in the plurality of data latches to the cache latches respectively.

10. The memory system of claim 9, wherein, The first command is configured by setting a feature command.

11. The memory system of claim 6, wherein, The memory controller is configured to: Decoding the data of the storage bit corresponding to the data latch whose data has not been updated to obtain user data of the storage bit corresponding to the data latch that has not been updated; Recovering erroneous data of the storage bits corresponding to the data latches whose data has been updated using the user data of the storage bits corresponding to the data latches that have not been updated, in combination with an independent redundant disk array, to obtain user data of the storage bits corresponding to the updated data latches; The user data of all the storage bits are encoded, and the memory device is controlled to program the encoded data to a location different from a programming location where an error occurs in the programming state.

12. The memory system of claim 5, wherein, The memory controller includes a buffer; the memory controller is configured to: send a second command and a third command; The memory device is configured to: receive and, in response to the second command, send the data in the cache latch to the cache; and In response to receiving the third command, the recovery data is programmed to a location different from a program location where an error in the program state occurs.

13. The memory system of claim 12, wherein, The memory device includes at least one memory chip; the memory chip includes at least one memory plane; the memory plane includes a plurality of memory blocks; The memory controller is configured to send a fourth command; The memory device is configured to receive and respond to the fourth command by programming the error recovery data into other memory blocks.

14. The memory system according to any one of claims 11 to 13, wherein The memory controller is configured to: Control the memory device to re-perform a programming operation using the recovery data; Update a logical-physical mapping table after the re-programming operation is completed.

15. An operating method of a memory system, characterized by, Comprise: In response to a program state error occurring when a memory device of the memory system performs a programming operation, obtain data in a latch of a page buffer of the memory device; Obtain at least part of the recovery data using the obtained data in the latch.

16. The method of operation of claim 15, wherein, The memory device further comprises a plurality of storage units each storing a plurality of bits; and the latch comprises one or more data latches and a cache latch, wherein one of the data latches is configured to cache one bit of data to be written into the storage unit respectively; The method further comprises: Before obtaining the data in the latch, obtaining information indicating a programming mode of the memory device; different programming modes correspond to different times at which the cache data in the latch is released; According to the programming mode, determine whether to control the memory device to transfer data in the plurality of data latches to the cache latch, and obtain the data transferred to the cache latch; wherein, before the data in the data latches is transferred to the cache latch, part of the recovery data is obtained using the cache data.

17. The method of operation of claim 16, wherein, The determination whether to control the memory device to transfer data in the plurality of data latches to the cache latch according to the programming mode information comprises: Based on the programming mode being a first mode, directly obtain the data in the cache latch of the page buffer, and obtain at least part of the recovery data; Based on the programming mode being a second mode, control the memory device to transfer data in the plurality of data latches to the cache latch respectively, and obtain the data transferred from the plurality of data latches to the cache latch, and obtain part of the recovery data; and, before the data in the data latches is transferred to the cache latch, part of the recovery data is obtained using the cache data in the cache latch.

18. The method of operation of claim 17, wherein, The duration for which the cache latch corresponding to the first mode stores cache data is greater than the duration for which the cache latch corresponding to the second mode stores cache data.

19. The method of claim 17, wherein, The programming mode of the memory device is the first mode; when a program state error occurs in a programming operation of the memory device, the data in the cache latch is the data corresponding to the programming operation; The method further comprises: Based on the data obtained directly from the cache latch, obtain recovery data for all the storage bits of the storage unit.

20. The operating method according to claim 17, characterized in that, The programming mode of the memory device is the second mode; the programming operation performed by the memory device comprises a multi-pass programming operation on a group of the storage units; When a programming state error occurs in a programming operation of a group of the memory cells of the memory device, data in some of the plurality of data latches has been updated to data corresponding to a next iteration of a current iteration of the multiple iteration programming operation; The method further includes: Based on the data transmitted from the data buffer to the cache latch, obtaining recovery data of the storage bit corresponding to the data latch whose data has not been updated; And Using the independent redundant disk array to recover error data of the storage bit corresponding to the data latch whose data has been updated.

21. The operating method according to claim 19, characterized in that: The second mode includes a first sub-mode and a second sub-mode; the time at which the cache latch corresponding to the first sub-mode releases cache data is later than the time at which the cache latch corresponding to the second sub-mode releases cache data; The amount of data recovered using the independent redundant disk array when the memory device performs a programming operation in the first sub-mode is less than the amount of data recovered using the independent redundant disk array when the memory device performs a programming operation in the second sub-mode.

22. The method of claim 20, wherein, When the memory device performs a programming operation in the first mode, the cache latch releases cache data corresponding to the programming operation after all programming states are verified; When the memory device performs a programming operation in the first sub-mode, the cache latch releases cache data corresponding to the programming operation after a first portion of programming states are verified, and updates data corresponding to a next programming operation to some data latches; When the memory device performs a programming operation in the second sub-mode, the cache latch releases cache data corresponding to the programming operation after a second portion of programming states are verified, and updates data corresponding to a next programming operation to some data latches; The number of programming states corresponding to the first portion is greater than the number of programming states corresponding to the second portion.

23. The method of claim 17, wherein: The method further includes: Based on the programming mode being the second mode, sending a first command; the first command instructs the memory device to transmit data in the plurality of data latches to the cache latch, respectively.

24. The method of operation of claim 23, wherein, The first command is configured by setting a feature command.

25. The method of claim 20, wherein, The method further includes: Decoding the data of the data latch whose data has not been updated to obtain user data of the storage bit corresponding to the data latch whose data has not been updated; Using the user data of the storage bit corresponding to the data latch whose data has not been updated, in combination with the independent redundant disk array, to recover error data of the storage bit corresponding to the data latch whose data has been updated, to obtain user data of the storage bit corresponding to the data latch whose data has been updated; Encoding the user data of all the storage bits, and controlling the memory device to program the encoded data to a position different from the position of the programming state in which an error occurs.

26. The operating method according to claim 19, characterized in that, The method further includes: based on the programming mode being the first mode, sending a second command and a third command; the second command instructing the memory device to output data in a cache latch of the page buffer; the third command instructing the memory device to program the recovery data to a location different from a programming location where an error in a programming state occurs.

27. The method of operating according to claim 26, wherein, The memory device includes at least one memory chip; the memory chip includes at least one memory plane; the memory plane includes a plurality of memory blocks; The method further includes: based on the programming mode being the first mode, sending a fourth command; the fourth command instructing the memory device to obtain the recovery data with data in the cache buffer and program the recovery data to other memory blocks of the memory plane where the error in the programming state occurs.

28. A method of operation according to any of claims 15 to 27, characterised by, The method further includes: controlling the memory device to re-perform a programming operation with the recovery data; after the re-programming operation is completed, updating a logical-physical mapping table.

29. A readable storage medium, characterized by, The readable storage medium stores a computer program, which, when executed, implements the operation method of any one of claims 15-28.

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