Method for manufacturing electronic chip with electromagnetic shielding

Abstract

A method for manufacturing an electronic chip with electromagnetic shielding is provided. An example method includes: i) providing a chip, the chip including: an insulating substrate covered by an interconnect structure, the interconnect structure including an insulating layer in which a conductive track is formed, the conductive track exposed onto an upper surface of the interconnect structure and onto one of side surfaces of the interconnect structure, and a connection pad portion coated with a resin, a conductive rail to be connected to the conductive rail and connectable to an external element; and ii) forming a conductive coating to cover the side surfaces of the substrate and the interconnect structure, whereby the conductive coating is connected to the conductive track.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATION(S)

[0002] This application claims the benefit of priority to French patent application No. 2404174, filed on April 23, 2024, entitled “Procédéde fabrication d'une puceélectronique ayant un blindageélectromagnétique,” ​​which is hereby incorporated herein by reference to the fullest extent permitted by law. Technical Field

[0003] The present disclosure relates to the field of chips of the CSP (“Chip Scale Package”) or WLCSP (“Wafer Chip Scale Package”) type and more particularly to a method for manufacturing an electronic chip with electromagnetic shielding. Background Art

[0004] An electronic chip comprises a substrate in or on which electronic circuits have been manufactured. The substrate is covered with connection areas to allow the chip to be assembled with, for example, a printed circuit board.

[0005] However, the chip may be subject to, and / or may generate, electromagnetic interference (EMI) that may disrupt its operation or even cause significant damage.

[0006] To protect the chip from unwanted electromagnetic radiation, a molding is typically formed around the chip at the component level, and an electromagnetic shield is formed around the molding. Optionally, a second molding can be formed over the electromagnetic shield. Grounding of the electromagnetic shield can be achieved with the aid of vias and / or laminates, and can also be used to add an antenna.

[0007] To manufacture electronic chips, low temperature co-fired ceramics (LTCC) may be used, which comprise a plurality of dielectric layers, conductive material (eg screen printed) and holes for interconnecting the different layers. Due to the use of holes / vias, shielding is easy to manufacture.

[0008] However, such chips include many interconnect layers and components, thus complicating fabrication and / or increasing the size of the final chip. Summary of the Invention

[0009] There is a need to at least partially improve certain aspects of known methods of manufacturing electronic chips comprising electromagnetic shielding.

[0010] This object is achieved by a method for manufacturing an electronic chip with electromagnetic shielding, the method comprising the following steps:

[0011] i) providing an electronic chip, the electronic chip comprising:

[0012] - an insulating substrate comprising a lower surface, lateral surfaces and an upper surface;

[0013] - an interconnection structure covering the upper surface of the substrate, the interconnection structure comprising an insulating layer in which electrically conductive tracks are formed, the connection pads being arranged on the interconnection structure, the electrically conductive tracks being arranged to be exposed to at least one of the lateral surfaces of the interconnection structure;

[0014] - a resin covering the upper surface of the interconnection structure and partially coating the connection pads to enable the connection of the connection pads to external elements;

[0015] ii) forming an electrically conductive coating on the lateral surfaces and the lower surface of the substrate and on the lateral surfaces of the interconnection structure, whereby the electrically conductive coating is connected to the electrically conductive tracks on at least one of the lateral surfaces of the interconnection structure.

[0016] According to a particular embodiment, step ii) is performed by spraying a solution or by inkjet.

[0017] According to a particular embodiment, the solution or the ink comprises silver nanoparticles.

[0018] According to a particular embodiment, the electronic chip provided at step i) is obtained according to the following steps:

[0019] - providing a substrate covered by an interconnection structure, the connection pads being arranged on the interconnection structure, the electrically conductive tracks being arranged to be exposed to at least one of the lateral surfaces of the interconnection structure,

[0020] - depositing a resin on the interconnection structure and on the connection pads,

[0021] - thinning the resin to leave a passage to a portion of the connection pads,

[0022] - possibly, thinning the substrate and / or covering the back of the chip with an additional resin layer,

[0023] - cutting the substrate into different chips.

[0024] This object is also achieved by an electronic chip comprising:

[0025] - an insulating substrate comprising a lower surface, lateral surfaces and an upper surface;

[0026] - an interconnection structure covering the upper surface of the substrate, the interconnection structure comprising an insulating layer in which electrically conductive tracks are formed, the connection pads being arranged on the interconnection structure, the electrically conductive tracks being arranged to be exposed to at least one of the lateral surfaces of the interconnection structure;

[0027] - a resin covering the interconnection structure and leaving a passage to a portion of the connection pads;

[0028] - an electrically conductive coating covering and contacting the side surface and the lower surface of the substrate of the chip and the side surface of the interconnection structure to connect the electrically conductive track to the electrically conductive coating on at least one of the side surfaces of the interconnection structure.

[0029] According to a particular embodiment, the thickness of the electrically conductive track is in the range from 2 to 12 pm.

[0030] According to a particular embodiment, the width of the electrically conductive track is greater than 10 pm.

[0031] According to a particular embodiment, the electrically conductive coating is made of silver.

[0032] According to a particular embodiment, the electrically conductive track exposed on the side surface of the interconnection structure comprises a comb-shaped end.

[0033] According to a particular embodiment, the electrically conductive track is exposed on two opposite side surfaces of the interconnection structure.

[0034] This object is also achieved by using such an electronic chip in the automotive field, for example in advanced driver assistance systems, in personal electronic products, communication equipment such as one of a computer, a cellular phone ("smartphone"), an Internet of Things (IoT) or a peripheral device thereof.

[0035] This object is also achieved by an automobile, communication equipment such as one of a computer, a cellular phone ("smartphone"), an Internet of Things (IoT) or a peripheral device thereof comprising such an electronic chip. BRIEF DESCRIPTION OF DRAWINGS

[0036] The foregoing features and advantages, as well as others, will be described in detail in the description of specific embodiments given below with reference to the accompanying drawings, in which:

[0037] FIG. 1A , FIG. 1B , FIG. 1C , FIG. 1D , FIG. 1E , FIG. 1F , FIG. 1G , FIG. 1H , FIG. 1I and FIG. 1J shows a cross-sectional view illustrating different steps of a method of manufacturing an electronic chip with electromagnetic shielding according to a particular embodiment;

[0038] FIG. 2 shows a cross-sectional view of an electronic chip with electromagnetic shielding according to another particular embodiment;

[0039] FIG. 3 shows a top view of an electronic chip with electromagnetic shielding according to another particular embodiment. DETAILED DESCRIPTION

[0040] In the various figures, identical features are denoted using identical reference numerals. In particular, structural and / or functional features common to the various embodiments can have identical reference numerals and be deployed with identical structural, dimensional and material properties.

[0041] For the sake of clarity, only the operations and elements that are helpful for understanding the operation of the embodiments described herein are illustrated and described in detail.

[0042] Unless otherwise stated, when two elements are mentioned as being connected together, this means that they are directly connected, without any intermediate element other than a conductor, and when two elements are mentioned as being coupled together, this means that the two elements can be connected, or they can be coupled via one or more other elements.

[0043] In the following disclosure, unless otherwise stated, when an absolute position qualifier such as the terms "front", "back / backward", "top", "bottom", "left", "right" and the like, or a relative position qualifier such as the terms "above", "below", "higher", "lower" and the like, or an orientation qualifier such as "horizontal", "vertical" and the like, are mentioned, they refer to the orientation shown in the figures.

[0044] Unless otherwise stated, the expressions "about", "approximately", "substantially" and "on the order of" mean within 10%, preferably within 5%.

[0045] A method of manufacturing an electronic chip with electromagnetic shielding will now be described in further detail. FIGS. 1A-1J A method of manufacturing an electronic chip with electromagnetic shielding will now be described in further detail.

[0046] The method comprises the following steps:

[0047] i) providing an electronic chip 100 comprising:

[0048] - an insulating substrate 12 comprising a lower surface 14, side surfaces 15 and an upper surface 16;

[0049] - an interconnection structure 22 covering the upper surface 16 of the substrate 12, the interconnection structure 22 comprising an upper surface, side surfaces and a lower surface in contact with the substrate 12, the interconnection structure 22 comprising an insulating layer 24 in which electrically conductive tracks 26 are formed, the electrically conductive tracks being exposed on the one hand onto the upper surface to form connection areas and on the other hand onto one of the side surfaces of the interconnection structure 22;

[0050] - connection pads 30 joined to the connection areas 26;

[0051] - a resin 40 covering the interconnection structure 22 and leaving a passage to a portion of the connection pads 30 so as to be able to connect them to external elements;

[0052] ii) forming an electrically conductive coating 50 on the side surface 15 and on the lower surface 16 of the substrate 12 of the chip 100 and on the side of the interconnection structure 22, whereby the electrically conductive tracks 26 are connected to the electrically conductive coating 50 on the side of the interconnection structure 22.

[0053] With this method, the grounding of the electromagnetic coating 50 is directly at the tracks 26 of the interconnection structure 22 of the chip 100. This makes it possible not only to free up space, since no further additional elements are necessary to couple the chip to the coating, but also to leave a passage to the interconnection pads 30 for the subsequent assembly of the chip to an external element (for example, a chip or a printed circuit).

[0054] The electromagnetic shield (EMI) is connected to ground via the interconnection structure. The electrically conductive tracks connected to the electromagnetic shield are ground interconnections.

[0055] This method does not require covering the side surface of the substrate 12 with a resin layer nor forming a via in the substrate 12.

[0056] More particularly, the method can comprise the following steps:

[0057] a) providing a structure comprising a plurality of chips 100, the structure comprising a substrate 12 covered by an interconnection structure 22, connection pads 30 joined to the interconnection structure 22 FIG. 1A ),

[0058] b) depositing a resin 40 on the interconnection structure 22 and on the connection pads 30 and thinning the resin 40 to leave a passage to a portion of the connection pads 30 FIG. 1B ),

[0059] c) preferably, thinning the substrate 12 FIG. 1C ) and / or covering the back surface 16 of the chip 100 with an additional resin layer,

[0060] d) separating the chips 100 by cutting the structure between the chips, whereby individualized chips 100 such as previously defined at step i) are obtained FIG. 1D , wherein the cutting step can be performed by joining the structure obtained at step c) to a first adhesive 201 (or carrier), preferably the substrate 12 is joined to the first adhesive 201 on its back surface to perform the cutting step from the front;

[0061] e) simultaneously joining the cut chips 100 to a second adhesive 202, the chips being joined on their front, i.e. the resin 40 and the connection pads 30 of the chips 100 are joined to the second adhesive 202 FIG. 1E ).

[0062] f) removing the first adhesive 201 FIG. 1F ),

[0063] g) if necessary, stretching the second adhesive 202 so as to leave more passage to the side surface of the substrate 12 and to the side surface of the interconnection structure 22 of the chip 100 FIG. 1G

[0064] h) implementing step ii), i.e. depositing an electromagnetic coating 50 on the side surface 15 and on the back 14 of the chip 100 and on the side surface of the interconnection structure 22 FIG. 1H

[0065] The method can also comprise, after step ii), the following steps:

[0066] - on the back of the chip 100, bonding the chip 100 to a third adhesive 203

[0067] ( carrier ) by bonding the coating 50 to the third adhesive 203 FIG. 1I

[0068] - removing the third adhesive 203 FIG. 1J

[0069] Preferably, the steps of the method are implemented so as to simultaneously treat all the chips originating from the same substrate.

[0070] At the end of the method, a chip 100 comprising an electromagnetic coating 50 is obtained FIG. 2 and FIG. 3 .

[0071] Each of the different steps will now be described in further detail.

[0072] During step a), the active parts of the chips 100 are formed on the same substrate 12 and have not yet been individualized.

[0073] During step a), one or more discrete components, not shown, can have been formed. The one or more discrete components are for example chosen among transistors, diodes, thyristors, triacs, filters, etc. The chip 100 can comprise one or more electronic circuits. The chip 100 makes it possible to implement different electronic functions.

[0074] The chips can be identical or different.

[0075] Each electronic chip 100 comprises:

[0076] - an insulating substrate 12,

[0077] - an interconnection structure 22 covering the substrate 12,

[0078] - connection pads 30 arranged on the interconnection structure 20.

[0079] ​​​​According to an embodiment, at this stage of the process, the substrate 12 corresponds to a plate.

[0080] The substrate 12 is an insulating substrate (“highly insulating substrate”). Its resistivity is for example higher than 1 kQ.cm. For example, it is a high resistivity silicon substrate (HRSI, for “High Resistivity Silicon”) or a glass substrate. Any other highly electrically insulating substrate or electrically insulating substrate can be used.

[0081] The thickness of the substrate 12 ranges for example from 100 to 900 pm, preferably from 300 to 900 pm, for example the thickness is approximately 725 pm.

[0082] The substrate 12 comprises a first surface 16 (upper surface or front face or active surface) and a second surface 14 (lower surface or back face). The two surfaces 14 and 16 are parallel to each other. They are coupled together by a lateral wall 15. An insulating layer can cover the lower surface 14.

[0083] The interconnection structure 22 comprises one or more (for example two or three) levels of electrically conductive tracks 26 and insulating layers 24.

[0084] The electrically conductive tracks 26 are for example made of one or more materials chosen among copper, copper alloy, titanium, titanium alloy, titanium nitride, gold, tungsten, platinum and platinum alloy. The electrically conductive tracks 26 can also be aluminum. According to an embodiment, the thickness of each metal track 26 is in the range from 2 to 40 pm, for example in the range from 2 to 12 pm. A thicker track facilitates the contact surface area between the track 26 and the electromagnetic coating 50. A thinner track 26 will be easier to cut.

[0085] The insulating layers 24 can be multilayered, formed of a plurality of insulating layers. According to an embodiment, the thickness of each insulating layer 24 is in the range from 0.5 pm to 15 pm.

[0086] The insulating layers 24 can be made of a dielectric material, for example an oxide or a nitride, preferably silicon dioxide (Si02), silicon nitride (for example Si3N4). Alternatively, the insulating layers can also be made of a polymer, in particular a polyimide.

[0087] The interconnection structure 22 comprises an upper surface, a lower surface and lateral faces. The lower surface is in contact with the upper surface 16 of the substrate 12.

[0088] The metal tracks 26 are flush with the upper surface to form connection areas. The connection areas, also called electrical contacts, make it possible to connect the electrical terminals of the chip 100 to other elements (for example a chip or a printed circuit) by means of connection pads 30.

[0089] The electrical connection areas are also called “UBM” (Under Bump Metallization). Preferably, there are at least two connection areas. For example, in the case of a chip 100 with a square shape, there are four connection areas.FIG. 3 Six electrical connection areas are shown in the middle.

[0090] For example, the electrical connection areas are at a distance from 10 to 30 pm from the sidewalls of the chip. This distance depends on the chip. It can be several hundreds of micrometers, or even a few millimeters, depending on the assembly produced.

[0091] A portion of the metal tracks 26 is accessible from the side of the interconnection structure 22 to be able to connect directly to the metal coating 50, thus grounding the coating 50. The metal tracks can be accessible on at least one face of the chip 100. They can be accessible on several sides of the chip 100, for example on two opposite sides.

[0092] The connection pads 30 are joined to the connection areas. The connection pads 30 are advantageously soldered to the electrical connection areas. The connection pads 30 are formed of an electrically conductive and wettable (i.e. solderable or weldable) material, i.e. a material on which soldering can be performed. For example, the metal pads are made of a tin-based solderable material, typically SnAgCu or Cu / SnAg.

[0093] During step b), a layer of resin 40 is deposited on the front face on the interconnection structure 22 and on the connection pads 30.

[0094] The resin 40 is an electrically insulating resin. It can be a thermosetting resin or a thermoplastic resin. The material should be chosen as a material that is not meltable in the temperature range of use of the electronic assembly. The resin can be chosen from the group comprising: epoxy-based resins, phenolic-based resins, acrylic-based resins.

[0095] The resin can also contain electrically insulating particles. These particles are, for example, oxide particles, and in particular alumina or silica particles.

[0096] The layer of resin 40 comprises an upper face, a lower face in contact with the interconnection structure 22, and lateral faces.

[0097] The resin 40 is thinned after it has been deposited, to leave a passage to the upper part of the pads.

[0098] During step c), the substrate 12 can be thinned on its back face 14, and / or a layer of resin 30 can be deposited on the back of the substrate 12. To do this, the structure is turned over and joined to a first support 201 by its front face. The first support 201 is, for example, an adhesive strip. The structure is then thinned on its back face, so that the substrate 12 has its final thickness.

[0099] Preferably, the lateral faces of the substrate 12 are not covered with resin.

[0100] During step d), the substrate 110 is cut between the chips 100 to singulate the chips. To this end, a trench is formed which goes right through the structure obtained at step c). The trench 120 defines the lateral profile of the chip 100.

[0101] The width of the trench 120 is for example in the range from 20 to 80 pm.

[0102] This cutting step can be performed by means of a cutting or etching device. The cutting device is for example a mechanical cutting tool such as a saw. The cutting can be performed with a single blade or a double blade.

[0103] It can also be a laser cutting ("laser grooving" or "laser scribing") or a plasma scribing. These different cutting processes can also be used together.

[0104] The trench can also be formed by a laser dislocation cutting (stealth dicing) step followed by an expansion step. In the stealth dicing step, specific lasers are used to create dislocations in the substrate in the cutting path. These dislocations are defects in the thickness of the substrate which, under the effect of mechanical stress, will make it possible to separate the chips. It is simply a question of stretching the adhesive carrier to pull the chips apart and deposit the material.

[0105] It is also possible to implement a first step during which a laser is used to cut the upper part of the device which extends from the front of the interconnection structure 22 to the lower part; then, a second step during which a saw is used to cut the substrate 12. The use of a laser to cut the tracks of the interconnection structure, in particular the tracks made of copper, and the insulating layer makes it possible to obtain a clean cut and to avoid delamination phenomena.

[0106] The cutting step is preferably performed from the front. To this end, the structure obtained at step c) is joined by its back face to a first adhesive 201.

[0107] Once the substrate has been cut, the structure is turned over so as to be able to deposit the coating from the back face. To this end, a second adhesive 202 is joined to the front face of the cut chips (step e)). The second adhesive 202 is a stretchable adhesive.

[0108] The first adhesive 201 is removed (step f)). Then, the second adhesive 202 is stretched to increase the distance between the two chips 100 and to make it easier to access the side faces of the electronic chips (step g)). This step is optional. It depends on the width of the cut made in step d) and / or the type of process used to deposit the shielding layer 50.

[0109] Alternatively, during step c), the chip 100 can be bonded by its front face to a stretchable adhesive. Then, the cutting step (step c) and the step of coating deposition (step h) can be performed on the same stretchable adhesive. There is no need to flip the chip 100.

[0110] The various adhesives used in this process can be ultraviolet (UV) sensitive adhesives for cutting applications ("UV dicing tape").

[0111] Step ii) is then implemented.

[0112] The coating can be deposited at once. In other words, the back face and the lateral surfaces of the chip 100 are covered at the same time.

[0113] Preferably, the coating 50 is deposited by liquid phase deposition. The electromagnetic coating 50 is for example deposited by solution spray or inkjet. It can also be screen printed. The coating can also be deposited by evaporation or atomic layer deposition (ALD).

[0114] The solution or ink used contains electrically conductive nanoparticles, generally metallic nanoparticles, for example silver nanoparticles. Alternatively, the nanoparticles can be granules or microparticles.

[0115] Depending on the process used, the lateral wings 15 of the chip can be partially or completely covered by the coating. For example, the side walls of the resin layer 40 can or can not be covered by the coating 50.

[0116] At the end of this method, a chip 100 such as FIG. 2 and FIG. 3 is obtained. The electronic chip 100 comprises:

[0117] - an insulating substrate 12 comprising a lower face 14, lateral surfaces 15 and an upper face 16,

[0118] - an interconnection structure 22 covering the upper face 16 of the substrate, the interconnection structure 22 comprising an upper face, lateral surfaces and a lower face in contact with the substrate 12, the interconnection structure comprising an insulating layer 24 in which electrically conductive tracks 26 are formed, the electrically conductive tracks being exposed on the one hand onto the upper face of the interconnection structure to form connection areas and on the other hand onto one of the lateral surfaces of the interconnection structure 22,

[0119] - connection pads 30 connected to the connection areas,

[0120] - a resin 40 covering the interconnection structure and leaving a passage to a part of the connection pads

[0121] - an electrically conductive coating 50 covering and in contact with the lateral surfaces 15 and the lower face 14 of the substrate of the chip 100 and the lateral surfaces of the interconnection structure 22, connecting the electrically conductive tracks 26 to the electrically conductive coating on the lateral surfaces of the interconnection structure 22.

[0122] The conductive coating is for example a metallic coating. It can be silver.

[0123] The conductive tracks 26, which are exposed on the sides of the interconnection structure 22, can comprise comb-shaped ends FIG. 3 ) or have a solid shape, for example a strip.

[0124] The same chip 100 can comprise the same or different tracks. The conductive tracks 26 can be symmetrical or asymmetrical.

[0125] It will be desirable to maximize the surface area of contact between the metallic tracks 26 and the conductive coating 50 to ensure good electrical contact.

[0126] Preferably, the different conductive tracks 26 are exposed on several sides of the interconnection structure 22. Preferably, the conductive tracks 26 are exposed on two opposite sides of the interconnection structure 22.

[0127] The tracks 26 are preferably made of copper or aluminum.

[0128] Each electronic chip 100 can then be joined to an external element, for example another chip, a package, a printed circuit board or another electronic chip.

[0129] Such electronic chips can be applied in many industrial fields, in particular in the automotive field, for personal electronic products, in particular communication equipment, or in computers and peripherals.

[0130] For example, these can be 5G connectivity devices, or more generally, connected devices.

[0131] They can also be advanced driver assistance systems (ADAS).

[0132] Microchips can be used in smartphones, or for the Internet of Things (IoT). Devices are connected, for example via 5G, WIFI or Ultra Wide Band (UWB).

[0133] The chip can also attract interest in other fields, such as industrial applications, in particular green energy.

[0134] Such applications are given by way of illustration only and are not limiting.

[0135] Various embodiments and variants have been described. The person skilled in the art will understand that certain features of these various embodiments and variants can be combined and that other variants will occur to the person skilled in the art.

[0136] A variety of embodiments and variant examples have been described. Those of skill in the art will understand that certain features of the various embodiments and variant examples can be combined, and that other variants will occur to those of skill in the art.

Claims

1. A method of manufacturing an electronic chip of CSP type with electromagnetic shielding, comprising: i) providing an electronic chip of CSP type, the electronic chip of CSP type comprising: - an insulating substrate having an electrical resistivity higher than 1 kQ.cm and comprising a lower surface, lateral surfaces and an upper surface, an active part of the electronic chip being formed on the substrate; - an interconnection structure covering the upper surface of the substrate, the interconnection structure comprising an insulating layer in which conductive tracks are formed, connection pads being arranged on the interconnection structure, the conductive tracks being arranged to be exposed to at least one of the lateral surfaces of the interconnection structure; - a resin covering the upper surface of the interconnection structure and partially coating the connection pads to enable the connection pads to be connected to external elements; and ii) forming a conductive coating on the lateral surfaces and on the lower surface of the substrate and on the lateral surfaces of the interconnection structure, the conductive coating covering and contacting the lateral surfaces and the lower surface of the substrate of the electronic chip and the lateral surfaces of the interconnection structure, whereby the conductive coating is connected to the conductive tracks on at least one of the lateral surfaces of the interconnection structure.

2. The method of claim 1, wherein step ii) is performed by spraying a solution or by inkjet.

3. The method of claim 2, wherein the solution or the ink comprises silver nanoparticles.

4. The method of claim 1, wherein the electronic chip provided at step i) is obtained according to the following steps: - providing a substrate covered by an interconnection structure, connection pads being arranged on the interconnection structure, the conductive tracks being arranged to be exposed to at least one of the lateral surfaces of the interconnection structure; - depositing a resin on the interconnection structure and on the connection pads; - thinning the resin to leave a passage to a portion of the connection pads; and - cutting the substrate into different electronic chips.

5. The method of claim 1, wherein the electronic chip provided at step i) is obtained according to the following steps: - providing a substrate covered by an interconnection structure, connection pads being arranged on the interconnection structure, the conductive tracks being arranged to be exposed to at least one of the lateral surfaces of the interconnection structure; - depositing a resin on the interconnection structure and on the connection pads; - thinning the resin to leave a passage to a portion of the connection pads; - thinning the substrate or covering the lower surface of the electronic chip formed on the substrate of the electronic chip with an additional layer of resin; and - cutting the substrate into different electronic chips.

6. An electronic chip of CSP type with electromagnetic shielding, comprising: - an insulating substrate having an electrical resistivity higher than 1 kQ.cm and comprising a lower surface, lateral surfaces and an upper surface, an active part of the electronic chip being formed on the substrate; - an interconnection structure covering the upper surface of the substrate, the interconnection structure comprising an insulating layer in which conductive tracks are formed, connection pads being arranged on the interconnection structure, the conductive tracks being arranged to be exposed to at least one of the lateral surfaces of the interconnection structure; - a resin covering the interconnection structure and leaving a passage to a portion of the connection pads; and ​ - an electrically conductive coating covering and contacting the side surfaces and the lower surface of the substrate of the chip and the side surfaces of the interconnect structure to connect the electrically conductive tracks to the electrically conductive coating on at least one of the side surfaces of the interconnect structure.

7. The electronic chip of claim 6, wherein the thickness of the electrically conductive tracks is in the range from 2 to 12 pm.

8. The electronic chip of claim 6, wherein the width of the electrically conductive tracks is greater than 10 pm.

9. The electronic chip of claim 6, wherein the electrically conductive coating is made of silver.

10. The electronic chip of claim 6, wherein the electrically conductive tracks exposed to the side surfaces of the interconnect structure have comb-shaped end portions.

11. The electronic chip of claim 6, wherein the electrically conductive tracks are exposed to two opposite side surfaces of the interconnect structure.

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