Semiconductor packaging structure
By employing bonding wires and bumps in the electrical connection design of the semiconductor packaging structure, the problem of excessively long I/O connection path length in stacked packaging is solved, realizing a low-power and low-cost semiconductor packaging structure, and improving performance and efficiency.
Patent Information
- Application Number
- CN202411121571.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Priority Date
- 2024-04-18
- Filing Date
- 2024-08-15
- Publication Date
- 2025-10-24
AI Technical Summary
In existing multilayer packaging structures, the I/O connection path between memory chips and system chips is relatively long, which leads to increased power consumption and increased demand for I/O drivers, as well as higher manufacturing costs.
The design employs a structure where the first chip is connected to the carrier board via bonding wires, and the second chip is connected to the first chip via bumps. This reduces the length of the I/O connection path and achieves smaller chip spacing and shorter connection paths through micro-bumps, hybrid bumps, or nano-bumps.
It significantly reduces power consumption, decreases manufacturing costs, and improves the performance of semiconductor packaging structures, particularly in terms of memory access power, I/O capacitance, and voltage requirements.
Smart Images
Figure CN120834085A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present invention relates to a semiconductor package structure, and more particularly, to a semiconductor package structure with superior performance and low manufacturing cost. BACKGROUND
[0002] The semiconductor industry has experienced rapid growth due to the increasing integration of various electronic components (e.g., transistors, diodes, resistors, capacitors, etc.) onto semiconductor chips. In large part, this increase in integration has come from a continuous reduction in minimum feature size, which allows more components to be integrated into a given area. These smaller electronic components also require smaller packaging, thus using less area than previous generation packages. Currently, package-on-package (PoP) structures are becoming more popular due to their compactness.
[0003] Generally, in a PoP structure including a memory chip and a system-on-chip (SoC), the memory chip is electrically connected to the SoC by bonding wires. As a result, the input / output (I / O) connection path between the memory chip and the SoC from the bonding wires typically has a length of several millimeters. Such an I / O connection path can cause an increase in memory I / O power consumption. In addition, since the memory chip is electrically connected to the SoC by the bonding wires, large I / O drivers are required, which further increases the overall capacitance of the I / O connection path. SUMMARY
[0004] The present invention is directed to a semiconductor package structure in which a first chip is disposed on a carrier and electrically connected to the carrier by bonding wires, and a second chip is disposed on the first chip and electrically connected to the first chip by bumps.
[0005] The semiconductor package structure of the present invention includes a carrier, a first chip, a second chip, a plurality of bonding wires, and a plurality of first bumps. The first chip is disposed on the carrier. The second chip is disposed on the first chip. The plurality of bonding wires is disposed to electrically connect the first chip and the carrier. The plurality of first bumps is disposed to electrically connect the second chip and the first chip. The plurality of first bumps is interposed between the second chip and the first chip.
[0006] In an embodiment of the semiconductor package structure of the present invention, at least one of the first bumps is disposed as an input / output connection path between the first chip and the second chip.
[0007] In an embodiment of the semiconductor package structure of the present invention, the first chip is disposed on the carrier with a back surface of the first chip facing the carrier.
[0008] In an embodiment of the semiconductor package structure of the present application, the second chip is disposed on the first chip with a front surface of the second chip facing a front surface of the first chip.
[0009] In an embodiment of the semiconductor package structure of the present application, for each of the first bumps, one end of the first bump is attached to a first contact pad formed on the front surface of the first chip, and the other end of the first bump is attached to a second contact pad formed on the front surface of the second chip.
[0010] In an embodiment of the semiconductor package structure of the present application, thicknesses of the first contact pads, the first bumps, and the second contact pads substantially serve as a distance between the first chip and the second chip, and the distance is between 50 μm and 150 μm.
[0011] In an embodiment of the semiconductor package structure of the present application, for each of the wire bonds, one end of the wire bond is connected to a first contact pad formed on the front surface of the first chip, and the other end of the wire bond is electrically connected to the carrier.
[0012] In an embodiment of the semiconductor package structure of the present application, the first chip comprises a system chip having an advanced RISC machine (ARM) architecture.
[0013] In an embodiment of the semiconductor package structure of the present application, the second chip comprises a memory chip.
[0014] In an embodiment of the semiconductor package structure of the present application, the memory chip comprises a dynamic random access memory (DRAM) based chip having a 1 transistor and 1 capacitor (1T1C) architecture.
[0015] In an embodiment of the semiconductor package structure of the present application, the first bumps comprise micro-bumps, hybrid-bumps, or nano-bumps.
[0016] In an embodiment of the semiconductor package structure of the present application, a spacing between the first chip and the second chip is less than 1 mm.
[0017] In an embodiment of the semiconductor package structure of the present application, a spacing between the first chip and the second chip is less than 150 μm.
[0018] In an embodiment of the semiconductor package structure of the present application, a size of the second chip is 16 mm 2or less.
[0019] In one embodiment of the semiconductor package structure of the present application, the carrier board includes a lead frame.
[0020] In one embodiment of the semiconductor package structure of the present application, the carrier board includes a printed circuit board (PCB) or a circuit substrate including a printed circuit board and an interposer disposed on the printed circuit board and electrically connected to the printed circuit board.
[0021] In one embodiment of the semiconductor package structure of the present application, a plurality of second bumps are further included, which are disposed on a surface of the carrier board opposite to the first chip.
[0022] In one embodiment of the semiconductor package structure of the present application, the plurality of first bumps include at least 100 first bumps.
[0023] In one embodiment of the semiconductor package structure of the present application, an adhesive layer is further included, which is disposed between a back surface of the first chip and the carrier board, and a material of the adhesive layer includes an Ajinomoto build-up film (ABF), a polyimide resin, or an epoxy resin.
[0024] In one embodiment of the semiconductor package structure of the present application, an encapsulation layer is further included, which encapsulates at least the carrier board, the first chip, the plurality of bonding wires, the second chip, and the plurality of first bumps, and a material of the encapsulation layer includes a molding compound.
[0025] Based on the above, in the semiconductor package structure of the present application, the first chip is disposed on the carrier board and electrically connected to the carrier board through the bonding wires, and the second chip is disposed on the first chip and electrically connected to the first chip through the bumps. Since the first chip is electrically connected to the carrier board through the bonding wires, the manufacturing cost can be reduced. In addition, since the second chip is electrically connected to the first chip through the bumps, the length of the I / O connection path between the first chip and the second chip can be reduced. Therefore, the power consumption can be significantly reduced, so that the semiconductor package structure of the present application has superior performance. BRIEF DESCRIPTION OF DRAWINGS
[0026] Figure 1 is a cross-sectional schematic view of a semiconductor package structure of a first embodiment of the present application; Figure 2 is a cross-sectional schematic view of a semiconductor package structure of a second embodiment of the present application; Figure 3Definitions of front side and back side of a semiconductor structure or wafer are shown. DETAILED DESCRIPTION
[0027] Embodiments are illustrated by way of example in the following detailed description and are not intended to limit the scope of the application, as understood by persons of ordinary skill in the art. Further, the detailed description is structured with the intent that the examples provided are not limiting of the scope of the application. In addition, the drawings are not drawn to scale and are for purposes of explanation only. For ease of understanding, the same reference numbers will be used across figures to refer to the same or like components.
[0028] As used herein, the terms "comprise", "comprising", "include", "including", "have", "having" or the like are open-ended and do not exclude additional, unrecited elements or method steps.
[0029] When using terms like "first" and "second" to describe components, these terms are used to distinguish one component from another, and do not limit the order or importance of the components. Thus, a first component could also be termed a second component, and, similarly, a second component could also be termed a first component, without departing from the scope of the present application.
[0030] Further, directional terms as used herein - such as "upper", "lower", and the like - are made only by reference to the accompanying drawings, and are not intended to limit the present application. Thus, it is to be understood that "upper" can be referenced as "lower", and "lower" can be referenced as "upper", and that when a layer or film is placed "on" another, the layer or film can be placed directly on the other, or intervening components can be present. Conversely, when a component is said to be placed "directly" on another, no intervening components are present.
[0031] In addition, ranges expressed in this document by "from X to Y" are shorthand for "X or more and Y or less" and are meant to encompass all values from X to Y, inclusive. Thus, a range of "1 to 10" is meant to encompass all values from 1 to 10, inclusive.
[0032] In the following embodiments, the semiconductor package structure comprises at least a chip stack on a carrier board, wherein a first chip is arranged and electrically connected to the carrier board, and a second chip is arranged and electrically connected to the first chip on a bump. Thus, power consumption can be significantly reduced. The semiconductor package structure or embodiments of the present application are described in detail below.
[0033] Figure 1 A cross-sectional view of a semiconductor package structure according to a first embodiment of the present application.
[0034] Reference Figure 1The semiconductor package structure 10 includes a carrier board 100, a first chip 102, a plurality of bonding wires 104, a second chip 106, a plurality of bumps 108, and an encapsulation layer 110. The carrier board 100 is used to carry chips stacked thereon. In this embodiment, the carrier board 100 is a lead frame including a carrying portion 100a for carrying stacked chips and a plurality of pins 100b surrounding the carrying portion 100a. In this embodiment, the material of the carrier board 100 can be metal or alloy, such as Cu or Cu alloy, but the present application is not limited thereto.
[0035] The first chip 102 is disposed on the carrier board 100. In this embodiment, the first chip 102 can be a system chip. In this embodiment, the system chip has an advanced reduced instruction set computer (RISC) machine architecture, but the present application is not limited thereto. The first chip 102 has a front surface S1 and a back surface S2, and the first chip 102 is disposed on the carrying portion 100a of the carrier board 100 with the back surface S2 facing the carrier board 100. For the first chip 102, the range of memory I / O voltage can be 0.6 V to 1.2 V, which is feasible for a shared SoC core voltage. In addition, the I / O pin capacitance of the first chip 102 can be 0.5 pF or less.
[0036] In this embodiment, an adhesive layer 103 can be disposed between the back surface S2 of the first chip 102 and the carrying portion 100a of the carrier board 100. The material of the adhesive layer 103 can be a dry film adhesive, a polyimide resin, or an epoxy resin, but the present application is not limited thereto. The adhesive layer 103 serves as a die attach film to secure the first chip 102.
[0037] In addition, the first chip 102 includes a plurality of pads at the front surface S1. In detail, the first chip 102 includes pads 102a and pads 102b surrounded by the pads 102a. In this embodiment, the pads 102a are adjacent to the edges of the first chip 102. The first chip 102 can be electrically connected to the carrier board 100 through the plurality of bonding wires 104 connected to the pads 102a and the pins 100b. In other words, for each bonding wire 104, one end of the bonding wire 104 is connected to a pad 102a formed on the front surface S1 of the first chip 102, and the other end of the bonding wire 104 is connected to the carrier board 100.
[0038] The second chip 106 is disposed on the first chip 102. The second chip 106 can be a memory chip, such as a dynamic random access memory (DRAM) based chip. In the present embodiment, the second chip 106 has a one transistor and one capacitor architecture, but the present application is not limited thereto. The second chip 106 has a front side S3 and a back side S4, and the second chip 106 is disposed on the first chip 102 with the front side S3 facing the front side S l of the first chip 102. That is, the second chip 106 is disposed on the first chip 102 in a flip-chip manner.
[0039] Furthermore, the second chip 106 includes a plurality of pads 106a at the front side S3. A plurality of bumps 108 is disposed between the pads 102b and the pads 106a. Thus, the second chip 106 can be electrically connected to the first chip 102 through the plurality of bumps 108. In other words, for each bump 108, one end of the bump 108 is attached to a pad 102b formed on the front side S l of the first chip 102, and the other end of the bump 108 is attached to a pad 106a formed on the front side S3 of the second chip 106. Thus, the pads 102b, the bumps 108, and the pads 106a can form an I / O connection path between the first chip 102 and the second chip 106. Since the pads 102b and the pads 106a have a small thickness, the bumps 108 can be substantially considered as the I / O connection path, i.e., the bumps 108 can be disposed as the I / O connection path between the first chip 102 and the second chip 106, where the I / O connection path is disposed to transmit input / output signals or power signals of the first chip 102. In the present embodiment, the bumps 108 can be micro bumps, hybrid bumps, or nano bumps. That is, in the present embodiment, the bumps 108 can have a small size, which is feasible for a fine pitch of the pads 106a of the second chip 106. In other words, in the present embodiment, the second chip 106 can thus have a smaller size, and without having an excessive layout penalty. In one embodiment, the size of the second chip 106 can be 16 mm 2 or less, the second chip 106 can support more than 64 I / O terminals, and the second chip 106 can include at least 100 pads 106a. Furthermore, the second chip 106 can have a memory array density of less than or equal to 1 Gb.
[0040] Furthermore, in the present embodiment, since the bump 108 can be a micro bump, a hybrid bump, or a nano bump, the pitch P between the first chip 102 and the second chip 106 can be reduced. Thus, a shorter I / O connection path between the first chip 102 and the second chip 106 can be achieved. In the present embodiment, the pitch P between the first chip 102 and the second chip 106 (i.e., the length of the I / O connection path between the first chip 102 and the second chip 106) can be less than 1 mm. In one embodiment, the pitch P can be less than 150 μm, less than 100 μm, or less than 50 μm. In other words, in one embodiment, the thickness of the pad 102b, the bump 108, and the pad 106a can substantially be the distance between the first chip 102 and the second chip 106, and the distance can be in the range of about 50 μm to 150 μm.
[0041] The encapsulation layer 110 covers the surface of the carrier 100, the first chip 102, the wire bonds 104, the second chip 106, and the bump 108. The material of the encapsulation layer 110 can be a molding compound. In one embodiment, the material of the encapsulation layer 110 can be an epoxy, but the present application is not limited thereto.
[0042] In the semiconductor package structure 10 of the present embodiment, the first chip 102 and the second chip 106 are stacked on the carrier 100. The first chip 102 is disposed on the carrier 100 and electrically connected to the carrier 100 by the wire bonds 104, thus the manufacturing cost can be reduced. Furthermore, the second chip 106 is disposed on the first chip 102 and electrically connected to the first chip 102 by the bump 108, thus the length of the I / O connection path between the first chip 102 and the second chip 106 can be reduced, and thus the power consumption of the first chip 102 and the second chip 106 can be significantly reduced. Therefore, the semiconductor package structure 10 of the present embodiment can have superior performance and lower manufacturing cost.
[0043] In the present embodiment, the first chip 102 and the second chip 106 are stacked on a lead frame, but the present application is not limited thereto. In other embodiments, the first chip 102 and the second chip 106 can be stacked on other types of carriers.
[0044] Figure 2 A cross-sectional view of a semiconductor package structure of a second embodiment of the present application is shown in FIG. 2. In the present embodiment, the same components as in the first embodiment will be denoted by the same reference numerals, and will not be described again.
[0045] Referring to Figure 2The semiconductor package structure 20 of the present embodiment differs from the semiconductor package structure 10 in that the first chip 102 and the second chip 106 are stacked on the carrier board 200. In the present embodiment, the carrier board 200 can be a printed wiring board or a wiring substrate including a printed wiring board and an interposer disposed on the printed wiring board and electrically connected to the printed wiring board.
[0046] Furthermore, the carrier board 200 has a first surface S5 and a second surface S6. The first surface S5 and the second surface S6 can be the front surface and the back surface of the carrier board 200. The carrier board 200 includes a plurality of pads 200a at the first surface S5. In addition, a plurality of bumps 202 are disposed on the second surface S6 of the carrier board 200. The first chip 102 is disposed on the carrier board 200 with the back surface S2 facing the first surface S5 of the carrier board 200. In the present embodiment, the first chip 102 can be electrically connected to the carrier board 200 through the wire bonds 104 connecting the pads 102a and the pads 200a. In other words, for each wire bond 104, one end of the wire bond 104 is connected to a pad 102a formed on the front surface S1 of the first chip 102, and the other end of the wire bond 104 is connected to a pad 200a formed on the first surface S5 of the carrier board 200.
[0047] In the semiconductor package structure 20 of the present embodiment, the first chip 102 and the second chip 106 are stacked on the carrier board 200. The first chip 102 is disposed on the carrier board 200 and electrically connected to the carrier board 200 through the wire bonds 104, so the manufacturing cost can be reduced. Furthermore, the second chip 106 is disposed on the first chip 102 and electrically connected to the first chip 102 through the bumps 108, so the length of the I / O connection path between the first chip 102 and the second chip 106 can be reduced, and thus the power consumption of the first chip 102 and the second chip 106 can be significantly reduced. Therefore, the semiconductor package structure 20 of the present embodiment can have superior performance and lower manufacturing cost.
[0048] In summary, the semiconductor package structure of the present embodiment has at least the following features.
[0049] (1) The memory access power of the semiconductor package structure can be less than 1 pj / b.
[0050] (2) The semiconductor package structure can have a small density support of 64 Mb to 1 Gb.
[0051] (3) The semiconductor package structure can have excellent bandwidth support through wide I / O.
[0052] (4) The second chip 106 may be a multi-banks memory bank to improve random access efficiency.
[0053] (5) The I / O voltage of the second chip 106 can meet the requirements of the SoC.
[0054] (6) The semiconductor packaging structure can have an economical package, such as a ball grid array (BGA) package or a quad flat non-leaded (QFN) package.
[0055] In one embodiment, the semiconductor package structure of the embodiment of the present invention may have the following characteristics compared with a common semiconductor package structure (DDR3L including bonding wires), as shown in Table 1.
[0056] Table 1
[0057] It should be noted that in the above description, the "front side" (also called the front side) refers to the surface where the back-end-of-line (BEOL) process is performed, and the "back side" (also called the back side) refers to the surface of the semiconductor substrate opposite to the front side. For the purpose of explanation, Figure 3 The definitions of the front and back sides of a semiconductor structure or semiconductor wafer are shown. Figure 1 For example, as shown in FIG. 1 , the semiconductor structure 80 may include a semiconductor substrate 83 and a back-end-of-line (BEOL) structure 85, wherein a front-end-of-line (FEOL) structure 84 is formed in or on the semiconductor substrate 83. Active components or semiconductor components may be formed in the semiconductor substrate 83. According to the present embodiment, the surface of the BEOL structure 85 may be the front side 81 of the semiconductor structure 80, and the surface of the semiconductor substrate 83 may be the back side 82 of the semiconductor structure 80. However, this is not a limitation of the present invention. The definitions of the front side and the back side of the semiconductor structure may be interchangeable.
[0058] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the above embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the above embodiments, or replace some or all of the technical features therein with equivalents. However, these modifications or replacements do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A semiconductor package structure, comprising: Comprising: a carrier board; a first chip disposed on the carrier board; a second chip disposed on the first chip; a plurality of bonding wires disposed to electrically connect the first chip and the carrier board; and a plurality of first bumps disposed to electrically connect the second chip and the first chip, wherein the plurality of first bumps are sandwiched between the second chip and the first chip. At least one of the first bumps is disposed as an input / output connection path between the first chip and the second chip.
2. The semiconductor package structure of claim 1, wherein, The first chip is disposed on the carrier board with a back surface of the first chip facing the carrier board.
3. The semiconductor package structure of claim 1, wherein, The second chip is disposed on the first chip with a front surface of the second chip facing a front surface of the first chip.
4. The semiconductor package structure of claim 1, wherein, For each of the first bumps, one end of the first bump is attached to a first landing pad formed on the front surface of the first chip, and the other end of the first bump is attached to a second landing pad formed on the front surface of the second chip.
5. The semiconductor package structure of claim 4, wherein, A thickness of the first landing pad, the first bump, and the second landing pad is a distance between the first chip and the second chip, and the distance is between 50 μm and 150 μm.
6. The semiconductor package structure of claim 5, wherein, For each of the bonding wires, one end of the bonding wire is connected to a first landing pad formed on the front surface of the first chip, and the other end of the bonding wire is electrically connected to the carrier board.
7. The semiconductor package structure of claim 4, wherein, The first chip comprises a system chip having an advanced reduced instruction set computer machine architecture.
8. The semiconductor package structure of claim 1, wherein, The second chip comprises a memory chip.
9. The semiconductor package structure of claim 1, wherein, The memory chip comprises a dynamic random access memory based chip having a 1 transistor and 1 capacitor architecture.
10. The semiconductor package structure of claim 9, wherein, The first bumps comprise micro bumps, hybrid bumps, or nano bumps.
11. The semiconductor package structure of claim 1, wherein, A pitch between the first chip and the second chip is less than 1 mm.
12. The semiconductor package structure of claim 1, wherein, A pitch between the first chip and the second chip is less than 150 μm.
13. The semiconductor package structure of claim 1, wherein, The carrier board comprises a lead frame.
14. The semiconductor package structure of claim 1, wherein, The second chip has a size of 16 mm 2 or less.
15. The semiconductor package structure of claim 1, wherein, The carrier board comprises a printed wiring board or a wiring board comprising a printed wiring board and an interposer disposed on and electrically connected to the printed wiring board.
16. The semiconductor package structure of claim 1, wherein, Further comprising a plurality of second bumps disposed on a surface of the carrier board opposite the first chip.
17. The semiconductor package structure of claim 16, wherein, The plurality of first bumps comprises at least 100 first bumps.
18. The semiconductor package structure of claim 1, wherein, Further comprising an adhesive layer disposed between a back surface of the first chip and the carrier board, and a material of the adhesive layer comprises a dry film adhesive, a polyimide resin, or an epoxy resin.
19. The semiconductor package structure of claim 1, wherein, Further comprising an encapsulation layer encapsulating at least the carrier board, the first chip, the plurality of bonding wires, the second chip, and the plurality of first bumps, and a material of the encapsulation layer comprises a molding compound.
20. The semiconductor package structure of claim 1, wherein,