Semiconductor structure, forming method thereof and semiconductor device

Abstract

The embodiment of the invention provides a semiconductor structure, a forming method thereof and a semiconductor device. The semiconductor structure comprises a dielectric layer, an adhesion barrier layer and a metal interconnection layer are deposited in a through hole formed in the dielectric layer, and the adhesion barrier layer is only located on the side wall of the through hole and is an amorphous tantalum sulfide or titanium sulfide film. The adhesion barrier layer can be obtained by adopting an inhibitor-assisted atomic layer deposition process to form a tantalum sulfide or titanium sulfide thin film and then annealing the tantalum sulfide or titanium sulfide thin film. In the semiconductor structure, the adhesion barrier layer is adopted to replace a conventional stacked structure of a barrier layer and an adhesion layer, so that the volume ratio of a metal interconnection material in the through hole interconnection structure is large, the adhesion barrier layer does not exist at the bottom of the through hole of the through hole interconnection structure, the volume ratio of the metal interconnection material can be further increased, and the performance of the semiconductor structure is improved. And the problem that the resistance value of the interconnection structure is large due to the adhesion barrier layer at the bottom of the through hole is solved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of semiconductor manufacturing, and in particular to a semiconductor structure, a forming method thereof and a semiconductor device. BACKGROUND

[0002] In the process of manufacturing semiconductor devices, it is usually necessary to prepare a metal interconnection structure to realize the connection between the same layer or upper and lower layers of metal materials. In a typical metal interconnection process, an interlayer dielectric layer is first formed on a previous interconnection layer, then a via and / or a trench is formed in the interlayer dielectric, then the via or the trench is filled with electroplated metal (such as copper), and finally the overfilled copper is removed to form a new metal interconnection layer (i.e., a metal interconnection line).

[0003] Among them, between filling the via or the trench with electroplated copper, a barrier layer and a liner layer are usually sequentially deposited on the bottom and sidewall of the via or the trench to inhibit the diffusion of the metal copper into the surrounding dielectric layer and to improve the adhesion between the copper layer and the barrier layer. The barrier layer material used in the current mainstream process is tantalum nitride (TaN), and the liner layer material is tantalum (Ta). In order to ensure that the TaN layer and the Ta layer effectively play the above functions, they should have sufficient thickness respectively. However, as the size of the interconnection line continues to decrease, this leads to a gradual decrease in the volume ratio of the copper interconnection line in the via interconnection structure, and a larger resistance of the via interconnection structure. In addition, the coverage of the barrier layer and the liner layer at the bottom of the via significantly increases the resistance at the bottom of the via, thereby increasing the resistance of the overall interconnection structure and increasing the loss of power or signal in the interconnection structure. SUMMARY

[0004] In view of this, the embodiments of the present application provide a semiconductor structure and a forming method thereof to solve the problems of the small volume ratio of the metal interconnection material and the large resistance at the bottom of the via in the via interconnection structure of the existing semiconductor structure.

[0005] Specifically, the first aspect of the embodiments of the present application provides a semiconductor structure, comprising:

[0006] a dielectric layer, wherein a via is formed in the dielectric layer;

[0007] a liner barrier layer formed on the sidewall of the via; wherein the liner barrier layer is an amorphous metal sulfide film, and the metal sulfide film comprises tantalum sulfide or titanium sulfide;

[0008] a metal interconnection layer filled in the via and covering the liner barrier layer.

[0009] The application adopts one such adhesion barrier layer to replace the conventional barrier layer + adhesion layer stacked structure, which makes the volume ratio of the metal interconnection material in the via interconnection structure larger, and the adhesion barrier layer does not exist at the bottom of the via of the via interconnection structure, which can further increase the volume ratio of the metal interconnection material and avoid the problem of larger resistance of the interconnection structure caused by the existence of the adhesion barrier layer at the bottom of the via.

[0010] In the embodiment of the application, the chemical formula of the tantalum sulfide is TaS x , the chemical formula of the titanium sulfide is TiS x , and each x is independently between 1.5 and 3.3.

[0011] In the embodiment of the application, the thickness of the adhesion barrier layer is less than or equal to 1.6 nm. The thickness of the adhesion barrier layer is extremely low, which can obviously improve the volume ratio of the copper interconnection line filled in the via subsequently, and at such a thin thickness, it can still effectively inhibit the diffusion of the metal copper and ensure better adhesion of the copper.

[0012] In the embodiment of the application, the thickness deviation of the adhesion barrier layer on any two of the upper, middle and lower parts of the via sidewall is not more than 10%. The adhesion barrier layer of the application is selectively deposited on the via sidewall, and has good thickness uniformity. Other prior arts generally perform additional etching with difficult-to-control precision to eliminate the barrier material at the bottom of the via, which usually damages the barrier material formed on the sidewall and causes poor thickness uniformity.

[0013] In the embodiment of the application, the adhesion barrier layer does not contain halogen. The adhesion barrier layer without halogen has good barrier and adhesion effects. Correspondingly, the raw material for forming the adhesion barrier layer does not contain halogen, which will not cause corrosion to the equipment during the formation process.

[0014] In the embodiment of the application, the adhesion barrier layer does not contain nitrogen and carbon elements. The purity of the metal sulfide in the adhesion barrier layer is extremely high, and the adhesion of the metal interconnection material is stronger.

[0015] In the embodiment of the application, the adhesion barrier layer is formed by an atomic layer deposition process assisted by a suppressor to form an amorphous metal sulfide film and then annealing. When the adhesion barrier layer is prepared by this method, it can be selectively grown in situ on the sidewall of the via, without the need to remove the metal sulfide formed at the bottom of the via by etching as in other prior arts.

[0016] In the embodiment of the application, the opening size of the via is not more than 25 nm. The selective deposition of the adhesion barrier layer on the sidewall of the via can still be realized in the via with a smaller opening size, and the thickness uniformity of the adhesion barrier layer on the sidewall is higher.

[0017] In some embodiments of the present application, a first trench is further formed in the dielectric layer, and the adhesion barrier layer is further located on the sidewalls and bottom of the first trench. The first trench is further filled with the metal interconnect layer, which covers the adhesion barrier layer in the first trench. Depositing the adhesion barrier layer in the trench of the dielectric layer also helps ensure a high volume ratio of the metal interconnect layer in the trench filling structure.

[0018] In the embodiment of the present application, the opening size of the first groove does not exceed 25 nm. In a groove with a smaller opening size, the adhesion barrier layer can still be deposited in the groove with high thickness uniformity.

[0019] In some embodiments of the present application, the semiconductor structure further includes a first dielectric layer located below the dielectric layer, wherein the first dielectric layer has a second trench extending therethrough, and the bottom opening of the second trench is partially sealed by a metal layer in a lower dielectric layer located below the first dielectric layer; wherein a second adhesion barrier layer is formed on the sidewalls and a portion of the bottom of the first trench, the second adhesion barrier layer is not formed on the metal layer, and another metal interconnection layer filling the second trench is formed on the second adhesion barrier layer; and the second adhesion barrier layer is an amorphous tantalum sulfide film or a titanium sulfide film.

[0020] When filling the second trench in the first dielectric layer below the dielectric layer, a second adhesion barrier layer is used instead of the existing TaN barrier layer and Ta adhesion layer. This ensures that the volume of the other metal interconnect layer M1 in the trench interconnect structure within the second trench is relatively high, thus ensuring a low resistance value for the overall trench interconnect structure. Furthermore, when the bottom of the second trench partially exposes the metal interconnect material below, the selective distribution of the second adhesion layer can also achieve a direct connection between M1 and the metal layer below it.

[0021] In the embodiment of the present application, the thickness deviation of the second adhesion barrier layer on any two of the upper, middle, and lower portions of the second trench sidewall does not exceed 10%. The second adhesion barrier layer is selectively deposited on the sidewalls and a portion of the bottom of the second trench, resulting in good thickness uniformity, particularly on the trench sidewalls. In contrast, other prior arts typically perform additional etching to remove barrier material from the trench bottom, which often damages the barrier material formed on the trench sidewalls, resulting in poor thickness uniformity.

[0022] In the embodiment of the present application, the material of the other metal interconnect layer and the metal layer is independently selected from one or more of W, Co, Cu, Ru, Mo, and Al. When the second adhesion barrier layer and the first adhesion barrier layer are formed using an inhibitor-assisted atomic layer deposition process, the inhibitor has good adsorption properties on the exposed metal material of such a material.

[0023] The second aspect of the embodiments of the present application provides a method for forming a semiconductor structure, comprising the following steps:

[0024] (1) providing a first dielectric layer, wherein a first metal interconnection layer is formed in the first dielectric layer;

[0025] forming a second dielectric layer on the first dielectric layer, and forming a via in the second dielectric layer, wherein the via exposes the first metal interconnection layer;

[0026] (2) depositing an amorphous metal sulfide film on the sidewall of the via by using an atomic layer deposition process, and then performing annealing treatment to obtain an adhesion barrier layer; wherein the metal sulfide film comprises tantalum sulfide or titanium sulfide; in each deposition cycle of the atomic layer deposition process, a suppressant is first introduced, and then a metal element precursor and a sulfur source are alternately exposed to the via;

[0027] (3) electroplating metal to fill the via with the adhesion barrier layer to form a second metal interconnection layer.

[0028] Before filling the metal interconnection material into the via in the second dielectric layer, the present application only forms an adhesion barrier layer to block the diffusion of the subsequently prepared metal interconnection material to the surrounding dielectric layer and to ensure that the adhesion between the metal interconnection layer and the metal interconnection material is high, which can replace the two-layer stacked structure of the TaN barrier layer and the Ta adhesion layer in the prior art, thereby reducing the preparation process of the back-end-of-line process of the semiconductor structure, shortening the process path, and increasing the volume ratio of the subsequently filled metal interconnection material in the via interconnection structure, thereby reducing the resistance of the via structure and reducing power consumption. Moreover, when forming the adhesion barrier layer, the present application uses the ALD process assisted by the suppressant to selectively deposit the crystalline metal sulfide film only on the sidewall of the via, which eliminates the problem of the resistance at the bottom of the via caused by the adhesion barrier layer at the bottom of the via, reduces the loss of power or signal in the via interconnection structure, and does not need to perform additional etching with difficult-to-control precision as in other prior arts to reduce the resistance of the via bottom filler.

[0029] In the embodiments of the present application, the suppressant comprises one or more of aniline, p-phenylenediamine, styrene, azobenzene, 1-methyl-2-pyrrolidone, 2-methylpyrrole, 1-(2-aminophenyl)pyrrole, acetylacetone, and propargylamine. Using these substances as suppressants can better adsorb on the surface of the metal material, thereby inhibiting the deposition of the sulfide film on the metal material exposed at the bottom of the via and better eliminating the resistance at the bottom of the via.

[0030] In the embodiments of the present application, the material of the first metal interconnection layer is selected from one or more of W, Co, Cu, Ru, Mo, and Al. The above-mentioned inhibitor has good adsorption on the exposed metal interconnection layer of such material.

[0031] In the embodiments of the present application, the deposition temperature of the metal sulfide film and the annealing temperature of the annealing treatment are both less than or equal to 400°C. When forming the adhesion barrier layer, the formed device structure can be prevented from being adversely affected.

[0032] In some embodiments of the present application, in step (1), the second dielectric layer further has a first trench formed therein; and in step (2), the metal sulfide film is formed on the sidewall of the via and the sidewall and bottom of the first trench at the same time. In this way, the selective deposition of the adhesion barrier layer on the sidewall of the via in the second dielectric layer and the deposition on the sidewall and bottom of the trench can be achieved at the same time, which can save the process flow of the back-end manufacturing of the semiconductor structure and also facilitate reducing the volume ratio of the metal interconnection material in the trench filler.

[0033] In some embodiments of the present application, the method for forming the first metal interconnection layer comprises:

[0034] providing a lower dielectric layer having a metal layer formed therein;

[0035] forming the first dielectric layer on the lower dielectric layer and etching the first dielectric layer to form a second trench; the bottom end opening of the second trench is partially sealed by the metal layer;

[0036] forming an amorphous metal sulfide film on the sidewall and bottom of the second trench by using an atomic layer deposition process and performing an annealing treatment to obtain a second adhesion barrier layer, wherein the metal sulfide film comprises a tantalum sulfide or a titanium sulfide; in each deposition cycle of the atomic layer deposition process, an inhibitor is first introduced, and then a metal element precursor and a sulfur source are alternately exposed to the second trench; the inhibitor is used to inhibit the deposition of the metal sulfide film on the exposed metal layer at the bottom of the second trench;

[0037] electroplating the first trench with the second adhesion barrier layer to form the first metal interconnection layer.

[0038] When part of the bottom of some trenches exposes the metal material thereunder, a second adhesion barrier layer can also be selectively deposited in situ on the sidewall and part of the bottom of such trenches by using a similar forming method as the first adhesion layer, so as to ensure the direct connection between the first metal interconnection layer filled in the trench and the metal layer thereunder, and reduce the RC delay and power consumption.

[0039] The third aspect of the embodiments of the present application provides a semiconductor device including the semiconductor structure of the first aspect of the embodiments of the present application or the semiconductor structure formed by the method of the second aspect of the embodiments of the present application. The semiconductor device using the semiconductor structure has better performance, lower power consumption, and the RC delay problem is effectively inhibited.

[0040] In the embodiments of the present application, the semiconductor device includes a power device, a radio frequency device, or an optoelectronic device. BRIEF DESCRIPTION OF DRAWINGS

[0041] Figure 1 A process diagram of forming a copper interconnection line in a prior semiconductor process is shown.

[0042] Figures 2 to 7 The structure diagram corresponding to each step in the method for forming the semiconductor structure of an embodiment of the present application is shown.

[0043] Figures 8a to 8e An intermediate process diagram of transforming the structure shown in Figure 3 to the structure shown in Figure 4 is shown.

[0044] Figure 9 A process flow diagram of preparing a metal sulfide film in the embodiments of the present application is shown.

[0045] Figure 10 The change of the volume ratio of the Cu interconnection line filled in the existing trench with the decrease of the trench line width is summarized.

[0046] Figure 11 The structure diagrams of the existing via interconnection structure (a) and the via interconnection structure (b) of the present application and their equivalent resistances when there is electron flow through the via are summarized.

[0047] Figures 12 to 14 A structure diagram of the first metal interconnection layer M1 in the structure shown in Figure 2 is shown.

[0048] Figure 15 Elemental analysis results of the tantalum sulfide film prepared by the atomic layer deposition process at different deposition temperatures in the embodiments of the present application are shown. (a) to (d) are high-resolution spectra of Ta, S, C, and N elements in the film at a deposition temperature of 150°C; (e) to (h) are high-resolution spectra of Ta, S, C, and N elements in the film at a deposition temperature of 250°C; (i) to (l) are high-resolution spectra of Ta, S, C, and N elements in the film at a deposition temperature of 300°C.

[0049] Figure 16 The TaS xDiffusion of thin film and 100 nm thick copper layer on 50 nm thick silicon oxide substrate (a) and copper diffusion rate graph (b).

[0050] Figure 17 Diffusion of Cu on different substrates under optical microscope is summarized. (a) Diffusion of 100 nm thick copper layer on 50 nm thick silicon oxide substrate; (b) Diffusion of 1.5 nm thick annealed TaS x Diffusion of thin film and 100 nm thick copper layer.

[0051] Figure 18 Diffusion of annealed TaS x Atomic force microscope (AFM) image (a) and step scan image (b) of thin film, and transmission electron microscope (TEM) image (c) of thin film using annealed TaS x Time-dependent breakdown test results (d) of devices with thin film or TaN thin film as barrier layer and devices without barrier layer.

[0052] Figure 19 The surface is sequentially deposited with 1.5 nm thick TaS x Process schematic of adhesion test of thin film, 100 nm thick copper film on Si wafer with SiO2 layer using 3M transparent adhesive tape.

[0053] Figure 20 Diffusion of TaS x Cross-sectional TEM image of thin film, wherein (b) is the framed TaS x Magnified view of thin film region.

[0054] Figure 21 The top view and structural schematic of (a) trench region and (f) via region in Damascene chip, and TaS x Cross-sectional annular bright field image (b) and corresponding energy spectrum mapping images of Ta element (c) and S element (d) of thin film, TaS x Cross-sectional scanning transmission electron microscope (STEM) image (e) of thin film, and TaS x Cross-sectional annular bright field image (g) and corresponding energy spectrum mapping images of Ta element (h) and S element (i) of thin film, TaS x STEM image (f) of thin film.

[0055] Explanation of main reference signs:

[0056] 300 - second dielectric layer, 310 - first sub-dielectric layer, 330 - second sub-dielectric layer, 301 - via, 302 - first trench, 303 - adhesion barrier layer, M2 - second metal interconnect layer; 200 - first dielectric layer, M1 - first metal interconnect layer, 200a - second trench, 201 - second adhesion barrier layer; 100 - lower dielectric layer, M0 - metal layer; 110 - first etch stop layer; 220 - second etch stop layer, 320 - third etch stop layer. DETAILED DESCRIPTION

[0057] The embodiments of the present application will be described below with reference to the accompanying drawings.

[0058] Figure 1 A process flow for forming a copper interconnect in a conventional semiconductor process is shown. Referring to FIG. 1, Figure 1 A substrate 10 is provided, and a metal structure 10a, which needs to be electrically connected to the copper interconnect to be formed, is also formed on the substrate 10. First, a dielectric layer 20 is formed on the substrate 10. Then, by a patterning process, the interconnect position is defined, and the dielectric layer 20 is etched to form a plurality of holes (trenches) in the dielectric layer 20. Figure 1 The holes 20a expose part of the top surface of the metal structure 10a. Then, a barrier layer 30 is formed on the sidewalls and bottom of each hole 20a. It can be understood that the dielectric layer 20 is also inevitably formed with the barrier layer 30 during the deposition process. Next, an adhesion layer 40 is formed on the sidewalls and bottom of each hole 20a. The barrier layer 30 inside the hole 20a and the barrier layer 30 outside the hole 20a are both formed with the adhesion layer 40. After that, copper is electro-deposited into the holes 20a by an electroplating process. The dielectric layer 20 is filled with copper, and the copper layer includes a hole-filling layer filled in the holes 20a and a surface deposition layer covering the adhesion layer 40 outside the holes 20a. Generally, before the electro-deposition of copper in step ⑤, a copper seed layer is usually formed on the inner wall (top and sidewall) of the hole to realize the electrical connection between the hole to be electroplated and the anode of the electroplating device during the electroplating of copper. Finally, after the electro-deposition of copper, the overfilling coating (e.g., the barrier layer 30, the adhesion layer 40, and the copper layer 50 outside the hole 20a) is removed by a chemical mechanical polishing (CMP) process. The bottom and sidewalls of the holes in the dielectric layer 20 are finally left with the barrier layer 30, the adhesion layer 40, and the copper layer 50 (the copper layer 50 is the copper interconnect), which together form a via interconnect structure.

[0059] With the improvement of the precision of integrated circuit process and the continuous reduction of the feature size of the device, the size of the interconnection structure is also getting smaller and smaller. The barrier layer 30 in the interconnection structure effectively prevents the diffusion of copper to the surrounding dielectric material, and the adhesion layer 40 effectively increases the adhesion of the copper interconnection line and the barrier layer. They must maintain a sufficient thickness. The common barrier layer is a tantalum nitride (TaN) layer, and the adhesion layer material is a tantalum (Ta) layer. The limit thickness of each is usually 1.5-2.5mm, and the total limit thickness of the two is usually 3-5mm. In the case of the continuous reduction of the size of the interconnection structure and the constant thickness of the barrier layer and the adhesion layer, the volume ratio of the barrier layer and the adhesion layer in the interconnection structure gradually increases, and the volume ratio of the copper interconnection line in the interconnection structure gradually decreases, which will increase the resistance of the interconnection structure.

[0060] In addition, it can be seen from Figure 1 When the electron flows through the above-mentioned via interconnection structure, it will pass through the barrier layer 30, the adhesion layer 40 and the copper interconnection line filled in the bottom of the via, which are equivalent to a series connection. The barrier layer 30 and the adhesion layer 40 usually do not have conductivity, which will make the bottom resistance of the interconnection structure large, resulting in a large resistance of the overall via interconnection structure, increasing the loss of the power supply and the signal in the interconnection structure, degrading the resistance-capacitance (RC) delay in the interconnection structure, and affecting the performance of the semiconductor structure.

[0061] Therefore, it is necessary to improve the preparation process of the copper interconnection line to increase the volume ratio of the copper interconnection line in the interconnection structure, reduce / eliminate the bottom resistance of the via, and make the resistance of the overall interconnection structure low. Therefore, the present application provides a forming method of a semiconductor structure and a semiconductor structure.

[0062] Specifically, the forming method of the semiconductor structure provided by the embodiment of the present application can include the following steps S101, S102 and S103. Wherein, Figures 2 to 7 The structure diagram corresponding to each step of the forming method of the semiconductor structure provided by an embodiment of the present application is shown.

[0063] Step S101, as shown in Figure 2 A first dielectric layer 200 is provided, and a first metal interconnection layer M1 is formed in the first dielectric layer 200; as shown in Figure 3 A second dielectric layer 300 is formed on the first dielectric layer 200; as shown in Figure 4 A via 301 is formed in the second dielectric layer 300, and the first metal interconnection layer M1 is exposed.

[0064] In the present application, the first dielectric layer 200 is used to realize isolation between adjacent first metal interconnection layers M1. The material of the first dielectric layer 200 can include one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), etc. Generally, the first dielectric layer 200 is carried on a substrate (not shown in the figure), and the material of the substrate can be silicon, silicon-on-insulator (SOI), germanium, silicon germanium, III-V compound (such as gallium nitride, gallium arsenide, etc.), or sapphire, etc. Figure 2 In some embodiments of the present application, as shown in the figure, the substrate and the first dielectric layer 200 are further provided with other coating layers.

[0065] In some embodiments of the present application, as shown in the figure, the substrate and the first dielectric layer 200 are further provided with other coating layers. Figure 2 In some embodiments of the present application, as shown in the figure, the substrate and the first dielectric layer 200 are further provided with other coating layers. Figure 2 In some embodiments of the present application, as shown in the figure, the upper side of the first metal interconnection layer M1 can further be provided with a capping layer 210. The capping layer 210 can be used to inhibit the diffusion of the metal of M1, for example, to inhibit the diffusion of the metal elements of M1 into the first dielectric layer 200 to cause the degradation of the dielectric performance.

[0066] Figure 3 In some embodiments of the present application, as shown in the figure, before the second dielectric layer 300 is formed on the first dielectric layer 200, a second etching stop layer 220 is first formed on the first dielectric layer 200. The second etching stop layer 220 is used to temporarily define the position of etching stop in the process of forming the via hole 301 (see the figure) in the second dielectric layer 300, so as to improve the consistency of etching. Figure 4 In some embodiments of the present application, as shown in the figure, the second dielectric layer 300 includes a first sub-dielectric layer 310 and a second sub-dielectric layer 330 formed above the first sub-dielectric layer 310. The second dielectric layer 300 further includes a third etching stop layer 320 between the first sub-dielectric layer 310 and the second sub-dielectric layer 330. The third etching stop layer 320 can be used to temporarily define the position of etching stop in the process of forming the upper half of the via hole 301, so as to improve the consistency of etching.

[0067] In some embodiments of the present application, as shown in the figure, the second dielectric layer 300 includes a first sub-dielectric layer 310 and a second sub-dielectric layer 330 formed above the first sub-dielectric layer 310. The second dielectric layer 300 further includes a third etching stop layer 320 between the first sub-dielectric layer 310 and the second sub-dielectric layer 330. The third etching stop layer 320 can be used to temporarily define the position of etching stop in the process of forming the upper half of the via hole 301, so as to improve the consistency of etching. Figure 3

[0068] ​The second etching stop layer 220 and the third etching stop layer 320 are made of materials having etching selectivity with the materials of the first sub dielectric layer 310 or the second sub dielectric layer 330. For example, the materials of the second etching stop layer 220 and the third etching stop layer 320 can be independently selected from aluminum oxide, aluminum nitride, or the like. The materials of the second etching stop layer 220 and the third etching stop layer 320 are independently selected from one or more of silicon oxide (SiOx), silicon nitride (SiNx), silicon oxynitride (SiON), or the like.

[0069] Figure 4 The first metal interconnection layer M1 is exposed from the via hole 301, and specifically, a part of the top surface of the first metal interconnection layer M1 is exposed from the via hole 301. The via hole 301 includes an upper interconnection groove 301a and a lower via hole 301b. The lower via hole 301b penetrates the first sub dielectric layer 310. The upper interconnection groove 301a is located in the second sub dielectric layer 330, and a part of the bottom of the upper interconnection groove 301a is in communication with the lower via hole 301b. It can be understood that, in the case where the M1 further includes the cover layer 210 and the second etching stop layer 220, the lower via hole 301b also penetrates the second etching stop layer 220 and the cover layer 210, so as to expose the top surface of the M1.

[0070] In some embodiments of the present application, referring to Figure 4 , the first trench 302 is further formed in the second dielectric layer 300. The third etching stop layer 320 can also temporarily define the etching stop position during the formation of the first trench 302. The first trench 302 penetrates the second sub dielectric layer 330 and the third etching stop layer 320, and the bottom end of the first trench 302 is sealed by the first sub dielectric layer 310. That is, the first trench 302 exposes a part of the top surface of the first sub dielectric layer 310.

[0071] The formation of the via hole 301 and the first trench 302 in the second dielectric layer 300 can be achieved by etching the second dielectric layer 300 with the aid of a patterned photoresist layer. Generally, a patterned photoresist layer is first formed on the second dielectric layer 300 (generally by going through the processes of spin-coating a photoresist material, exposure, development, etc.), so as to define the interconnection position, and then the second dielectric layer 300 is etched with the patterned photoresist layer as a mask.

[0072] In an embodiment of the present application, the intermediate process experienced by the structure shown in Figure 3 changing into the structure shown in Figure 4 may be as shown in Figures 8a to 8e . Specifically, as shown in Figure 8a , a first photoresist film 400 is first formed on the second sub dielectric layer 330, and then the first photoresist film 400 is exposed by using a mask plate having a predetermined pattern, and a patterned first photoresist layer 400' is obtained by development (as shown in Figure 8bThe first photoresist layer 400' is patterned to define the positions of the via 301 (more precisely, the upper interconnection trench 301a), and the first trench 302. Then, the second dielectric layer 330 and the third etching stop layer 320 are etched to form the upper interconnection trench 301a and the first trench 302, with the patterned first photoresist layer 400' as a mask (as shown in FIG. 4C). Figure 8c Then, a second photoresist layer 500 is coated on the structure shown in FIG. 4C, and the second photoresist layer 500 also fills the upper interconnection trench 301a and the first trench 302 (as shown in FIG. 4D). Figure 8c After selective exposure and development, the patterned second photoresist layer 500' is obtained (as shown in FIG. 4E), which defines the positions of the via 301b to be formed, and protects the first trench 302 from being damaged in the process of etching the first dielectric layer 310. Then, the first dielectric layer 310 and the second etching stop layer 220 are etched to form the via 301b, with the patterned second photoresist layer 500' as a mask. Finally, the patterned second photoresist layer 500' is ashed to obtain the structure shown in FIG. 4F. Figure 8d Figure 8e Figure 4

[0073] In step S102, an amorphous metal sulfide film is deposited on the sidewall of the via 301 by an atomic layer deposition (ALD) process, and then annealed to obtain the adhesion barrier layer 303 (as shown in FIG. 5B) ; wherein the metal sulfide film comprises a tantalum sulfide or a titanium sulfide; in each deposition cycle of the atomic layer deposition process, a suppressant is first introduced, and then a metal element precursor and a sulfur source are alternately exposed to the via. Figure 5

[0074] ​​​​In the present application, before the via hole 301 is filled with electroplated metal such as copper, only one layer of stable amorphous metal sulfide is formed as the adhesion barrier layer 303 to simultaneously achieve the diffusion barrier of copper plating to the surrounding medium layer and ensure the adhesion between the copper plating layer, which can replace the two-layer laminated structure of the TaN barrier layer and the Ta adhesion layer, thereby reducing the preparation process of the semiconductor structure back-end process and shortening the process path. Moreover, the thickness of the adhesion barrier layer 303 is much lower than that of the two-layer laminated structure of the TaN barrier layer and the Ta adhesion layer, thereby reducing the volume ratio of the adhesion barrier layer in the via hole interconnection structure and increasing the volume ratio of the metal interconnection layer in the via hole interconnection structure. In particular, the tantalum sulfide (TaSx) or titanium sulfide (TiSx) film has the characteristics of two-dimensional material, and its barrier effect on copper metal is better than that of traditional bulk barrier materials (such as TaN). When the thickness is thin, it can still effectively play the above-mentioned role of inhibiting copper diffusion, and the tantalum sulfide or titanium sulfide film is amorphous rather than polycrystalline, which has a better barrier diffusion effect on copper metal. Therefore, the use of amorphous metal sulfide film as an adhesion barrier layer can effectively provide the volume ratio of the subsequent electrodeposited copper interconnection layer in the via hole interconnection structure, thereby reducing the resistance of the via hole interconnection structure and reducing power consumption.

[0075] More importantly, when the above-mentioned metal sulfide film is deposited by ALD in the present application, by introducing an inhibitor, the film can be selectively deposited only on the sidewall of the via hole without being deposited on the bottom of the via hole, which can avoid the problem of the existence of the adhesion barrier layer at the bottom of the via hole causing the resistance of the via hole bottom to be large, thereby significantly reducing the loss of power or signal in the via hole interconnection structure. There is no need to etch the barrier layer and the adhesion layer deposited at the bottom of the via hole as in other prior art to reduce the resistance of the via hole bottom filler. Moreover, the precision of etching the coating at the bottom of the via hole is difficult to control, and the preparation process of the semiconductor structure back-end process is increased. In addition, the metal sulfide film prepared by the improved ALD process of the present application has good step coverage, uniformity and conformality, which can better meet the continuous development of advanced process technology.

[0076] ALD is a method that can deposit substances on the surface of a substrate in the form of a monatomic film layer by layer. ALD is a technology that forms a deposition film by alternately introducing different gas precursors into a deposition chamber and chemically adsorbing and reacting on a molecular layer of the substrate to be deposited. Figure 9 A process flow chart for preparing a metal sulfide film according to an embodiment of the present application is shown. Referring to FIG. 1, the process flow chart comprises the following steps: Figure 9In one cycle of the ALD process, the inhibitor is first introduced to adsorb on the surface of the metal material, thereby inhibiting the subsequent deposition of the metal sulfide film on the adsorbed area. After the inert purge gas is used to remove the inhibitor that is not adsorbed on the metal material, the gaseous metal element precursor is introduced to adsorb on the surface of the substrate to be deposited, and then the purge gas is used to remove the excess metal element precursor that is not adsorbed on the surface of the substrate. Then, the gaseous sulfur source (such as H2S) is introduced into the deposition chamber, and the metal element precursor adsorbed on the surface of the substrate reacts with the sulfur source diffused to the surface of the substrate to form a monatomic layer of metal sulfide. Finally, the inert purge gas is used to remove the reaction by-products and excess sulfur source on the surface of the substrate. Thus, one deposition cycle is completed. By repeating several deposition cycles, a metal sulfide film with a desired thickness is formed on the predetermined area of the substrate surface.

[0077] The inhibitor can be introduced together with an inert gas as a carrier. The metal element precursor can be introduced together with an inert gas as a carrier. In some embodiments of the present application, when the gaseous sulfur source is introduced, the radio frequency source can also be turned on to convert the gaseous sulfur source into plasma by discharge. In this case, the ALD process can be referred to as plasma-enhanced atomic layer deposition (PEALD). The plasma helps to improve the rate and accuracy of the deposition reaction and inhibit the formation of impurities.

[0078] Since Figure 5 The bottom of the via hole 301 exposes part of the top surface of the first metal interconnection layer M1 in the lower layer, so the inhibitor is adsorbed on the part of the top surface of M1 and no metal sulfide film is deposited in this area, and only the metal sulfide film is formed on the sidewall of the via hole 301. Since the sidewall and the bottom of the first trench 302 are not exposed to the metal material, the sidewall and the bottom of the first trench 302 are deposited with the metal sulfide film.

[0079] In step S102, while the metal sulfide film is deposited on the sidewall of the via hole 301, the amorphous metal sulfide film is simultaneously formed on the sidewall and the bottom of the first trench 302, and then the adhesion barrier layer 303 is formed after annealing. That is, the selective deposition of the adhesion barrier layer in the via hole 301 and the deposition in the first trench 302 can be simultaneously achieved. In this way, the process flow of the back-end-of-line of the semiconductor structure can be saved, and there is no need to etch the bottom of the via hole in which the adhesion barrier layer is deposited, as required by other prior art.

[0080] In the embodiments of the present application, the opening size of the via hole 301 is not more than 25 nm. Specifically, the maximum opening size of the via hole 301 is not more than 25 nm, and the minimum opening size of the via hole 301 is not less than 5 nm. Figure 4In some embodiments, the first trench 302 has an opening size of no more than 25 nm. Specifically, the maximum opening size of the via 301 is no more than 25 nm. In this case, the opening size of the trench is small, and is particularly suitable for the use of the inhibitor-assisted ALD process described above to deposit an adhesion barrier layer in the trench with uniform thickness and good conformality.

[0081] In some embodiments, the first trench 302 has an opening size of no more than 25 nm. Specifically, the maximum opening size of the via 301 is no more than 25 nm. In this case, the opening size of the trench is small, and is particularly suitable for the use of the inhibitor-assisted ALD process described above to deposit an adhesion barrier layer in the trench with uniform thickness and good conformality.

[0082] In some embodiments, the inhibitor includes one or more of aniline, p-phenylenediamine, styrene, azobenzene, 1-methyl-2-pyrrolidone, 2-methylpyrrole, 1-(2-aminophenyl)pyrrole, acetylacetone, and propargylamine. These inhibitors have good adsorption to metal materials.

[0083] In some embodiments, the material of the first metal interconnection layer M1 includes one or more of copper (Cu), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), and aluminum (Al). Specifically, M1 can be a metal element, an alloy of two or more metal elements, a stacked structure of metal elements, or a stacked structure of a metal element and an alloy, etc. The above inhibitors have good adsorption to such materials of M1, and thus will not form an adhesion barrier layer 303 with poor conductivity on the exposed M1. In some embodiments, the material of the first metal interconnection layer M1 is copper. Copper has a low resistivity, which is beneficial to reducing RC signal delay and power consumption.

[0084] In some embodiments, the gaseous metal element precursor is a tantalum organic precursor or a titanium organic precursor. An exemplary tantalum organic precursor can be tert-butylimidotri(diethylamino) tantalum (TBTDET for short). An exemplary titanium organic precursor can be tetrakis(dimethylamino) titanium (TDMAT for short). The structural formulas of TBTDET and TDMAT are as follows:

[0085]

[0086] In some embodiments, the gaseous metal element precursor does not contain halogen. This can effectively avoid damage to the deposition chamber and valves of the deposition equipment by the precursor.

[0087] In some embodiments, the chemical formula of the metal sulfide film formed by the ALD process includes MS x, M represents a metal element, M is Ta or Ti, and x is between 1.5 and 3.3. After the amorphous metal sulfide film is formed, annealing treatment is performed to make the sulfur element in the film more stable, avoiding the influence of free sulfur element on the stability of the subsequently formed metal interconnection layer. The adhesion barrier layer 303 is an amorphous metal sulfide film after annealing treatment, and its chemical formula can also be represented as MS x , and wherein the sulfur element is stable, and the molar ratio of sulfur to M element hardly changes with the placement time of the adhesion barrier layer 303.

[0088] In the embodiments of the present application, the deposition temperature of the metal sulfide film and the annealing temperature of the annealing treatment are each less than or equal to 400°C. In this way, adverse effects on the already formed device structure can be avoided, for example, copper melting of the first metal interconnection layer M1. Exemplarily, the deposition temperature of the metal sulfide film can be specifically 100°C, 120°C, 150°C, 180°C, 200°C, 220°C, 250°C, 280°C, 300°C, or 350°C, etc. In some embodiments, the deposition temperature of the metal sulfide film is in the range of 120°C-300°C. The annealing temperature can be in the range of 200°C-400°C to effectively increase the binding between the tantalum or titanium element and the sulfur element while avoiding adverse effects on the already formed device structure. Exemplary annealing temperatures can be 390°C, 380°C, 360°C, 350°C, 320°C, 300°C, 280°C, 250°C, or 200°C, etc. The time of the annealing treatment can be in the range of 10 min-60 min, for example, specifically 15 min, 20 min, 30 min, 40 min, 45 min, or 50 min, etc. In addition, the annealing treatment can be performed in an inert or reducing atmosphere. For example, the annealing treatment can be performed in an argon (Ar) and / or hydrogen (H2) atmosphere.

[0089] In the embodiments of the present application, the adhesion barrier layer 303 is an amorphous metal sulfide film, which does not contain halogen. The film has a good effect of blocking copper metal diffusion, and will not cause corrosion to the deposition equipment during its preparation process. Further, the adhesion barrier layer 303 also does not contain carbon and nitrogen elements. The purity of the metal sulfide in the adhesion barrier layer is extremely high, and it has strong adhesion to metal interconnection materials such as copper.

[0090] In some embodiments, the adhesion barrier layer 303 has a thickness of 0.7 nm to 1.6 nm. Such a thickness is much lower than the thickness of 3-5 nm of the TaN-Ta layer stack in the prior art, and can significantly increase the volume ratio of the copper interconnect line filled in the via hole. In addition, the adhesion barrier layer 303 with such a thin thickness can effectively inhibit the diffusion of copper and promote the adhesion of copper in the dielectric material. For example, the adhesion barrier layer 303 has a thickness of 0.8 nm, 1.0 nm, 1.2 nm, 1.4 nm, 1.5 nm, or 1.6 nm.

[0091] In some embodiments, the adhesion barrier layer 303 formed on any two of the upper, middle and lower portions of the sidewall of the via hole 301 has a thickness deviation of less than or equal to 10%. This indicates that the adhesion barrier layer formed by the method described above has high uniformity in thickness on any region of the sidewall of the via hole. However, when the adhesion barrier layer deposited on the bottom of the via hole is etched in the prior art, the adhesion barrier layer on the sidewall is easily damaged, resulting in uneven thickness. For example, if the thickness of the adhesion barrier layer on one portion (e.g., the upper portion) of the sidewall of the via hole is denoted as d1, and the thickness of the adhesion barrier layer on another portion (e.g., the lower portion) of the sidewall of the via hole is denoted as d2, the thickness deviation k = |d1-d2| / d1 or |d1-d2| / d2. In some embodiments, k≤10%. Further, k≤8%, or k≤7%, or k≤5%, k≤2%, or even k=0. In addition, the upper, middle and lower portions of the sidewall of the via hole can be evenly divided from top to bottom according to the surface area of the sidewall of the via hole, or can be unevenly divided. In some embodiments, the adhesion barrier layer 303 formed on any two of the upper, middle and lower portions of the sidewall of the via hole 301 has a thickness deviation of less than or equal to 10%.

[0092] In some embodiments, the adhesion barrier layer 303 formed on any two of the upper, middle and lower portions of the sidewall of the via hole 301 has a thickness deviation of less than or equal to 10%. This indicates that the adhesion barrier layer formed by the method described above has high uniformity in thickness on any region of the sidewall of the via hole. However, when the adhesion barrier layer deposited on the bottom of the via hole is etched in the prior art, the adhesion barrier layer on the sidewall is easily damaged, resulting in uneven thickness. For example, if the thickness of the adhesion barrier layer on one portion (e.g., the upper portion) of the sidewall of the via hole is denoted as d1, and the thickness of the adhesion barrier layer on another portion (e.g., the lower portion) of the sidewall of the via hole is denoted as d2, the thickness deviation k = |d1-d2| / d1 or |d1-d2| / d2. In some embodiments, k≤10%. Further, k≤8%, or k≤7%, or k≤5%, k≤2%, or even k=0. In addition, the upper, middle and lower portions of the sidewall of the via hole can be evenly divided from top to bottom according to the surface area of the sidewall of the via hole, or can be unevenly divided. In some embodiments, the adhesion barrier layer 303 formed on any two of the upper, middle and lower portions of the sidewall of the via hole 301 has a thickness deviation of less than or equal to 10%.

[0093] Similarly, in the present application, the thickness of the adhesion barrier layer 303 formed on the sidewall and bottom of the first trench 302 can also be less than or equal to 1.6 nm, further within the range of 0.7 nm to 1.6 nm. Similarly, the thickness of the adhesion barrier layer 303 on any two of the upper, middle and lower portions of the sidewall of the first trench 302 can not deviate by more than 10%, further not more than 8% or 7%, etc.

[0094] In step S103, the via 301 with the adhesion barrier layer 303 is subjected to electroplating metal filling to form a second metal interconnection layer M2 (see Figure 7 ). In this process, the second metal interconnection layer M2 can also be formed in the first trench 302 with the adhesion barrier layer 303 at the same time.

[0095] In some embodiments of the present application, before the electroplating metal in the via 301 and the first trench 302, a metal seed layer (not shown in the figure) such as a copper seed layer is also formed in the via 301 and the first trench 302. The metal seed layer is mainly used to realize the electrical connection between the via or trench to be electroplated and the anode of the electroplating device during electroplating, so as to smoothly form the electroplated metal layer.

[0096] Similar to the material of M1 described above, the material of the second metal interconnection layer M2 includes one or more of copper (Cu), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), aluminum (Al), etc. In some embodiments, the electroplated metal is specifically electroplated copper, and the corresponding M2 is specifically a copper interconnection layer, or a copper interconnection line.

[0097] The step of forming the second metal interconnection layer M2 can include: electroplating metal filling to the via 301 with the adhesion barrier layer 303 and the first trench 302 to form an electroplated metal layer 304, which includes a hole filling layer (i.e., the second metal interconnection layer M2) filled in the via 301 and the first trench 302, and a surface deposition layer 3041 deposited on the second dielectric layer 300 (as shown in Figure 6 ); and then, removing the surface deposition layer 3041 on the second dielectric layer 300, leaving the M2 filled in the via 301 and the first trench 302 (as shown in Figure 7 ).

[0098] The surface deposition layer 3041 on the second dielectric layer 300 is removed by a planarization process. An exemplary planarization process can be chemical mechanical polishing (CMP). In addition, as described above when forming the adhesion barrier layer in the via 301 or the first trench 302, if the adhesion barrier layer is also formed on the second dielectric layer 300, it can also be removed by the CMP method. In this case, Figure 7In the via interconnect structure, the via interconnect structure filled in the via hole 301 includes the adhesion barrier layer 303 located on the side wall of the via hole and the second metal interconnect layer M2 located on the adhesion barrier layer 303 and covering the bottom of the via hole. In the trench interconnect structure, the trench interconnect structure filled in the first trench 302 includes the adhesion barrier layer 303 located on the side wall and the bottom of the trench and the second metal interconnect layer M2 located on the adhesion barrier layer 303.

[0099] The foregoing Figure 1 In the interconnect structure, the limit thickness of the TaN barrier layer and the Ta adhesion layer is in the range of 1.5 nm-2.5 nm, and the limit thickness of the two is in the range of 3 nm-5 nm. Taking the trench with a depth-width (AR) ratio of 2:1 as an example (see Table 1 below and Figure 10 ), if the total limit thickness of the barrier layer and the adhesion layer filled in the side wall and the bottom of the trench is 3 nm, the volume ratio of the Cu interconnect line in the trench with a line width of 18 nm is about 40.7%, the volume ratio of the Cu interconnect line in the trench with a line width of 15 nm is about 32.4%, and the volume ratio of the Cu interconnect line in the trench with a line width of 12 nm is only about 21.8%. If the total thickness of the barrier layer and the adhesion layer can be changed to 1 nm, then the volume ratio of the Cu interconnect line in the trench with a line width of 18 nm is about 76.8%, the volume ratio of the Cu interconnect line in the trench with a line width of 15 nm is about 72.6%, and the volume ratio of the Cu interconnect line in the trench with a line width of 12 nm is about 66.6%. It can be seen that the volume ratio of the Cu interconnect line in the interconnect structure is greatly improved with the decrease of the total thickness of the barrier layer and the adhesion layer. However, the thickness of the TaN barrier layer and the Ta adhesion layer has been reduced to the limit in order to effectively play the role of diffusion barrier and effectively increase the adhesion.

[0100] Table 1 Volume ratio of copper interconnect line with different line widths in interconnect structure changes with total thickness of barrier layer-adhesion layer

[0101]

[0102] And the present application Figure 7 In the present application, one layer of adhesion barrier layer 303 is used to replace the existing TaN barrier layer+Ta diffusion layer stacked structure, and the thickness is about 0.7-1.6 nm, which is extremely thin compared with the limit thickness of 3-5 nm of the existing TaN-Ta stacked structure. Therefore, the adhesion barrier layer of the present application can effectively improve the volume ratio of the copper interconnect line in the via interconnect structure and the trench interconnect structure, and reduce the resistance of the interconnect structure.

[0103] In addition, Figure 11 The structure diagrams of the existing via interconnect structure (a) and the via interconnect structure (b) of the present application and their equivalent resistance when there is electron flow through the via are summarized. See Figure 11The via interconnection structure formed in the via hole is used for metal interconnection between the upper layer and the lower layer. When the electron flows through the existing via interconnection structure, the electron passes through the adhesion layer and the barrier layer in turn in addition to the copper interconnection line in the current layer before reaching the copper interconnection line in the lower layer. The adhesion layer and the barrier layer at the bottom of the via hole are in series, and the resistivity of the two is hundreds of times of that of copper metal, which greatly increases the bottom resistance of the interconnection structure.

[0104] The bottom of the via interconnection structure of the present application does not have the adhesion barrier layer 303, and the volume ratio of the copper interconnection line can be further increased. When the electron flows through the bottom of the via interconnection structure, it does not pass through any non-conductive material (such as the adhesion barrier layer 303), and the copper interconnection lines in the upper layer and the lower layer are directly connected, which can avoid the large bottom resistance of TaS x or TiS x thin film on the resistance of the via interconnection structure. Therefore, the via interconnection structure of the present application can reduce the RC signal delay, improve the processing speed of the semiconductor structure, and reduce the power consumption of the semiconductor structure.

[0105] In addition, in the present application Figure 7 The adhesion barrier layer 303 exists on the sidewall and the bottom of the first trench 302, but since the trench interconnection structure formed in the trench is used for interconnection between metal materials in the same layer, when the electron flows through the trench interconnection structure, the resistances of the copper interconnection line and the adhesion barrier layer can be equivalent to a parallel relationship. Therefore, the resistivity of the adhesion barrier layer 303 with poor conductivity has little effect on the total resistance of the trench interconnection structure, and the total resistance value is closer to the resistance value of the copper interconnection line itself.

[0106] It should be noted that subsequent Figure 7 The structure shown in the present application can be continued to form other interconnection structures on the second metal interconnection layer M2. The other interconnection structures can be formed according to the method for forming the semiconductor structure described in the foregoing of the present application. For example, an etching stop layer and a dielectric layer are first formed, and then the dielectric layer is etched to form the required via hole and / or trench. Then, the adhesion barrier layer is deposited on the sidewall of the via hole and the bottom and sidewall of the trench by using the ALD process assisted by the inhibitor provided in the foregoing of the present application. Finally, the metal material filling the via hole or the trench is formed on the diffusion barrier layer. Similarly, the volume ratio of the metal interconnection material in the other interconnection structure is also large, the resistance is small, and the adhesion barrier layer does not exist at the bottom of the via interconnection structure filled in the via hole, which will not cause the bottom resistance of the via interconnection structure to be large, thereby reducing the power consumption.

[0107] In addition, in the structure shown in the foregoing Figure 2 The trench filled with the first metal interconnection layer M1 in the first dielectric layer 200 is also filled with a second adhesion barrier layer 201, and the M1 covers the second adhesion barrier layer 201. Among them, the second adhesion barrier layer 201 is formed Figure 2The first metal interconnection layer M1 in the structure shown can also be formed using the method for forming the second metal interconnection layer M2. Figures 12 to 14 Shown Figure 2 Schematic diagram of the structure corresponding to each step in a method for forming the first metal interconnection layer M1 in the structure shown. Specifically, the method for forming the first metal interconnection layer M1 includes:

[0108] S01, see Figure 12 , providing a lower dielectric layer 100, wherein a metal layer M0 is formed in the lower dielectric layer 100; forming a first dielectric layer 200 on the lower dielectric layer 100;

[0109] S02, such as Figure 13 As shown, the first dielectric layer 200 is etched to form a second trench 200a; wherein the bottom opening of the second trench 200a is partially sealed by the metal layer M0;

[0110] S03, such as Figure 14 As shown, an amorphous metal sulfide film is formed on the sidewalls and bottom of the second trench 200a using an atomic layer deposition process, and then annealed to obtain a second adhesion barrier layer 201; wherein the metal sulfide film includes tantalum sulfide or titanium sulfide; in each deposition cycle of the atomic layer deposition process, an inhibitor is first introduced, and then a metal element precursor and a sulfur source are alternately exposed to the second trench 200a; the inhibitor is used to inhibit the deposition of the metal sulfide film on the metal layer M0 exposed at the bottom of the second trench 200a;

[0111] S04, yes Figure 14 The second trench 200a with the second adhesion barrier layer 201 is filled with metal by electroplating to form the above-mentioned first metal interconnection layer M1.

[0112] Similar to the above, in step S01, before forming the first dielectric layer 200 on the lower dielectric layer 100, a first etch stop layer 110 is generally formed on the lower dielectric layer 100. The first etch stop layer 110 is used to temporarily define the etching stop position during the formation of the second trench 200a to reduce damage to the metal layer M0 located thereunder.

[0113] In step S02, the second trench 200a penetrates the first dielectric layer 200, exposing a portion of the top surface of the underlying dielectric layer 100 and the metal layer M0. When etching the first dielectric layer 200, the first etch-stop layer 110 is also etched. The second trench 200a also penetrates the first etch-stop layer 110, so that the bottom opening of the second trench 200a is partially sealed by the metal layer M0. Figure 13In the embodiment, the top surface of the lower dielectric layer 100 not covered by the first dielectric layer 200 or the first etching stop layer 110 serves as a sealing surface of the bottom end opening of the second trench 200a. Since the metal layer M0 fills the via hole in the lower dielectric layer 100, the metal layer M0 also partially seals the bottom end opening of the second trench 200a accordingly, and the bottom of the second trench 200a exposes the metal layer M0. It can be understood that the size of the bottom end opening of the second trench 200a is smaller than the cross-sectional width of the lower dielectric layer 100 and greater than the sum of the cross-sectional widths of the adjacent plurality of metal layers M0.

[0114] The material of the metal layer M0 can include one or more of copper (Cu), tungsten (W), cobalt (Co), molybdenum (Mo), ruthenium (Ru), and aluminum (Al). In some embodiments, the material of the metal layer M0 is tungsten. The material of the lower dielectric layer 100 can be selected from the same range as the material of the first dielectric layer 200. The lower dielectric layer 100 can be a silicon oxide layer, a silicon nitride layer, or a silicon oxynitride layer. In addition, a device structure is usually formed below the lower dielectric layer 100, and the metal layer M0 is electrically connected to the device structure, so that the device structure can be powered when the device is working. For example, the device structure can include a gate electrode formed on a substrate, a source electrode and a drain electrode located on both sides of the gate electrode and isolated from each other.

[0115] The second adhesion barrier layer 201 is formed on the sidewall and part of the bottom of the second trench 200a in step S03 in a manner similar to the formation of the adhesion barrier layer 303 in the via hole 301 in step S102 of the foregoing embodiment, and the formation manner and structural characteristics of the second adhesion barrier layer 201 are not described herein. For example, the thickness of the second adhesion barrier layer 201 on any two places on the sidewall of the second trench 200a deviates by no more than 10%. Specifically, the thickness of the second adhesion barrier layer 201 on any two of the upper, middle, and lower portions of the sidewall of the second trench 200a deviates by no more than 10%. The absolute value of the difference between the thicknesses of the second adhesion barrier layer 201 on any two of the upper, middle, and lower portions of the sidewall of the second trench 200a is less than or equal to 0.15 nm.

[0116] Since Figure 12The top surface of the metal layer M0 under the partial bottom of the second trench 200a is exposed, so in the deposition of the metal sulfide film by the inhibitor-assisted ALD process, the inhibitor will only be adsorbed on the top surface of the metal layer M0 to inhibit the deposition of the amorphous metal sulfide film in this area, and the second adhesion barrier layer 201 is not formed on the bottom of the second trench corresponding to the metal layer M0. Therefore, the second adhesion barrier layer 201 is formed on the sidewall of the second trench 200a and the bottom of the second trench not corresponding to the metal layer M0. Accordingly, after the step S04, the volume fraction of M1 in the overall interconnection structure in the second trench 200a can also be increased.

[0117] Similarly, the top opening size of the second trench 200a is also less than or equal to 25 nm. It is particularly suitable to use the inhibitor-assisted ALD process provided in the present application to deposit and form the second adhesion barrier layer 201 in the second trench 200a with uniform thickness and good conformality.

[0118] In some embodiments of the present application, after the above step S04, the following step S05 is further included. S05: forming a cover layer 210 on the first metal interconnection layer M1 to obtain a semiconductor structure as shown in Figure 2 The cover layer 210 can be used to inhibit the outward diffusion of the metal elements of M1 as described above.

[0119] The present application also provides a semiconductor structure. Referring to Figure 7 , the semiconductor structure 1000 includes a second dielectric layer 300, an adhesion barrier layer 303, and a second metal interconnection layer M2; wherein the second dielectric layer 300 forms a via hole 301 therein, the sidewall of the via hole 301 forms the adhesion barrier layer 303; and the second metal interconnection layer M2 fills the via hole 301 and covers the adhesion barrier layer 303. The adhesion barrier layer 303 is an amorphous metal sulfide film, specifically a tantalum sulfide (TaS x ) film or a titanium sulfide (TiS x ) film, and each x is independently between 1.5 and 3.3. The adhesion barrier layer 303 is obtained by forming a metal sulfide film by an inhibitor-assisted ALD process and then annealing, which can realize selective deposition on the sidewall of the via hole.

[0120] As described above, in the via interconnection structure formed in the via 301, there is only one adhesion barrier layer 303 made of amorphous metal sulfide film in addition to the metal interconnection material, which is different from the conventional double-layered barrier / adhesion layer structure. This makes the volume ratio of the metal interconnection material in the via interconnection structure larger, and the resistance of the interconnection structure smaller. In addition, there is no adhesion barrier layer at the bottom of the via in the via interconnection structure, which can further increase the volume ratio of the metal interconnection material and avoid the problem of larger resistance caused by the adhesion barrier layer at the bottom of the via. Therefore, the semiconductor structure 1000 with the via interconnection structure can reduce power consumption, reduce RC signal delay, and improve the performance of the semiconductor structure. For specific structural characteristics of the adhesion barrier layer 303, please refer to the description above.

[0121] Further, the first trench 302 is also formed in the second dielectric layer 300, and the sidewall and bottom of the first trench 302 are also formed with the adhesion barrier layer 303. The second metal interconnection layer M2 is also filled in the first trench 302, and the M2 covers the adhesion barrier layer 303. The trench interconnection structure formed in the first trench 302 has only one adhesion barrier layer 303 made of amorphous metal sulfide film in addition to the metal interconnection material, which is also conducive to ensuring that the volume ratio of the metal interconnection material in the trench interconnection structure is large and the total resistance of the interconnection structure is small.

[0122] In some embodiments of the present application, the semiconductor structure 1000 further includes a first dielectric layer 200 located below the second dielectric layer 300, wherein the first dielectric layer 200 has a second trench 200a penetrating therethrough, and the bottom end opening of the second trench 200a is partially sealed by the metal layer M0 in the lower dielectric layer 100 located below the first dielectric layer 200. The first metal interconnection layer M1 is filled in the second trench 200a. Further, the sidewall and part of the bottom of the second trench 200a are also formed with a second adhesion barrier layer 201, and the second adhesion barrier layer 201 is not formed on the metal layer M0, and the first metal interconnection layer M1 covers the second adhesion barrier layer 201.

[0123] The composition and structural characteristics of the second adhesion barrier layer 201 can be referred to the adhesion barrier layer 303 described above. By using one second adhesion barrier layer 201 to replace the existing TaN barrier layer and Ta adhesion layer, the volume ratio of M1 in the trench interconnection structure located in the second trench 200a is also large, which is conducive to ensuring that the overall resistance of the trench interconnection structure is low.

[0124] In some cases, the second dielectric layer 300 further forms a second etching stop layer 220 between the second dielectric layer 300 and the first dielectric layer 200. The first dielectric layer 200 further forms a first etching stop layer 110 between the first dielectric layer 200 and the lower dielectric layer 100. The first metal interconnection layer M1 further forms a cover layer 210 selectively exposing the M1. For the layer structures of the numbers 110, 220, 210, and the specific structure of the second dielectric layer 300, refer to the foregoing description.

[0125] In addition, in other embodiments of the present application, the semiconductor structure 1000 can further include one or more other interconnection structures (not shown in the figure) which can be located on the second metal interconnection layer M2. Among them, the other interconnection structure is filled in the via and / or the trench in the corresponding other dielectric layer. The other interconnection structure includes an adhesion barrier layer filled in the via or the trench, and an other metal interconnection layer covering the adhesion barrier layer. When the other interconnection structure is located in the via, only the sidewall of the via forms the adhesion barrier layer of the present application; when the other interconnection structure is located in the trench, the sidewall and the bottom of the trench can form the adhesion barrier layer of the present application.

[0126] The embodiments of the present application further provide a semiconductor device including the semiconductor structure of the above-mentioned embodiments of the present application, or the semiconductor structure obtained by the formation method of the above-mentioned semiconductor structure of the embodiments of the present application. The semiconductor device uses the semiconductor structure provided by the embodiments of the present application, and the performance of the device can be improved.

[0127] In the present application, the semiconductor device can be various electronic devices that use the special electrical characteristics of semiconductor materials to complete specific functions, and can be used to generate, control, receive, transform, amplify signals and perform energy conversion, etc. The specific structure of the semiconductor device can be designed according to the needs of the actual application scene, and the present application does not make specific limitations on its structure.

[0128] In the embodiments of the present application, the semiconductor device can include, but is not limited to, a power device, a radio frequency device, or an optoelectronic device, etc. The power device can be a diode, a field effect transistor, or an insulated gate bipolar transistor (IGBT). The diode can be, for example, but is not limited to, a Schottky barrier diode (SBD), and the exemplary field effect transistor can be, for example, but is not limited to, a metal-oxide-semiconductor field-effect transistor (MOSFET), a junction field-effect transistor (JFET), etc. The radio frequency device can be a radio frequency diode, a radio frequency field effect transistor, a radio frequency chip, a radio frequency switch, a radio frequency power amplifier, a radio frequency filter, etc. The optoelectronic device can be an electroluminescent device, such as a light emitting diode (LED) or a laser diode (LD).

[0129] The electronic device can be various consumer electronics, such as a mobile phone, a tablet computer, a notebook computer, a mobile power supply, a portable computer, and other wearable or movable electronic devices, a television, a video player, a video recorder, a camcorder, a radio, a recorder, a combination sound system, a record player, a laser record player, a home office device, a home electronic health care device, a vehicle such as a car, or an energy storage device, etc.

[0130] The electronic device can be various consumer electronics, such as a mobile phone, a tablet computer, a notebook computer, a mobile power supply, a portable computer, and other wearable or movable electronic devices, a television, a video player, a video recorder, a camcorder, a radio, a recorder, a combination sound system, a record player, a laser record player, a home office device, a home electronic health care device, a vehicle such as a car, or an energy storage device, etc.

[0131] The embodiments of the present application are further described below in multiple embodiments.

[0132] Embodiment 1

[0133] A wafer with a structure as shown in Figure 4 is provided as a substrate, and a TaS x film is selectively deposited on the sidewall of the via 301 by the following method to form a TaS x film. The TaS x film is prepared by plasma enhanced atomic layer deposition (PEALD) using aniline as an inhibitor, BTDET as an organic tantalum precursor, and H2S as a sulfur source, and the process flow chart is as shown in Figure 9 . The preparation of the TaS x film specifically includes the following steps:

[0134] 1) The temperature of the reaction chamber and the sample stage loaded with the substrate is heated to 150°C;

[0135] 2) The inhibitor aniline is heated to 90°C, and the saturated vapor of aniline is loaded into the reaction chamber with argon (Ar) as the carrier gas, and the inlet time is 10 seconds;

[0136] 3) Purge for 30s with Ar as the purge gas to remove the unabsorbed inhibitors and byproducts on the metal material;

[0137] 4) The tantalum precursor (specifically TBTDET) is heated to 90°C, and the saturated vapor of the TBTDET precursor is loaded into the reaction chamber in 5 times with Ar as the carrier gas;

[0138] 5) Purge for 30s with Ar as the purge gas to remove the unreacted tantalum precursor and byproducts;

[0139] 6) H2S gas is used as the sulfur source, and the radio frequency source is turned on to discharge H2S to generate plasma and react with the tantalum precursor adsorbed on the surface of the substrate to form tantalum sulfide; wherein the inlet flow rate of H2S gas is 50sccm, the discharge duration is 20s, the discharge power is 110W, and the frequency is 13.56MHz;

[0140] 7) Purge again for 30s with Ar as the purge gas to remove the reaction byproducts. Thus, one deposition cycle is completed;

[0141] 8) Repeat the above steps 2)-7) for several deposition cycles to obtain a TaS x thin film of the desired thickness.

[0142] After that, the above formed TaS x thin film is annealed at 300°C for 60min in an Ar and H2 mixed atmosphere to obtain a stable TaS x thin film, and the preparation of the adhesion barrier layer is completed.

[0143] Example 2

[0144] A wafer with a structure as shown in Figure 4 is provided as a substrate, and a TiSx thin film is formed on the sidewall of the via 301 and the sidewall and bottom of the first trench 302. The TiSx thin film is prepared by PEALD technology using p-phenylenediamine (PPD) as the inhibitor, TDMAT as the organic titanium precursor, and H2S as the sulfur source, and the process flowchart can be as shown in Figure 9 , and the specific steps of the TiSx thin film include:

[0145] 1) Heat the chamber containing the organic titanium precursor to 40°C and the sample stage containing the substrate to 200°C;

[0146] 2) The inhibitor p-phenylenediamine (PPD) was heated to 100°C and saturated p-phenylenediamine vapor was introduced into the reaction chamber using argon (Ar) as a carrier gas for 10 seconds.

[0147] 3) Use Ar as the purge gas for 30 seconds to remove the inhibitors and byproducts that are not adsorbed on the metal material;

[0148] 4) Using Ar as the carrier gas, saturated vapor of the titanium precursor TDMAT was loaded into the reaction chamber in five batches;

[0149] 5) Using Ar as a purge gas for 30 seconds to remove unreacted titanium precursor and by-products;

[0150] 6) Using H2S gas as a sulfur source, and turning on a radio frequency source to discharge H2S to generate plasma, which reacts with the titanium precursor adsorbed on the surface of the substrate to form titanium sulfide; wherein the flow rate of the H2S gas is 50 sccm, the discharge duration is 20 s, the discharge power is 110 W, and the frequency is 13.56 MHz;

[0151] 7) Purge again with Ar as the purge gas for 30 seconds to remove reaction byproducts. This completes one deposition cycle.

[0152] 8) Repeat the above steps 2)-7) for several deposition cycles to obtain the desired thickness of TiS x film.

[0153] Afterwards, the TiS x The film was annealed at 300 °C for 60 min in a mixed atmosphere of Ar and H2 to obtain a stable TiS x film, completing the preparation of the adhesion barrier layer.

[0154] In order to verify the effect of the preparation process of the sulfide film provided in the examples of the present application, taking the preparation of tantalum sulfide in Example 1 as an example, the XPS (X-ray Photoelectron Spectroscopy) results of TaSx films prepared by the PEALD process at different deposition temperatures on a silicon dioxide substrate were explored. Figure 15 The elemental analysis results of tantalum sulfide films prepared by atomic layer deposition at different deposition temperatures are listed. The tantalum sulfide films were deposited at deposition temperatures of 150°C, 250°C, and 350°C for 100 cycles.

[0155] Figure 15The results show that the molar ratio of Ta to S is about 1:2, and the film does not contain halogen elements, C elements, or N elements, but only contains Ta, S, and O. The O element in the film is mainly introduced during the test process, which is due to the TaS prepared by the ALD process. x The film is easily oxidized in the air. Therefore, the TaS film prepared in situ by ALD process is used in this application. x The film only contains Ta and S elements.

[0156] To evaluate TaS x The compatibility of the film with the Cu layer when used as an adhesion barrier layer, the present application first deposited and grew a 1.5nm thick TaS on a 50nm thick silicon oxide substrate. x film, then on TaS x A 100nm thick copper layer was deposited on the film. The diffusion of copper was observed over time and a copper diffusion rate graph was obtained. The results are as follows: Figure 16 shown.

[0157] from Figure 16 (a) It is known that as time increases, TaS x There is a significant interdiffusion between the film and the Cu layer, forming CuS x , and its diffusion coefficient is 2.97*10 -9 cm 2 / s, such as Figure 16 As shown in (b). It can be seen that the TaS prepared by ALD method x The film has sulfur diffusion problems, which causes corrosion to the Cu layer.

[0158] To solve the problem of TaS x The film has the problem that sulfur (S) diffusion will cause corrosion to the Cu layer. The applicant has carried out TaS x Annealing study of thin films. 1.5nm thick TaS was deposited on a 50nm thick silicon oxide substrate. x The film was then annealed at 300 ° C for 60 min in a mixed atmosphere of argon and hydrogen, and then the annealed TaS x A 100nm thick copper layer was deposited on the film and the diffusion of copper was observed over time. The results are as follows: Figure 17 As shown in (b), and compared with a 50nm thick silicon oxide substrate with a 100nm thick copper layer evaporated on the surface ( Figure 17 (a)) for comparison. Figure 17 It can be seen that the TaS produced by ALD process x After annealing, no S diffusion occurs in the film within 48 hours. x The film was annealed to solve the problem of unannealed TaS xThe film has a sulfur diffusion problem, so it will not cause corrosion to copper wires.

[0159] Furthermore, a TaS x The TaS thin film was prepared by PEALD process on silicon oxide substrate at a deposition temperature of 150℃ for 13 deposition cycles. x Atomic force microscope (AFM) images of the film after annealing are shown in Figure 2. Figure 18 As shown in (a), the AFM step scan image obtained based on this is as follows Figure 18 As shown in (b). Figure 18 The AFM test results of (a) and (b) show that the TaS x The thickness of the film is about 1.5nm. x The film was characterized by transmission electron microscopy (TEM). The obtained TEM images are as follows: Figure 18 As shown in (c). The TEM characterization results show that the TaS x The film is in an amorphous state. Amorphous films have better diffusion barrier properties for copper metal and are significantly better than traditional polycrystalline TaN films.

[0160] In addition, a 1.5 nm thick TaS x A SiO2 substrate with a thin film and a 100nm thick Cu layer, a SiO2 substrate with a TaN film made by PEALD and a 100nm thick Cu layer stacked in sequence, and a SiO2 substrate with a 100nm thick Cu layer were used as simple test devices for time-dependent dielectric breakdown (TDDB) tests, and the corresponding cumulative distribution data were obtained, such as Figure 18 As shown in (d).

[0161] from Figure 18 (d) It is known that the half device breakdown time (TTF) of the test device of the TaN film prepared by the PEALD process in this application is 50％ ) is 27.6 seconds, and TaS prepared by PEALD process x TTF of thin film devices 50％ is 71.9s. Therefore, at 7MV·cm -1 Under the field strength of 1.5nm thick annealed TaS x The life of the device using thin film as a barrier layer is about 2.6 times that of the device using 3nm thick TaN film as a barrier layer. 50％The values ​​are greater than those of the control device without a barrier layer, where the TFF of the control device is 50％ The value is only 3 seconds. These results show that the annealed TaS x The film has excellent barrier properties. Under low line width conditions, the layered TaS x The thin film can replace the TaN / Ta double-layer structure, thereby increasing the volume proportion of copper metal in the interconnect structure, reducing the resistance of the interconnect structure, and ultimately achieving the goal of reducing RC delay.

[0162] Next, the annealed TaS prepared in this application was verified by a tape adhesion test. x Adhesion performance between the film and the Cu layer. The PEALD process of the present application was used to prepare 1.5nm thick annealed TaS on a Si wafer with a 50nm thick SiO2 layer on the surface. x The film was deposited at 150°C for 13 cycles and annealed at 300°C for 60 min. x A Cu film with a thickness of about 100 nm is deposited on the film. Then a simple adhesion test is performed by sticking 3M transparent tape on the Cu layer. The process is shown in the figure below. Figure 19 shown. Figure 19 The first row is a schematic diagram of the structure of the sample to be tested for adhesion test. The second row is, from left to right, the product to be tested, the sample to be tested with 3M tape attached, the sample to be tested with 3M tape peeled off, and the sample to be tested after the 3M tape is peeled off.

[0163] from Figure 19 It can be seen that after peeling off the 3M tape from the Cu film, the TaS x The Cu film on the film is completely preserved. The above test results show that the annealed TaSx film prepared by the PEALD process in this application has strong adhesion to the Cu film, which can serve as an adhesion layer for the Cu film, ensuring that it will not be peeled off from the trench / via during the CMP process of the Cu layer.

[0164] In order to clearly characterize the aforementioned TaS prepared in this application x Microstructural properties of the film. 15.6nm thick annealed TaS deposited on SiO2 film x The film was deposited at 150°C for 100 cycles and annealed at 300°C for 60 min. x A 100 nm thick Cu layer was evaporated on the film, and then cross-sectional TEM characterization was performed. The results are as follows Figure 20 As shown, Figure 20 (b) is the TaS boxed in (a) x Magnified view of the film area. Figure 20In (a), the lighter gray area is the SiO2layer, and the darker gray area is the TaS x thin film.

[0165] From Figure 20 It can be seen that the TaS x thin film has obvious layer characteristics, which shows that the TaS x thin film prepared by the PEALD process described in the present application is a two-dimensional material, and the interlayer spacing thereof is about 0.59 nm.

[0166] In order to further verify the application of the metal sulfide thin film prepared by the PEALD process described in the present application in the small critical size of Cu interconnection, the present applicant deposited TaS x film (the aspect ratio of the trench and the via structure is 4.6:1, wherein the width is 50 nm, and the depth is 230 nm) in the trench and the via structure of a damascene chip, as shown in Figure 21 . Figure 21 (a) and (f) sequentially show the top-view scanning electron microscope (SEM) photos of the trench area and the corresponding structural schematic diagram; (b) is a cross-sectional annular bright field (ABF) image of the TaS x thin film deposited in the trench; (c) and (d) are the Energy Dispersive Spectrometer (EDS) mapping images of the Ta element and the S element in (b) respectively; (e) is a cross-sectional scanning transmission electron microscopy (STEM) image of the thickness of the TaS x thin film; (g) is a cross-sectional ABF image of the TaS x thin film deposited in the via structure; (h) and (i) are the EDS mapping images of the Ta element and the S element in (g) respectively; (j) is a cross-sectional STEM image of the thickness of the TaS x thin film in the via structure.

[0167] From Figure 21 (b) and (g), it can be seen that, due to the self-limiting deposition characteristics of the PEALD process, the deposited TaS x thin film can conformally cover the trench and the via. According to Figure 21 (c), (h), (d) and (i), it can be confirmed that the Ta and S elements are uniformly distributed in the trench structure and the via structure. From Figure 21 (e), it can be concluded that the TaS xThe thickness of the film is less different in different regions (the TaS x The thickness of the film is less different in different regions (the TaS x The thickness of the film is less different in different regions (the TaS x The film can be uniformly and conformally deposited in the trench. As Figure 21 As shown in (j), the thickness uniformity of the TaS x film is also obtained in the via structure. Since the via structure is relatively narrow Figure 21 As shown in (f), the diffusion rate of the tantalum precursor in the via structure is slower than that in the trench, and the thickness of the TaS x The deposition thickness of the film is slightly reduced. Figure 21 As shown in (j), the thickness uniformity of the TaS x The thickness of the film is about 1.4 nm.

[0168] The experimental results show that the TaS x film prepared by the inhibitor-assisted PEALD process of the present application has excellent conformal deposition and thickness uniformity, and can meet the requirements of the chip back-end process technology, especially in the low-line-width trench and via, and the TaS x The thickness of the film can be less than 2 nm, which can ensure that the volume ratio of the Cu interconnection layer in the via / trench interconnection structure is high, and the resistance of the overall interconnection structure is low.

[0169] The above merely expresses the exemplary embodiments of the present application, which are described in detail, but should not be understood as limiting the scope of the present application. It should be noted that, for those skilled in the art, without departing from the concept of the present application, several modifications and improvements can be made, which are all within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the appended claims.

[0170] It should be understood that the first, second, and various numerical numbers involved herein are only for the convenience of differentiation, and do not limit the scope of the present application.

[0171] In the present application, "and / or" describes the association relationship of the associated objects, which means that there can be three relationships, for example, A and / or B, which can represent the following cases: A exists alone, A and B exist together, and B exists alone, wherein A and B can be singular or plural. The character " / " generally represents an "or" relationship between the associated objects before and after it.

[0172] In the description of the present application, unless otherwise specified, the meaning of "a plurality of" is greater than or equal to two. "At least one" refers to one or more. "At least one of the following" or the like refers to any combination of these items, including any combination of single or multiple items. For example, "at least one of a, b, or c", or "at least one of a, b, and c", can represent: a, b, c, a-b (i.e. a and b), a-c, b-c, or a-b-c, where a, b, and c can be single or multiple.

[0173] In addition, the numerical range indicated by "-" in the present application means a range including the minimum value and the maximum value indicated by the numerical value before and after the "-" respectively. In the present application, the expressions such as "greater than or equal to (≥)", "less than or equal to (≤)", "above", "below" with respect to the range of parameters include the present number. The numerical values and numerical ranges involved in the embodiments of the present application are approximate values, and there may be a certain range of error due to the influence of manufacturing process / testing method, etc., which can be considered negligible by those skilled in the art.

Claims

1. A semiconductor structure, characterized by, The semiconductor structure comprises: a dielectric layer having a via formed therein; an adhesion barrier layer formed on the sidewall of the via; wherein the adhesion barrier layer is an amorphous metal sulfide film, and the metal sulfide film comprises tantalum sulfide or titanium sulfide; a metal interconnect layer filled in the via and covering the adhesion barrier layer.

2. The semiconductor structure of claim 1, wherein, The chemical formula of the tantalum sulfide is TaS x The chemical formula of the titanium sulfide is TiS x Each x is independently between 1.5 and 3.

3.

3. The semiconductor structure of claim 1 or 2, wherein, The thickness of the adhesion barrier layer is less than or equal to 1.6 nm.

4. The semiconductor structure of any one of claims 1 to 3, wherein the semiconductor structure comprises a plurality of semiconductor structures. The thickness of the adhesion barrier layer on any two of the upper, middle and lower portions of the sidewall of the via deviates by no more than 10%.

5. The semiconductor structure of any of claims 1-4, wherein the semiconductor structure is a semiconductor-on-insulator structure. The adhesion barrier layer does not contain halogen.

6. The semiconductor structure of any one of claims 1-5, wherein, The adhesion barrier layer does not contain nitrogen and carbon elements.

7. The semiconductor structure of any of claims 1-6, wherein, The adhesion barrier layer is formed by an atomic layer deposition process assisted by an inhibitor to form an amorphous metal sulfide film, and then annealing.

8. The semiconductor structure of any of claims 1-7, wherein, The opening size of the via is no more than 25 nm.

9. The semiconductor structure of any of claims 1-8, wherein, The dielectric layer further has a first trench formed therein, and the adhesion barrier layer is also located on the sidewall and bottom of the first trench; the first trench is also filled with the metal interconnect layer, and the metal interconnect layer covers the adhesion barrier layer in the first trench.

10. The semiconductor structure of claim 9, wherein, The opening size of the first trench is no more than 25 nm.

11. The semiconductor structure of any of claims 1-10, wherein, The semiconductor structure further comprises a first dielectric layer located below the dielectric layer, wherein the first dielectric layer has a second trench penetrating therethrough, and the bottom end opening of the second trench is partially sealed by a metal layer in a lower dielectric layer located below the first dielectric layer; wherein a second adhesion barrier layer is formed on the sidewall and part of the bottom of the first trench, the second adhesion barrier layer is not formed on the metal layer, and another metal interconnect layer filling the second trench is formed on the second adhesion barrier layer; the second adhesion barrier layer is an amorphous tantalum sulfide film or titanium sulfide film.

12. The semiconductor structure of claim 11, wherein, The thickness of the second adhesion barrier layer on any two of the upper, middle and lower portions of the sidewall of the second trench deviates by no more than 10%.

13. The semiconductor structure of claim 11 or 12, wherein, The material of the another metal interconnect layer and the metal layer is independently selected from one or more of W, Co, Cu, Ru, Mo and Al.

14. A method of forming a semiconductor structure, comprising: The semiconductor structure comprises the following steps: (1) providing a first dielectric layer having a first metal interconnect layer formed therein; forming a second dielectric layer on the first dielectric layer, and forming a via in the second dielectric layer; wherein the via exposes the first metal interconnect layer; (2) depositing an amorphous metal sulfide film on the sidewall of the via by an atomic layer deposition process, and then annealing to obtain an adhesion barrier layer; wherein the metal sulfide film comprises tantalum sulfide or titanium sulfide; in each deposition cycle of the atomic layer deposition process, an inhibitor is first introduced, and then a metal element precursor and a sulfur source are alternately exposed to the via; the inhibitor is used to inhibit the deposition of the metal sulfide film on the first metal interconnect layer exposed at the bottom of the via; (3) electroplating metal to fill the via with the adhesion barrier layer to form a second metal interconnect layer.

15. The method of claim 14, wherein The inhibitor includes one or more of aniline, p-phenylenediamine, styrene, azobenzene, 1-methyl-2-pyrrolidone, 2-methylpyrrole, 1-(2-aminophenyl)pyrrole, acetylacetone, and propargylamine.

16. The forming method of claim 14 or 15, wherein, The first metal interconnection layer is made of one or more of W, Co, Cu, Ru, Mo, and Al.

17. The forming method of any of claims 14-16, wherein, The deposition temperature of the metal sulfide film and the annealing temperature of the annealing process are both less than or equal to 400℃.

18. The forming method of any of claims 14-17, wherein, In step (1), the second dielectric layer further has a first trench formed therein; in step (2), the metal sulfide film is formed on the sidewall of the via and the sidewall and bottom of the first trench.

19. The forming method of any of claims 14-18, wherein, The method for forming the first metal interconnection layer comprises: providing a lower dielectric layer having a metal layer formed therein; forming the first dielectric layer on the lower dielectric layer and etching the first dielectric layer to form a second trench; the bottom end opening of the second trench is partially sealed by the metal layer; forming an amorphous metal sulfide film on the sidewall and bottom of the second trench by an atomic layer deposition process and performing an annealing process to obtain a second adhesion barrier layer, wherein the metal sulfide film includes a tantalum sulfide or a titanium sulfide; in each deposition cycle of the atomic layer deposition process, an inhibitor is first introduced, and then a metal element precursor and a sulfur source are alternately exposed to the second trench; the inhibitor is used to inhibit the deposition of the metal sulfide film on the metal layer exposed at the bottom of the second trench; electroplating the first trench with the second adhesion barrier layer to form the first metal interconnection layer.

20. A semiconductor device, characterized by comprising: The semiconductor structure includes any one of claims 1-13, or the semiconductor structure formed by the forming method of any one of claims 14-19.

21. The semiconductor device of claim 20, wherein, The semiconductor device includes a power device, a radio frequency device, or an optoelectronic device. The semiconductor device includes a power device, a radio frequency device, or an optoelectronic device.

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