Battery reverse connection protection circuit and analog power chip

Abstract

This invention provides a battery reverse connection protection circuit and an analog power chip, belonging to the field of battery protection. It includes: a control circuit with its power supply terminal connected to a first power supply terminal; a first NMOS transistor with its gate connected to the first output terminal of the control circuit and its drain connected to a second power supply terminal; a protection module with one end connected to the power supply terminal of the control circuit and the other end grounded; and a first switching unit connected between the drain of the first NMOS transistor and the substrate, with the second output terminal of the control circuit connected to the first switching unit. When the battery is connected correctly, the source of the first NMOS transistor is connected to the negative terminal of the battery, and the control circuit controls the first NMOS transistor to turn on or off. When the battery is connected in reverse, the source of the first NMOS transistor is connected to the positive terminal of the battery, and the control circuit controls the first switching unit to close. The purpose is to solve the problem that the internal circuitry of batteries in the prior art does not have reverse connection protection functionality, thus enabling the battery to have reverse connection protection to ensure safety.

Description

Technical Field

[0001] This invention relates to the field of battery protection technology, and more particularly to a battery reverse connection protection circuit, as well as an analog power chip. Background Technology

[0002] With the rapid development of technology, chemical batteries, with their advantages of high energy density and rechargeability, have been widely used in many fields such as consumer electronics, electric vehicles, and energy storage systems. In the consumer electronics field, chemical batteries provide stable power for various portable devices, supporting their long-term operation; in the electric vehicle industry, they are a key power source for driving vehicles; and in energy storage systems, chemical batteries can realize the storage and rational allocation of electrical energy, improving energy utilization efficiency.

[0003] However, the safety and stability of chemical batteries have become a focus of industry attention. On the battery manufacturing side, the production process is complex, and improper management can easily create safety hazards. On the battery usage side, there is a serious problem that urgently needs to be addressed: when the positive and negative terminals of a battery are reversed in the system, some load sources lack reverse connection protection, which can damage some components in the entire system. Furthermore, during reverse connection, the battery may also experience extreme dangers such as fire or explosion due to internal short circuits, causing not only property damage but also potentially threatening personal safety. Summary of the Invention

[0004] This invention provides a battery reverse connection protection circuit and an analog power chip to solve the defect that the internal circuit of the battery in the prior art does not have a reverse connection protection function, so as to enable the battery to have a reverse connection protection function to ensure safety.

[0005] The first aspect of the present invention provides a battery reverse connection protection circuit, including a control circuit, a protection module, a first switching unit and a first NMOS transistor;

[0006] The power supply terminal of the control circuit is connected to the first power supply terminal;

[0007] The gate of the first NMOS transistor is connected to the first output terminal of the control circuit, and the drain of the first NMOS transistor is connected to the second power supply terminal.

[0008] One end of the protection module is connected to the power supply terminal of the control circuit, and the other end of the protection module is grounded;

[0009] The first switching unit is connected between the drain of the first NMOS transistor and the substrate of the first NMOS transistor, and the second output terminal of the control circuit is connected to the first switching unit.

[0010] When the battery is positively connected, the source of the first NMOS transistor is connected to the negative terminal of the battery, and the control circuit is used to control the first NMOS transistor to be turned on or off.

[0011] When the battery is reverse-connected, the source of the first NMOS transistor is connected to the positive terminal of the battery, and the control circuit controls the first switching unit to close.

[0012] The first and second power terminals are used to connect to the charger or load.

[0013] In addition, the battery reverse connection protection circuit according to the present invention may also have the following additional technical features:

[0014] In some embodiments of the present invention, a low-voltage comparator is also included. The low-voltage comparator is integrated on the control circuit. The first input terminal of the low-voltage comparator is grounded, the second input terminal of the low-voltage comparator is connected to the power supply terminal of the control circuit, and the output terminal of the low-voltage comparator is connected to the first switching unit.

[0015] In some embodiments of the present invention, the low-voltage comparator includes a minimum voltage selection circuit, a comparator circuit, and a comparator output stage. The first input terminal of the minimum voltage selection circuit is connected to the second power supply terminal, the second input terminal of the minimum voltage selection circuit is grounded, and the output terminal of the minimum voltage selection circuit is connected to the first input terminal of the comparator circuit. The second input terminal of the comparator circuit is connected to the power supply terminal of the control circuit, and the output terminal of the comparator circuit is connected to the first switching unit.

[0016] In some embodiments of the present invention, the minimum voltage selection circuit includes a second NMOS transistor and a third NMOS transistor. The gate of the second NMOS transistor is connected to a second power supply terminal, the gate of the third NMOS transistor is grounded, the drain of the second NMOS transistor is grounded, and the drain of the third NMOS transistor is connected to the second power supply terminal. The sources of both the second and third NMOS transistors are connected to the first input terminal of the comparator circuit.

[0017] In some embodiments of the present invention, the comparator circuit includes a first comparator module and a first three-transistor. The first terminal of the first three-transistor is connected to the output terminal of the lowest voltage selection circuit. The first input terminal of the first comparator module is connected to the second terminal of the first three-transistor. The second input terminal of the first comparator module is connected to the power supply terminal of the control circuit. The output terminal of the first comparator module is connected to the comparator output stage.

[0018] In some embodiments of the present invention, the comparator output stage includes a first inverter, the input of which is connected to the output of the first comparator module, and the output of which is connected to the first switching unit.

[0019] In some embodiments of the present invention, the first comparator module includes a fourth NMOS transistor, a fifth NMOS transistor, a first PMOS transistor, and a second PMOS transistor, and the first three transistors include a sixth NMOS transistor;

[0020] The gates of the fourth NMOS transistor, the fifth NMOS transistor, and the source of the sixth NMOS transistor are all connected to the output of the lowest voltage selection circuit; the sources of the fourth and fifth NMOS transistors are all connected to the drain of the sixth NMOS transistor; the gate of the sixth NMOS transistor is grounded.

[0021] The drain, gate, and gate of the first PMOS transistor are all connected to the drain of the fourth NMOS transistor. The drain of the fifth NMOS transistor is connected to the drain of the second PMOS transistor. The input terminal of the first inverter is connected between the drain of the fifth NMOS transistor and the drain of the second PMOS transistor. The source of the first PMOS transistor is grounded, and the source of the second PMOS transistor is connected to the power supply terminal of the control circuit.

[0022] In some embodiments of the present invention, the comparator circuit includes a second three-transistor and a second comparator module. The first terminal of the second three-transistor is connected to the output terminal of the lowest voltage selection circuit. The first input terminal of the second comparator module is connected to the second terminal of the second three-transistor. The second input terminal of the second comparator module is connected to the power supply terminal of the control circuit. The output terminal of the second comparator module is connected to the input terminal of the comparator output stage.

[0023] In some embodiments of the present invention, the comparator output stage includes a second inverter and a third inverter. The input terminal of the second inverter is connected to the output terminal of the second comparator module, the input terminal of the third inverter is connected to the output terminal of the second inverter, and the output terminal of the third inverter is connected to the first switching unit.

[0024] In some embodiments of the present invention, the second comparator module includes a seventh NMOS transistor, an eighth NMOS transistor, a third PMOS transistor, and a fourth PMOS transistor, and the second triode includes a ninth NMOS transistor;

[0025] The gates of the seventh NMOS transistor, the eighth NMOS transistor, and the source of the ninth NMOS transistor are all connected to the output of the lowest voltage selection circuit; the sources of the seventh and eighth NMOS transistors are both connected to the drain of the ninth NMOS transistor; the gate of the ninth NMOS transistor is grounded.

[0026] The source of the third PMOS transistor is grounded, and the drain of the third PMOS transistor is connected to the drain of the seventh NMOS transistor.

[0027] The gate of the third PMOS transistor, the gate of the fourth PMOS transistor, the drain of the fourth PMOS transistor, and the drain of the eighth NMOS transistor are all connected to node B. The input of the comparator output stage is connected between the drain of the eighth NMOS transistor and node B.

[0028] The source of the fourth PMOS transistor is connected to the power supply terminal of the control circuit.

[0029] A second aspect of the present invention provides an analog power chip, which includes all the technical features of the battery reverse connection protection circuit of the first aspect of the present invention.

[0030] In summary, this application includes the following beneficial technical effects: when the battery is reverse-connected, the control circuit controls the first switching unit to close, so that the parasitic diode of the first NMOS transistor will not conduct, thereby making the current flowing through the load circuit zero, thus protecting the load, avoiding damage to various circuit components, and also avoiding extreme dangerous situations such as fire and explosion caused by internal short circuits, reducing property losses and ensuring safety performance. Attached Figure Description

[0031] Various other advantages and benefits will become apparent to those skilled in the art upon reading the following detailed description of preferred embodiments. The accompanying drawings are for illustrative purposes only and are not intended to limit the invention. Furthermore, the same reference numerals denote the same parts throughout the drawings. In the drawings:

[0032] Figure 1 A schematic diagram of the battery reverse connection protection circuit according to some embodiments of the present invention is shown.

[0033] Figure 2 A schematic diagram of the control first switching unit of the low-voltage comparator in a battery reverse connection protection circuit according to some embodiments of the present invention is shown.

[0034] Figure 3 A schematic diagram of the low-voltage comparator of a battery reverse connection protection circuit according to some embodiments of the present invention is shown.

[0035] Figure 4 This diagram illustrates another circuit structure of the low-voltage comparator for the battery reverse connection protection circuit according to some embodiments of the present invention.

[0036] Figure 5 This diagram illustrates another circuit structure of the low-voltage comparator for the battery reverse connection protection circuit according to some embodiments of the present invention.

[0037] Figure 6 This diagram illustrates another circuit structure of the low-voltage comparator for the battery reverse connection protection circuit according to some embodiments of the present invention.

[0038] Figure 7 This diagram illustrates another circuit structure of the low-voltage comparator for the battery reverse connection protection circuit according to some embodiments of the present invention.

[0039] Figure 8This diagram illustrates another circuit structure of the low-voltage comparator for the battery reverse connection protection circuit according to some embodiments of the present invention.

[0040] Figure 9 This diagram illustrates another circuit structure of the low-voltage comparator for the battery reverse connection protection circuit according to some embodiments of the present invention.

[0041] Figure 10 A schematic diagram of the minimum voltage selection circuit of the battery reverse connection protection circuit of some embodiments of the present invention is shown.

[0042] Figure 11 A schematic diagram of the existing battery reverse connection circuit structure is shown for some embodiments of the present invention.

[0043] Figure 12 A schematic diagram of the structure of a conventional battery discharge plus battery simulation power chip is shown for some embodiments of the present invention.

[0044] Figure label:

[0045] 1. Control circuit; 2. Battery; 3. Load; 4. First NMOS transistor; 5. First switching unit; 6. Second switching unit; 7. Protection module; 8. Filter resistor; 9. Low-voltage comparator; 91. Comparator circuit; 911. First comparator module; 9111. Fourth NMOS transistor; 9112. Fifth NMOS transistor; 9113. First PMOS transistor; 9114. Second PMOS transistor; 9115. Adjustment resistor; 912. First three-transistor; 9121. Sixth NMOS transistor; 913. Second comparator module; 9131. Seventh NMOS transistor; 9132. Eighth NMOS transistor. S-transistor, 9133, third PMOS transistor, 9134, fourth PMOS transistor, 9135, tenth NMOS transistor, 9136, eleventh NMOS transistor, 9137, fifth PMOS transistor, 9138, sixth PMOS transistor, 914, second three-transistor, 9141, ninth NMOS transistor, 9142, twelfth NMOS transistor, 9143, thirteenth NMOS transistor, 92, lowest voltage selection circuit, 921, second NMOS transistor, 922, third NMOS transistor, 93, comparator output stage, 931, first inverter, 932, second inverter, 933, third inverter. Detailed Implementation

[0046] Exemplary embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of the present disclosure are shown in the drawings, it should be understood that the present disclosure may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided so that this disclosure will be thorough and complete, and will fully convey the scope of the disclosure to those skilled in the art.

[0047] It should be understood that the terminology used herein is for the purpose of describing particular exemplary embodiments only and is not intended to be limiting. Unless the context clearly indicates otherwise, the singular forms “a,” “an,” and “” used herein may also indicate the inclusion of the plural forms. The terms “comprising,” “including,” “containing,” and “having” are inclusive and therefore indicate the presence of the stated features, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, elements, components, and / or combinations thereof. The method steps, processes, and operations described herein are not construed as requiring them to be performed in a particular order described or illustrated, unless the order of performance is explicitly indicated. It should also be understood that additional or alternative steps may be used.

[0048] Although terms such as first, second, third, etc., may be used in this document to describe multiple elements, components, regions, layers, and / or segments, these elements, components, regions, layers, and / or segments should not be limited by these terms. These terms may be used only to distinguish one element, component, region, layer, or segment from another. Unless the context clearly indicates otherwise, terms such as "first," "second," and other numerical terms used herein do not imply order or sequence. Therefore, the first element, component, region, layer, or segment discussed below may be referred to as the second element, component, region, layer, or segment without departing from the teachings of the exemplary embodiments.

[0049] For ease of description, spatial relative terms may be used in the text to describe the relationship of one element or feature relative to another element or feature, as shown in the figure. These relative terms include, for example, "inside," "outside," "middle," "outer," "below," "below," "above," "over," etc. Such spatial relative terms are intended to include different orientations of the device in use or operation, other than those depicted in the figure. For example, if the device in the figure is flipped, an element described as "below other elements or features" or "below other elements or features" would subsequently be oriented "above other elements or features" or "above other elements or features." Therefore, the example term "below" can include both upper and lower orientations. The device may also be rotated 90 degrees or in other orientations, and the spatial relative descriptors used in the text will be interpreted accordingly.

[0050] In daily use, a common phenomenon is the reverse connection of three batteries under load. This is illustrated by the traditional chemical battery discharge model combined with a battery simulation power chip model, such as... Figure 12As shown, an IC is used to detect the battery voltage and discharge current to control the conduction or cutoff of the first NMOS transistor 4 (NM0), thereby ensuring that the battery operates in a safe state. When a load 3 is connected between the first power supply terminal (P+) and the second power supply terminal (P-), the analog power chip controls SW0 (the second switching unit) to close. At this time, the battery is in a discharge state and operates normally with the load 3.

[0051] When the battery is reversed, such as Figure 11 As shown, the VDD voltage, i.e., the voltage at the first power supply terminal, is negative. The voltage at the power supply terminal of control circuit 1, i.e., VDD1, is also negative, meaning the supply voltage of the analog power chip is negative, thus preventing the first NMOS transistor 4, i.e., NM0, from turning on. Simultaneously, because the voltage at the power supply terminal, VDD1, is negative, the internal control of the analog power chip becomes chaotic, failing to guarantee the states of the first switch unit 5, i.e., SW1, and the second switch unit 6, i.e., SW0, as shown in the diagram. When switch SW0 is closed, NM0 is turned off. At this time, the parasitic diode Dnm0 of the first NMOS transistor 4, i.e., NM0, points from ground to the second power supply terminal, P-. Assuming the battery voltage is 4V, the forward voltage of diode D0 is 0.65V, and the forward voltage of parasitic diode Dnm0 is 0.6V; while at this time, the voltage at the first power supply terminal, VDD, is -4V, equal to P+, and the voltage at the power supply terminal of control circuit 1, VDD1, is clamped to -0.65V due to the clamping effect of diode D0. When the power supply of the analog power chip is negative, the system logic is disordered and the output voltage is negative. At this time, the highest drain voltage of the first NMOS transistor 4, i.e., NM0, is -0.65V, which is the highest voltage of the system. Then the parasitic diode Dnm0 of the first NMOS transistor 4, i.e., NM0, is turned on. At this time, a large current flows through the load circuit 3, which will cause damage to some components of the system or cause fire and explosion.

[0052] like Figures 1 to 10 As shown, according to an embodiment of the first aspect of the present invention, a battery reverse connection protection circuit is proposed, including a control circuit 1, a protection module 7, a first switching unit 5, a low-voltage comparator 9, and a first NMOS transistor 4;

[0053] The power supply terminal of control circuit 1 is connected to the first power supply terminal;

[0054] The gate of the first NMOS transistor 4 is connected to the first output terminal of the control circuit 1, the source of the first NMOS transistor 4 is connected to the battery 2, and the drain of the first NMOS transistor 4 is connected to the second power supply terminal.

[0055] One end of the protection module 7 is connected to the power supply terminal of the control circuit 1, and the other end of the protection module 7 is grounded;

[0056] The first switching unit 5 is connected between the drain of the first NMOS transistor 4 and the substrate of the first NMOS transistor 4, and the second output terminal of the control circuit 1 is connected to the first switching unit 5.

[0057] When battery 2 is positively connected, the source of the first NMOS transistor 4 is connected to the negative terminal of battery 2, and the control circuit 1 is used to control the first NMOS transistor 4 to be turned on or off.

[0058] When battery 2 is reversed, the source of the first NMOS transistor 4 is connected to the positive terminal of battery 2, and the control circuit 1 controls the first switching unit 5 to close.

[0059] The first and second power terminals are used to connect the charger or load 3.

[0060] In the above embodiments, it should be noted that the control circuit 1 is used to control the on and off of the first NMOS transistor 4, and also includes a second switching unit 6 and a filter resistor 8. The protection module 7 is a diode, NMOS transistor, PMOS transistor, or transistor, etc. The filter resistor 8 is connected in series before the control circuit 1 and the protection module 7; the filter resistor 8 can be a variable resistor, or it can be a resistor with an external capacitor connected to it; the second switching unit 6 is connected in parallel between the gate and source of the first NMOS transistor 4; in addition, as Figure 1 As shown, the first power supply terminal is P+, which is VDD; the second power supply terminal is P-; and the battery's power supply terminal is VDD1.

[0061] The technical effect achieved by the above embodiment is as follows: when the battery 2 is reverse-connected, the control circuit 1 controls the first switch unit 5 to close, thereby preventing the parasitic diode of the first NMOS transistor 4 from conducting, thus making the current flowing through the circuit of the load 3 zero, thereby protecting the load 3, avoiding damage to various circuit components, and also avoiding extreme dangerous situations such as fire and explosion caused by internal short circuits, reducing property losses and ensuring safety performance.

[0062] Optional, such as Figures 1 to 10 As shown, it also includes a low-voltage comparator 9. The low-voltage comparator 9 is integrated on the control circuit 1. The first input terminal of the low-voltage comparator 9 is grounded, the second input terminal of the low-voltage comparator 9 is connected to the power supply terminal of the control circuit 1, and the output terminal of the low-voltage comparator 9 is connected to the first switching unit 5.

[0063] The working principle of this circuit is as follows: When the battery is reversed, the power supply terminal VDD1 of the control circuit 1 is negative, which is lower than the ground voltage VSS. The low voltage comparator outputs a logic signal with a relatively high level 9 to control the first switch unit 5, i.e., SW1, to close.

[0064] When the voltage at the second power supply terminal of the low-voltage comparator 9 is less than the signal of the voltage to ground, it outputs the correct logic signal to control the first switching unit 5, i.e., SW1, to close. The analog power chip controls the gate terminal of the first NMOS transistor 4 to be at a low voltage, and the first NMOS transistor 4 is turned off. At this time, the direction of the parasitic diode Dnm0 of the first NMOS transistor 4 is from the second power supply terminal P- to ground.

[0065] Assuming the conduction voltage of protection module 7 is 0.6V, the parasitic diode Dnm0 will only conduct when the signal at the second power supply terminal P- is greater than the conduction voltage of protection module 7, i.e., above 0.6V. At this time, the voltage at the power supply terminal of control circuit 1, i.e., VDD1, which is the highest voltage of the system, is near -0.6V. Therefore, the parasitic diode Dnm0 will definitely not conduct, and the current I0 flowing through the loop of load 3 will be almost zero.

[0066] In addition to using the low-voltage comparator 9 to control the closing of the first switch unit 5, the control circuit 1 can also use other methods that enable the first switch unit 5 to close when the battery 2 is reverse-connected.

[0067] The beneficial effects of the above optional embodiments are as follows: by setting the low-voltage comparator 9, the first switching unit 5 is immediately controlled to close when the battery is reverse-connected, so that the parasitic diode of the first NMOS transistor 4 will not conduct, so that the current flowing through the circuit of the load 3 is 0, thereby protecting the load 3, avoiding damage to various circuit components, and avoiding extreme dangerous situations such as fire and explosion caused by internal short circuits, reducing property losses and ensuring safety performance.

[0068] Optional, such as Figures 2 to 10 As shown, the low-voltage comparator 9 includes a minimum voltage selection circuit 92, a comparator circuit 91, and a comparator output stage 93. The first input terminal of the minimum voltage selection circuit 92 is connected to the second power supply terminal, the second input terminal of the minimum voltage selection circuit 92 is grounded, and the output terminal of the minimum voltage selection circuit 92 is connected to the first input terminal of the comparator circuit 91. The second input terminal of the comparator circuit 91 is connected to the power supply terminal of the control circuit 1, the output terminal of the comparator circuit 91 is connected to the input terminal of the comparator output stage 93, and the output terminal of the comparator output stage 93 is connected to the first switching unit 5.

[0069] Optional, such as Figure 10As shown, the lowest voltage selection circuit 92 includes a second NMOS transistor 921 and a third NMOS transistor 922. The gate of the second NMOS transistor 921 is connected to the second power supply terminal, the gate of the third NMOS transistor 922 is grounded, the drain of the second NMOS transistor 921 is grounded, and the drain of the third NMOS transistor 922 is connected to the second power supply terminal; the source of the second NMOS transistor 921 and the source of the third NMOS transistor 922 are both connected to the first input terminal of the comparator circuit 91.

[0070] In the above optional embodiment, it should be noted that the working principle of the lowest voltage selection circuit 92 is that when the battery 2 is normally loaded, the grounded voltage is less than the voltage of the second power supply terminal, that is, VSS < P-; at this time, the second NMOS transistor 921 is turned on; the voltage at the output terminal of the lowest voltage selection circuit 92 is equal to the grounded voltage and equal to 0V, that is, VB = VSS = 0V.

[0071] When the battery is reversely connected and loaded, the grounded voltage is greater than the voltage of the second power supply terminal, that is, when VSS > P-; the third NMOS transistor 922 is turned on, and the voltage at the output terminal of the lowest voltage selection circuit 92 is less than the grounded voltage, that is, VB < VSS. At this time, the comparator circuit 91 and the comparator output stage 93 of the low voltage comparator 9 work, and the logic signal with a relatively high output level controls the first switch unit 5 to close.

[0072] The beneficial effect of the above optional embodiment is that by setting the lowest voltage selection circuit 92, the low voltage comparator 9 is not controlled by the control circuit 1 and can independently control the closing of the first switch unit 5 according to the reverse connection situation of the battery 2, ensuring reliability.

[0073] Optionally, as Figure 4 、 Figure 6 and Figure 7 shown, the comparator circuit 91 includes a first comparator module 911 and a first three-transistor 912. The first end of the first three-transistor 912 is connected to the output terminal of the lowest voltage selection circuit 92, the first input terminal of the first comparator module 911 is connected to the second end of the first three-transistor 912, the second input terminal of the first comparator module 911 is connected to the power supply terminal of the control circuit 1, and the output terminal of the first comparator module 911 is connected to the comparator output stage 93.

[0074] The comparator output stage 93 includes a first inverter 931. The input terminal of the first inverter 931 is connected to the output terminal of the first comparator module 911, and the output terminal of the first inverter 931 is connected to the first switch unit 5.

[0075] Optionally, as Figure 6 and Figure 7As shown, the first comparator module 911 includes a fourth NMOS transistor 9111, a fifth NMOS transistor 9112, a first PMOS transistor 9113, and a second PMOS transistor 9114, and the first three transistors 912 include a sixth NMOS transistor 9121;

[0076] The gate of the fourth NMOS transistor 9111, the gate of the fifth NMOS transistor 9112, and the source of the sixth NMOS transistor 9121 are all connected to the output of the minimum voltage selection circuit 92; the source of the fourth NMOS transistor 9111 and the source of the fifth NMOS transistor 9112 are all connected to the drain of the sixth NMOS transistor 9121; the gate of the sixth NMOS transistor 9121 is grounded.

[0077] The drain and gate of the first PMOS transistor 9113 and the gate of the second PMOS transistor 9114 are all connected to the drain of the fourth NMOS transistor 9111. The drain of the fifth NMOS transistor is connected to the drain of the second PMOS transistor 9114. The input terminal of the first inverter 931 is connected between the drain of the fifth NMOS transistor and the drain of the second PMOS transistor 9114. The source of the first PMOS transistor 9113 is grounded, and the source of the second PMOS transistor 9114 is connected to the power supply terminal of the control circuit 1.

[0078] The first comparator module 911 also includes an adjustment resistor 9115, which is connected between the second PMOS transistor 9114 and the power supply terminal of the control circuit 1.

[0079] In the above optional embodiments, it should be noted that when the battery is reverse-connected, assuming the conduction voltage of the protection module 7 is 0.65V, the voltage at the power supply terminal of the control circuit 1, i.e., VDD1, is -0.65V; wherein, the output voltage VB of the minimum voltage selection circuit 92 is the lowest level in the analog power chip, which is the negative voltage of the battery 2, i.e., -VBAT, assumed to be -4V; at this time, the sixth NMOS transistor 9121 is turned on, acting as a current source in the circuit, and the fourth NMOS transistor 9111, the fifth NMOS transistor 9112, and the sixth NMOS transistor 9121 are all depletion-type NMOS transistors, which are also turned on at this time; the first PMOS transistor 9113, which is connected in diode mode, is turned on. Figure 6 The voltage at point A is the threshold voltage of the first PMOS transistor 9113. Assuming the threshold voltage of the first PMOS transistor 9113 is -0.7V, then PM1 is cut off. The voltage at point B is the output voltage of the minimum voltage selection circuit 92, i.e., VB voltage, which is relatively low. After passing through the first inverter 931 (DC to AC inverter), the output signal_select signal is relatively high compared to the output voltage of the minimum voltage selection circuit 92, controlling the first switch unit 5 to close.

[0080] The fourth NMOS transistor 9111, the fifth NMOS transistor 9112, and the sixth NMOS transistor 9121 can all be replaced by NPN transistors. The specific circuit diagram can be adjusted according to the actual situation, which will not be discussed in detail here.

[0081] Both the first PMOS transistor 9113 and the second PMOS transistor 9114 can be replaced by PNP transistors. The specific circuit diagram can be adjusted according to the actual situation, which will not be discussed in detail here.

[0082] The advantages of the above optional embodiments are as follows: by cooperating with the fourth NMOS transistor 9111, the fifth NMOS transistor 9112, the first PMOS transistor 9113, the second PMOS transistor 9114, and the sixth NMOS transistor 9121, the level of node B can be flexibly controlled, and the final output level can be precisely adjusted by the first inverter 9321, thereby realizing functions such as signal detection and level conversion, and accurately controlling the closing of the first switching unit 5.

[0083] The switching threshold of the low-voltage comparator 9 can be changed by adjusting the setting of resistor 9115, thereby adapting to the reverse connection protection of different batteries 2.

[0084] Optional, such as Figure 5 , Figure 8 and Figure 9 As shown, the comparator circuit 91 includes a second three-transistor 914 and a second comparator module 913. The first terminal of the second three-transistor 914 is connected to the output terminal of the lowest voltage selection circuit 92. The first input terminal of the second comparator module 913 is connected to the second terminal of the second three-transistor 914. The second input terminal of the second comparator module 913 is connected to the power supply terminal of the control circuit 1. The output terminal of the second comparator module 913 is connected to the input terminal of the comparator output stage 93.

[0085] Optional, such as Figure 8 and Figure 9 As shown, the comparator output stage 93 includes a second inverter 932 and a third inverter 933. The input terminal of the second inverter 932 is connected to the output terminal of the second comparator module 913, the input terminal of the third inverter 933 is connected to the output terminal of the second inverter 932, and the output terminal of the third inverter 933 is connected to the first switching unit 5.

[0086] like Figure 8 As shown, the second comparator module 913 includes a seventh NMOS transistor 9131, an eighth NMOS transistor 9132, a third PMOS transistor 9133 and a fourth PMOS transistor 9134, and the second triode 914 includes a ninth NMOS transistor 9141;

[0087] The gate of the seventh NMOS transistor 9131, the gate of the eighth NMOS transistor 9132, and the source of the ninth NMOS transistor 9141 are all connected to the output of the minimum voltage selection circuit 92; the source of the seventh NMOS transistor 9131 and the source of the eighth NMOS transistor 9132 are all connected to the drain of the ninth NMOS transistor 9141; the gate of the ninth NMOS transistor 9141 is grounded.

[0088] The source of the third PMOS transistor 9133 is grounded, and the drain of the third PMOS transistor 9133 is connected to the drain of the seventh NMOS transistor 9131.

[0089] The gate of the third PMOS transistor 9133, the gate of the fourth PMOS transistor 9134, the drain of the fourth PMOS transistor 9134, and the drain of the eighth NMOS transistor 9132 are all connected to node B. The input of the comparator output stage 93 is connected between the drain of the eighth NMOS transistor 9132 and node B.

[0090] The source of the fourth PMOS transistor 9134 is connected to the power supply terminal of control circuit 1.

[0091] In the above optional embodiments, it should be noted that the seventh NMOS transistor 9131, the eighth NMOS transistor 9132 and the ninth NMOS transistor 9141 are all depletion-type NMOS transistors.

[0092] The comparator circuit 91, formed by combining the second transistor 914 and the second comparator module 913, utilizes the substrate bias effect of the MOS transistor.

[0093] The substrate terminals of the third PMOS transistor 9133 and the fourth PMOS transistor 9134 are connected to different potentials. The power supply terminal VDD1 of the control circuit is lower than the ground terminal VSS. Therefore, the threshold voltage of the fourth PMOS transistor 9134 is less than the threshold voltage of the third PMOS transistor 9133. Assuming that the threshold voltage of the fourth PMOS transistor 9134 is -0.2V and the threshold voltage of the third PMOS transistor 9133 is -0.7V, the fourth PMOS transistor 9134 is connected as a diode and is turned on. The potential at node B is near -0.2V, and the third PMOS transistor 9133 cannot be turned on. The current generated by the ninth NMOS transistor 9141 flows entirely to the branch of the fourth PMOS transistor 9134. Point B is pulled to a relatively high level. After passing through the second inverter 9321 and the third inverter 9322, the output signal_select signal is higher than the output voltage VB of the lowest voltage selection circuit 92, controlling the first switch unit 5 to close at this time.

[0094] The seventh NMOS transistor 9131, the eighth NMOS transistor 9132, and the ninth NMOS transistor 9141 can all be replaced by NPN transistors. The specific circuit diagram can be adjusted according to the actual situation, which will not be discussed in detail here.

[0095] Both the third PMOS transistor 9133 and the fourth PMOS transistor 9134 can be replaced by PNP transistors. The specific circuit diagram can be adjusted according to the actual situation, which will not be discussed in detail here.

[0096] Optional, such as Figure 9 As shown, the second comparator module 913 includes a tenth NMOS transistor 9135, an eleventh NMOS transistor 9136, a fifth PMOS transistor 9137 and a sixth PMOS transistor 9138, and the second triode 914 includes a twelfth NMOS transistor 9142 and a thirteenth NMOS transistor 9143;

[0097] The source of the tenth NMOS transistor 9135 and the source of the eleventh NMOS transistor 9136 are both connected to the drain of the thirteenth NMOS transistor. The gate of the twelfth NMOS transistor 9142 and the source of the thirteenth NMOS transistor 9143 are connected to the output of the minimum voltage selection circuit 92. The drain of the twelfth NMOS transistor 9142 is connected to the source of the thirteenth NMOS transistor. The gate of the thirteenth NMOS transistor is grounded.

[0098] The drain and gate of the fifth PMOS transistor 9137 are both connected to the drain of the tenth NMOS transistor 9135, the drain of the sixth PMOS transistor 9138 is connected to the drain of the eleventh NMOS transistor 9136, and the input terminal of the second inverter 9231 is connected between the drain of the sixth PMOS transistor 9138 and the drain of the eleventh NMOS transistor 9136.

[0099] The gate of the tenth NMOS transistor 9135 is grounded, the gate of the eleventh NMOS transistor 9136 is connected to the power supply terminal of the control circuit, and the source of the fifth PMOS transistor 9137 and the source of the sixth PMOS transistor 9138 are both connected to the power supply terminal of the control circuit.

[0100] In the above optional embodiments, it should be noted that the tenth NMOS transistor 9135, the eleventh NMOS transistor 9136 and the twelfth NMOS transistor 9142 are all depletion-type NMOS transistors;

[0101] The tenth NMOS transistor 9135, the eleventh NMOS transistor 9136, the twelfth NMOS transistor 9142, and the thirteenth NMOS transistor 9143 can all be replaced by NPN transistors. The specific circuit diagram can be adjusted according to the actual situation, which will not be discussed in detail here.

[0102] Both the fifth PMOS transistor 9137 and the sixth PMOS transistor 9138 can be replaced by PNP transistors. The specific circuit diagram can be adjusted according to the actual situation, which will not be discussed in detail here.

[0103] By setting the dimensions of the twelfth NMOS transistor 9142 and the thirteenth NMOS transistor 9143, when the power supply voltage VDD1 of the control circuit 1 is less than the ground voltage VSS, the eleventh NMOS transistor 9136 is cut off, and the output at point B is relatively high. After passing through the second inverter 9321 and the third inverter 9322, the output signal_select signal is high relative to VB, controlling the first switching unit 5 to close at this time.

[0104] The advantages of the above optional embodiments are as follows: The above scheme can monitor the power supply voltage status in real time, thereby detecting whether the battery 2 is reverse-connected. When the power supply voltage VDD1 of the control circuit 1 is abnormal, the protection mechanism is quickly triggered, closing the first switching unit 5, which can prevent the circuit from being damaged due to power supply failure. By using the size design of the NMOS transistor to adjust the threshold and response characteristics of the circuit, precise control of the first switching unit 5 is achieved, improving the reliability and stability of the circuit.

[0105] A second aspect of the present invention provides an analog power chip that includes all the technical features of the battery reverse connection protection circuit of the first aspect of the present invention.

[0106] The above description is merely a preferred embodiment of the present invention, but the scope of protection of the present invention is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the technical scope disclosed in the present invention should be included within the scope of protection of the present invention. Therefore, the scope of protection of the present invention should be determined by the scope of the claims.

Claims

1. A battery reverse connection prevention circuit, characterized by comprising: The control circuit, the protection module, the first switch unit and the first NMOS tube are included. The power supply end of the control circuit is connected with the first power supply end. The gate of the first NMOS tube is connected with the first output end of the control circuit, and the drain of the first NMOS tube is connected with the second power supply end. One end of the protection module is connected with the power supply end of the control circuit, and the other end of the protection module is grounded. The first switch unit is connected between the drain of the first NMOS tube and the substrate of the first NMOS tube, and the second output end of the control circuit is connected with the first switch unit. When the battery is connected in positive, the source of the first NMOS tube is connected with the negative pole of the battery, and the control circuit is used for controlling the first NMOS tube to be turned on or turned off. When the battery is connected in reverse, the source of the first NMOS tube is connected with the positive pole of the battery, and the control circuit controls the first switch unit to be closed. The first power supply end and the second power supply end are used for connecting the charger or the load, and the control circuit further includes a low-voltage comparator, the low-voltage comparator is integrated on the control circuit, the first input end of the low-voltage comparator is grounded, the second input end of the low-voltage comparator is connected with the power supply end of the control circuit, the output end of the low-voltage comparator is connected with the first switch unit, and the low-voltage comparator includes a minimum voltage selection circuit, a comparator circuit and a comparator output stage: The first input end of the minimum voltage selection circuit is connected with the second power supply end, the second input end of the minimum voltage selection circuit is grounded, and the output end of the minimum voltage selection circuit is connected with the first input end of the comparator circuit. The second input end of the comparator circuit is connected with the power supply end of the control circuit, the output end of the comparator circuit is connected with the input end of the comparator output stage, the output end of the comparator output stage is connected with the first switch unit, and the comparator circuit includes a second triode and a second comparator module. The first end of the second triode is connected with the output end of the minimum voltage selection circuit. The first input end of the second comparator module is connected with the second end of the second triode, the second input end of the second comparator module is connected with the power supply end of the control circuit, the output end of the second comparator module is connected with the input end of the comparator output stage, and the second comparator module includes a seventh NMOS tube, an eighth NMOS tube, a third PMOS tube and a fourth PMOS tube, and the second triode includes a ninth NMOS tube. The gate of the seventh NMOS tube, the gate of the eighth NMOS tube and the source of the ninth NMOS tube are all connected with the output end of the minimum voltage selection circuit, the source of the seventh NMOS tube and the source of the eighth NMOS tube are both connected with the drain of the ninth NMOS tube, and the gate of the ninth NMOS tube is grounded. The source of the third PMOS tube is grounded, and the drain of the third PMOS tube is connected with the drain of the seventh NMOS tube. The gate of the third PMOS tube, the gate of the fourth PMOS tube, the drain of the fourth PMOS tube and the drain of the eighth NMOS tube are connected with a node B, and the input end of the comparator output stage is connected between the drain of the eighth NMOS tube and the node B; The source of the fourth PMOS tube is connected with the power supply end of the control circuit.

2. The battery reverse connection prevention circuit according to claim 1, characterized by, The lowest voltage selection circuit comprises a second NMOS tube and a third NMOS tube; The gate of the second NMOS tube is connected with the second power supply end, and the gate of the third NMOS tube is grounded; The drain of the second NMOS tube is grounded, and the drain of the third NMOS tube is connected with the second power supply end; The source of the second NMOS tube and the source of the third NMOS tube are connected with the first input end of the comparator circuit.

3. The battery reverse connection prevention circuit according to claim 2, characterized by, The comparator circuit comprises a first comparator module and a first three-transistor; The first end of the first three-transistor is connected with the output end of the lowest voltage selection circuit; The first input end of the first comparator module is connected with the second end of the first three-transistor, the second input end of the first comparator module is connected with the power supply end of the control circuit, and the output end of the first comparator module is connected with the comparator output stage.

4. The battery reverse connection prevention circuit according to claim 3, wherein The comparator output stage comprises a first inverter; The input end of the first inverter is connected with the output end of the first comparator module, and the output end of the first inverter is connected with the first switch unit.

5. The battery reverse connection prevention circuit according to claim 4, wherein The first comparator module comprises a fourth NMOS tube, a fifth NMOS tube, a first PMOS tube and a second PMOS tube, and the first three-transistor comprises a sixth NMOS tube; The gate of the fourth NMOS tube, the gate of the fifth NMOS tube and the source of the sixth NMOS tube are connected with the output end of the lowest voltage selection circuit; the source of the fourth NMOS tube and the source of the fifth NMOS tube are connected with the drain of the sixth NMOS tube; and the gate of the sixth NMOS tube is grounded; The drain of the first PMOS tube, the gate of the first PMOS tube and the gate of the second PMOS tube are connected with the drain of the fourth NMOS tube, the drain of the fifth NMOS tube is connected with the drain of the second PMOS tube, the input end of the first inverter is connected between the drain of the fifth NMOS tube and the drain of the second PMOS tube, the source of the first PMOS tube is grounded, and the source of the second PMOS tube is connected with the power supply end of the control circuit.

6. The battery reverse connection prevention circuit according to claim 1, wherein The comparator output stage comprises a second inverter and a third inverter; The input end of the second inverter is connected with the output end of the second comparator module; The input end of the third inverter is connected with the output end of the second inverter, and the output end of the third inverter is connected with the first switch unit.

7. An analog power chip, characterized by The battery reverse connection protection circuit comprises the battery reverse connection protection circuit according to any one of claims 1 to 6.

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