Error polarity detection for timing skew calibration

Abstract

The invention relates to error polarity detection for timing skew calibration. An electronic circuit includes a plurality of analog-to-digital converters (ADCs), clock circuitry, and calibration circuitry. The clock circuitry is configured to provide a clock signal to the plurality of ADCs to advance the plurality of ADCs by time-interleaved analog-to-digital (A / D) conversion. The calibration circuitry is configured to determine a magnitude of a timing skew error between any two of the clock signals; applying a jitter sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC; an a polarity of the timing skew error is determined by determining a polarity of a gain experienced by the dither sequence from the time-interleaved A / D conversion.

Description

BACKGROUND

[0001] Electronic systems can include analog-to-digital (A / D) converters (ADCs). ADCs are circuits that convert analog signals into digital quantities to allow a processor of the electronic system to perform signal processing functions for the system. To improve the speed of A / D conversion, ADCs can be time-interleaved. When multiple ADCs are time-interleaved, each ADC samples an analog input signal at a certain rate, and the outputs of all of the ADCs are combined to produce a digital output sequence at a rate that corresponds to the rate of the individual ADCs multiplied by the number of time-interleaved ADCs. Thus, time-interleaved ADCs produce A / D conversion at a higher rate than individual ADCs operating independently. However, mismatches between the ADCs that make up a time-interleaved ADC present challenges to these systems. SUMMARY

[0002] This document relates generally to analog-to-digital converter (ADC) circuits, and in particular to improvements in the operation of time-interleaved ADCs. An exemplary electronic circuit includes a plurality of ADCs, clock circuitry, and calibration circuitry. The clock circuitry is configured to provide clock signals to the plurality of ADCs to advance the plurality of ADCs through time-interleaved analog-to-digital (A / D) conversion. The calibration circuitry is configured to determine a magnitude of a timing skew error between any two of the clock signals, apply a dithering sequence to a first clock signal of the any two clock signals, where the first clock signal is applied to a first ADC of the plurality of ADCs, and determine a polarity of the timing skew error by determining a polarity of a gain experienced by the dithering sequence from the time-interleaved A / D conversion.

[0003] This section is intended to provide an overview of subject matter of the present patent application. It is not intended to provide an exclusive or exhaustive explanation of the application. The detailed description is included to provide further information about the present patent application. BRIEF DESCRIPTION OF DRAWINGS

[0004] In the drawings, which are not necessarily drawn to scale, like numerals can describe similar components in different views. Like numerals having different letter suffixes can represent different instances of similar components. The drawings illustrate generally, by way of example, various embodiments discussed in the present document.

[0005] Figure 1 FIG. is an example of bi-directional time-interleaved A / D conversion.

[0006] Figure 2 FIG. is a circuit diagram of an exemplary bi-directional time-interleaved ADC.

[0007] Figure 3is a graph showing A / D conversion of an input signal in the frequency domain.

[0008] Figure 4 is a graph showing timing of A / D conversion of an input signal without timing skew error.

[0009] Figure 5 is a graph showing timing of A / D conversion of an input signal with timing skew error.

[0010] Figure 6 is a circuit diagram of an exemplary bi-directional time-interleaved ADC and calibration circuitry.

[0011] Figure 7 is a circuit diagram of an exemplary time-interleaved ADC and timing skew polarity detection circuitry.

[0012] Figure 8 is a flowchart of an example of a method of determining and correcting timing skew in bi-directional time-interleaved A / D conversion. DETAILED DESCRIPTION

[0013] By time-interleaving the conversions of multiple A / D converters (ADCs), the rate of analog-to-digital (A / D) conversion can be improved. For example, a first ADC circuit can perform a conversion while a second ADC circuit samples an input. This eliminates the sampling time from the time used for conversion. More than two ADCs can be time-interleaved, with the phase of each of the multiple ADCs staggered from the phases of the other ADCs to create a conversion "pipeline" in which conversion results are produced faster than the conversion rate of any one ADC. However, challenges can exist in time-interleaved A / D conversion that limit the accuracy of the overall output of the system.

[0014] Figure 1 is a schematic diagram of exemplary bi-directional time-interleaved A / D conversion. ADC 102 samples and converts one analog input signal x(t) to a digital quantity. ADC 102 is time-interleaved and operates as a phase-shifted parallel A / D converter to provide a two-fold time reduction in the time required to complete A / D conversion. More ADCs 102 can be interleaved (e.g., 4, 5, 8, 12, 16, etc.) to further improve the overall A / D conversion rate.

[0015] Figure 1Interleaving of the acquisition and conversion operation states of the ADCs 102 is also shown. In this example, the sampling clock phases of the two ADCs 102 are 180° apart (360° / N, where N = 2. For N = 4, the sampling clock phases of the four ADCs would be 90° apart). A disadvantage of time-interleaved ADCs is that the overall output sequence of the time-interleaved ADCs can introduce interleaving conversion artifacts due to mismatches between the ADCs. These artifacts can cause errors in the A / D conversion. One source of error is timing mismatch between the sampling times of the time-interleaved ADCs. One cause of timing mismatch is the accuracy of the clock phase input to the ADCs.

[0016] Figure 2 is a circuit diagram of an example of two time-interleaved ADCs 102 and clock circuitry 206 that generates clock signals (clk0(t) and clk1(t)) that are used by each ADC 102, respectively, to sample an analog input signal x(t). The ADCs 102 can be referred to as sub-ADCs or ADC “slices”. In this example, the digital output sequences of the sub-ADCs are labeled y0[n] and y1[n]. Figure 2 An example waveform 208 of the clock signals is also shown, as well as the timing skew error (τ) between their phases as shown. In the absence of timing skew error, the transitions of the clock signals are aligned.

[0017] Figure 3 is a plot showing the expected A / D conversion of an analog input signal in the frequency domain, as well as artifacts of the conversion due to clock timing skew. The expected conversion of the analog input signal is centered at the frequency of the input signal f x , and the artifacts occur at ( 1 / 2f s – f x ), where f s is the sampling frequency of the time-interleaved ADC (i.e., the sampling rate of each sub-ADC is given by 1 / 2f s ).

[0018] Figure 4 is a time-domain plot showing the output samples of a two-way time-interleaved ADC obtained from an analog input signal x(t) in the absence of timing skew error. The converted values from the two slices of the interleaved A / D conversion are labeled Slice 0 (from ADC 0) and Slice 1 (from ADC 1). In the plot, the arrows show that the outputs from the slices of the two ADCs are uniformly spaced in time. Figure 5 is a time-domain plot that is nearly identical to Figure 4 , except Figure 5The diagram takes into account the effect of timing skew error. The arrows show that the slices from the two ADCs are not evenly spaced. Figure 5 In the figure, the slice 0 transition to the left of the slice 1 transition is closer to the slice 1 transition than the slice 0 transition to the right of the slice 1 transition. Figure 4 and Figure 5 In , three adjacent transformations are labeled y0[n], y1[n–1], and y0[n–1], where the subscripts indicate which slice each transformation corresponds to. Figure 4 In the absence of timing skew errors, adjacent transition pairs are evenly spaced in time. Therefore, for some input signals, on average, y1[n–1] is equally similar to y0[n] and y0[n–1]. Figure 5 In , due to timing skew errors, adjacent pairs of transitions are not evenly spaced in time. As a result, for some input signals, y1[n–1] is, on average, more similar to y0[n–1] than to y0[n].

[0019] Figure 6 is a system diagram illustrating exemplary two-way time-interleaved A / D conversion and calibration circuitry 610 for calibrating clock circuitry 206 to reduce timing skew errors in clock signals provided to sub-ADCs 102. To reduce clock skew, calibration circuitry 610 determines the similarity between adjacent conversions passing through sub-ADCs 102, and calibration circuitry 610 adjusts the relative timing of the clock signals so that, on average, adjacent pairs of conversions are equally similar (e.g., so that y0[n-1] and y1[n-1] are equally similar to y0[n] and y1[n-1]).

[0020] In some examples, calibration circuitry 610 determines a first measure of similarity between an A / D conversion by ADC1 and an A / D conversion by ADC0 that immediately precedes the A / D conversion by ADC1, and determines a second measure of similarity between the A / D conversion by ADC1 and an A / D conversion by ADC0 that follows the A / D conversion by ADC1. Different methods may be used to determine the similarity of the A / D conversions, and Figure 6 The circuit diagram is only an example.

[0021] exist Figure 6 In the system diagram of FIG, the first measure of similarity is c0[p] and the second measure of similarity is c1[p]. Calibration circuitry 610 includes a digital delay (shown as z –1 ), multiplier 612, block average accumulator 614 (whose output is divided by the number of accumulated samples N, and the accumulator is reset after each accumulation), difference node 616 and a forward gain μ tThe calibration circuit system 610 may also include a microcontroller, a processor (eg, a microprocessor), an application specific integrated circuit (ASIC), a programmable gate array (PGA), etc. Delay z –1 One or more of the multiplier 612, the block average accumulator 614, the difference node 616, and the accumulator 618 may be implemented by a microcontroller.

[0022] Multiplier 612 forms the product of the A / D conversions including y0[n–1]y1[n–1] and y0[n]y1[n–1]. Multiple products of N A / D conversions (e.g., N=1000) are summed and averaged by block average accumulator 614. After N samples are averaged, block average accumulator 614 is reset. The averaged products are the measures of similarity c0[p] and c1[p]. The difference between the measures of similarity is generated by difference node 616. Accumulator 618 uses the difference in the similarity measures to generate an estimate of the timing skew error τ est [p], and calibration circuitry 610 is based on τ est [p] is used to adjust the clock signal clk1(t) to reduce the effective timing skew error. The waveform 208 of the clock signal shows that the positive transition of clk1(t) lags the negative transition of clk0(t), but the skew may also cause the positive transition of clk1(t) to lead the negative transition of clk0(t). est The polarity of [p] determines whether calibration circuitry 610 alters the clock signal to advance or delay the phase transition of clk1(t) to reduce timing skew errors.

[0023] When the frequency of the input signal x(t) is within the known Nyquist zone of the time-interleaved ADC, Figure 6 The method shown in is valid. Figure 6 In the example of , if the sub-ADCs are each 5 gigasamples per second (5 GSPS) ADCs, then the time-interleaved A / D conversion increases the first Nyquist zone from 2.5 GHz to 5 GHz. However, there may be implementations where the sub-ADCs receive input signals at frequencies higher than the first Nyquist zone of the time-interleaved ADCs. In such cases, the difference in the similarity metric may correspond to a timing skew error multiplied by a noise metric of minus one, which would result in an estimated timing skew error τ determined by the calibration circuitry 610. est [p] deviates from its ideal value and, therefore, degrades performance. A / D conversion of a signal that falls in an unknown Nyquist zone or that falls in multiple Nyquist zones may erroneously reverse the polarity of the error measurement.

[0024] Figure 7 is a system diagram of another example of a two-way time-interleaved A / D conversion that injects dither into a phase of a clock signal. To reliably determine the polarity of the estimated timing skew error, in Figure 7 In the example of FIG. 6, a known pseudo-random dither sequence d[n] is injected into the phase of the clk1(t) clock signal. The dither sequence d[n] can be a two-level zero-mean sequence that takes values of -1 and +1 with equal probability. Other dither sequences with other properties can also be used. With the injected dither sequence, the timing skew error is given by τ - τ est [p] + Td[n], where T is the gain (e.g., in femtoseconds) experienced by the dither sequence d[n] when injected into the phase of the clock signal clk1(t). From the perspective of the output of the time-interleaved ADC 102, the sequence Td[n] experiences the same gain A as the residual timing skew error τ - τ est [p] that needs to be measured. Thus, the polarity of the timing skew error measurement can be extracted from the polarity of the gain experienced by the dither sequence by the time-interleaved A / D conversion.

[0025] One method of extracting the polarity of the gain experienced by the sequence Td[n] is to associate the product of the multipliers 612 y0[n - 1] y1[n - 1] and y0[n] y1[n - 1] with the dither sequence d[n]. Figure 7 The calibration circuitry of FIG. 6 includes multipliers 720 that produce the products d[n - 1] y0[n - 1] y1[n - 1] and d[n - 1] y0[n] y1[n - 1], and includes a block average accumulator 724 to accumulate and average the difference of the products produced by the difference node 722. The extracted gain A est [p] is an estimate of the gain A that can be filtered to mitigate measurement noise. The extracted A est [p] can be used to determine the polarity of the timing skew error measurement performed by the calibration circuitry 610, which results in the estimated timing skew error τ est [p] being correctly updated.

[0026] Figure 8 is a flowchart of an example of a method 800 of determining and correcting for a timing skew error in a two-way time-interleaved A / D conversion. An analog signal is converted to a series of digital values using time-interleaved ADCs. The method 800 can be performed using the circuitry of Figure 6 and Figure 7 At block 805, the analog signal is converted to a sequence of digital values by time-interleaved A / D conversion by a plurality of ADCs according to a plurality of clock signals applied to the ADCs. The sampling clock signals have a defined phase relationship between them.

[0027] At block 810, a magnitude of a timing skew error in a clock signal of the ADC is determined. The timing skew error can be between any two clock signals applied to the ADC.

[0028] At block 815, a dither sequence is applied to a phase of a first clock signal of the two clock signals having the timing skew error. The first clock signal is applied to a first ADC of the plurality of ADCs, and a second clock signal of the two clock signals is applied to another ADC. At block 820, a polarity of a gain experienced by the dither sequence at an output of the circuitry is determined. The polarity of the gain is a polarity of the timing skew error measurement. At block 825, the second clock signal is adjusted using a calibration loop. The determined magnitude and polarity of the timing skew error measurement are used to reduce the timing skew error.

[0029] In the presence of an input signal that can span multiple unknown Nyquist zones, the time-interleaved ADCs described herein operate with reduced timing skew error between clock signals of the ADCs. The reduced timing skew error improves matching between slices of the interleaved ADCs and reduces errors associated with interleaved A / D conversion.

[0030] Additional descriptions and embodiments

[0031] A first embodiment (Embodiment 1) includes subject matter (such as an electronic circuit) comprising a plurality of analog-to-digital converters (ADCs); clock circuitry configured to provide clock signals to the plurality of ADCs to advance the plurality of ADCs by time-interleaved analog-to-digital (A / D) conversion; and calibration circuitry. The calibration circuitry is configured to: determine a magnitude of a timing skew error between any two of the clock signals; apply a dither sequence to a first clock signal of the any two clock signals, wherein the first clock signal is applied to a first ADC of the plurality of ADCs; and determine a polarity of the timing skew error by determining a polarity of a gain experienced by the dither sequence from the time-interleaved A / D conversion.

[0032] In Embodiment 2, the subject matter described in Embodiment 1 optionally includes calibration circuitry configured to adjust a phase relationship of the first clock signal and the second clock signal of the two clock signals in accordance with the determined magnitude and polarity of the timing skew error.

[0033] In embodiment 3, the subject matter of one or both of embodiments 1 and 2 optionally includes calibration circuitry configured to determine a first measure of similarity of the A / D conversion by the first ADC to a previous A / D conversion by the other ADC, determine a second measure of similarity of the A / D conversion by the first ADC to a subsequent A / D conversion by the other ADC, compute a difference between the first measure of similarity and the second measure of similarity as a magnitude of a timing skew error, and adjust a phase of the first clock signal relative to a phase of the other clock signal to minimize the difference between the first measure of similarity and the second measure of similarity.

[0034] In embodiment 4, the subject matter of embodiment 3 optionally includes calibration circuitry configured to determine a plurality of first products of the A / D conversion of the first ADC and the A / D conversion of the other ADC preceding the A / D conversion of the first ADC, determine a plurality of second products of the A / D conversion of the first ADC and the A / D conversion of the other ADC following the A / D conversion of the first ADC, and average the plurality of first products to determine the first measure of similarity and average the plurality of second products to determine the second measure of similarity.

[0035] In embodiment 5, the subject matter of one or any combination of embodiments 1 to 4 optionally includes calibration circuitry configured to apply a dithering sequence to the calibration circuitry to vary the phase of the first clock signal according to the dithering sequence.

[0036] In embodiment 6, the subject matter of embodiment 5 optionally includes calibration circuitry configured to extract a gain experienced by the dithering sequence by associating the difference between pairs of A / D conversions to the dithering sequence.

[0037] In embodiment 7, the subject matter of one or both of embodiments 5 and 6 optionally includes calibration circuitry configured to determine a first product of the A / D conversion of the first ADC at a first sampling time and the A / D conversion of the other ADC at a sampling time preceding the first sampling time, determine a second product of the A / D conversion of the first ADC at the first sampling time and the A / D conversion of the other ADC at a sampling time following the first sampling time, and determine a polarity of a gain experienced by the dithering sequence by associating a value of the dithering sequence to a difference between the first product and the second product.

[0038] In embodiment 8, the subject matter of one or any combination of embodiments 1-7 optionally includes calibration circuitry configured to adjust a phase of the first clock signal by a magnitude of the determined timing skew error relative to a phase of the other clock signal according to a polarity of a gain experienced by the determined dithering sequence.

[0039] In embodiment 9, the subject matter of one or any combination of embodiments 1-8 optionally includes a plurality of ADCs that produce time-interleaved A / D conversion of an input analog signal having signal components in a plurality of Nyquist zones.

[0040] Embodiment 10 includes subject matter (such as a method of processing an analog signal) or can optionally be combined with one or any combination of embodiments 1-9 to include such subject matter comprising time-interleaving analog-to-digital (A / D) conversion of an analog signal using a plurality of analog-to-digital converters (ADCs) according to a plurality of clock signals applied to the plurality of ADCs, determining a magnitude of a timing skew error between any two clock signals of the plurality of clock signals, applying a dithering sequence to a phase of a first clock signal of the two clock signals, wherein the first clock signal is applied to a first ADC of the plurality of ADCs, and determining a polarity of the timing skew error by determining a polarity of a gain experienced by the dithering sequence through the time-interleaved A / D conversion.

[0041] In embodiment 11, the subject matter of embodiment 10 optionally includes adjusting the phase of the first clock signal relative to a phase of a second clock signal of the two clock signals according to the determined magnitude and polarity of the timing skew error.

[0042] In embodiment 12, the subject matter of one or both of embodiments 10 and 11 optionally includes determining a first measure of similarity of the time-interleaved A / D conversion of the first ADC to a preceding time-interleaved A / D conversion of another ADC, determining a second measure of similarity of the time-interleaved A / D conversion of the first ADC to a subsequent time-interleaved A / D conversion of the other ADC, computing a difference between the first measure of similarity and the second measure of similarity, and adjusting the phase of the first clock signal relative to a phase of the other clock signal to minimize the difference between the first measure of similarity and the second measure of similarity.

[0043] In Example 13, the subject matter of Example 12 optionally includes determining a plurality of first products of the A / D conversion of the first ADC and the A / D conversion of the other ADC before the A / D conversion of the first ADC, averaging the plurality of first products to determine a first measure of similarity, determining a plurality of second products of the A / D conversion of the first ADC and the A / D conversion of the other ADC after the A / D conversion of the first ADC, and averaging the plurality of second products to determine a second measure of similarity.

[0044] In Example 14, the subject matter of one or any combination of Examples 10-13 optionally includes time interleaving of A / D conversion of an input analog signal having signal components in a plurality of Nyquist zones.

[0045] In Example 15, the subject matter of one or any combination of Examples 10-14 optionally includes changing a phase of the first clock signal according to a dither sequence.

[0046] In Example 16, the subject matter of Example 15 optionally includes associating the dither sequence with a difference between adjacent pairs of interleaved A / D conversions.

[0047] In Example 17, the subject matter of one or both of Examples 15 and 16 optionally includes determining a first product of the A / D conversion of the other ADC at a first sampling time and the A / D conversion of the first ADC at a previous sampling time before the first sampling time, determining a second product of the A / D conversion of the first ADC at the previous sampling time and the A / D conversion of the other ADC at the previous sampling time, and associating a value of the dither sequence at the previous sampling time with a difference of the first product and the second product.

[0048] In Example 18, the subject matter of one or any combination of Examples 10-17 optionally includes adjusting the phase of the first clock signal by a magnitude of the determined timing skew error relative to a phase of the other clock signal according to a polarity of a gain experienced by the determined dither sequence.

[0049] Embodiment 19 includes subject matter such as a time-interleaved analog-to-digital converter (ADC) circuit, or can be optionally combined with one or any combination of embodiments 1 to 18 to include such subject matter, comprising a first sub-ADC, a second sub-ADC, clock circuitry configured to provide a first clock signal to the first sub-ADC and a second clock signal to the second sub-ADC to advance the first and second sub-ADCs through time-interleaved analog-to-digital (A / D) conversions; and calibration circuitry configured to apply a specified dither sequence to a clock phase of the second clock signal, extract a gain experienced by the dither sequence from the time-interleaved A / D conversions, and adjust a phase relationship between the first and second clock signals according to a polarity of the extracted gain.

[0050] In Example 20, the subject matter of Example 19 optionally includes calibration circuitry configured to determine a first measure of similarity of an A / D conversion by the second sub-ADC to a previous A / D conversion by the first sub-ADC, determine a second measure of similarity of an A / D conversion by the second sub-ADC to a subsequent A / D conversion by the first sub-ADC, calculate a difference between the first measure of similarity and the second measure of similarity, and adjust a phase of the second clock signal based on a polarity of the extracted gain to minimize the difference between the first measure of similarity and the second measure of similarity.

[0051] These non-limiting embodiments may be combined in any arrangement or combination. The above detailed description includes reference to the accompanying drawings, which form a part of the detailed description. The accompanying drawings show, by way of illustration, specific embodiments in which the invention may be practiced. These embodiments are also referred to herein as "embodiments". All publications, patents, and patent documents cited in this document are incorporated herein by reference in their entirety, even if individually incorporated by reference. In the event of inconsistent usages between this document and those documents so incorporated by reference, the usage in the incorporated references shall be deemed to supplement the usage of this document; for any inconsistencies, the usage in this document shall prevail.

[0052] In this document, the terms "a" or "an" are used, as is common in patent documents, to include one or more than one, independent of any other instances or usages of "at least one" or "one or more." In this document, the term "or" is used to refer to a nonexclusive or, such that "A or B" includes "A but not B," "B but not A," and "A and B," unless otherwise indicated. In the appended claims, the terms "including" and "in which" are used as the plain English equivalents of the respective terms "comprising" and "wherein." Also, in the following claims, the terms "including" and "comprising" are open-ended, that is, a system, device, article, or process that includes elements in addition to those listed after such a term in a claim are still deemed to fall within the scope of that claim. Moreover, in the following claims, the terms "first," "second," and "third," etc. are used merely as labels, and are not intended to impose numerical requirements on their objects. The method examples described herein can be machine or computer- implemented at least in part.

[0053] The above description is intended to be illustrative, and not restrictive. For example, the above-described embodiments (or one or more aspects thereof) can be used in combination with each other. Other embodiments will be apparent to those of ordinary skill in the art upon reviewing the above description. The Abstract is provided to comply with 37 C.F.R. § 1.72(b) to allow the reader to quickly ascertain the nature of the technical disclosure. It is submitted with the understanding that it will not be used to interpret or limit the scope or meaning of the claims. Also, in the above Detailed Description, various features can be grouped together to streamline the disclosure. This should not be interpreted as intending that the disclosed features are essential to any claim. Rather, inventive subject matter can lie in less than all features of a particular disclosed embodiment. Thus, the following claims are hereby expressly incorporated into this Detailed Description, with each claim standing on its own as a separate embodiment. The scope of the application should be determined, not by the Abstract, but by the appended claims and their full scope of equivalents.

Claims

1. An electronic circuit comprising: a plurality of analog-to-digital converters (ADCs); clock circuitry configured to provide clock signals to the plurality of ADCs to advance the plurality of ADCs through time-interleaved analog-to-digital (A / D) conversion; and calibration circuitry configured to: determine a magnitude of a timing skew error between any two of the clock signals; apply a dither sequence to a first of the any two clock signals, wherein the first clock signal is applied to a first of the plurality of ADCs; and determine a polarity of the timing skew error by determining a polarity of a gain experienced by the dither sequence from the time-interleaved A / D conversion.

2. The electronic circuit of claim 1, wherein the calibration circuitry is configured to adjust a phase relationship of the first and second of the two clock signals according to the determined magnitude and polarity of the timing skew error.

3. The electronic circuit of claim 1, wherein the calibration circuitry is configured to: determine a first measure of similarity of an A / D conversion by the first ADC to a previous A / D conversion by another ADC; determine a second measure of similarity of the A / D conversion by the first ADC to a subsequent A / D conversion by another ADC; calculate a difference between the first measure of similarity and the second measure of similarity as the magnitude of the timing skew error; and adjust the phase of the first clock signal relative to a phase of another clock signal to minimize the difference between the first measure of similarity and the second measure of similarity.

4. The electronic circuit of claim 3, wherein the calibration circuitry is configured to: determine a plurality of first products of A / D conversions of the first ADC and another ADC preceding the A / D conversion of the first ADC; determine a plurality of second products of the A / D conversion of the first ADC and another ADC following the A / D conversion of the first ADC; and average the plurality of first products to determine the first measure of similarity and average the plurality of second products to determine the second measure of similarity.

5. The electronic circuit of claim 1, wherein the calibration circuitry is configured to apply the dither sequence to the calibration circuitry to change a phase of the first clock signal according to the dither sequence.

6. The electronic circuit of claim 5, wherein the calibration circuitry is configured to extract the gain experienced by the dither sequence by correlating a difference between pairs of A / D conversions to the dither sequence.

7. The electronic circuit of claim 5, wherein the calibration circuitry is configured to: determine a first product of an A / D conversion of the first ADC at a first sampling time and an A / D conversion of another ADC at a sampling time preceding the first sampling time; determine a second product of the A / D conversion of the first ADC at the first sampling time and an A / D conversion of another ADC at a sampling time following the first sampling time; and calculate a difference between the first product and the second product as the gain experienced by the dither sequence. ​ determining a second product of A / D conversion of the first ADC at the first sampling time and A / D conversion of another ADC at a sampling time after the first sampling time; and determining the polarity of the gain experienced by the dither sequence by correlating values of the dither sequence with differences between the first product and the second product.

8. The electronic circuit of claim 1, wherein the calibration circuitry is configured to adjust a phase of the first clock signal by a magnitude of the determined timing skew error relative to a phase of another clock signal according to the determined polarity of the gain experienced by the dither sequence.

9. The electronic circuit of claim 1, wherein the plurality of ADCs produce time-interleaved A / D conversion of an input analog signal having signal components in a plurality of Nyquist zones.

10. A method of processing an analog signal, the method comprising: time-interleaving analog-to-digital (A / D) conversion of the analog signal using a plurality of analog-to-digital converters (ADCs) according to a plurality of clock signals applied to the plurality of ADCs; determining a magnitude of a timing skew error between any two clock signals of the plurality of clock signals; applying a dither sequence to a phase of a first clock signal of the two clock signals, wherein the first clock signal is applied to a first ADC of the plurality of ADCs; and determining a polarity of the timing skew error by determining a polarity of a gain experienced by the dither sequence from the time-interleaved A / D conversion.

11. The method of claim 10, comprising adjusting a phase of the first clock signal relative to a phase of a second clock signal of the two clock signals according to the determined magnitude and polarity of the timing skew error.

12. The method of claim 10, wherein the determining the magnitude of the timing skew error comprises: determining a first measure of similarity of a time-interleaved A / D conversion of the first ADC to a preceding time-interleaved A / D conversion of another ADC; determining a second measure of similarity of the time-interleaved A / D conversion of the first ADC to a subsequent time-interleaved A / D conversion of another ADC; and computing a difference between the first measure of similarity and the second measure of similarity; and adjusting a phase of the first clock signal relative to a phase of another clock signal to minimize the difference between the first measure of similarity and the second measure of similarity.

13. The method of claim 12, wherein the determining the first measure of similarity comprises: determining a plurality of first products of A / D conversion of the first ADC and A / D conversion of another ADC preceding the A / D conversion of the first ADC; and averaging the plurality of first products to determine the first measure of similarity; wherein the determining the second measure of similarity comprises: determining a plurality of second products of the A / D conversion of the first ADC and A / D conversion of another ADC following the A / D conversion of the first ADC; and averaging the plurality of second products to determine the second measure of similarity. ​ ​ ​ averaging the plurality of second products to determine a second measure of the similarity.

14. The method of claim 10, wherein the time interleaving of A / D conversion of the analog signal comprises time interleaving of A / D conversion of an input analog signal having signal components in a plurality of Nyquist zones.

15. The method of claim 10, wherein the applying the dither sequence to the first clock signal comprises changing the phase of the first clock signal according to the dither sequence.

16. The method of claim 15, wherein the determining the polarity of the gain experienced by the dither sequence comprises correlating the dither sequence with a difference between adjacent interleaved pairs of A / D conversions.

17. The method of claim 15, wherein the determining the polarity of the gain experienced by the dither sequence comprises: determining a first product of A / D conversion of the first ADC at a first sample time and A / D conversion of another ADC at a sample time preceding the first sample time; determining a second product of A / D conversion of the first ADC at a first sample time and A / D conversion of another ADC at a sample time succeeding the first sample time; and associating a value of the dither sequence at the preceding sample time with a difference between the first product and the second product.

18. The method of claim 10, comprising adjusting a phase of the first clock signal by a magnitude of a determined timing skew error relative to a phase of another clock signal according to a determined polarity of the gain experienced by the dither sequence.

19. A time-interleaved analog-to-digital converter (ADC) circuit, the ADC circuit comprising: a first sub-ADC; a second sub-ADC; clock circuitry configured to provide a first clock signal to the first sub-ADC and a second clock signal to the second sub-ADC to advance the first sub-ADC and the second sub-ADC by time-interleaved analog-to-digital (A / D) conversion; and calibration circuitry configured to: apply a specified dither sequence to a clock phase of the second clock signal; extract a gain experienced by the dither sequence from the time-interleaved A / D conversion; and adjust a phase relationship of the first clock signal and the second clock signal according to a polarity of the extracted gain according to a polarity of the extracted gain.

20. The ADC circuit of claim 19, wherein the calibration circuitry is configured to: determine a first measure of similarity of A / D conversion by the second sub-ADC to a preceding A / D conversion by the first sub-ADC; determine a second measure of similarity of the A / D conversion of the second sub-ADC to a subsequent A / D conversion by the first sub-ADC; compute a difference between the first measure of similarity and the second measure of similarity; and ​ ​ ​ adjusting the phase of the second clock signal according to the polarity of the extracted gain to minimize the difference between a first measure of the similarity and a second measure of the similarity.

Images