Integrated inverted / non-inverted recovery high voltage conversion ratio capacitive load driver

Abstract

The invention relates to an integrated inverting / non-inverting recovery high voltage conversion ratio capacitive load driver. A driver circuit includes a series-parallel charge pump, wherein the series-parallel charge pump generates a plurality of coarse signal steps at a first output node and a second output node; a flying capacitor coupled between the first output node and the second output node; and a digital-to-analog converter (DAC) coupled between the first output node and the second output node, the DAC including a plurality of switched capacitors for generating a plurality of fine signal steps.

Description

TECHNICAL FIELD

[0001] The present invention relates generally to an integrated inverting / non-inverting recovery high voltage conversion ratio capacitive load driver and corresponding driving method. BACKGROUND

[0002] Microelectromechanical systems (MEMS) enable high levels of miniaturization, robustness and integration, as well as cost and manufacturing advantages such as flow soldering capabilities. As known in the art, MEMS devices are used as ultrasonic actuators and sensors in many applications. A typical MEMS equivalent circuit is generally represented by a capacitive load, which requires a high drive voltage significantly exceeding the battery voltage level compared to traditional inductive actuators. Due to the capacitive nature of MEMS actuator and sensor devices, the charging and discharging associated with periodic excitation, actuation or sensing requires high reactive power. This is especially true when modulating the MEMS device at high operating frequencies.

[0003] Most prior art drivers lack recovery capability and therefore completely dissipate all of their stored energy. This in turn results in excessive power dissipation and battery consumption, which is unacceptable for small form factor battery powered applications. A 200pF MEMS load driven without compensation at 30Vpp (peak to peak) at a frequency of 1 MHz results in a power dissipation of 180mW, or more than ten times the typical system power dissipation of, for example, a portable earbud or true wireless (TWS) earbud. Therefore, capacitive MEMS devices typically do not work with portable applications unless energy can be recovered in the face of high voltage conversion ratio and high operating frequency as mutually exclusive design goals.

[0004] High dynamic range applications, especially audio applications, require efficient driving over peak and typical least significant bit conversion (LSB) amplitudes in order to be energy efficient overall. Since recovery drops with decreasing amplitude for established known integrated capacitive MEMS drivers, significant recovery and sufficient efficiency cannot be achieved at typical playback with prior art concepts.

[0005] Figure 2 An example of a prior art driver circuit for driving a MEMS load is shown in FIG. 1. The driver circuit 200 includes differential inputs at nodes 210 and 212 for receiving a supply or input voltage V In . The driver circuit 200 includes multiple switching cells 202, 204 and 206, and an output cell 208. Switching cell 202 is coupled to flying capacitor circuit 228, switching cell 204 is coupled to flying capacitor circuit 230, and switching cell 206 is coupled to flying capacitor circuit 232. Each switching cell includes three switching transistors including transistors M ParP , MUp and M ParN .

[0006] In the switch unit 202, the transistor M ParP is coupled between nodes 210 and 214, the transistor M Up is coupled between nodes 210 and 216, and the transistor M ParN is coupled between nodes 212 and 216. The capacitor circuit 228 includes a capacitor C Fly coupled between nodes 214 and 216, a parasitic capacitance a T *C Fly coupled between node 214 and ground, and a parasitic capacitance a B *C Fly coupled between node 216 and ground, where a T indicates the fraction of the parasitic body capacitance relative to the flying capacitor.

[0007] In the switch unit 202, the transistor M ParP is coupled between nodes 210 and 214, the transistor M Up is coupled between nodes 210 and 216, and the transistor M ParN is coupled between nodes 212 and 216. The capacitor circuit 228 includes a capacitor C Fly coupled between nodes 214 and 216, a parasitic capacitance a T *C Fly coupled between node 214 and ground, and a parasitic capacitance a B *C Fly .

[0008] In the switch unit 204, the transistor M ParP is coupled between nodes 214 and 218, the transistor M Up is coupled between nodes 214 and 220, and the transistor M ParN is coupled between nodes 216 and 220. The capacitor circuit 230 includes a capacitor C Fly coupled between nodes 218 and 220, a parasitic capacitance a T *C Fly coupled between node 218 and ground, and a parasitic capacitance a B *C Fly .

[0009] In the switch unit 206, the transistor M ParP is coupled between nodes 218 and 222, the transistor M Upcoupled between nodes 218 and 224, and transistor M ParN coupled between nodes 220 and 224. Capacitor circuit 232 includes capacitor C Fly coupled between nodes 222 and 224, and capacitor a T C Fly coupled between nodes 222 and ground, and capacitor a B C Fly .

[0010] Finally, output unit 208 includes transistor M ParP coupled between nodes 222 and output node 226, and transistor M ParN Although driver circuit 200 includes several advantages, such as the use of low voltage transistors, it can be difficult in some applications to significantly increase the output voltage without suffering from parasitic power dissipation losses due to the number of switching units required. SUMMARY

[0011] According to an embodiment, a driver circuit includes a series-parallel charge pump including a plurality of switched capacitor units, wherein the series-parallel charge pump is configured for generating a plurality of coarse signal steps between a first output node and a second output node; a flying capacitor coupled between the first output node and the second output node; and a digital-to-analog converter (DAC) coupled between the first output node and the second output node, the digital-to-analog converter including a plurality of switched capacitors configured for generating a plurality of fine signal steps.

[0012] According to an embodiment, a driver circuit includes a series-parallel charge pump configured for generating a plurality of coarse signal steps; a digital-to-analog converter (DAC) coupled to the series-parallel charge pump, the digital-to-analog converter including a plurality of switched capacitors; and a flying capacitor inserted between the series-parallel charge pump and the DAC, wherein the DAC is configured for generating a plurality of fine signal steps and for charging the plurality of switched capacitors only when a load is coupled to the driver circuit.

[0013] According to an embodiment, a driver circuit includes a plurality of series- linked macro units, wherein each macro unit includes: a plurality of up-conversion units for generating a plurality of coarse signal steps; and a plurality of down-conversion units for generating a plurality of fine signal steps by dividing each coarse signal step. BRIEF DESCRIPTION OF DRAWINGS

[0014] For a more complete understanding of the present application and its advantages, reference is now made to the following description taken in conjunction with the accompanying drawings in which:

[0015] Figure 1 is a block diagram of a load driver circuit according to an embodiment;

[0016] Figure 2 is a schematic diagram of a prior art driver circuit;

[0017] Figure 3 is a schematic diagram of a load driver circuit according to an embodiment.

[0018] Figure 4 is a timing diagram for the load driver circuit of Figure 3

[0019] Figure 5A is a schematic diagram of a fine DAC according to another embodiment;

[0020] Figure 5B is a schematic diagram of a fine DAC according to another embodiment;

[0021] Figure 5C is a schematic diagram of a fine DAC according to another embodiment;

[0022] Figure 5D is a schematic diagram of a fine DAC according to another embodiment;

[0023] Figure 5E is a schematic diagram of a fine DAC according to another embodiment;

[0024] Figure 5F is a schematic diagram of a fine DAC according to another embodiment;

[0025] Figure 6 is a schematic diagram of a system including a load driver circuit according to an embodiment;

[0026] Figure 7 is a block diagram of a load driver circuit according to another embodiment; and

[0027] Figure 8 is a schematic diagram of a fine DAC according to another embodiment associated with the load driver circuit of Figure 7 DETAILED DESCRIPTION

[0028] The manufacture and use of the presently preferred embodiments will now be discussed in detail with reference to the figures. It should be appreciated that the specific embodiments discussed are merely illustrative of specific ways to make and use the application and do not limit the scope of the application.

[0029] ​​In the following detailed description, reference is made to the accompanying drawings, which form a part hereof, and in which are shown by way of illustration specific embodiments in which the application can be practiced. It is understood that other embodiments can be utilized and structural or logical changes can be made without departing from the scope of the present application. For example, the specific features described for an embodiment can be used on other embodiments or combined with other embodiments to produce yet other embodiments. The present application is intended to include these modifications and changes. The use of particular language in describing the examples is not intended to limit the scope of the claims. The drawings are not scaled, and are for illustrative purposes only. If not otherwise specified, identical or similar elements are denoted throughout the various figures by the same reference numbers. For the purpose of clarity, not all features of the embodiments described are necessarily shown in all of the figures.

[0030] According to embodiments, the wide dynamic range, recovery, high voltage conversion ratio, integrated capacitive load driver generates periodic or arbitrarily segmented waveforms with dynamically configurable frequency, amplitude, phase, and waveform shape. According to embodiments, the load driver operates at audio, ultrasonic, or other operating frequencies when modulating the capacitive load, and recovers energy at low amplitudes as well as high amplitudes. While embodiments of the present application are well suited to driving capacitive loads such as MEMS speakers, other types of loads that are not MEMS devices and are not primarily capacitive can also be driven. In some embodiments, the load can be differential and driven by two load drivers according to embodiments, as described in further detail later. According to embodiments, the load driver includes a single or dual (non-inverting and inverting) charge pump based on a configurable cap array, with flying capacitors operating in a parallel-series configuration, as the coarse step-up voltage converter provides (open circuit) positive multiples or positive and negative multiples of the input voltage at the output, and with a floating source of integrated switches and their gate drivers supplied from the flying capacitor referenced to the parallel-series charge pump level. According to embodiments, the load driver also includes a fine converter that provides one or more intermediate voltage levels between voltage levels at the last flying capacitor terminal(s) by referencing and providing a capacitance tank or capacitive divider from the same flying capacitor voltage(s) as the coarse converter. The intermediate voltage levels are used to step through intermediate levels, thereby increasing the number of steps in the step-up process beyond the number of coarse step range levels. These and other features of the load driver according to embodiments are described in further detail below.

[0031] The load driver circuit described below is counterintuitive because the fine converter adds parasitic loads to the series-shunt charge pump. The series-shunt (SP) charge pump boost function is extremely sensitive to load and parasitic capacitance, and the capacitive voltage divider network adds additional switching and parasitic capacitance losses to load the SP charge pump. In some prior art designs, the voltage boost function, voltage conversion ratio (VCR), and charge pump efficiency are affected by the additional parasitic capacitance and losses. However, according to embodiments, using the fine converter circuit described below, the reduction in dynamic losses outweighs the additional losses. Furthermore, the sub-regulation described in detail below advantageously increases the charge pump efficiency and VCR ratio of the SP charge pump.

[0032] Therefore, in an embodiment, the flying capacitor and the fine converter are configured to generate a plurality of fine signal steps and are implemented such that the plurality of switched capacitors are discharged and charged only when a load is coupled to the driver circuit, otherwise dynamic losses are minimized. This is because the flying capacitor and the fine converter act as a buffer and do not significantly load the SP charge pump when no load is present.

[0033] Figure 1 FIG. 1 is a block diagram of a load driver circuit 100 according to an embodiment. The load driver circuit 100 includes a bipolar series-parallel charge pump 106, which will be referred to below. Figure 3 The charge pump circuit shown is further described. The bipolar series-shunt charge pump 106 has a charge pump at node 108 (V P ) and node 110 (V N ) is coupled to the flying capacitor C FlyDAC The output of the series capacitor (SC) fine digital-to-analog converter (DAC) 112 has inputs coupled to nodes 108 and 110. Referring now to FIG. 5- Figure 8 The DAC circuit shown further describes the DAC 112. The bias capacitor C BIAS is coupled to the output of DAC 112 (V CP ) and node 114 (V L ). Load 118 is coupled to node 114. As previously described, load 118 may include a capacitive load, but may include any load, such as a resistive load or a sensor. Load driver circuit 100 may also include a resistor coupled between node 104 and V BIAS A quasi-static high impedance charge pump 116 is provided between the nodes. The charge pump 116 is advantageously independent of the AC excitation (V CP )Set V BIASBias voltage. The charge pump 116 can be implemented using any suitable low power charge pump implemented with techniques such as reduced drive strength, switching frequency, low quiescent current, and efficient circuit topology as known in the art. Low power charge pumps typically dissipate power in the range of microwatts or units of milliwatts. The bias resistor R BIAS is coupled between the V BIAS node and the node 114. Finally, the load driver circuit 100 can include an input DC-DC converter 102 for initial conditioning of the input voltage signal.

[0034] Figure 3 is a schematic diagram of a load driver circuit 300 according to an embodiment. The load driver circuit 300 is advantageously designed for driving a load, in particular a capacitive load, and comprises a dual rail charge pump 303 comprising a plurality of switched capacitor cells including at least a switched capacitor cell 302 and a switched capacitor cell 304, wherein the dual rail charge pump 303 is configured for generating a plurality of coarse signal steps between a first output node V DDN and a second output node V SSN . The load driver circuit 300 further comprises a flying capacitor C DDN coupled between the first output node V SSN and the second output node V FlyDAC . The load driver circuit 300 further comprises a fine digital-to-analog converter (DAC) 306 coupled between the first output node V DDN and the second output node V SSN , comprising a plurality of switched capacitors configured for generating a plurality of fine signal steps.

[0035] The dual rail charge pump 303 comprises at least the switched capacitor cell 302 and the switched capacitor cell 304, although more switched capacitor cells can be used to produce the required charge pump output voltage at the first output node V DDN and the second output node V SSN . The switched capacitor cell 302 comprises a plurality of switches including a first BYPASS switch coupled between the V In input node and the node 305, an UP switch coupled between the node 305 and the V In input node and the node 307, a DOWN switch coupled between the node 305 and ground, and a second BYPASS switch coupled between the node 307 and ground. The switched capacitor cell 304 comprises the same plurality of switches including a first BYPASS switch coupled between the node 305 and the first output node V DDN , an UP switch coupled between the node 305 and the second output node V SSNUP switch, coupled between node 307 and the first output node V DDN The DOWN switch between the node 307 and the second output node V SSN The switched capacitor unit 304 further includes a capacitor C coupled between the node 305 and the node 307. Fly If additional capacitor units are used, they will also include Figure 3 The capacitor C shown Fly .exist Figure 3 In, V In The voltage will be supplied by a constant battery voltage or output voltage of a sub-regulator or power converter. The constant battery voltage has a minimum voltage of approximately one or more volts, or other minimum voltage value determined by the semiconductor process used. Otherwise, the constant battery voltage is determined by the desired V DDN and V SSN The magnitude of the voltage and the number of switched capacitor units used determine the V Out The output is any analog segmented waveform generated by varying the number and timing of the various coarse and fine steps as described herein. In an embodiment, the generated output signal comprises or relates to an analog audio, speech, or music signal to drive a MEMS device (such as a direct drive), a parametric, or pumped MEMS speaker. Other MEMS and non-MEMS loads may also be driven.

[0036] The output of the bipolar series-parallel charge pump 303 is at the first output node V DDN With the second output node V SSN is coupled to the flying capacitor C FlyDAC Flying capacitor C FlyDAC It is part of the fine DAC or, in some embodiments, a separate component. The fine DAC 306 is described in more detail below.

[0037] The fine DAC 306 also includes an optional precharge circuit 308 and a decoder circuit 310 for supplying V Out The fine DAC 306 also includes a three-level switched capacitive voltage divider 314, which is also described below. In other embodiments, the voltage divider 314 may include fewer or additional levels.

[0038] The optional pre-charge circuit 308 includes switches S1, S2, S3, S4, S5, S6, S7, S8, S9, S10, S11, S12 and S13, and a capacitor C D1 、C D2 、C D3 and C D4 Capacitor C D1 、C D2, C D3 and C D4 are coupled in series to form voltage divider 312. Control nodes of switches SI, S2, S3, S4, S5, and S6 are controlled by an EQLZ equalization signal. Control nodes of switches S7, S8, S9, S10, S11, S12, and S13 are controlled by an INIT initialization signal. In Figure 3 the example, switch SI is coupled between node 309 and node 311, switch S2 is coupled between node 309 and node 313, and switch S3 is coupled between node 309 and node 315. Optional pre-charge circuit 308 also includes capacitor C D1 and switch S7, capacitor C D2 and switch S8, capacitor C D3 and switch S9 coupled in series between node 313 and node 315, and capacitor C SSN between node 309 and second output node V D4 . Switch S4 is coupled between second output node V SSN and the node between capacitor C D1 and switch S7, switch S5 is coupled between second output node V SSN and the node between capacitor CD2 and switch S8, and switch S6 is coupled between second output node V SSN and the node between capacitor C D3 and switch S9. Switch S10 is coupled between node 311 and first output node V DDN , switch SIl is coupled between node 313 and node 316, switch S12 is coupled between node 315 and node 318, and switch S13 is coupled between node 309 and node 320.

[0039] The timing of the EQLZ and INIT control signals and timing between them is described below. To initialize or refresh, capacitive voltage divider 312 can be initially or repeatedly charged by connecting capacitive voltage dividers C D1 , C D2 , C D3 , C D4 in parallel with flying capacitor C FlyDAC and can use periodic intermediate mutually exclusive equalization phases to equalize and balance the levels of DAC 306. The phases of the EQLZ and INIT signals are alternated as needed for initialization and refresh.

[0040] Voltage divider 314 includes capacitor C DDN coupled between first output node V S1, coupled between the first output node V DDN and node 318 S2 , coupled between the second output node V SSN and node 318 S3 , and coupled between the second output node V SSN and node 320 S4 .

[0041] In operation, in some embodiments, each of the capacitors C D1 , C D2 , C D3 , and C D4 has an equal value. Further, in some embodiments, each of the capacitors C S1 , C S2 , C S3 , and C S4 also has an equal value. In the example where the voltage at node 316 is 3 / 4 of the value of (V DDN -V SSN ), the voltage at node 318 is 1 / 2 of the value of (V DDN -V SSN ), and the voltage at node 320 is 1 / 4 of the value of (V DDN -V SSN ), all voltages are referenced to the V SSN voltage. Figure 3

[0042] The fine DAC 306 also includes a decoder 310 that includes a switch S DDN , coupled between the first output node V Out and the V PN output voltage node of the fine DAC 306, a switch F Out , coupled between node 316 and the V Dm+1 output voltage node of the fine DAC 306, a switch F Out , coupled between node 318 and the V Dm output voltage node of the fine DAC 306, a switch F Out , coupled between node 320 and the V D1 output voltage node of the fine DAC 306, and a switch F SSN , coupled between the second output node V Out and the V DN output voltage node of the fine DAC 306. In the fine DAC 306, the decoder 310 includes a one-hot decoder, according to embodiments.

[0043] ​In operation, one of the switches in the decoder 310 switches between the plurality of control signals ( Figure 3 (not shown) under the control of selectively DDN Voltage, V SSN The voltage or divider voltage is transferred to the output of the fine DAC in order to create the desired output voltage transient to drive a capacitive load or other type of load.

[0044] Figure 4 yes Figure 3 The timing diagram 400 of the load driver circuit is shown in FIG. In the timing diagram 400, the X-axis is time and the Y-axis is voltage. The following voltage waveform is shown in FIG. Figure 4 Shown: Waveform V P 402 is capacitor C FlyDAC The "top" voltage corresponds to Figure 3 The V DDN Voltage, waveform V N 406 is a capacitor C FlyDAC The "bottom" voltage corresponds to Figure 3 The V SSN voltage, and the waveform V CP 404 is Figure 3 The output voltage of the fine DAC 306 is shown in FIG and corresponds to Figure 3 The V Out Voltage. Figure 4 As can be seen from the timing diagram 400, V P and V N The voltage waveform is an input voltage V with a discrete number of rough voltage levels. In A rough representation of . Figure 4 The timing diagram 400 also shows that V CP The waveform provides the input voltage V In A more precise representation of , with an additional number of fine voltage levels. In an embodiment, each coarse voltage level is divided into an equal integer number of fine voltage levels by operation of the fine DAC 306. During operation, all fine DAC levels may be allowed or, in some embodiments, limited and omitted. Figure 4 In the example shown, each coarse voltage step is divided into three equal fine voltage steps. In other embodiments, fewer or additional fine voltage steps may be used for each coarse voltage step. In some embodiments, the fine voltage steps do not need to be exactly equal.

[0045] Described below Figure 3 The control signals for the UP, DOWN and BYPASS switches are shown, as well as the generation of the rough voltage relative to the input signal. Figure 4As the positive rising slope of the triangle wave depicted in FIG, the BYPASS switches are sequentially opened while the corresponding UP switches are closed (in each of the SP charge pump stages) until the maximum amplitude is reached. Then, the process is reversed and the UP switches are opened while the corresponding BYPASS switches are closed until the intermediate level is reached again and all BYPASS switches are closed and all flying capacitors C Fly and C FlyDAC is recharged. The process is then repeated to generate a negative half-wave, sequentially opening the bypass switches while closing the corresponding DOWN switches until the maximum negative amplitude is reached. The process is reversed again, with the DOWN switches opened and the corresponding BYPASS switches closed until the intermediate level is reached again. Thus, for "N" levels, 2N+1 coarse levels are generated, and the minimum step size becomes the peak-to-peak amplitude divided by 2N, which is twice the number of charge pump stages.

[0046] Figure 5A FIG is a schematic diagram of a fine DAC 500A according to another embodiment. The fine DAC 500A includes an energy storage capacitor array 505, which includes a capacitor divider 506 (capacitor C P1 and capacitor C N1 )、508(capacitor C P2 and capacitor C N2 )、510(capacitor C P3 and capacitor C N3 ) and 512 (capacitor C PN and C NN ), these capacitor voltage dividers are respectively configured to provide a first output node voltage V DDN and the second output node voltage V SSN There are multiple intermediate voltages 516, 518, 520 and 522 between them. Figure 5A Four capacitor dividers are shown in the schematic diagram of FIG, but more or fewer capacitor dividers may be used in other embodiments. The fine DAC 500A also includes a switch array 514 including parallel switches S0, S1, S2, S3, S N-1 and S N , these switches are configured to selectively couple a plurality of intermediate voltages 516, 518, 520, and 522 to the V Out Output. In some embodiments, "N" is an integer greater than or equal to three.

[0047] The fine DAC 500A optionally further includes a refresh and initialization circuit 501 coupled to the first output node V DDN and the second output node V SSNand is coupled to an energy storage capacitor array 505. The refresh and initialization circuit 501 includes a capacitor divider 502 that includes capacitors C D0 D1 D2 DN The capacitor divider 502 is in turn coupled to a switch array 504 that includes switches S D0 D1 D2 D3 DN-1 N While four capacitors are shown in the capacitor divider 502 and six switches are shown in the switch array 504, it will be apparent to those skilled in the art that additional or fewer components commensurate with the number of intermediate voltages used in other embodiments will be used.

[0048] In operation, when the C Dm pin, where C Dm corresponds to capacitor C D0 D1 D2 DN is repeatedly connected to adjacent levels of the energy storage capacitor array 505 between m-1 and m and between m and m+1, the voltage difference between the adjacent levels m-1, m, and m+1 is equalized. Thus, during the refresh and initialization period, all of the intermediate levels will stabilize to voltage levels distributed between V DDN or V SSN .

[0049] Figure 5B is a schematic diagram of a fine DAC 500B according to another embodiment. The fine DAC 500B includes an energy storage and capacitive divider array 502B configured to provide a combination of a plurality of intermediate voltages 516B, 518B, and 520B between a first output node voltage V DDN and a second output node voltage V SSN . The combined energy storage and capacitive divider array 502B includes a flying capacitor C FlyDAC and a capacitor divider that includes capacitors C 7B 8B 9B 10B D1 D2 D3 D4 ​​​​​​​​​​​​​​​​​​The fine DAC 500B also includes a switch array 506B configured to couple the plurality of intermediate voltages 516B, 518B, and 520B, and V DDN and V SSN are selectively coupled to the output V Out The switch array includes a plurality of parallel switches S F0 , S F1 , S Fm , S Fm+1 , and S FM In other embodiments, the number of switches and the number of capacitor divider capacitors can be reduced or increased. The fine DAC 500B optionally also includes a refresh and initialization circuit 504B coupled to the combined energy storage and capacitive divider array 502B. The refresh and initialization circuit 504B includes an enable switch S 1B , S 2B , S 3B , S 4B , S 5B , and S 6B , where the control node of each switch is coupled to the EQLZ equalization control signal.

[0050] In operation, when the enable switch is closed, the combined energy storage and capacitive divider array 502B operates as an energy storage cap array. The combined energy storage and capacitive divider array 502B provides intermediate voltage levels between V DDN or V SSN through a series connected capacitor array configuration between V DDN and V SSN . For refresh and initialization, the same array also forms a capacitive divider network that provides intermediate voltages by dividing the V DDN -V SSN difference voltage. When the enable switch is closed, the voltage across the capacitive divider capacitors can be equalized. An analog multiplexer or switch array 506B is used to connect the intermediate voltage levels and V DDN and V SSN voltages to the output node V Out .

[0051] Figure 5C is a schematic diagram of a fine DAC 500C according to another embodiment, which is similar to the fine DAC 500A previously described with reference to Figure 5A except that the refresh and initialization circuit 501 is omitted. In relevant part, the fine DAC 500C includes an energy storage capacitor array 501C coupled to a switch array 505C. The energy storage capacitor array 501C includes a flying capacitor C FlyDAC and a plurality of capacitor dividers 502C (capacitors CS1u and capacitor C S1l )、504C(capacitor C Smu and capacitor C Sm1 ) and 506C (capacitor C Smu+1u and capacitor C Sm1+1l ), for generating intermediate voltages at nodes 516C, 518C, and 520C, respectively. The switch array includes a plurality of switches coupled to the energy storage capacitor array 501C, and includes switches S F0 、S F1 、S Fm 、S Fm+1 and S FM In different embodiments, the exact number of capacitive dividers and switches in the switch array may be increased or decreased.

[0052] In operation, the energy storage capacitor array 501C provides the energy storage capacitors for the “M” DAC units at V DDN With V SSN At least one pin of a capacitor in the energy storage capacitor array 501C is coupled to V DDN or V SSN , or in other words, into an array of capacitors (C S1u 、C Smu and C Smu+1u ) and below (C S1l 、C S1u and C Sm1+1l ) capacitor array. The analog multiplexer or switch array 505C converts the intermediate voltage level and V DDN and V SSN coupled to the output node V Out .exist Figure 5C In the embodiment, the refresh and initialization circuits can be removed ( Figure 5A (as shown) to minimize parasitic bulk capacitance and enhance efficiency. If initial settling over a few modulation cycles is acceptable, the fine DAC intermediate levels will self-stabilize with a periodic switching sequence for continuous DC / AC modulation. Settling can be reduced by adjusting the ratio of the upper capacitor to the lower capacitor of the energy storage capacitor array 501C to form a capacitive divider that reflects the stable value of the fine DAC 500C voltage source as it ramps up. In one example, for three levels, C S1u / C S1l The ratio can be 1 / 3, C S2u / C S2l The ratio can be one, and C S3u / C S3l The ratio can be three, thus producing V DDN -V SSNLevels of 1 / 4, 1 / 2, and 3 / 4 of the voltage difference.

[0053] Figure 5D FIG2 is a schematic diagram of a fine DAC 500D according to another embodiment. The fine DAC 500D includes a plurality of unit cells 502D, 504D, and 506D coupled in series, which are configured to implement a binary-weighted sum of shifted input voltage components, wherein each unit cell includes a pair of capacitors coupled in series and two pairs of switches coupled to the pair of capacitors coupled in series. The unit cell 502D includes a capacitor C D1U and C D1L , including switch S D1U and S D1L The first pair of switches and the second pair of switches S D1U' and S D1L' The unit cell 504D includes a capacitor C DmU and C DmL , including switch S DmU and S DmL The first pair of switches and the second pair of switches S DmU' and SDmL' The Fine DAC 500D also includes a switch S coupled to F0 , S F1 、S F2 、S F3 and S F4 The fine DAC 500D optionally further includes a balancing capacitor C coupled to the unit cell 506D. E Specifically, capacitor C E is coupled at node 525D (switch S DMU With S DML The node between) and node 527D (switch S DMU' With S DML' between the nodes).

[0054] In operation, the fine DAC 500D is a binary adder-based fine DAC comprising "M" stages of unit cells that implement a binary-weighted sum of the shifted input voltage components. Figure 5D In the example of , "M" is an integer equal to three. However, "M" may assume other integer values. As previously mentioned, each unit cell includes two capacitors C forming a binary capacitive voltage divider. DmU and C DmL The capacitor voltage divider is used to cut the input voltage in half. Two pairs of switches (S FMU and S FML , and S FMU' and S FML') couples the input of the following unit cell “(m+1)” to the output of the “m”th preceding unit cell. When switch S DmU and S DmU' When enabled, each unit cell outputs the upper half of the input voltage, and when the switch S DmL and S DmL' When enabled, each unit cell outputs the lower half of the input voltage. The last stage "M" is coupled to a circuit comprising at least a switch S F1 、S F2 and S F3 A multiplexer to connect the upper, middle, or lower output of the last capacitive divider to V Out The load at the node. Balancing capacitor C E is coupled to the output of the last “M”th unit cell to balance the cross capacitor C DMU and C DML The voltage of each capacitor in . With each additional unit cell, the number of intermediate voltage levels more than doubles: "2M-1" unit cells provide => F = 1, 3, 7, 15, ... intermediate levels. Figure 5D In the embodiment shown, the capacitor voltages of up to "M-1" unit cells are self-balancing and typically no additional balancing capacitors are required. F0 and S F4 Optionally used to bypass the Fine DAC 500D.

[0055] Figure 5E FIG2 is a schematic diagram of a fine DAC 500E according to another embodiment. The fine DAC 500E includes a plurality of unit cells 502E, 504E, 506E, and 508E, each of which includes a plurality of series-coupled capacitor strings, each of which includes one or more capacitors; and a pair of switches coupled to each capacitor in the DAC, wherein a first capacitor string includes "M" series-coupled capacitors, where "M" is an integer greater than one, and a last capacitor string includes a single capacitor.

[0056] The capacitor string in unit cell 502E includes a capacitor coupled in series at V DDN With V SSN The four Cs D1 capacitors, and included in C D1 The intermediate nodes 516E, 518E and 520E between the capacitors. Similarly, in the capacitor string of the unit cell 502E, the first set of switches S coupled in series D1U and S D1L Cross-first C D1 The capacitor is coupled, and a second set of switches S coupled in series D1U and S D1Lacross the second C D1 capacitors are coupled, and a third set of series-coupled switches S D1U and S D1L across the first C D1 capacitors are coupled, a second set of series-coupled switches S D1U and S D1L across the second C D1 capacitors are coupled.

[0057] The capacitor string of unit cell 504E includes three C D2 capacitors coupled in series between nodes 528E and 522E, and includes intermediate nodes 524E and 526E between C D2 capacitors. Also in the capacitor string of unit cell 504E, a first set of series-coupled switches S D2U and S D2L across the first C D2 capacitors are coupled, a second set of series-coupled switches S D2U and S D2L across the second C D2 capacitors are coupled, and a third set of series-coupled switches S D2U and S D2L across the third C D2 capacitors are coupled.

[0058] The capacitor string of unit cell 506E includes two C Dm capacitors coupled in series between nodes 530E and 534E, and includes an intermediate node 532E between C Dm capacitors. Also in the capacitor string of unit cell 506E, a first set of series-coupled switches S DmU and S DmL across the first C D2 capacitors are coupled, and a second set of series-coupled switches S DmU and S DmL across the second C D2 capacitors are coupled. The capacitor string of unit cell 508E includes a single C DM capacitor coupled between nodes 538E and 536E. A set of series-coupled switches S DMU and S DML across the C DM capacitor is coupled. The node between S DMU and S DML switches is V Out node. Between the first capacitor string in unit cell 502E and the last capacitor string of unit cell 508E, the number of capacitors is reduced by one capacitor in each successive unit cell. Thus, in Figure 5EIn embodiments, the series coupled capacitor string in each unit cell drops from four capacitors to three capacitors, to two capacitors, and then to a single capacitor. In other embodiments, a different number of unit cells can be used to achieve V Out A different number of fine voltage levels are provided at the output node.

[0059] In operation, when switch S DmU is enabled, switch S DmL is disabled, and vice versa, and the successive stage is coupled to the upper or lower capacitor of the previous capacitor string. For each additional capacitor string and switch pair (unit cell), the number of voltage levels increases by one (F = M - 1). In Figure 5E In fine DAC 500E, the capacitor voltages are self-balancing. All capacitors have the same voltage = (V DDN - V SSN ) / M, where "M" = the number of unit cells. Each unit cell (except the last one) can shift the successive unit cell up or down by one voltage level, and by adjusting the shift of each unit cell, the output voltage V Out takes on one of "N" voltage levels between V DDN and V SSN .

[0060] Figure 5F is a schematic diagram of a fine DAC 500F according to another embodiment. Fine DAC 500F includes a plurality of unit cells 502F, 504F, 506F, and 508F. In embodiments, each unit cell includes a capacitor; and a half switch coupled to the capacitor, where the half switch is configured to selectively couple the unit cell to a next unit cell in the plurality of unit cells.

[0061] Thus, unit cell 502F includes capacitor C FlyDAC coupled to a half switch, which includes switch S D1U (an upper switch) and switch S D1L (a lower switch). Unit cell 504F includes capacitor C D2U coupled to a half switch that includes switch S D2L and switch S D1 . Unit cell 506F includes capacitor C DmU coupled to a half switch that includes switch S Dm1 and switch S Dm . Unit cell 508F includes capacitor C DMU coupled to a half bridge switch that includes switch S DML and switch S DMThe node between the switches in unit cell 508F is coupled to an output voltage node V Out Although four unit cells are shown in Figure 5F , it will be apparent to those skilled in the art that different numbers of unit cells can be used in different embodiments. In Figure 5F , flying capacitor C FlyDAC is shown as part of fine DAC 500F and is not specifically shown as separate from the fine DAC, such as shown in Figure 1 and Figure 3 .

[0062] In operation, fine DAC 500F implements a flying capacitor multi-level converter (FCMLI) or capacitor clamped multi-level converter based on the flying capacitor of fine DAC 500F. Fine DAC 500F is a string of pairs of switches with capacitors between the pairs of switches, where “M” stages of unit cells implement a weighted sum of scaled input voltage differences. Each unit cell is charged to a fraction m*(V DmU -V DmL ) / M of the input voltage by a half-bridge in each unit cell including two switches S DDN and S SSN . The half-bridge couples the upper or lower capacitor pin and potential to the next consecutive unit cell. By adjusting the switch pattern, different capacitors are configured to float or be in series, thereby ignoring, adding or subtracting the capacitor voltage from V DDN or V SSN voltage. For each additional switch pair and capacitor (unit cell), the number of fine DAC voltage levels increases by one (=M-1). In some embodiments, the capacitor voltage is actively balanced by alternating between redundant switch configurations so that capacitors are charged and discharged.

[0063] According to embodiments, the range of applications of the load driver circuits described herein can be extended by additional system aspects. Figure 6 is a schematic diagram of a system 600 including a load driver circuit, such as load driver circuit 300 shown in Figure 3 , and additional system circuitry described in further detail below.

[0064] System 600 includes, in relevant part, a load driver circuit of the type previously described, comprising: a series-parallel charge pump including capacitor and switch units 608 and 610, a flying capacitor CN (shown as internal to the LV unit, C-fine DAC, and sense circuit block 624), a precharge circuit 620, and a capacitor and switch array 622. System 600 also shows a capacitive load 626, which may include a MEMS device C driven by the load driver circuit. MEMS The system 600 also shows a voltage input source 602. Figure 6 Other types of loads may also be used in the illustrated system 600 .

[0065] The system 600 optionally includes a sub-regulation circuit 606 for sub-regulating the input voltage provided by the voltage input source 602. In some embodiments, the sub-regulation circuit 606 includes a "gearbox" charge pump (which includes a so-called "gearbox" that combines two or more different converter topologies in conjunction with a topological switching scheme), an inductive buck-boost converter, a low dropout (LDO) voltage converter, a DC-DC converter, or any other suitable voltage converter. Sub-regulating the input voltage using the sub-regulation circuit 606 advantageously allows for operation at a voltage source having a lower drain-to-source "on" resistance (R DSon ) and lower switching power (P SW ) load driver circuits. Sub-regulation circuit 606 also allows the use of more series-parallel charge pump stages, resulting in lower power consumption due to smaller coarse step sizes, and thus more steps to achieve the same output voltage and reduce reasonable power supply variations. In some embodiments, the supply current can be measured indirectly by measuring the current provided by the series-parallel charge pump (SP-CP).

[0066] The system 600 optionally includes a frequency divider circuit including a low power charge pump 604, resistor dividers R3 and R4, a switch S PW / Rup and bias capacitor C bias . In operation, the divider circuit provides independent setting of quasi-static MEMS actuator bias and AC excitation enable. Since only a static high voltage needs to be provided to the voltage divider R3 and R4, and the low power charge pump 604 can have a high output resistance, the crossover circuit has low static power consumption. The divider circuit enables power-efficient AC modulation of the series-parallel charge pump near battery level. The divider circuit advantageously adjusts the MEMS bias to maximum sensitivity, such as during lower LSB level (least significant bit) playback (this results in higher MEMS sensitivity (~+5dB) compared to omitting the divider circuit).

[0067] In some embodiments, the system 600 also includes optional sensing circuitry. An integrated low-sense circuitry in parallel with the SC-fine DAC (shown in block 624) is used to directly sense small signals without the need for high-voltage switches with low-voltage circuitry from the floating capacitor of the reference string parallel charge pump level. The output voltage (at node V SENS ) is sensed by amplifier 616 and ADC 612, and by amplifier 618 and ADC 614. The sensing branch including amplifier 618 and ADC 614 can include optional switch S SENSE . The sensed driver output voltage and / or current are used to control the driver operation. Amplifier 628 and ADC 630 further sense the output voltage through a capacitive (C1 and C2) and resistive (R1 and R2) voltage divider.

[0068] Figure 7 is a block diagram of a load driver circuit 700 according to another embodiment. The driver circuit includes a plurality of serially connected macro cells (706A / 712A, 706B / 712B), where each macro cell includes a plurality of up-conversion cells (embodied in SP charge pump 706A or SP charge pump 706B) for generating a plurality of coarse signal steps, and a plurality of down-conversion cells (embodied in fine DAC 712A or fine DAC 712B) for generating a plurality of fine signal steps by dividing each coarse signal step. Each macro cell also includes a flying capacitor C FlyDAC inserted between the SP charge pump and the fine DAC. A first flying capacitor C FlyDAC is coupled between node 708A and node 710A (V P and V N ). A second flying capacitor C FlyDAC is coupled between node 708B and node 710B (V P" and V N" ). The term "up-conversion" is used because the V In input voltage is "up-converted" in voltage to a maximum voltage that is greater than the V P voltage at the V N and V In nodes. The term "down-conversion" is used because the voltage at the V DDN and V SSN nodes is "down-converted" in voltage to an output voltage that is less than the differential voltage at the V P and V N nodes.

[0069] The load driver circuit 700 also includes an optional DC / DC converter 702 coupled to node 704, a DC / DC converter 704 coupled between V CP node and V LC between nodes (nodes 714) Bias Capacitor coupled between node 704 and V Bias Quasi-static charge pump 716 between nodes, and coupled between V Bias Bias resistor R Bias between nodes and node 714. Load 718 is coupled to V L node (node 714). Load 718 can include a MEMS device that is a speaker, an actuator, a sensor, a capacitive load, or any other suitable load. These additional components have been described previously.

[0070] Both SP charge pumps 706A and 707B have two inputs and two outputs, and have been described previously. Fine DAC 712B has two inputs and only one output, which has also been described previously. Fine DAC 712A, however, has two inputs and two outputs, which has not been described previously. While fine DAC 712A is similar to the fine DACs described previously, it includes a different output switch topology, which is described below with reference to Figure 8 schematic diagram. If more than two macrocells are used, then all fine DAC circuits except the fine DAC in the last macrocell will have the circuit as shown in Figure 8

[0071] Figure 8 schematic diagram of a fine DAC 800 according to another embodiment, which specifically includes two inputs (V DDN and V SSN nodes) and two outputs (V P" and V N" nodes). Thus, fine DAC 800 includes capacitors C DDN and C SSN between V D1U and V D1L nodes and nodes 802 and 804, and switches S D1U , S D1L , S D2U , and S D2L . Fine DAC 800 includes capacitors C DmU and C DmL between nodes 802 and 804 and nodes 806 and 808, and switches S DmU , S DmL , S DmU' , and S DmL' . Fine DAC 800 also includes capacitors C DMU , C DML , and C E between nodes 806 and 810, and switches S​DMU 、S DML 、S DMU' and S DML' . Reference below Figure 5D The fine DAC 500D shown depicts all of these components. However, the fine DAC 800 includes an additional switch S F0 、S F1 、S F2 、S F3 and S F4 To respectively V SSN Node, node 810, node 808, node 806 and V DDN Node coupled to node V P" The Fine DAC 800 includes additional switches S F5 、S F6 、S F7 、S F8 and S F9 To respectively V SSN Node, node 810, node 808, node 806 and V DDN Node coupled to node V N" .

[0072] In some embodiments, the timing of the load driver circuit and the DAC step size and timing are controlled directly or indirectly by the delta-sigma modulator or register settings. The control signals of the above switches can also be controlled by an external or integrated controller.

[0073] In some embodiments, the load may include a capacitive MEMS load (such as a cell phone speaker or MEMS) for eliciting static pressure, air flow, or pressure modulation as acoustic, infrasonic, or ultrasonic waves.

[0074] This document summarizes exemplary embodiments of the present invention. Other embodiments can be understood from the overall description and claims submitted herein.

[0075] Example 1. According to an embodiment, a driver circuit includes: a series-parallel charge pump, including a plurality of switched capacitor units, wherein the series-parallel charge pump is configured to generate a plurality of coarse signal steps at a first output node and a second output node; a flying capacitor, a capacitor array or a storage element, coupled between the first output node and the second output node; and a digital-to-analog converter (DAC), coupled between the first output node and the second output node, the DAC including a plurality of switched capacitors, the plurality of switched capacitors being configured to generate a plurality of fine signal steps.

[0076] Example 2. The driver circuit of Example 1, wherein the series-shunt charge pump comprises a bipolar series-shunt charge pump.

[0077] Example 3. The driver circuit of any of the preceding examples, further comprising a bias capacitor coupled to the output of the DAC and a load coupled to the bias capacitor.

[0078] Example 4. The driver circuit of any of the preceding examples, further comprising a quasi-static bias charge pump having an input coupled to the input of the series-parallel charge pump and a bias resistor coupled between an output of the quasi-static bias charge pump and a node between the bias capacitor and the load.

[0079] Example 5. The driver circuit of any of the preceding examples, further comprising a DC-DC converter coupled to the input of the series-parallel charge pump.

[0080] Example 6. The driver circuit of any of the preceding examples, wherein the DAC comprises: a first capacitor coupled between a first output node and a first intermediate node; a second capacitor coupled between a second output node and a second intermediate node; and a decoder coupled to the first output node, the second output node, the first intermediate node, and the second intermediate node.

[0081] Example 7. The driver circuit of any of the preceding examples, wherein the decoder comprises a one-hot decoder.

[0082] Example 8. The driver circuit of any of the preceding examples, wherein the DAC comprises: an energy storage capacitor array configured to provide a plurality of intermediate voltages between a first output node voltage and a second output node voltage; and a switch array configured to selectively couple the plurality of intermediate voltages to the output of the DAC.

[0083] Example 9. The driver circuit of any of the preceding examples, further comprising a refresh and initialization circuit coupled to the first output node and the second output node and coupled to the energy storage capacitor array.

[0084] Example 10. The driver circuit of any of the preceding examples, wherein the DAC comprises: a combined energy storage and capacitive voltage divider array configured to provide a plurality of intermediate voltages between a first output node voltage and a second output node voltage; and a switch array configured to selectively couple the plurality of intermediate voltages to the output of the DAC.

[0085] Example 11. The driver circuit of any of the preceding examples, further comprising a refresh and initialization circuit coupled to the combined energy storage and capacitive voltage divider array.

[0086] Example 12. The driver circuit of any of the above examples, wherein the DAC comprises: a plurality of series coupled unit cells configured to implement a binary weighted sum of shifted input voltage components, wherein each unit cell comprises a pair of series coupled capacitors and two pairs of switches coupled to the pair of series coupled capacitors; and a multiplexer coupled to at least one of the unit cells.

[0087] Example 13. The driver circuit of any of the above examples, further comprising an extra capacitor coupled to a last unit cell of the plurality of series coupled unit cells.

[0088] Example 14. The driver circuit of any of the above examples, wherein the DAC comprises a plurality of unit cells, wherein each unit cell comprises: a plurality of series coupled capacitor strings, wherein each capacitor string comprises one or more capacitors; and a pair of switches coupled to each capacitor in the DAC, wherein a first capacitor string comprises “M” series coupled capacitors, where “M” is an integer greater than one, and a last capacitor string comprises a single capacitor.

[0089] Example 15. The driver circuit of any of the above examples, wherein a number of capacitors decreases by one capacitor in each successive unit cell between the first capacitor string and the last capacitor string.

[0090] Example 16. The driver circuit of any of the above examples, wherein the DAC comprises a plurality of unit cells, and wherein at least one of the plurality of unit cells comprises: a capacitor; and a half-bridge switch coupled to the capacitor, wherein the half-bridge switch is configured to selectively couple the at least one of the plurality of unit cells to a next one of the plurality of unit cells.

[0091] Example 17. The driver circuit of any of the above examples, further comprising an extra half-bridge switch interposed between the flying capacitor and a first unit cell of the plurality of unit cells.

[0092] Example 18. In accordance with an embodiment, a driver circuit comprises: a series-parallel charge pump configured to generate a plurality of coarse signal steps; a digital-to-analog converter (DAC) coupled to the series-parallel charge pump, the DAC comprising a plurality of switched capacitors; and a flying capacitor interposed between the series-parallel charge pump and the DAC, wherein the DAC is configured to generate a plurality of fine signal steps and to charge the plurality of switched capacitors only when a load is coupled to the driver circuit.

[0093] Example 19. According to an embodiment, a driver circuit comprises: a plurality of serially connected macro cells, wherein each macro cell comprises: a plurality of up-conversion cells to generate a plurality of coarse signal steps; and a plurality of down-conversion cells to generate a plurality of fine signal steps by dividing each coarse signal step.

[0094] Example 20. The driver circuit of example 19, further comprising a load coupled to the plurality of down-conversion cells, wherein the load comprises a MEMS device, an actuator, a sensor, or a capacitive load.

[0095] While the application has been described with reference to illustrative embodiments, the description is not intended to be construed in a limiting sense. Various modifications and combinations of the illustrative embodiments, as well as other embodiments of the application, will be apparent to persons skilled in the art upon reference to the description. It is therefore intended that the appended claims encompass any such modifications or embodiments.

Claims

1. A driver circuit comprising: a series-parallel charge pump comprising a plurality of switched capacitor cells, wherein the series-parallel charge pump is configured to generate a plurality of coarse signal steps at a first output node and a second output node; a flying capacitor, a capacitor array, or a storage element coupled between the first output node and the second output node; and a digital-to-analog converter (DAC) coupled between the first output node and the second output node, the DAC comprising a plurality of switched capacitors configured to generate a plurality of fine signal steps.

2. The driver circuit of claim 1, wherein the series-parallel charge pump comprises a bipolar series-parallel charge pump.

3. The driver circuit of claim 1, further comprising a bias capacitor coupled to an output of the DAC and a load coupled to the bias capacitor.

4. The driver circuit of claim 3, further comprising: a quasi-static bias charge pump having an input coupled to an input of the series-parallel charge pump; and a bias resistor coupled between an output of the quasi-static bias charge pump and a junction between the bias capacitor and the load.

5. The driver circuit of claim 1, further comprising a DC-DC converter coupled to an input of the series-parallel charge pump.

6. The driver circuit of claim 1, wherein the DAC comprises: a capacitor coupled between the first output node and a first intermediate node; a decoder coupled to the first output node and the first intermediate node.

7. The driver circuit of claim 6, wherein the decoder comprises a one-hot decoder.

8. The driver circuit of claim 1, wherein the DAC comprises: an energy storage capacitor array configured to provide a plurality of intermediate voltages between a first output node voltage and a second output node voltage; and a switch array configured to selectively couple the plurality of intermediate voltages to an output of the DAC.

9. The driver circuit of claim 8, further comprising a refresh and initialization circuit coupled to the first output node and the second output node and coupled to the energy storage capacitor array.

10. The driver circuit of claim 1, wherein the DAC comprises: a combined energy storage and capacitive voltage divider array configured to provide a plurality of intermediate voltages between a first output node voltage and a second output node voltage; and a switch array configured to selectively couple the plurality of intermediate voltages to an output of the DAC.

11. The driver circuit of claim 10, further comprising a refresh and initialization circuit coupled to the combined energy storage and capacitive voltage divider array.

12. The driver circuit of claim 1, wherein the DAC comprises: ​ ​ ​ ​ a plurality of series coupled unit cells configured to implement a binary weighted sum of shifted input voltage components, wherein each unit cell comprises a pair of series coupled capacitors and two pairs of switches coupled to the pair of series coupled capacitors; and a multiplexer coupled to at least one of the unit cells.

13. The driver circuit of claim 12, further comprising an additional capacitor coupled to a last unit cell of the plurality of series coupled unit cells.

14. The driver circuit of claim 1, wherein the DAC comprises a plurality of unit cells, wherein each unit cell comprises: a plurality of series coupled capacitor strings, wherein each capacitor string comprises one or more capacitors; and a pair of switches coupled to each capacitor in the DAC, wherein a first capacitor string comprises "M" series coupled capacitors, where "M" is an integer greater than one, and a last capacitor string comprises a single capacitor.

15. The driver circuit of claim 14, wherein a number of capacitors decreases by one capacitor in each successive unit cell between the first capacitor string and the last capacitor string.

16. The driver circuit of claim 1, wherein the DAC comprises a plurality of unit cells, and wherein at least one unit cell of the plurality of unit cells comprises: a capacitor; and a half-bridge switch coupled to the capacitor, wherein the half-bridge switch is configured to selectively couple the at least one unit cell of the plurality of unit cells to a next unit cell of the plurality of unit cells.

17. The driver circuit of claim 16, further comprising an additional half-bridge switch interposed between the flying capacitor and a first unit cell of the plurality of unit cells.

18. A driver circuit comprising: a series-parallel charge pump configured to generate a plurality of coarse signal steps; a digital-to-analog converter (DAC) coupled to the series-parallel charge pump, the DAC comprising a plurality of switched capacitors; and a flying capacitor interposed between the series-parallel charge pump and the DAC, wherein the DAC is configured to generate a plurality of fine signal steps and to charge the plurality of switched capacitors only when a load is coupled to the driver circuit.

19. A driver circuit comprising: a plurality of series connected macro cells, wherein each macro cell comprises: a plurality of up-conversion cells to generate a plurality of coarse signal steps; and a plurality of down-conversion cells to generate a plurality of fine signal steps by dividing each of the coarse signal steps.

20. The driver circuit of claim 19, further comprising a load coupled to the plurality of down-conversion cells, wherein the load comprises a MEMS device, an actuator, a sensor, or a capacitive load.

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