Decoding method and decoding circuit for reducing influence of power signal line noise on decoding

Abstract

The invention relates to a decoding method and a decoding circuit for reducing the influence of power signal line noise on decoding. The decoding method for reducing the influence of the noise of the power signal line on decoding comprises the following steps of: comparing a voltage level of an analog signal to be decoded with a plurality of reference voltages to generate a plurality of comparison signals; performing an edge detection program according to the plurality of comparison signals to obtain an edge detection signal; decoding the edge detection signal to obtain a ratio of a time length of a first logic to a time length of a second logic of a decoded signal; when the proportion is greater than a first threshold value, adjusting the higher reference voltage; when the proportion is smaller than a second threshold value, the lower reference voltage is adjusted, and the analog signal to be decoded is obtained through transmission according to a known signal.

Description

TECHNICAL FIELD

[0001] The present application relates to a noise suppression technique, and in particular, to a decoding method and decoding circuit for reducing the effect of power signal line noise on decoding. BACKGROUND

[0002] Automatic charging is a popular device at present, and the Universal Serial Bus Power Delivery (USB PD) protocol is the most commonly used transmission specification. In addition to charging and discharging through the power flat cable pin (VBUS pin), another related interface signal is on the channel configuration pin (CC pin). During data transmission (bit rate about 300K / s), the voltage level of the channel configuration pin (CC pin) is about 1.1V. Therefore, if any noise is disturbed during transmission, it will affect the correct reception of data during information transmission in the Universal Serial Bus Power Delivery.

[0003] The Universal Serial Bus Power Delivery protocol not only includes power, but also handles the coordination of data flow, data format and master-slave relationship between two devices. Through the transmission of the channel configuration pin, when converted into a digital signal, the data packet also includes cyclic redundancy check calculation and comparison to avoid using incorrect packet data due to noise.

[0004] Therefore, in the known noise authentication process, the following three different noise authentication conditions are included:

[0005] Test noise conditions

[0006]

[0007] From the above three different noise verification conditions, it can be seen that the DC voltage level will drift up or down due to different test conditions. SUMMARY

[0008] Embodiments of the present application provide a decoding method for reducing the effect of power signal line noise on decoding and a decoding circuit using the same, which adjusts the edge detection strategy in advance under the condition that the signal is known. In this way, before the subsequent carrier is demodulated into a digital signal, the above noise conditions can be overcome, so that the correct digital signal can be solved.

[0009] Embodiments of the present application provide a decoding method for reducing the effect of power signal line noise, comprising: comparing a voltage level of an analog signal to be decoded with a plurality of reference voltages to generate a plurality of comparison signals; performing an edge detection procedure according to the plurality of comparison signals to obtain an edge detection signal; decoding the edge detection signal to obtain a ratio of a time length of a first logic to a time length of a second logic of a decoded signal; adjusting a higher reference voltage when the ratio is greater than a first threshold value; and adjusting a lower reference voltage when the ratio is less than a second threshold value, wherein the analog signal to be decoded is obtained according to a known signal transmission.

[0010] Embodiments of the present application provide a decoding circuit, comprising a plurality of comparators, a noise filtering and signal edge detection circuit, and a digital signal information processing circuit. The plurality of comparators comprise a first end, a second end, and an output end. The first end of the plurality of comparators receives an analog signal to be decoded. The second end of the plurality of comparators is coupled to a corresponding reference voltage level, wherein the plurality of reference voltage levels are all different. The output end of the plurality of comparators outputs a plurality of comparison signals. The noise filtering and signal edge detection circuit is coupled to the output end of the plurality of comparators. The noise filtering and signal edge detection circuit performs an edge detection procedure according to the plurality of comparison signals to obtain an edge detection signal.

[0011] The digital signal information processing circuit is coupled to the output end of the noise filtering and signal edge detection circuit. The digital signal information processing circuit generates a decoded signal according to the edge detection signal. The digital signal information processing circuit obtains a ratio of a time length of a first logic to a time length of a second logic of the decoded signal. When the ratio is greater than a first threshold value, a higher reference voltage is adjusted. When the ratio is less than a second threshold value, a lower reference voltage is adjusted. The analog signal to be decoded is obtained according to a known signal transmission.

[0012] According to the decoding method for reducing the effect of power signal line noise, the decoding circuit using the same, and the power supply / receiving device using the same, the analog signal to be decoded is obtained from a channel configuration pin (CC pin) of a universal serial bus port. In a preferred embodiment of the present application, the analog signal to be decoded is modulated according to a bi-phase mark code.

[0013] For further understanding of the technical solutions, means and effects of the present application, reference can be made to the following detailed description and drawings, so that the purpose, features and concepts of the present application can be thoroughly and specifically understood. However, the following detailed description and drawings are only used for reference and illustration of the implementation of the present application, and are not used for limiting the present application. BRIEF DESCRIPTION OF DRAWINGS

[0014] The accompanying drawings are provided to enable those skilled in the art to further understand the present invention and are incorporated in and constitute a part of the specification of the present invention. The accompanying drawings illustrate exemplary embodiments of the present invention and, together with the description of the present invention, serve to explain the principles of the present invention.

[0015] Figure 1 FIG. 1 is a system block diagram of a power supply / receiving device according to a preferred embodiment of the present invention.

[0016] Figure 2 FIG. 1 is a circuit diagram of the analog circuit block 104 according to a preferred embodiment of the present invention.

[0017] Figure 3 FIG. 1 is a flowchart illustrating the operation of the noise filtering and signal edge detection circuit 105 in performing the current level number in_level according to a preferred embodiment of the present invention.

[0018] Figure 4 FIG. 1 is a flowchart illustrating the operation of the noise filtering and signal edge detection circuit 105 in accordance with a preferred embodiment of the present invention, wherein the noise filtering and signal edge detection circuit 105 performs the operations of the highest level variable Hi_count and the lowest level variable Low_cout.

[0019] Figure 5 FIG. 1 is a waveform diagram illustrating the operation of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present invention.

[0020] Figure 6 FIG. 1 is a waveform diagram illustrating the operation of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present invention.

[0021] Figure 7 FIG2 shows an operation waveform diagram of the first comparator 201 , the second comparator 202 , and the third comparator 203 when encountering noise according to a preferred embodiment of the present invention.

[0022] Figure 8 FIG. 1 is a waveform diagram illustrating the operation of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present invention.

[0023] Figure 9 FIG. 1 is a circuit block diagram of a decoding circuit according to a preferred embodiment of the present invention.

[0024] Figure 10 FIG2 is a flow chart of a decoding method for reducing the influence of power signal line noise on decoding according to a preferred embodiment of the present invention.

[0025] Figure 11 FIG. 4 is a flow chart illustrating an edge detection procedure of a decoding method for reducing the influence of power signal line noise on decoding according to a preferred embodiment of the present invention.

[0026] [Explanation of symbols]

[0027] 101: Universal Serial Bus

[0028] 102: Decoding circuit

[0029] 103: Power supply / receiving circuit

[0030] CCpin: Channel configuration pin

[0031] 104: Analog circuit block

[0032] 105: Noise filtering and signal edge detection circuit

[0033] 106: Digital signal information processing circuit

[0034] Bit_OUT: Decoding signal

[0035] 201: First comparator

[0036] 202: Second comparator

[0037] 203: Third comparator

[0038] Analog_RCed: Analog signal to be decoded

[0039] HTH, MTH, LTH: Reference voltage levels

[0040] Comparator_Slice OUT[2]: Comparison signal output from the output terminal of the first comparator 201

[0041] Comparator_Slice OUT[1]: Comparison signal output from the output terminal of the second comparator 202

[0042] Comparator_Slice OUT[0]: Comparison signal output from the output terminal of the third comparator 203

[0043] Hi_count: Highest bit variable

[0044] Low_cout: Lowest bit variable

[0045] in_level: Current bit number

[0046] S301-S308: Steps

[0047] S401-S407: Steps

[0048] Edge_detected: Edge detection pulse output from the noise filtering and signal edge detection circuit 105

[0049] 701, 702, 703, 704: noise pulse

[0050] 901: first adjustable reference voltage generating circuit

[0051] 902: second adjustable reference voltage generating circuit

[0052] 903: third adjustable reference voltage generating circuit

[0053] 904: digital signal information processing circuit

[0054] Vedge: edge detection signal

[0055] S1001-S1007: flow steps of the decoding method for reducing the influence of the power signal line noise on decoding in a preferred embodiment of the present application

[0056] S1101-S1105: flow steps of the edge detection program of the decoding method for reducing the influence of the power signal line noise on decoding in a preferred embodiment of the present application DETAILED DESCRIPTION

[0057] Reference will now be made in detail to the exemplary embodiments of the present application, which will be illustrated in the accompanying drawings. Wherever possible, the same reference numbers will be used throughout the drawings to refer to the same or like parts. Additionally, the exemplary embodiments are merely one of the design concepts of the present application, and the following description is not intended to limit the present application.

[0058] Figure 1 A system block diagram of a power supply / receiving device in a preferred embodiment of the present application is shown. Please refer to Figure 1 In this embodiment, a power supply / receiving device in accordance with the Universal Serial Bus Power Delivery (USB-PD) protocol is taken as an example. The power supply / receiving device includes a USB port 101, a decoding circuit 102, and a power supply / receiving circuit 103. The USB port 101 includes a channel configuration pin CCpin. The decoding circuit 102 includes an analog circuit block 104, a noise filtering and signal edge detection circuit 105, and a digital signal information processing circuit 106. The power supply / receiving circuit 103 is coupled to the USB port 101 and the decoding circuit 102, receives a decoding signal Bit_OUT (packet data bit output) provided by the decoding circuit 102, and thereby communicates the power supply capability and demand with a device coupled to the other end of the USB port 101. Because of the reception of data, in the USB-PD system, in addition to the voltage signal input through the channel configuration pin, digital sampling processing is also performed to convert the noise-eliminated real digital information data, so as to facilitate the decoding of the content on the data packet.

[0059] Figure 2 A circuit diagram of the analog circuit slice 104, which is a preferred embodiment of the present application, is shown in FIG. 3. Please refer to FIG. 3. Figure 2 In this embodiment, the analog circuit slice 104 includes a first comparator 201, a second comparator 202, and a third comparator 203. Each of the comparators 201, 202, and 203 includes a first end, a second end, and an output end. The first end of each of the comparators 201, 202, and 203 receives the analog signal Analog_RCed to be decoded obtained from the channel configuration pin CCpin, and the second end of each of the comparators 201, 202, and 203 is coupled to a corresponding reference voltage level HTH (High Threshold), MTH (Middle Threshold), and LTH (Low Threshold), respectively. The comparison signals outputted from the output ends of the comparators 201, 202, and 203 are denoted as Comparator_Slice OUT[2], Comparator_Slice OUT[1], and Comparator_Slice OUT[0], respectively.

[0060] The noise filtering and signal edge detection circuit 105 is coupled to the output ends of the comparators 201, 202, and 203. In the noise filtering and signal edge detection circuit 105, three variables are set, which are a highest bit level variable Hi_count, a lowest bit level variable Low_count, and a current bit level number in_level.

[0061] Figure 3 A flow chart of the operation of the noise filtering and signal edge detection circuit 105, which is a preferred embodiment of the present application, in performing the current bit level number in_level is shown in FIG. 4. Please refer to FIG. 4. Figure 3 In this embodiment, the operation of the noise filtering and signal edge detection circuit 105 in performing the current bit level number in_level includes the following steps:

[0062] Step S301: Initial reset.

[0063] Step S302: Determine whether the signal Comparator_Slice OUT[2] at the output end of the comparator 201 is a logic high voltage. If the determination is yes, proceed to step S305. If the determination is no, proceed to step S303.

[0064] Step S303: Determine whether the signal Comparator_Slice OUT[1] at the output end of the comparator 202 is a logic high voltage. If the determination is yes, proceed to step S306. If the determination is no, proceed to step S304.

[0065] Step S304: Determine whether the signal Comparator_Slice OUT[0] at the output terminal of the comparator 203 is a logic high voltage. If the determination is yes, proceed to step S307. If the determination is no, proceed to step S308.

[0066] Step S305: Set the current level number in_level to the three-digit number 011.

[0067] Step S306: Set the current level number in_level to the three-digit number 010.

[0068] Step S307: Set the current level number in_level to the three-digit number 001.

[0069] Step S308: Set the current level number in_level to the three-digit number 000.

[0070] The running time (sampling time) of the above flow steps can be designed according to different requirements, and will not be described here.

[0071] Figure 4 The noise filtering and signal edge detection circuit 105, which is a preferred embodiment of the present application, is shown in the operation flowchart of the highest level variable Hi_count and the lowest level variable Low_cout. Please refer to Figure 4 The operation of the noise filtering and signal edge detection circuit 105, which is a preferred embodiment of the present application, includes the following steps:

[0072] Step S401: Initial reset. Set the highest level variable Hi_count and the lowest level variable Low_cout to 0.

[0073] Step S402: Input the current level number in_level.

[0074] Step S403: Determine whether the current level number in_level is greater than the highest level variable Hi_count. If the determination is yes, proceed to step S405.

[0075] Step S404: Determine whether the current level number in_level is less than the lowest level variable Low_cout. If the determination is yes, proceed to step S406.

[0076] Step S405: Set the highest level variable Hi_count to the current level number in_level. Then proceed to step S407.

[0077] Step S406: Set the lowest bit variable Low_cout to the current bit number in_level. After this, proceed to step S407.

[0078] Step S407: Determine whether the difference between the highest bit variable Hi_count and the lowest bit variable Low_cout is greater than a noise tolerance difference. In this embodiment, the noise tolerance difference is set to 1. When the difference between the highest bit variable Hi_count and the lowest bit variable Low_cout is greater than the noise tolerance difference, the noise filter and signal edge detection circuit 105 is triggered to output an edge detection pulse, and the highest bit variable Hi_count and the lowest bit variable Low_cout are set to the current bit number in_level.

[0079] Figure 5 The operation waveform diagram of the noise filter and signal edge detection circuit 105, which is a preferred embodiment of the present application, is shown in FIG. 4. Please refer to Figure 5 , so that those skilled in the art can understand the above-mentioned Figure 3 , Figure 4 embodiments, the variable visualization graph is used here, and the change of the variable is marked on the graph. As can be seen, at the beginning, when the signal Comparator_Slice OUT[0] at the output end of the comparator 203 changes from a logic low voltage to a logic high voltage, the highest bit variable Hi_count becomes 1, the lowest bit variable Low_cout remains 0, and the current bit number in_level changes from 0 to 1 via the flow of Figure 4 . Next, when the signal Comparator_Slice OUT[1] at the output end of the comparator 202 changes from a logic low voltage to a logic high voltage, the highest bit variable Hi_count becomes 2, the lowest bit variable Low_cout remains 0, and the current bit number in_level changes from 1 to 2 via the flow of Figure 4 . Since step S407 is triggered here, at this time, the noise filter and signal edge detection circuit 105 outputs an edge detection pulse, and the highest bit variable Hi_count becomes 2, the lowest bit variable Low_cout also changes to 2, and the current bit number in_level becomes 2.

[0080] Next, when the signal Comparator_Slice OUT[2] at the output end of the comparator 203 changes from a logic low voltage to a logic high voltage, the highest bit variable Hi_count becomes 3, the lowest bit variable Low_cout remains 2, and the current bit number in_level changes from 2 to 3 via the flow of Figure 4In the process, the highest level variable Hi_count will become 3, the lowest level variable Low_cout will maintain 2, and the current level number in_level will change from 2 to 3. Then, when the signal Comparator_Slice OUT[2] at the output end of the comparator 203 changes from a logic high voltage to a logic low voltage, Figure 4 In the process, the highest level variable Hi_count will maintain 3, the lowest level variable Low_cout will maintain 2, and the current level number in_level will change from 3 to 2. When the signal Comparator_Slice OUT[1] at the output end of the comparator 202 changes from a logic high voltage to a logic low voltage, Figure 4 In the process, the highest-level variable Hi_count remains at 3, the lowest-level variable Low_cout becomes 1, and the current-level number in_level changes from 2 to 1. Similarly, at this time, since step S407 is triggered, the noise filtering and signal edge detection circuit 105 outputs an edge detection pulse, and the highest-level variable Hi_count becomes 1, the lowest-level variable Low_cout also changes to 1, and the current-level number in_level becomes 1.

[0081] Next, when the signal Comparator_Slice OUT[0] at the output terminal of the comparator 201 changes from a logic high voltage to a logic low voltage, Figure 4 In the process, the highest level variable Hi_count will remain 1, the lowest level variable Low_cout will become 0, and the current level number in_level will change from 1 to 0. Then, when the signal Comparator_Slice OUT[0] at the output end of the comparator 201 changes from a logic low voltage to a logic high voltage, Figure 4 In the process, the highest level variable Hi_count will maintain 1, the lowest level variable Low_cout will maintain 0, and the current level number in_level will change from 0 to 1. The following embodiments can be deduced from the above rules. Therefore, they will not be described in detail here.

[0082] Figure 6 FIG2 is a waveform diagram of the operation of the noise filtering and signal edge detection circuit 105 according to a preferred embodiment of the present invention. Figure 6 , where Edge_detected is the edge detection pulse output by the noise filtering and signal edge detection circuit 105. Bit_OUT is the noise-eliminated decoded signal Bit_OUT decoded by the digital signal processing circuit 106 based on the edge detection pulse output by the noise filtering and signal edge detection circuit 105.

[0083] Figure 7 The operation waveform diagram of the first comparator 201, the second comparator 202, and the third comparator 203 when encountering noise is shown as a preferred embodiment of the present application. Please refer to Figure 7 In this embodiment, it can be seen that when the analog signal Analog_RCed to be decoded encounters noise passing through the reference voltage levels HTH, MTH, and LTH, the comparators 201, 202, 203 are triggered to change, resulting in the comparators 201, 202, 203 outputting inappropriate noise pulses 701, 702, 703, 704, respectively.

[0084] Figure 8 The operation waveform diagram of the noise filtering and signal edge detection circuit 105 is shown as a preferred embodiment of the present application. Please refer to Figure 8 In this embodiment, it can be seen that before the time of the noise pulse 701, the highest bit variable Hi_count and the lowest bit variable Low_cout are both set to 1 due to the triggering of step S407. Therefore, at the time of the noise pulse 701, the highest bit variable Hi_count changes to 2, and the lowest bit variable Low_cout remains at 1, so the noise filtering and signal edge detection circuit 105 is not triggered to output an edge detection pulse. By the same token, at the time of the noise pulse 703, the highest bit variable Hi_count is 1, and the lowest bit variable Low_cout remains at 0, so the noise filtering and signal edge detection circuit 105 is not triggered to output an edge detection pulse. At the time of the noise pulse 704, the highest bit variable Hi_count is 2, and the lowest bit variable Low_cout remains at 2, so the noise filtering and signal edge detection circuit 105 is not triggered to output an edge detection pulse as well.

[0085] The above embodiments are for those skilled in the art to understand the present application, so three comparators 201, 202, 203 and three values are used as examples, and the noise tolerance difference is simply set to 1. However, those skilled in the art, after referring to the above embodiments, should understand that the more comparators are designed, the more digital designs are made, and the noise tolerance difference is also designed to be larger, so that more accurate noise filtering results can be obtained. In addition, although the above embodiments are used as examples of the Universal Serial Bus Power Delivery (USB PD) protocol, and the Bi-Phase Marker Coded (BMC) decoding is used as an example. However, those skilled in the art should know that other encoding methods in other application fields, such as Manchester encoding, can also use the decoding and noise filtering techniques of the present application, so the present application is not limited thereto.

[0086] The above embodiment is an edge detection technique for noise cancellation of a burst pulse. However, there are also three types of DC noise as described in the prior art, i.e. the DC voltage amplitude of the external signal, which often causes the voltage of the input signal to deviate from the allowed logic voltage level, further causing decoding errors. In the following embodiment, the above edge detection method is also used. The difference is that the noise filtering and signal edge detection circuit 105 is optimized according to the above-processed DC noise.

[0087] Figure 9 A circuit block diagram of a decoding circuit according to a preferred embodiment of the present application is shown. Referring to Figure 9 The decoding circuit includes the above-mentioned three comparators 201, 202, 203, the first adjustable reference voltage generating circuit 901, the second adjustable reference voltage generating circuit 902, the third adjustable reference voltage generating circuit 903, the noise filtering and signal edge detection circuit 105, and the digital signal information processing circuit 904. In order to make the decoded decoding signal predictable, in this embodiment, the analog signal Analog_RCed to be decoded is derived from a known signal transmitted, in this case, the preferred choice is the preamble defined in the above transmission protocol, since the preamble is a 64-bit 010101 staggered occurrence, the decoded decoding signal is predictable.

[0088] In this embodiment, the noise filtering and signal edge detection circuit 105 uses the above-mentioned Figures 1 to 8 However, in the case of the above noise authentication condition TX_GROUP_3, the logic low voltage is forced to rise to 250mV, so in this case, if the reference voltage LTH generated by the third reference voltage generating circuit 903 is less than 250mV, the comparator 203 will always output, for example, a positive saturation voltage. By the same token, for example, in the case of the above noise authentication condition TX_GROUP_2, the logic high voltage is forced to drop to 790mV, so in this case, if the reference voltage HTH generated by the reference voltage generating circuit 901 is greater than 790mV, the comparator 201 will always output, for example, a negative saturation voltage.

[0089] The digital signal information processing circuit 904 receives the edge detection signal Vedge after edge detection by the comparators 201, 202, 203, and decodes the edge detection signal to obtain a bit restoration signal. At this time, since the signal before decoding is the preamble, the bit restoration signal should be the decoding result of 64 0101 interlaced codes in theory. At this time, any two adjacent bits must be a first logic (for example, logic 1) and a second logic (for example, logic 0). At this time, ideally, the bit time length of the first logic should be equal to the bit time length of the second logic. However, if disturbed by the TX_GROUP_2 or TX_GROUP_3 as described above, the bit time length of the first logic and the bit time length of the second logic will not be equal.

[0090] Therefore, in this embodiment, the digital signal information processing circuit 904 detects the time proportion of the logic 1 and the logic 0 of the bit restoration signal. Normally, the time proportion should be equal to 1. If the time proportion is greater than normal, for example, 80%, the first adjustable reference voltage generating circuit 901 is adjusted to lower the higher reference voltage HTH. Similarly, if the time proportion is less than normal, for example, 20%, the third adjustable reference voltage generating circuit 903 is adjusted to raise the lower reference voltage LTH. In this way, during decoding of the preamble, the bit time length of the first logic of the decoded bit restoration signal is made equal to the bit time length of the second logic. In this way, the subsequent data can be subjected to the best edge detection signal by the adjusted reference voltage, and the decoding result will tend to be ideal. The decoding accuracy will be greatly improved.

[0091] Figure 10 A flowchart of a decoding method for reducing the influence of power signal line noise on decoding, which is a preferred embodiment of the present application, is shown. Please refer to Figure 10 The decoding method for reducing the influence of power signal line noise on decoding includes the following steps:

[0092] Step S1001: Start.

[0093] Step S1002: Compare the voltage level of a to-be-decoded analog signal with a plurality of reference voltages to generate a plurality of comparison signals.

[0094] Step S1003: Perform an edge detection procedure according to the plurality of comparison signals to obtain an edge detection signal.

[0095] Step S1004: Decode the edge detection signal. In this way, the proportion of the time length of the first logic to the time length of the second logic of the decoded signal is obtained.

[0096] Step S1005: judging the ratio of the time length of the first logic to the time length of the second logic of the decoded signal. If the ratio is judged to be greater than the first threshold TH1, step S1006 is performed. If the ratio is judged to be less than the second threshold TH2, step S1007 is performed. The first threshold TH1 is, for example, 80% as described above, and the second threshold TH2 is, for example, 20% as described above. However, those skilled in the art should understand that the values are only for illustrating the spirit of the present application, and the values can be adjusted by the designer in actual operation, such as 60% and 40%, and the present application is not limited in this way.

[0097] Step S1006: adjusting the higher reference voltage HTH.

[0098] Step S1007: adjusting the lower reference voltage LTH.

[0099] In the above embodiment, the analog signal to be decoded is decoded according to the pre-signal. However, those skilled in the art should understand that any predictable known signal can be used. Therefore, the present application is not limited in this way. In addition, although the above embodiment only adjusts the higher reference voltage HTH and the lower reference voltage LTH, in implementation, the entire reference voltage can be adjusted upward or downward, and the present application is not limited in this way.

[0100] Figure 11 A flow chart of an edge detection procedure of a decoding method for reducing the influence of power signal line noise on decoding, which is a preferred embodiment of the present application, is shown. Please refer to Figure 11 The edge detection procedure includes the following steps:

[0101] Step S1101: dividing the voltage level of an analog signal to be decoded into a plurality of levels. As described above in the embodiment, a plurality of comparators are used to detect the voltage levels of the analog signal to be decoded. Figure 2

[0102] Step S1102: sequentially assigning a constant difference number to the plurality of levels. As described above in the preferred embodiment, 1, 2, and 3 are used as an example, and those skilled in the art can also use 2, 4, 6, etc., and the present application is not limited in this way. The numbers can be changed according to the difference between the levels.

[0103] Step S1103: judging the level of the analog signal to be decoded and obtaining a current level number of the analog signal to be decoded. As described above in the decoding method. Figure 3

[0104] ​​Step S1104: When the current step number is greater than a highest step variable, update the highest step variable, and when the current step number is less than a lowest step variable, update the lowest step variable. As described above in steps S403-S406 of the embodiment.

[0105] Step S1105: When the difference between the lowest step variable and the highest step variable is greater than a noise tolerance difference, output an edge detection pulse, and set the highest step variable and the lowest step variable to the current step number, and continue to determine the level of the analog signal to be decoded to obtain the current step number.

[0106] In summary, the embodiment of the present application uses a known signal, and through a plurality of comparators and a plurality of reference voltages, respectively samples the received signal to be decoded, converts it into a current step number, and generates an edge detection signal. And at the same time, it decodes, and compares the ratio of the time length of the first logic and the time length of the second logic of the decoded signal to the ideal ratio of the known signal. When the difference is higher than a first threshold value or lower than a second threshold value, the reference voltage is adjusted, so that the decoded signal tends to be the ideal decoded signal. In this way, the subsequent decoding can use the adjusted reference voltage for edge detection. Therefore, the present application can solve the bit misjudgment caused by DC noise.

[0107] In addition, in the preferred embodiment, the edge detection procedure uses a plurality of levels, defines the values corresponding to the plurality of levels, the current step number, the highest step variable, and the lowest step variable, detects the time when the analog signal to be decoded reaches the plurality of levels, changes the current step number, the highest step variable, and the lowest step variable according to the step number reached by the analog signal to be decoded, and when the difference between the highest step variable and the lowest step variable is greater than a noise tolerance difference, triggers an edge detection pulse and sets the highest step variable and the lowest step variable equal to the current step number. In this way, even if the difference between the highest step variable and the lowest step variable is affected by noise and changes, as long as it is less than the noise tolerance difference, it will not affect the operation of the circuit.

[0108] It should be understood that the examples and embodiments described herein are for illustrative purposes only, and various modifications or changes will be suggested to persons skilled in the art in light of the same, and will be included within the spirit and scope of the present application and the scope of the appended claims.

Claims

1. A decoding method for reducing the effect of power supply line noise on decoding, characterized by, The method comprises: comparing a voltage level of an analog signal to be decoded with a plurality of reference voltages to generate a plurality of comparison signals; performing an edge detection procedure according to the plurality of comparison signals to obtain an edge detection signal; decoding the edge detection signal to obtain a ratio of a time length of a first logic to a time length of a second logic of a decoded signal; adjusting a highest reference voltage among the plurality of reference voltages when the ratio is greater than a first threshold value; and adjusting a lowest reference voltage among the plurality of reference voltages when the ratio is less than a second threshold value, wherein the analog signal to be decoded is obtained according to a known signal transmission. The analog signal to be decoded is obtained from a channel configuration pin of a universal serial bus port.

2. The decoding method of claim 1, wherein the decoding method is characterized by: The analog signal to be decoded is modulated according to a bi-phase mark code.

3. The decoding method for reducing the influence of power signal line noise on decoding according to claim 1, characterized in that: The edge detection procedure comprises:

4. The decoding method of claim 1, wherein the decoding method is characterized by: judging a voltage level of the analog signal to be decoded and obtaining a current level number of the analog signal to be decoded to obtain a current level number; updating a highest level variable when the current level number is greater than the highest level variable; updating a lowest level variable when the current level number is less than the lowest level variable; and outputting an edge detection pulse when a difference between the lowest level variable and the highest level variable is greater than a noise tolerance difference, and setting the highest level variable and the lowest level variable to the current level number, and continuously judging the voltage level of the analog signal to be decoded to obtain the current level number; and generating the edge detection signal according to the edge detection pulse. The known signal is a preamble.

5. The decoding method of claim 1, wherein the step of decoding the data stream comprises the step of: decoding the data stream using a trellis decoder to produce a decoded data stream, wherein the trellis decoder is configured to decode the data stream using a trellis codebook that is based on a trellis codebook used by the encoder. The method comprises:

6. A decoding circuit, characterized by comprising: a plurality of comparators, wherein each of the plurality of comparators comprises a first end, a second end, and an output end, the first ends of the plurality of comparators receive an analog signal to be decoded, the second ends of the plurality of comparators are respectively coupled to a plurality of reference voltages, wherein the plurality of reference voltages are different from each other, and the output ends of the plurality of comparators output a plurality of comparison signals; a noise filtering and signal edge detection circuit coupled to the output ends of the plurality of comparators; wherein the noise filtering and signal edge detection circuit performs an edge detection procedure according to the plurality of comparison signals to obtain an edge detection signal; wherein the decoding circuit further comprises: a digital signal information processing circuit coupled to the output end of the noise filtering and signal edge detection circuit, and generates a decoded signal according to the edge detection signal to obtain a ratio of a time length of a first logic to a time length of a second logic of the decoded signal; wherein a highest reference voltage among the plurality of reference voltages is adjusted when the ratio is greater than a first threshold value, and a lowest reference voltage among the plurality of reference voltages is adjusted when the ratio is less than a second threshold value, wherein the analog signal to be decoded is obtained according to a known signal transmission. The analog signal to be decoded is obtained from a channel configuration pin of a universal serial bus port.

7. The decoding circuit of claim 6, wherein, ​ 8. The decoding circuit of claim 6, wherein, The analog signal to be decoded is modulated according to a bi-phase mark code, and the digital signal information processing circuit is a bi-phase mark code decoding circuit.

9. The decoding circuit of claim 6, wherein, The noise filtering and signal edge detection circuit judges the current level of the analog signal to be decoded according to the signals outputted by the outputs of the plurality of comparators to obtain a current bit level number; The noise filtering and signal edge detection circuit has a highest bit level variable and a lowest bit level variable inside, When the current bit level number is greater than the highest bit level variable, the highest bit level variable is updated to be the current bit level number; When the current bit level number is less than the lowest bit level variable, the lowest bit level variable is updated to be the current bit level number, When the difference between the lowest bit level variable and the highest bit level variable is greater than a noise tolerance difference value, the noise filtering and signal edge detection circuit outputs an edge detection pulse, sets the highest bit level variable and the lowest bit level variable to be the current bit level number, and continuously judges the level of the analog signal to be decoded to obtain the current bit level number.

10. The decoding circuit of claim 6, wherein, The known signal is a pre-signal.

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