Message uploading method, data processing unit and computer program product

Abstract

The invention relates to a message uploading method, a data processing unit and a computer program product, and the method comprises the steps: firstly caching and updating a count after receiving a queue message, determining the number n1 of descriptors needing to be read according to a descriptor index when a queue does not cache a descriptor, reading m1 descriptors (m1 is greater than or equal to n1) from a host side according to cache line alignment, writing the message into a host cache by using n1 descriptors, and updating a count and an index; if the message is processed and the descriptors are left, caching the descriptors which are not used; when the queue has cache descriptors, the cache descriptors are preferentially used for writing messages, if the cache descriptors are not completely written, the number n2 of the descriptors needing to be read is determined according to the descriptor index, m2 (m2 > = n2) descriptors are read from the host side according to cache line alignment to process remaining messages, and if the messages are completely processed and the descriptors are remaining after updating, the descriptors are not used in the same cache. According to the invention, the problem of read delay of the descriptor can be solved, and the overall message processing efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of VIRTIO, and particularly relates to a message uploading method, a data processing unit and a computer program product. BACKGROUND

[0002] VIRTIO is a general-purpose semi-virtualization I / O framework, which realizes data interaction between a host and a guest. VIRTIO is composed of a front-end driver, a back-end device and a virtualization queue (Virtqueue). In order to improve the performance of VIRTIO, a hardware offloading technology of a VIRTIO data plane appears, that is, the back-end device is implemented by hardware.

[0003] Data interaction between the front-end driver and the back-end device is implemented through the virtualization queue. According to the VIRTIO protocol, a commonly used virtualization queue is a Split Virtqueue, and one Split Virtqueue is composed of a descriptor table, an available ring table and a used ring table. In order to solve the performance problem of the Split Virtqueue, a Packed Virtqueue is proposed in the 1.1 version of the VIRTIO protocol. The Packed Virtqueue is equivalent to merging the three ring tables of the Split Virtqueue into one descriptor ring table (Descriptor Ring), and each descriptor of the descriptor ring table contains a buffer address, a buffer length, a buffer id and a flag of a buffer attribute.

[0004] Taking the Packed Virtqueue as an example, a typical VIRITO network device data receiving process is as shown in Figure 1 The VIRTIO driver needs to prepare a buffer unit before the VIRTIO network device works, and the steps are as follows: Step 11, the VIRTIO driver prepares a buffer unit for storing an Ethernet message, and stores the buffer unit address, buffer unit length, buffer unit index, buffer attribute flag and other information of the buffer unit into the descriptor of the descriptor ring table, and updates the index value buffer id of each descriptor.

[0005] Step 12: Send a notification (Notify) to the VIRTIO network device, indicating that the cache unit of the VIRTIO network device is ready.

[0006] After the VIRTIO driver prepares the cache unit, the VIRTIO network device starts working and receives packet data. The data receiving process of the VIRTIO network device is as follows: Step 21: Receive Ethernet message data and store the message data in the local cache of the device; Step 22: Initiate a descriptor read operation to the VIRTIO driver, read the descriptor of the descriptor ring table, and obtain information such as the cache unit address, cache unit length, cache unit index, and cache attribute flag in the descriptor; Step 23: read the Ethernet message data from the local cache of the VIRTIO network device, send it to the VIRTIO driver, and store it in the cache unit pointed to by the cache unit address; Step 24 updates the used descriptors, i.e., updates the descriptor information of the descriptor ring table, and reports an interrupt to the VIRTIO driver, so that the VIRTIO driver obtains the Ethernet message data stored in the cache unit by reading information such as the cache unit address and cache unit index, and recycles the descriptors in the descriptor ring table for continued use.

[0007] In the above scheme, the descriptor ring table driven by VIRTIO is stored in the cache on the host side. The CPU operates according to a cache line when reading or writing the cache. For example, assuming that the size of a cache line is 64 bytes and the size of a VIRTIO Packed descriptor is 16 bytes, a cache line can store 4 descriptors, such as Figure 2 As shown in the figure, under normal circumstances, the descriptor Descriptor0 of the descriptor ring table is the first 16 bytes of the cache line. The number of descriptors initiated by the VIRTIO network device to read is based on the actual number required. For example, the VIRTIO network device receives an Ethernet message and then reads a descriptor Descriptor0 from the VIRTIO driver, as shown in the figure. Figure 2The Device sends the packet to the buffer pointed by Descriptor0, and then updates Descriptor0 in the descriptor ring table of the VIRTIO driver. At this time, the VIRTIO driver needs to read the entire cache line (including Descriptor0, Descriptor1, Descriptor2, and Descriptor3) first, mark Descriptor0 as used, update the buffer length and buffer id of Descriptor0, and then write the entire cache line back to the descriptor ring table. If the VIRTIO network device initiates reading of Descriptor1 immediately after initiating updating of Descriptor0, Descriptor1 cannot be read until the updating of Descriptor0 is completed, and the updating of Descriptor0 needs the read-before-write operation of the cache line, which increases the reading delay of Descriptor1 and reduces the packet processing efficiency. SUMMARY

[0008] The present application aims to provide a packet uploading method, a data processing unit, and a computer program product to solve the reading delay of descriptors and improve the packet processing efficiency.

[0009] To achieve the above-mentioned purpose, according to a first aspect of the present application, a packet uploading method is provided, and the method comprises: when receiving a packet of any queue, buffering the packet in the data processing unit and updating the number of buffered packets of the queue; obtaining the number of descriptors and the descriptor index of the queue buffered in the data processing unit; wherein the descriptor index points to the position of the next descriptor to be read in the descriptor ring table; in the case where the number of descriptors is 0, determining the number n1 of descriptors to be read according to the descriptor index, reading m1 descriptors from the descriptor ring table on the host side based on the cache line alignment mode, obtaining n1 descriptors to be read according to the m1 descriptors, writing the packet of the queue into at least one descriptor pointed by the n1 descriptors on the host side, updating the number of buffered packets of the queue and the descriptor index, and buffering the unused descriptors in the data processing unit if the number of buffered packets of the queue after updating is 0 and the n1 descriptors are not all used; wherein m1≥n1; In the scenario where the number of the descriptors is greater than 0, the packets of the queue are written into the host-side cache unit pointed by the descriptors of the data processing unit, if the packets of the queue fail to be completely written into the host-side cache unit pointed by the descriptors of the data processing unit, the number n2 of descriptors to be read is determined according to the descriptor index, m2 descriptors are read from the descriptor ring table of the host side based on the cache line alignment mode, and n2 descriptors to be read are obtained according to the m2 descriptors, the remaining packets of the queue are written into the host-side cache unit pointed by at least one descriptor of the n2 descriptors, and the number of the cached packets of the queue and the descriptor index are updated; if the number of the cached packets of the queue after the update is 0 and the n2 descriptors are not all used, the unused descriptors are cached in the data processing unit; wherein m2≥n2.

[0010] Preferably, the method comprises: In the scenario where the number of the descriptors is 0, if the number of the cached packets of the queue after the update is not 0 and the n1 descriptors are all used, the number n3 of descriptors to be read is determined according to the updated descriptor index, m3 descriptors are read from the descriptor ring table of the host side based on the cache line alignment mode, n3 descriptors to be read are obtained according to the m3 descriptors, the remaining packets of the queue are written into the host-side cache unit pointed by at least one descriptor of the n3 descriptors, and the number of the cached packets of the queue and the descriptor index are updated; wherein m3≥n3.

[0011] Preferably, the step of determining the number n1, n2 or n3 of descriptors to be read according to the descriptor index comprises: n = cache_bd_num - 1 - (bd_index + req_num - 1) % cache_bd_num + req_num; Wherein n is the number n1, n2 or n3 of descriptors to be read, % is the remainder operator, cache_bd_num is the number of descriptors in a cacheline, bd_index is the descriptor index, and req_num is the predicted number of descriptors required, one packet processing request requires one descriptor.

[0012] Preferably, the step of obtaining n1 descriptors to be read according to the m1 descriptors comprises: selecting n1 descriptors from the m1 descriptors as the n1 descriptors to be read according to the descriptor index; The step of obtaining n2 descriptors to be read according to the m2 descriptors comprises: selecting n2 descriptors from the m2 descriptors as the n2 descriptors to be read according to the descriptor index. The step of obtaining n3 descriptors to be read from the m3 descriptors according to the m3 descriptors comprises: selecting n3 descriptors from the m3 descriptors as the n3 descriptors to be read according to the descriptor index.

[0013] According to a second aspect of the present application, a data processing unit is provided, comprising: a packet storage module, configured to buffer a packet of any queue in the data processing unit when the packet is received, and update the number of buffered packets of the queue; a descriptor query module, configured to obtain the number of descriptors of the queue buffered in the data processing unit; an index obtaining module, configured to obtain a descriptor index; wherein the descriptor index points to the position of the next descriptor to be read in the descriptor ring table; a descriptor reading module, configured to, in a scenario where the number of descriptors is 0, determine the number n1 of descriptors to be read according to the descriptor index, read m1 descriptors from the descriptor ring table on the host side based on a cache line alignment mode, and obtain n1 descriptors to be read according to the m1 descriptors; wherein m1≥n1; a packet reporting module, configured to write the packets of the queue into the host side cache unit pointed to by the currently read descriptor, and update the number of buffered packets of the queue and the descriptor index; and a descriptor storage module, configured to, if the updated number of buffered packets of the queue is 0 and the n1 descriptors are not all used, buffer the unused descriptors in the data processing unit; The packet reporting module is further configured to, in a scenario where the number of descriptors is greater than 0, write the packets of the queue into the host side cache unit pointed to by the descriptor buffered in the data processing unit; The descriptor reading module is further configured to, if the packets of the queue fail to be completely written into the host side cache unit pointed to by the descriptor buffered in the data processing unit, determine the number n2 of descriptors to be read according to the descriptor index, read m2 descriptors from the descriptor ring table on the host side based on the cache line alignment mode, and obtain n2 descriptors to be read according to the m2 descriptors; wherein m2≥n2; The packet reporting module is further configured to write the remaining packets of the queue into the host side cache unit pointed to by at least one of the n2 descriptors, and update the number of buffered packets of the queue and the descriptor index; The descriptor storage module is further configured to, if the updated number of buffered packets of the queue is 0 and the n2 descriptors are not all used, buffer the unused descriptors in the data processing unit.

[0014] Preferably, the descriptor reading module is further configured to, in a scenario where the number of the descriptors is 0, if the number of cached packets of the queue after updating is not 0 and the n1 descriptors have all been used, determine the number n3 of descriptors to be read according to the updated descriptor index, read m3 descriptors from the descriptor ring table on the host side based on the cache line alignment mode, and obtain the n3 descriptors to be read according to the m3 descriptors; wherein m3≥n3. The packet reporting module is further configured to write the packets of the queue into the host side cache unit pointed to by at least one of the n3 descriptors, and update the number of cached packets of the queue and the descriptor index.

[0015] Preferably, the descriptor reading module comprises: a first descriptor number obtaining module configured to predict the number of descriptors needed, one packet processing request needing one descriptor; a second descriptor number obtaining module configured to determine the number n1, n2 or n3 of descriptors to be read according to the descriptor index and the predicted number of descriptors needed; a descriptor reading module configured to read corresponding m1, m2 or m3 descriptors from the descriptor ring table on the host side based on the cache line alignment mode according to the number n1, n2 or n3 of descriptors; a descriptor processing module configured to obtain corresponding n1, n2 or n3 descriptors according to the m1, m2 or m3 descriptors.

[0016] Preferably, the data processing unit comprises: a packet storage RAM configured to store the packets of the any queue; a packet number RAM configured to store the number of cached packets of the any queue; a descriptor storage RAM configured to store the unused descriptors; a descriptor read-write pointer RAM configured to store a read pointer and a write pointer, the read pointer pointing to the position of the descriptor currently read from the descriptor storage RAM, and the write pointer pointing to the position of the descriptor currently written into the descriptor storage RAM; a descriptor FIFO module configured to store the n1, n2 or n3 descriptors read; a descriptor index storage RAM configured to store the descriptor index; wherein the value of the descriptor index is incremented by one each time a descriptor is read from the descriptor FIFO module.

[0017] According to a third aspect of the present application, a data processing unit is provided, comprising: a communication interface configured to communicate with other electronic devices; a memory for storing computer program instructions; A processor is used to execute the computer program instructions to support the data processing unit to implement the method as described in the first aspect of the present application.

[0018] According to a fourth aspect of the present application, a computer program product is provided, comprising computer program instructions, wherein the computer program instructions instruct a computer device to perform corresponding operations as described in the first aspect of the present application.

[0019] The present application proposes a message sending method, a data processing unit, and a computer program product having the following beneficial effects: Each time the data processing unit reads a descriptor, it batch-reads multiple descriptors from the descriptor ring table on the host side through the "cache line alignment method". The multiple descriptors read are used for message uploading. When the message uploading is completed and there are unused descriptors, the unused descriptors are temporarily stored in the data processing unit, thereby quickly providing ready descriptors for message writing operations. Specifically, when the host side is processing the previous message, the data processing unit can simultaneously take out the next descriptor from the local cache for message uploading, thereby eliminating the idle waiting time caused by waiting for descriptors to be read, greatly improving the descriptor reading efficiency, and fundamentally solving the descriptor reading delay problem caused by the cache line characteristics in the traditional VIRTIO Packed Virtqueue mode, thereby improving message processing efficiency.

[0020] Other features and advantages of the present application will be set forth in the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0022] Figure 1 This is a schematic diagram of the message receiving principle of the VIRITO network device disclosed in the background technology.

[0023] Figure 2 The schematic diagram of the descriptor reading disclosed in the background art.

[0024] Figure 3 This is a flowchart of a message sending method in one embodiment of the present application.

[0025] Figure 4 A schematic diagram of a descriptor reading principle in one embodiment of the present application.

[0026] Figure 5 A software module diagram of a data processing unit in one embodiment of the present application.

[0027] Figure 6 A hardware circuit diagram of a data processing unit in one embodiment of the present application. DETAILED DESCRIPTION

[0028] The detailed description of the drawings is intended as a description of the current preferred embodiments of the present application and is not intended to represent the only forms in which the present application can be constructed or utilized. It is to be understood that the same or equivalent functions can be accomplished by different embodiments that are intended to be encompassed within the scope of the application.

[0029] One embodiment of the present application provides a packet uploading method applied to a data processing unit (i.e. hardware implementing a VIRTIO network device), which introduces a pre-fetch mechanism on the data processing unit side to prepare descriptors in advance, thereby eliminating descriptor reading waiting time, avoiding conflicts with host side operations of updating a descriptor ring table, and the like. Figure 3 The method of the present embodiment includes the following steps: Step S10, when receiving a packet of any queue, buffering the packet in the data processing unit and updating the number of buffered packets of the queue; Specifically, a data processing unit (DPU) and a host (Host) perform data communication through multiple queues (Virtqueues). When the DPU receives a packet of any queue, the DPU stores the received packet in the DPU buffer according to the queue, waits for uploading to the Host, and maintains the number of buffered packets of each queue, which is updated in real time according to the packets currently buffered in the DPU.

[0030] Step S20, obtaining the number of descriptors and a descriptor index of the descriptors buffered in the data processing unit, wherein the descriptor index points to the position of the next descriptor to be read in the descriptor ring table; Specifically, before processing the packet in the DPU buffer, the DPU first checks whether a usable descriptor has been pre-fetched and buffered in the DPU. This is a key decision point of the method of the present embodiment, which determines which processing path the DPU should adopt next: whether to read a descriptor from the host side descriptor ring table or to directly use the descriptor buffered in the DPU. In addition, the DPU locally maintains a descriptor index, which points to the position of the next descriptor to be read in the descriptor ring table.

[0031] In step S30, in the case where the number of descriptors is 0, the number n1 of descriptors to be read is determined according to the descriptor index, m1 descriptors are read from the descriptor ring table on the host side based on cache line alignment, n1 descriptors to be read are obtained according to the m1 descriptors, the packets of the queue are written to the host side buffer unit pointed to by at least one of the n1 descriptors, and the number of cached packets of the queue and the descriptor index are updated; if the updated number of cached packets of the queue is 0 and the n1 descriptors are not all used, the unused descriptors are cached in the data processing unit; wherein m1≥n1. Specifically, if it is found in step S20 that there are no descriptors of the queue pre-fetched locally in the DPU (i.e. the number is 0), the DPU will start a one-time batch reading operation of the descriptors. First, the number n1 of descriptors to be read is determined according to the descriptor index, which can be understood as a read address, and the number n1 of descriptors, which can be understood as the number of available descriptors in the m1 descriptors read, i.e. the number of effective descriptors. Based on the descriptor index and the number n1 of descriptors, it can be determined how many cache lines of descriptors need to be batch read. Assuming that each descriptor is 16 bytes and each cache line is 64 bytes, one cache line contains 4 descriptors, then m1 is an integer multiple of 4, and n1 is the number of descriptors that the DPU expects to batch read, which is related to the descriptor index. The descriptors are read in a cache line alignment manner as shown in Figure 4 . After obtaining the n1 descriptors, the DPU sends the locally cached packets one by one to the host side buffer unit (buffer) pointed to by at least one of the n1 descriptors. If there are remaining n1 descriptors after all the packets of the queue are processed, the unused descriptors will be reserved in the DPU cache for later use, realizing pre-fetching and standby of the descriptors.

[0032] In the case where the number of descriptors is greater than 0, the packets of the queue are written into the host-side cache unit pointed to by the descriptors of the data processing unit, and if the packets of the queue cannot be completely written into the host-side cache unit pointed to by the descriptors of the data processing unit, the number n2 of descriptors to be read is determined according to the descriptor index, m2 descriptors are read from the descriptor ring table of the host side based on the cache line alignment mode, and n2 descriptors to be read are obtained according to the m2 descriptors, the remaining packets of the queue are written into the host-side cache unit pointed to by at least one of the n2 descriptors, and the number of cached packets of the queue and the descriptor index are updated; if the number of cached packets of the queue after the update is 0 and the n2 descriptors are not all used, the unused descriptors are cached in the data processing unit; wherein m2≥n2.

[0033] Specifically, when the number of descriptors is greater than 0, it indicates that there are still unused descriptors remaining after the last execution of the write operation of the packets of the queue, and then the descriptors cached in the DPU can be directly used to improve the packet processing efficiency; if the storage space of the buffer pointed to by the descriptors cached in the DPU is insufficient to store all the packets of the queue, after the descriptors cached in the DPU are used up, a one-time batch reading operation of descriptors is started; first, the number n2 of descriptors to be read is determined according to the descriptor index, the descriptor index can be understood as a read address, and the number n2 of descriptors can be understood as a length, based on the descriptor index and the number n2 of descriptors, it can be determined how many cache lines of descriptors need to be batch read, assuming that each descriptor is 16 bytes and each cache line is 64 bytes, and one cache line contains 4 descriptors, then m2 is an integer multiple of 4, and n2 is the number of descriptors expected to be batch read by the DPU, which is related to the descriptor index; after obtaining the n2 descriptors, the DPU uploads the remaining packets of the queue in the local cache one by one to the buffer pointed to by at least one of the n2 descriptors, if the n2 descriptors read still have remaining after all the packets of the queue are processed, the unused descriptors will be reserved in the DPU cache for later use, realizing the pre-fetching and standby of the descriptors.

[0034] Based on the description of the above embodiments, it can be known that in the method of the embodiment, the DPU reads multiple descriptors from the descriptor ring table on the host side in batches through the "cache line alignment mode" each time the descriptor is read, and the multiple descriptors read are used for packet uploading. When the packet uploading is completed and there is an unused descriptor, the unused descriptor is temporarily stored in the DPU, so as to quickly provide a ready descriptor for packet write operation. Specifically, when the host side is processing the last packet, the DPU can simultaneously take out the next descriptor from the local cache for packet uploading, thereby eliminating the idle waiting time caused by waiting to read the descriptor, greatly improving the descriptor reading efficiency, fundamentally solving the descriptor reading delay problem caused by the cache line feature in the PackedVirtqueue mode of the traditional VIRTIO, and improving the packet processing efficiency.

[0035] In some embodiments, the method comprises: In the scenario where the number of the descriptors is 0, if the number of the cached packets of the queue after the update is not 0 and the n1 descriptors have all been used, the number n3 of the descriptors to be read is determined according to the updated descriptor index, m3 descriptors are read from the descriptor ring table on the host side based on the cache line alignment mode, the n3 descriptors to be read are obtained according to the m3 descriptors, the remaining packets of the queue are written into the host side cache unit pointed to by at least one of the n3 descriptors, and the number of the cached packets of the queue and the descriptor index are updated; wherein m3≥n3.

[0036] Specifically, in the scenario where the number of the descriptors is 0, if the n1 descriptors currently read have all been used, and there are still messages of the queue that have not been sent to the host side buffer, it is necessary to start the operation of batch reading descriptors again. First, the number n3 of descriptors to be read is determined according to the descriptor index, which can be understood as a read address, and the number n3 of descriptors, which can be understood as a length. Based on the descriptor index and the number n3 of descriptors, it can be determined that several cache lines of descriptors need to be batch read. Assuming that each descriptor is 16 bytes, each cache line is 64 bytes, and one cache line contains 4 descriptors, then m3 is an integer multiple of 4, and n3 is the number of descriptors that the DPU expects to batch read, which is related to the descriptor index. After obtaining the n3 descriptors, the DPU sends the remaining messages of the queue in the local cache to the buffer pointed to by at least one descriptor in the n3 descriptors. If the n3 descriptors currently read have all been used, and there are still messages of the queue that have not been sent to the host side buffer, the above steps are repeated until all messages of the queue are processed. If the n3 descriptors read still have a surplus after all messages of the queue are processed, the unused descriptors will be reserved in the DPU cache for later use, realizing the pre-fetching and standby of the descriptors.

[0037] In some embodiments, the step of determining the number n1, n2 or n3 of descriptors to be read according to the descriptor index comprises: n = cache_bd_num - 1 - (bd_index + req_num - 1) % cache_bd_num + req_num; Wherein, n is the number n1, n2 or n3 of descriptors to be read, % is the remainder operator, cache_bd_num is the number of descriptors in a cacheline, bd_index is the descriptor index, and req_num is the predicted number of descriptors needed, one message processing request needs one descriptor according to the prediction mode.

[0038] Specifically, in the prediction mode, one message receiving request corresponds to one descriptor, therefore, based on the message receiving request issued by the host side and received by the DPU, the corresponding req_num is predicted. The following is a calculation example: cache_bd_num = 4, bd_index = 2, req_num = 3, then: n=cache_bd_num-1-(bd_index+req_num-1)%cache_bd_num+req_num=4-1-(2+3-1)%4+3=4-1-0+3=6; That is to say, six descriptors actually need to be read, that is, n1, n2 or n3 = 6, but each cache line contains four descriptors. Therefore, when reading the descriptor ring table on the host side, descriptors of two cache lines need to be read, that is, the corresponding m1, m2 or m3 = 8.

[0039] In some embodiments, the step of obtaining n1 descriptors to be read according to the m1 descriptors includes: selecting n1 descriptors from the m1 descriptors as the n1 descriptors to be read according to the descriptor index; The step of obtaining n2 descriptors to be read according to the m2 descriptors includes: selecting n2 descriptors from the m2 descriptors as the n2 descriptors to be read according to the descriptor index; The step of obtaining n3 descriptors to be read according to the m3 descriptors includes: selecting n3 descriptors from the m3 descriptors according to the descriptor index as the n3 descriptors to be read.

[0040] Specifically, continuing with cache_bd_num = 4, bd_index = 2, and req_num = 3 as an example, n1, n2, or n3 = 6, and m1, m2, or m3 = 8. Each descriptor has a corresponding index, and the descriptors are read and used in index order. Therefore, assuming that the 8 descriptors read from the descriptor ring table are descriptors 0 to 7, and bd_index = 2 at this time, then with bd_index = 2 as the starting position, 6 descriptors such as descriptors 2 to 7 are selected from descriptors 0 to 7 as the n1, n2, or n3 descriptors that the DPU actually expects to read. Descriptors 0 to 1 are invalid descriptors and are discarded.

[0041] Another embodiment of the present application provides a data processing unit that can be used to execute the steps of the message sending method described in the above embodiment, such as Figure 5 As shown, the data processing unit of this embodiment includes: The message storage module 1 is used for caching the message in the data processing unit when receiving a message from any queue, and updating the number of cached messages in the queue; a descriptor query module 2, configured to obtain the number of descriptors cached by the queue in the data processing unit; an index obtaining module 3, configured to obtain a descriptor index; wherein the descriptor index points to a position of a next descriptor to be read in the descriptor ring table; a descriptor reading module 4, configured to, in a scenario where the number of descriptors is 0, determine a number n1 of descriptors to be read according to the descriptor index, read m1 descriptors from the descriptor ring table on the host side based on a cache line alignment manner, and obtain the n1 descriptors to be read according to the m1 descriptors; wherein m1 ≥ n1; a packet uploading module 5, configured to write packets of the queue into a host side cache unit pointed by the currently read descriptor, and update a number of cached packets of the queue and the descriptor index; and a descriptor storage module 6, configured to, if the number of cached packets of the queue after the update is 0 and the n1 descriptors are not all used, cache the unused descriptors in the data processing unit; The packet uploading module 5 is further configured to, in a scenario where the number of descriptors is greater than 0, write the packets of the queue into a host side cache unit pointed by the descriptor cached in the data processing unit. The descriptor reading module 4 is further configured to, if the packets of the queue fail to be completely written into the host side cache unit pointed by the descriptor cached in the data processing unit, determine a number n2 of descriptors to be read according to the descriptor index, read m2 descriptors from the descriptor ring table on the host side based on the cache line alignment manner, and obtain the n2 descriptors to be read according to the m2 descriptors; wherein m2 ≥ n2. The packet uploading module 5 is further configured to write the remaining packets of the queue into a host side cache unit pointed by at least one descriptor of the n2 descriptors, and update the number of cached packets of the queue and the descriptor index. The descriptor storage module 6 is further configured to, if the number of cached packets of the queue after the update is 0 and the n2 descriptors are not all used, cache the unused descriptors in the data processing unit.

[0042] In some embodiments, the descriptor reading module 4 is further configured to, in the scenario where the number of descriptors is 0, if the number of cached packets of the queue after the update is not 0 and the n1 descriptors are all used, determine a number n3 of descriptors to be read according to the updated descriptor index, read m3 descriptors from the descriptor ring table on the host side based on the cache line alignment manner, and obtain the n3 descriptors to be read according to the m3 descriptors; wherein m3 ≥ n3. The message reporting module 5 is further configured to write the messages of the queue into a host-side cache unit pointed by at least one of the n3 descriptors, and update the number of cached messages of the queue and the descriptor index.

[0043] In some embodiments, the descriptor reading module 4 comprises: a first descriptor number obtaining module configured to predict the number of descriptors needed, one message processing request needing one descriptor; a second descriptor number obtaining module configured to determine the number of descriptors n1, n2 or n3 to be read according to the descriptor index and the predicted number of descriptors needed; a descriptor reading module configured to read m1, m2 or m3 descriptors from the descriptor ring table on the host side according to the number of descriptors n1, n2 or n3 based on the cache line alignment mode; a descriptor processing module configured to obtain n1, n2 or n3 descriptors according to the m1, m2 or m3 descriptors.

[0044] In some embodiments, the data processing unit comprises: a message storage RAM configured to store the messages of any queue; a message number RAM configured to store the number of cached messages of any queue; a descriptor storage RAM configured to store the unused descriptors; a descriptor read-write pointer RAM configured to store a read pointer and a write pointer, the read pointer pointing to the position of the descriptor currently read from the descriptor storage RAM, and the write pointer pointing to the position of the descriptor currently written into the descriptor storage RAM; a descriptor FIFO module configured to store the n1, n2 or n3 descriptors read; a descriptor index storage RAM configured to store the descriptor index; wherein the value of the descriptor index is incremented by one each time a descriptor is read from the descriptor FIFO module.

[0045] Referring to Figure 6 , the following will describe in detail how the DPU reports messages by taking a queue (Virtqueue) as an example: Step 1: the Device receives an Ethernet message from a network port; Step 2: save the message into the message storage RAM of the Device according to the queue; Step 3, whenever a packet of a queue is stored in the "packet storage RAM", the value of the queue in the "packet number RAM" (i.e. the number of buffered packets of the queue) is read out and added by 1 to be written back to the "packet number RAM", whenever a packet of a queue is read out from the "packet storage RAM", the value of the queue in the "packet number RAM" (i.e. the number of buffered packets of the queue) is read out and subtracted by 1 to be written back to the "packet number RAM"; Step 4, query the "descriptor read-write pointer RAM", determine the number of descriptors in the "descriptor storage RAM" through the read-write pointer, if the number of descriptors in the "descriptor storage RAM" is 0, go to step 5 to initiate reading of the "descriptor index storage RAM", otherwise go to step 8 to directly read the descriptors in the "descriptor storage RAM"; Step 5, query the descriptor index maintained by the DPU in the "descriptor index storage RAM"; Step 6, calculate the number of descriptors to be read through the read descriptor index; Step 7, initiate reading of the descriptors to the host driver; Step 8, when there are packets in the "packet storage RAM" and there are descriptors in the "descriptor storage RAM", read the descriptors in the "descriptor storage RAM", and add 1 to the read pointer of the "descriptor read-write pointer RAM" for each descriptor read from the "descriptor storage RAM" to indicate which position is read; Step 9, the host driver returns the descriptors and stores the descriptors in the "descriptor storage FIFO module" of the DPU; Step 10, when the "descriptor storage FIFO module" is not empty, read the descriptors in the "descriptor storage FIFO module", and go to step 11, 14 or 15 according to different situations; Step 11, a part of the descriptors read from the "descriptor storage FIFO module" will be directly used to send packets, since the reading of the descriptors to the host driver is initiated only when the "descriptor storage RAM" is empty, so step 8 and step 11 will not exist at the same time for the same queue; Step 12, read the packets in the "packet storage RAM", send the packets to the host side cache unit pointed by the descriptor, and then update the used descriptor to the descriptor ring table of the host driver; Step 13, whenever a packet is read out from the "packet storage RAM", subtract 1 from the value (the number of buffered packets of the queue) in the "packet number RAM"; Step 14, every time a descriptor is read from the "descriptor storage FIFO module", a read of the "descriptor index storage RAM" is triggered, the read descriptor index is incremented by 1 and written back to the "descriptor index storage RAM" to update the descriptor index; Step 15, if the packet in the "packet storage RAM" has been read out, but there are still descriptors in the "descriptor storage FIFO module", these remaining descriptors are stored in the "descriptor storage RAM", every time a descriptor is stored in the "descriptor storage RAM", the write pointer of the "descriptor read-write pointer RAM" is incremented by 1 to indicate where to write.

[0046] Another embodiment of the present application provides a data processing unit (DPU), comprising: a communication interface, configured to communicate with other electronic devices; a memory, configured to store computer program instructions; a processor, configured to execute the computer program instructions to support the data processing unit to implement the method as described in the above embodiments.

[0047] In the embodiment, the memory mainly includes a program storage area and a data storage area, wherein the program storage area can store application programs required by at least one function of the operation device, and the data storage area can store related data. In addition, the memory can be a high-speed random access memory, and can also be a non-volatile memory such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card, or the like. Alternatively, the memory can also be other volatile solid-state storage devices.

[0048] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, or the like. The general-purpose processor can be a microprocessor, or the processor can also be any conventional processor. The processor is the control center of the data processing unit, and connects various parts of the data processing unit through various interfaces and lines.

[0049] Another embodiment of the present application provides a computer program product comprising computer program instructions instructing a computer device to perform operations corresponding to the packet uploading method as described in the above embodiments.

[0050] In particular, the computer program product comprises a series of computer program instructions, which are codes written in a computer program and define how to perform specific operations. The computer program instructions are designed to be loaded onto a computer device and guide the device to perform specific operations, which are steps in the packet uploading method as described in the above embodiments. In this way, the computer program product of the present embodiment provides a complete software solution, which can be run on various computer devices to implement the packet uploading method of the above embodiments.

[0051] The above has described the embodiments of the present application, and the above description is exemplary, not exhaustive, and is not limited to the disclosed embodiments. Many updates and changes are obvious to those skilled in the art without departing from the scope and spirit of the described embodiments. The selection of the terms used herein is intended to best explain the principles, practical applications, or technical improvements in the market of the embodiments, or to enable other ordinary skilled persons in the art to understand the embodiments disclosed herein.

Claims

1. A message sending method applied to a data processing unit, characterized in that, The method comprises: when receiving a packet of any queue, buffering the packet in the data processing unit, and updating the number of buffered packets of the queue; obtaining the number of descriptors and the descriptor index of the queue buffered in the data processing unit; wherein the descriptor index points to the position of the next descriptor to be read in the descriptor ring table; in the scenario where the number of descriptors is 0, determining the number n1 of descriptors to be read according to the descriptor index, reading m1 descriptors from the descriptor ring table on the host side based on the cache line alignment mode, obtaining the n1 descriptors to be read according to the m1 descriptors, writing the packets of the queue into the host side cache unit pointed to by at least one of the n1 descriptors, and updating the number of buffered packets of the queue and the descriptor index; if the updated number of buffered packets of the queue is 0 and the n1 descriptors are not all used, buffering the unused descriptors in the data processing unit; wherein m1≥n1; in the scenario where the number of descriptors is greater than 0, writing the packets of the queue into the host side cache unit pointed to by the descriptors buffered in the data processing unit, if the packets of the queue cannot be all written into the host side cache unit pointed to by the descriptors buffered in the data processing unit, determining the number n2 of descriptors to be read according to the descriptor index, reading m2 descriptors from the descriptor ring table on the host side based on the cache line alignment mode, obtaining the n2 descriptors to be read according to the m2 descriptors, writing the remaining packets of the queue into the host side cache unit pointed to by at least one of the n2 descriptors, and updating the number of buffered packets of the queue and the descriptor index; if the updated number of buffered packets of the queue is 0 and the n2 descriptors are not all used, buffering the unused descriptors in the data processing unit; wherein m2≥n2.

2. The method of claim 1, wherein, The method comprises: in the scenario where the number of descriptors is 0, if the updated number of buffered packets of the queue is not 0 and the n1 descriptors are all used, determining the number n3 of descriptors to be read according to the updated descriptor index, reading m3 descriptors from the descriptor ring table on the host side based on the cache line alignment mode, obtaining the n3 descriptors to be read according to the m3 descriptors, writing the remaining packets of the queue into the host side cache unit pointed to by at least one of the n3 descriptors, and updating the number of buffered packets of the queue and the descriptor index; wherein m3≥n3.

3. The method of claim 2, wherein, The step of determining the number n1, n2 or n3 of descriptors to be read according to the descriptor index comprises: n=cache_bd_num-1-(bd_index+req_num-1)%cache_bd_num+req_num; Wherein, n is the number of descriptors to be read n1, n2 or n3, % is the remainder operator symbol, cache_bd_num is the number of descriptors in a cacheline, bd_index is the descriptor index, req_num is the number of predicted required descriptors, a packet processing request requires a descriptor in a predicted manner.

4. The method of claim 2, wherein, the step of obtaining n1 descriptors to be read from the m1 descriptors comprises selecting n1 descriptors from the m1 descriptors as the n1 descriptors to be read according to the descriptor index; the step of obtaining n2 descriptors to be read from the m2 descriptors comprises selecting n2 descriptors from the m2 descriptors as the n2 descriptors to be read according to the descriptor index; the step of obtaining n3 descriptors to be read from the m3 descriptors comprises selecting n3 descriptors from the m3 descriptors as the n3 descriptors to be read according to the descriptor index.

5. A data processing unit, characterized by comprises: a packet storage module, configured to cache a packet of any queue in the data processing unit when the packet is received, and update the number of cached packets of the queue; a descriptor query module, configured to obtain the number of descriptors cached in the data processing unit by the queue; an index obtaining module, configured to obtain a descriptor index; wherein the descriptor index points to the position of the next descriptor to be read in the descriptor ring table; a descriptor reading module, configured to, in a scenario where the number of descriptors is 0, determine the number of descriptors to be read n1 according to the descriptor index, read m1 descriptors from the descriptor ring table on the host side based on the cache line alignment mode, and obtain n1 descriptors to be read from the m1 descriptors; wherein m1 ≥ n1; a packet reporting module, configured to write the packet of the queue into the host side cache unit pointed to by the currently read descriptor, and update the number of cached packets of the queue and the descriptor index; and a descriptor storage module, configured to, if the updated number of cached packets of the queue is 0 and the n1 descriptors are not all used, cache the unused descriptors in the data processing unit; the packet reporting module is further configured to, in a scenario where the number of descriptors is greater than 0, write the packet of the queue into the host side cache unit pointed to by the descriptor cached in the data processing unit; the descriptor reading module is further configured to, if the packet of the queue fails to be completely written into the host side cache unit pointed to by the descriptor cached in the data processing unit, determine the number of descriptors to be read n2 according to the descriptor index, read m2 descriptors from the descriptor ring table on the host side based on the cache line alignment mode, and obtain n2 descriptors to be read from the m2 descriptors; wherein m2 ≥ n2; The message reporting module is further configured to write the remaining messages of the queue into a host-side cache unit pointed to by at least one of the n2 descriptors, and update the number of cached messages of the queue and the descriptor index; The descriptor storage module is further configured to cache unused descriptors in the data processing unit if the number of cached messages in the queue after update is 0 and the n2 descriptors are not all used.

6. The data processing unit according to claim 5, characterized in that, The descriptor reading module is further configured to, in a scenario where the number of descriptors is 0, if the number of cached messages in the updated queue is not 0 and all of the n1 descriptors have been used, determine the number n3 of descriptors to be read according to the updated descriptor index, and read m3 descriptors from the descriptor ring table on the host side based on a cache line alignment method, and obtain n3 descriptors to be read according to the m3 descriptors; wherein m3 ≥ n3; The message reporting module is further configured to write the message of the queue into a host-side cache unit pointed to by at least one of the n3 descriptors, and update the number of cached messages of the queue and the descriptor index.

7. The data processing unit according to claim 6, characterized in that, The descriptor reading module includes: A first descriptor number acquisition module is used to predict the number of descriptors required, where one message requires one descriptor to process the request according to the predicted method; A second descriptor number acquisition module is used to determine the number of descriptors to be read, n1, n2 or n3, according to the descriptor index and the predicted number of descriptors required; A descriptor reading module is used to read corresponding m1, m2 or m3 descriptors from the descriptor ring table on the host side based on the cache line alignment mode according to the number of descriptors n1, n2 or n3; The descriptor processing module is used to obtain corresponding n1, n2 or n3 descriptors according to the m1, m2 or m3 descriptors.

8. The data processing unit according to any one of claims 5 to 7, characterized in that, The data processing unit includes: A message storage RAM, used for storing messages in any queue; Message number RAM, used to store the number of cached messages in any queue; A descriptor storage RAM, used for storing the unused descriptors; A descriptor read / write pointer RAM, used to store a read pointer and a write pointer, wherein the read pointer points to the position of the descriptor currently read from the descriptor storage RAM, and the write pointer points to the position of the descriptor currently written to the descriptor storage RAM; Descriptor FIFO module, used to store n1, n2 or n3 descriptors read; The descriptor index storage RAM is used to store the descriptor index; wherein, whenever a descriptor is read from the descriptor FIFO module, the value of the descriptor index is increased by one.

9. A data processing unit, characterized by include: Communication interface, used for communicating with other electronic devices; a memory for storing computer program instructions; A processor, configured to execute the computer program instructions to support the data processing unit in implementing the method according to any one of claims 1 to 4.

10. A computer program product, characterised in that, The method comprises computer program instructions, wherein the computer program instructions instruct a computer device to perform operations corresponding to the method according to any one of claims 1 to 4.

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