A message uploading method, a data processing unit and a computer program product

Abstract

The application relates to a message uploading method, a data processing unit and a computer program product, which comprises the following steps: after receiving a queue message, first buffering and updating a count, when the queue has no buffered descriptor, determining the number n1 of descriptors to be read according to a descriptor index, reading m1 (m1 >= n1) descriptors from a host side according to a cache line alignment, writing the message into a host cache by using the n1 descriptors, updating the count and the index; if the message is processed and there are remaining descriptors, then buffering unused descriptors; when the queue has buffered descriptors, preferentially writing the message by using the descriptors, if the message is not written completely, then determining the number n2 of descriptors to be read according to the descriptor index, reading m2 (m2 >= n2) descriptors from the host side according to the cache line alignment to process the remaining message, and if the message is processed and there are remaining descriptors after the updating, then buffering unused descriptors. Through the application, the reading delay problem of the descriptors can be solved, and the overall message processing efficiency is improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of VIRTIO, and particularly relates to a message uploading method, a data processing unit and a computer program product. BACKGROUND

[0002] VIRTIO is a general-purpose semi-virtualization I / O framework, which realizes data interaction between a host and a guest. VIRTIO is composed of a front-end driver, a back-end device and a virtualization queue (Virtqueue). In order to improve the performance of VIRTIO, a hardware offloading technology of a VIRTIO data plane appears, that is, the back-end device is implemented by hardware.

[0003] Data interaction between the front-end driver and the back-end device is realized through the virtualization queue. According to the VIRTIO protocol, a commonly used virtualization queue is a Split Virtqueue, and one Split Virtqueue is composed of a descriptor table, an available ring table and a used ring table. In order to solve the performance problem of the Split Virtqueue, a Packed Virtqueue is proposed in the 1.1 version of the VIRTIO protocol. The Packed Virtqueue is equivalent to merging the three ring tables of the Split Virtqueue into one descriptor ring table (Descriptor Ring), and each descriptor of the descriptor ring table contains a buffer address, a buffer length, a buffer id and a flag of a buffer attribute.

[0004] Taking the Packed Virtqueue as an example, a typical VIRITO network device data receiving process is as shown in Figure 1 The VIRTIO driver needs to prepare a buffer before the VIRTIO network device works, and the steps are as follows:

[0005] Step 11, the VIRTIO driver prepares a buffer for storing an Ethernet message, and stores the buffer address, the buffer length, the buffer id, the flag of the buffer attribute and other information of the buffer in the descriptor of the descriptor ring table, and updates the index value buffer id of each descriptor.

[0006] Step 12, a notification is issued to the VIRTIO network device that the cache unit is ready.

[0007] When the VIRTIO driver prepares the cache unit, the VIRTIO network device starts working and receives message data, and the VIRTIO network device receives data processing flow as follows:

[0008] Step 21, receiving Ethernet message data and storing the message data in the local cache of the Device;

[0009] Step 22, initiating a descriptor read operation to the VIRTIO driver to read the descriptor of the descriptor ring table, to obtain the cache unit address, cache unit length, cache unit index, cache attribute flag and other information in the descriptor;

[0010] Step 23, reading out the Ethernet message data from the local cache of the VIRTIO network device and sending it to the VIRTIO driver and storing it in the cache unit pointed by the cache unit address;

[0011] Step 24, updating the used descriptor, i.e. updating the descriptor information of the descriptor ring table, and reporting an interrupt to the VIRTIO driver, so that the VIRTIO driver obtains the Ethernet message data stored in the cache unit through reading the cache unit address and cache unit index, and recycles the descriptor of the descriptor ring table for continuous use.

[0012] In the above scheme, the descriptor ring table of the VIRTIO driver is stored in the cache of the host side, and the CPU reads or writes the cache according to a cache line. For example, assuming that the size of a cache line is 64 bytes and the size of a descriptor of VIRTIO Packed is 16 bytes, that is, one cache line can store four descriptors, as shown in Figure 2 Normally, the descriptor Descriptor0 of the descriptor ring table is the first 16 bytes of the cache line. The VIRTIO network device initiates the read quantity of the descriptor based on the actual required quantity, for example, the VIRTIO network device receives an Ethernet message and then reads one descriptor Descriptor0 to the VIRTIO driver, as shown in Figure 2The Device sends the packet to the buffer pointed by Descriptor0, and then updates Descriptor0 in the descriptor ring table of the VIRTIO driver. At this time, the VIRTIO driver needs to read the entire cache line (including Descriptor0, Descriptor1, Descriptor2, and Descriptor3) first, mark Descriptor0 as used, update the buffer length and buffer id of Descriptor0, and then write the entire cache line back to the descriptor ring table. If the VIRTIO network device initiates reading of Descriptor1 immediately after initiating updating of Descriptor0, Descriptor1 cannot be read until the updating of Descriptor0 is completed, because the updating of Descriptor0 needs the read-before-write operation of the cache line, which increases the reading delay of Descriptor1 and reduces the packet processing efficiency. SUMMARY

[0013] The present application aims to provide a packet uploading method, a data processing unit, and a computer program product to solve the reading delay of descriptors and improve the packet processing efficiency.

[0014] To achieve the above-mentioned purpose, according to a first aspect of the present application, a packet uploading method is provided, which comprises:

[0015] When receiving a packet of any queue, the packet is cached in the data processing unit, and the number of cached packets of the queue is updated;

[0016] The number of descriptors and the descriptor index of the queue cached in the data processing unit are obtained; wherein the descriptor index points to the position of the next descriptor to be read in the descriptor ring table;

[0017] In the case where the number of descriptors is 0, the number n1 of descriptors to be read is determined according to the descriptor index, m1 descriptors are read from the descriptor ring table on the host side based on the cache line alignment mode, n1 descriptors to be read are obtained according to the m1 descriptors, the packet of the queue is written into at least one descriptor pointed by the n1 descriptors on the host side, and the number of cached packets of the queue and the descriptor index are updated; if the number of cached packets of the queue after updating is 0 and the n1 descriptors are not all used, the unused descriptors are cached in the data processing unit; wherein m1≥n1;

[0018] In the scenario where the number of the descriptors is greater than 0, the packets of the queue are written into the host-side cache unit pointed by the descriptors of the data processing unit, if the packets of the queue fail to be completely written into the host-side cache unit pointed by the descriptors of the data processing unit, the number n2 of the descriptors to be read is determined according to the descriptor index, m2 descriptors are read from the descriptor ring table of the host side based on the cache line alignment mode, and n2 descriptors to be read are obtained according to the m2 descriptors, the remaining packets of the queue are written into the host-side cache unit pointed by at least one descriptor of the n2 descriptors, and the number of the cached packets of the queue and the descriptor index are updated; if the number of the cached packets of the queue after the update is 0 and the n2 descriptors are not all used, the unused descriptors are cached in the data processing unit; wherein m2≥n2.

[0019] Preferably, the method comprises:

[0020] In the scenario where the number of the descriptors is 0, if the number of the cached packets of the queue after the update is not 0 and the n1 descriptors are all used, the number n3 of the descriptors to be read is determined according to the updated descriptor index, m3 descriptors are read from the descriptor ring table of the host side based on the cache line alignment mode, n3 descriptors to be read are obtained according to the m3 descriptors, the remaining packets of the queue are written into the host-side cache unit pointed by at least one descriptor of the n3 descriptors, and the number of the cached packets of the queue and the descriptor index are updated; wherein m3≥n3.

[0021] Preferably, the step of determining the number n1, n2 or n3 of the descriptors to be read according to the descriptor index comprises:

[0022] n = cache_bd_num - 1 - (bd_index + req_num - 1) % cache_bd_num + req_num;

[0023] Wherein n is the number n1, n2 or n3 of the descriptors to be read, % is a remainder operator, cache_bd_num is the number of the descriptors in a cacheline, bd_index is the descriptor index, and req_num is the predicted number of the descriptors required, one packet processing request requires one descriptor.

[0024] Preferably, the step of obtaining n1 descriptors to be read according to the m1 descriptors comprises: selecting n1 descriptors from the m1 descriptors as the n1 descriptors to be read according to the descriptor index;

[0025] The step of obtaining n2 descriptors to be read according to the m2 descriptors comprises: selecting n2 descriptors from the m2 descriptors as the n2 descriptors to be read according to the descriptor index.

[0026] The step of obtaining n3 descriptors to be read according to the m3 descriptors comprises: selecting n3 descriptors from the m3 descriptors as the n3 descriptors to be read according to the descriptor index.

[0027] According to a second aspect of the present application, a data processing unit is provided, comprising:

[0028] A packet storage module is configured to buffer a packet of any queue in the data processing unit and update the number of buffered packets of the queue when the packet is received;

[0029] A descriptor query module is configured to obtain the number of descriptors of the queue buffered in the data processing unit;

[0030] An index obtaining module is configured to obtain a descriptor index, wherein the descriptor index points to the position of the next descriptor to be read in the descriptor ring table;

[0031] A descriptor reading module is configured to determine the number n1 of descriptors to be read according to the descriptor index in the case that the number of descriptors is 0, read m1 descriptors from the descriptor ring table on the host side based on the cache line alignment mode, and obtain n1 descriptors to be read according to the m1 descriptors, wherein m1≥n1;

[0032] A packet uploading module is configured to write the packet of the queue into the host side cache unit pointed by the currently read descriptor, and update the number of buffered packets of the queue and the descriptor index; and

[0033] A descriptor storage module is configured to buffer the unused descriptors in the data processing unit if the updated number of buffered packets of the queue is 0 and the n1 descriptors are not all used.

[0034] The packet uploading module is further configured to write the packet of the queue into the host side cache unit pointed by the descriptor buffered in the data processing unit in the case that the number of descriptors is greater than 0.

[0035] The descriptor reading module is further configured to, if the packets of the queue fail to be completely written into the host-side cache unit pointed to by the descriptor of the data processing unit, determine the number n2 of descriptors to be read according to the descriptor index, read m2 descriptors from the descriptor ring table on the host side based on the cache line alignment mode, and obtain the n2 descriptors to be read according to the m2 descriptors; wherein m2≥n2.

[0036] The packet reporting module is further configured to write the remaining packets of the queue into the host-side cache unit pointed to by at least one of the n2 descriptors, and update the number of cached packets of the queue and the descriptor index.

[0037] The descriptor storage module is further configured to, if the updated number of cached packets of the queue is 0 and the n2 descriptors are not all used, cache the unused descriptors in the data processing unit.

[0038] Preferably, the descriptor reading module is further configured to, in the scenario where the number of descriptors is 0, if the updated number of cached packets of the queue is not 0 and the n1 descriptors are all used, determine the number n3 of descriptors to be read according to the updated descriptor index, read m3 descriptors from the descriptor ring table on the host side based on the cache line alignment mode, and obtain the n3 descriptors to be read according to the m3 descriptors; wherein m3≥n3.

[0039] The packet reporting module is further configured to write the packets of the queue into the host-side cache unit pointed to by at least one of the n3 descriptors, and update the number of cached packets of the queue and the descriptor index.

[0040] Preferably, the descriptor reading module comprises:

[0041] The first descriptor number obtaining module is configured to predict the number of descriptors needed, one packet processing request needing one descriptor.

[0042] The second descriptor number obtaining module is configured to determine the number n1, n2 or n3 of descriptors to be read according to the descriptor index and the predicted number of descriptors needed.

[0043] The descriptor reading module is configured to read the corresponding m1, m2 or m3 descriptors from the descriptor ring table on the host side based on the cache line alignment mode according to the number n1, n2 or n3 of descriptors.

[0044] The descriptor processing module is configured to obtain the corresponding n1, n2 or n3 descriptors according to the m1, m2 or m3 descriptors.

[0045] Preferably, the data processing unit comprises:

[0046] a packet storage RAM for storing packets of any queue;

[0047] a packet number RAM for storing the number of buffered packets of any queue;

[0048] a descriptor storage RAM for storing the unused descriptors;

[0049] a descriptor read-write pointer RAM for storing a read pointer and a write pointer, the read pointer pointing to the location of the current read-out descriptor from the descriptor storage RAM, and the write pointer pointing to the location of the current write-in descriptor into the descriptor storage RAM;

[0050] a descriptor FIFO module for storing n1, n2 or n3 read descriptors;

[0051] a descriptor index storage RAM for storing the descriptor index; wherein the value of the descriptor index is incremented by one whenever a descriptor is read from the descriptor FIFO module.

[0052] According to a third aspect of the present application, a data processing unit is provided, comprising:

[0053] a communication interface for communicating with other electronic devices;

[0054] a memory for storing computer program instructions;

[0055] a processor for executing the computer program instructions to support the data processing unit to implement the method according to the first aspect of the present application.

[0056] According to a fourth aspect of the present application, a computer program product is provided, comprising computer program instructions instructing a computer device to perform corresponding operations according to the first aspect of the present application.

[0057] The present application provides a packet uploading method, a data processing unit and a computer program product, which have the following beneficial effects:

[0058] The data processing unit reads multiple descriptors from the descriptor ring table on the host side in batches through "cache line alignment" each time the descriptor is read, and the read multiple descriptors are used for message uploading. When the message uploading is completed and there is an unused descriptor, the unused descriptor is temporarily stored in the data processing unit, so as to quickly provide a ready descriptor for message writing operation. Specifically, when the host side is processing the last message, the data processing unit can simultaneously take out the next descriptor from the local cache for message uploading, thereby eliminating the idle waiting time caused by waiting to read the descriptor, greatly improving the descriptor reading efficiency, fundamentally solving the descriptor reading delay problem caused by the cache line characteristics in the Packed Virtqueue mode of the traditional VIRTIO, and improving the message processing efficiency.

[0059] Other features and advantages of the present application will be illustrated in the following description. BRIEF DESCRIPTION OF DRAWINGS

[0060] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the following will briefly introduce the drawings needed in the embodiment or prior art description. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other drawings according to these drawings without creative labor.

[0061] Figure 1 The VIRITO network device message receiving principle disclosed in the background art.

[0062] Figure 2 The descriptor reading principle disclosed in the background art.

[0063] Figure 3 The flowchart of a message uploading method in an embodiment of the present application.

[0064] Figure 4 The descriptor reading principle in an embodiment of the present application.

[0065] Figure 5 The software module example diagram of a data processing unit in an embodiment of the present application.

[0066] Figure 6 The hardware circuit schematic diagram of a data processing unit in an embodiment of the present application. DETAILED DESCRIPTION

[0067] The detailed description of the drawings is intended as an illustration of the current preferred embodiments of the application, and is not intended to represent the only forms in which the application can be practiced. It should be understood that the same or equivalent functions can be accomplished by different embodiments that are intended to be within the scope of the application.

[0068] One embodiment of the present application provides a packet uploading method applied to a data processing unit (i.e. hardware implementing a VIRTIO network device), which introduces a prefetch mechanism on the data processing unit side to prepare descriptors in advance, thereby eliminating descriptor reading waiting time, avoiding conflicts with host side operations of updating the descriptor ring table, and the like. Figure 3 The method of the embodiment includes the following steps:

[0069] Step S10, when receiving a packet of any queue, buffering the packet in the data processing unit and updating the number of buffered packets of the queue;

[0070] Specifically, a data processing unit (DPU) and a host (Host) perform data communication through multiple queues (Virtqueue). When the DPU receives a packet of any queue, the DPU stores the received packet in the DPU buffer according to the queue, waits for uploading to the Host, and maintains the number of buffered packets of each queue. The number of buffered packets of each queue is updated in real time according to the packets currently buffered in the DPU.

[0071] Step S20, obtaining the number of descriptors and a descriptor index of the descriptors buffered in the data processing unit, wherein the descriptor index points to the position of the next descriptor to be read in the descriptor ring table;

[0072] Specifically, before processing the packets buffered in the DPU, the DPU first checks whether the DPU has prefetched and buffered available descriptors internally. This is a key decision point of the method of the embodiment, which determines which processing path the DPU should adopt next: whether the DPU needs to read descriptors from the host side descriptor ring table or whether the DPU can directly use the buffered descriptors. In addition, the DPU locally maintains a descriptor index, which points to the position of the next descriptor to be read in the descriptor ring table.

[0073] Step S30, in the case where the number of descriptors is 0, determining the number n1 of descriptors to be read according to the descriptor index, reading m1 descriptors from the descriptor ring table on the host side based on cache line alignment, obtaining n1 descriptors to be read according to the m1 descriptors, writing the packets of the queue to the host side buffer unit pointed to by at least one of the n1 descriptors, and updating the number of cached packets of the queue and the descriptor index; if the updated number of cached packets of the queue is 0 and the n1 descriptors are not all used, caching the unused descriptors in the data processing unit; wherein m1≥n1.

[0074] Specifically, if it is found in step S20 that there are no descriptors of the queue pre-fetched locally in the DPU (i.e. the number is 0), the DPU will start a one-time batch reading operation of the descriptors. First, the number n1 of descriptors to be read is determined according to the descriptor index, which can be understood as a read address, and the number n1 of descriptors, which can be understood as the number of available descriptors in the m1 descriptors read, i.e. the number of effective descriptors. Based on the descriptor index and the number n1 of descriptors, it can be determined how many cache lines of descriptors need to be batch read. Assuming that each descriptor is 16 bytes and each cache line is 64 bytes, one cache line contains 4 descriptors, then m1 is an integer multiple of 4, and n1 is the number of descriptors that the DPU expects to batch read, which is related to the descriptor index. The descriptors are read in a cache line alignment manner as shown in Figure 4 .

[0075] After obtaining the n1 descriptors, the DPU will send the locally cached packets one by one to the host side buffer unit (buffer) pointed to by at least one of the n1 descriptors. If there are remaining n1 descriptors after all the packets of the queue are processed, the unused descriptors will be reserved in the DPU cache for later use, realizing pre-fetching and standby of the descriptors.

[0076] In the case where the number of descriptors is greater than 0, the packets of the queue are written into the host-side cache unit pointed to by the descriptors of the data processing unit, and if the packets of the queue cannot be completely written into the host-side cache unit pointed to by the descriptors of the data processing unit, the number n2 of descriptors to be read is determined according to the descriptor index, m2 descriptors are read from the descriptor ring table of the host side based on the cache line alignment mode, and n2 descriptors to be read are obtained according to the m2 descriptors, the remaining packets of the queue are written into the host-side cache unit pointed to by at least one of the n2 descriptors, and the number of cached packets of the queue and the descriptor index are updated; if the number of cached packets of the queue after the update is 0 and the n2 descriptors are not all used, the unused descriptors are cached in the data processing unit; wherein m2≥n2.

[0077] Specifically, when the number of descriptors is greater than 0, it indicates that there are still unused descriptors remaining after the last execution of the write operation of the packets of the queue, and then the descriptors cached in the DPU can be directly used to improve the packet processing efficiency; if the storage space of the buffer pointed to by the descriptors cached in the DPU is insufficient to store all the packets of the queue, after the descriptors cached in the DPU are used up, a one-time batch reading operation of descriptors is started; first, the number n2 of descriptors to be read is determined according to the descriptor index, which can be understood as a read address, and the number n2 of descriptors, which can be understood as a length, based on the descriptor index and the number n2 of descriptors, it can be determined that several cache line descriptors need to be batch read, assuming that each descriptor is 16 bytes and each cache line is 64 bytes, and a cache line contains 4 descriptors, then m2 is an integer multiple of 4, and n2 is the number of descriptors expected to be batch read by the DPU, which is related to the descriptor index; after obtaining n2 descriptors, the DPU uploads the remaining packets of the queue in the local cache one by one to the buffer pointed to by at least one of the n2 descriptors, if the n2 descriptors read still have remaining after all the packets of the queue are processed, the unused descriptors will be reserved in the DPU cache for later use, realizing the pre-fetching and standby of the descriptors.

[0078] Based on the description of the above embodiments, it can be known that in the method of the embodiment, the DPU reads multiple descriptors from the descriptor ring table on the host side in batches through the "cache line alignment mode" each time the descriptor is read, and the multiple descriptors read are used for packet uploading. When the packet uploading is completed and there is an unused descriptor, the unused descriptor is temporarily stored in the DPU, so as to quickly provide a ready descriptor for packet write operation. Specifically, when the host side is processing the last packet, the DPU can simultaneously take out the next descriptor from the local cache for packet uploading, thereby eliminating the idle waiting time caused by waiting to read the descriptor, greatly improving the descriptor reading efficiency, fundamentally solving the descriptor reading delay problem caused by the cache line feature in the PackedVirtqueue mode of the traditional VIRTIO, and improving the packet processing efficiency.

[0079] In some embodiments, the method comprises:

[0080] In the scenario where the number of the descriptors is 0, if the number of the cached packets of the queue after the update is not 0 and the n1 descriptors have all been used, the number n3 of descriptors to be read is determined according to the updated descriptor index, m3 descriptors are read from the descriptor ring table on the host side based on the cache line alignment mode, the n3 descriptors to be read are obtained according to the m3 descriptors, the remaining packets of the queue are written into the host side cache unit pointed to by at least one of the n3 descriptors, and the number of the cached packets of the queue and the descriptor index are updated; wherein m3≥n3.

[0081] Specifically, in the scenario where the number of the descriptors is 0, if the n1 descriptors currently read are all used, and there are still messages of the queue that are not sent to the host side buffer, it is necessary to start the operation of batch reading descriptors again. First, the number n3 of descriptors to be read is determined according to the descriptor index, which can be understood as a read address, and the number n3 of descriptors, which can be understood as a length. Based on the descriptor index and the number n3 of descriptors, it can be determined that several cache lines of descriptors need to be batch read. Assuming that each descriptor is 16 bytes, each cache line is 64 bytes, and one cache line contains 4 descriptors, then m3 is an integer multiple of 4, and n3 is the number of descriptors that the DPU expects to batch read, which is related to the descriptor index. After obtaining the n3 descriptors, the DPU sends the remaining messages of the queue in the local cache to the buffer pointed to by at least one of the n3 descriptors. If the n3 descriptors currently read are all used, and there are still messages of the queue that are not sent to the host side buffer, the above steps are repeated until all messages of the queue are processed. If the n3 descriptors read are still remaining after all messages of the queue are processed, the unused descriptors will be reserved in the DPU cache for later use, realizing the pre-fetching and standby of the descriptors.

[0082] In some embodiments, the step of determining the number n1, n2 or n3 of descriptors to be read according to the descriptor index comprises:

[0083] n = cache_bd_num - 1 - (bd_index + req_num - 1) % cache_bd_num + req_num;

[0084] Wherein, n is the number n1, n2 or n3 of descriptors to be read, % is the remainder operator, cache_bd_num is the number of descriptors in a cacheline, bd_index is the descriptor index, and req_num is the predicted number of descriptors needed, one message processing request needs one descriptor according to the prediction mode.

[0085] Specifically, in the prediction mode, one message receiving request corresponds to one descriptor, therefore, based on the message receiving request issued by the host side and received by the DPU, the corresponding req_num is predicted.

[0086] The following is a calculation example:

[0087] cache_bd_num = 4, bd_index = 2, req_num = 3, then:

[0088] n = cache bd num - 1 - (bd index + req num - 1) % cache bd num + req num = 4 - 1 - (2 + 3 - 1) % 4 + 3 = 4 - 1 - 0 + 3 = 6;

[0089] That is, actually required to read is 6 descriptors, namely n1, n2 or n3 = 6, but each cache line contains 4 descriptors, therefore, when reading the descriptor ring table on the host side, 2 cache lines of descriptors need to be read, namely corresponding m1, m2 or m3 = 8.

[0090] In some embodiments, the step of obtaining n1 descriptors to be read according to the m1 descriptors comprises: selecting n1 descriptors from the m1 descriptors as n1 descriptors to be read according to the descriptor index;

[0091] The step of obtaining n2 descriptors to be read according to the m2 descriptors comprises: selecting n2 descriptors from the m2 descriptors as n2 descriptors to be read according to the descriptor index;

[0092] The step of obtaining n3 descriptors to be read according to the m3 descriptors comprises: selecting n3 descriptors from the m3 descriptors as n3 descriptors to be read according to the descriptor index.

[0093] Specifically, continuing to take cache bd num = 4, bd index = 2, req num = 3 as an example, n1, n2 or n3 = 6, m1, m2 or m3 = 8, each descriptor has a corresponding index, and the descriptors are read and used in index order, therefore, assuming that the 8 descriptors read from the descriptor ring table are descriptors 0~7, at this time bd index = 2, then taking bd index = 2 as the starting position, descriptors 2~7 are selected from descriptors 0~7 as n1, n2 or n3 descriptors actually expected to be read by the DPU, and descriptors 0~1 are invalid descriptors, which are discarded.

[0094] Another embodiment of the present application provides a data processing unit, which can be used to execute the steps of the packet uploading method described in the above embodiments, as shown in the figure, the data processing unit of the embodiment comprises: Figure 5

[0095] A packet storage module 1, configured to buffer a packet of any queue in the data processing unit when the packet is received, and update the number of buffered packets of the queue;

[0096] ​a descriptor query module 2, configured to obtain a number of descriptors of the queue cached at the data processing unit;

[0097] an index obtaining module 3, configured to obtain a descriptor index, wherein the descriptor index points to a position of a next descriptor to be read in the descriptor ring table;

[0098] a descriptor reading module 4, configured to, in a scenario where the number of descriptors is 0, determine a number n1 of descriptors to be read according to the descriptor index, read m1 descriptors from the descriptor ring table on the host side based on a cache line alignment manner, and obtain the n1 descriptors to be read according to the m1 descriptors; wherein m1 ≥ n1;

[0099] a packet uploading module 5, configured to write packets of the queue into a host side cache unit pointed to by the currently read descriptor, and update a number of cached packets of the queue and the descriptor index; and

[0100] a descriptor storing module 6, configured to, if the updated number of cached packets of the queue is 0 and the n1 descriptors are not all used, cache the unused descriptors at the data processing unit;

[0101] the packet uploading module 5 is further configured to, in a scenario where the number of descriptors is greater than 0, write the packets of the queue into a host side cache unit pointed to by the descriptor cached at the data processing unit;

[0102] the descriptor reading module 4 is further configured to, if the packets of the queue fail to be completely written into the host side cache unit pointed to by the descriptor cached at the data processing unit, determine a number n2 of descriptors to be read according to the descriptor index, read m2 descriptors from the descriptor ring table on the host side based on the cache line alignment manner, and obtain the n2 descriptors to be read according to the m2 descriptors; wherein m2 ≥ n2;

[0103] the packet uploading module 5 is further configured to write remaining packets of the queue into a host side cache unit pointed to by at least one descriptor of the n2 descriptors, and update the number of cached packets of the queue and the descriptor index;

[0104] the descriptor storing module 6 is further configured to, if the updated number of cached packets of the queue is 0 and the n2 descriptors are not all used, cache the unused descriptors at the data processing unit.

[0105] In some embodiments, the descriptor reading module 4 is further configured to, in a scenario where the number of descriptors is 0, if the number of buffered packets of the queue after updating is not 0 and the n1 descriptors have all been used, determine the number n3 of descriptors to be read according to the updated descriptor index, read m3 descriptors from the descriptor ring table on the host side based on the cache line alignment mode, and obtain the n3 descriptors to be read according to the m3 descriptors; wherein m3≥n3.

[0106] The packet reporting module 5 is further configured to write the packets of the queue into the host side cache unit pointed to by at least one of the n3 descriptors, and update the number of buffered packets of the queue and the descriptor index.

[0107] In some embodiments, the descriptor reading module 4 comprises:

[0108] A first descriptor number obtaining module configured to predict the number of descriptors needed, one packet processing request needing one descriptor;

[0109] A second descriptor number obtaining module configured to determine the number n1, n2 or n3 of descriptors to be read according to the descriptor index and the predicted number of descriptors needed;

[0110] A descriptor reading module configured to read m1, m2 or m3 descriptors from the descriptor ring table on the host side based on the cache line alignment mode according to the number n1, n2 or n3 of descriptors;

[0111] A descriptor processing module configured to obtain n1, n2 or n3 descriptors according to the m1, m2 or m3 descriptors.

[0112] In some embodiments, the data processing unit comprises:

[0113] A packet storage RAM configured to store the packets of any queue;

[0114] A packet number RAM configured to store the number of buffered packets of any queue;

[0115] A descriptor storage RAM configured to store the unused descriptors;

[0116] A descriptor read-write pointer RAM configured to store a read pointer and a write pointer, the read pointer pointing to the position of the descriptor currently read from the descriptor storage RAM, and the write pointer pointing to the position of the descriptor currently written into the descriptor storage RAM;

[0117] A descriptor FIFO module configured to store the n1, n2 or n3 descriptors read;

[0118] A descriptor index storage RAM is used to store the descriptor index; wherein, whenever a descriptor is read from the descriptor FIFO module, the value of the descriptor index is incremented by one.

[0119] Referring to Figure 6 The following describes in detail how the DPU sends messages by taking a queue (Virtqueue) as an example:

[0120] Step 1: The Device receives an Ethernet message from a network interface;

[0121] Step 2: The message is saved in the message storage RAM of the Device according to the queue;

[0122] Step 3: Whenever a message of a queue is stored in the message storage RAM, the value of the queue in the message number RAM (i.e. the number of buffered messages of the queue) is read out and incremented by one and written back to the message number RAM; whenever a message of a queue is read from the message storage RAM, the value of the queue in the message number RAM (i.e. the number of buffered messages of the queue) is read out and decremented by one and written back to the message number RAM;

[0123] Step 4: The descriptor read-write pointer RAM is queried to determine the number of descriptors in the descriptor storage RAM through the read-write pointer; if the number of descriptors in the descriptor storage RAM is 0, step 5 is performed to initiate reading of the descriptor index storage RAM, otherwise, step 8 is performed to directly read the descriptor in the descriptor storage RAM;

[0124] Step 5: The descriptor index maintained by the DPU is queried in the descriptor index storage RAM;

[0125] Step 6: The number of descriptors to be read is calculated through the read descriptor index;

[0126] Step 7: The descriptor reading is initiated to the host driver;

[0127] Step 8: When there are messages in the message storage RAM and there are descriptors in the descriptor storage RAM, the descriptor in the descriptor storage RAM is read; every time a descriptor is read from the descriptor storage RAM, the read pointer of the descriptor read-write pointer RAM is incremented by one to indicate which position is read;

[0128] Step 9: The host driver returns the descriptor and stores the descriptor in the descriptor storage FIFO module of the DPU;

[0129] Step 10, when the "descriptor storage FIFO module" is not empty, read the descriptor in the "descriptor storage FIFO module", and go to step 11, 14, 15 according to different cases;

[0130] Step 11, the descriptor read from the "descriptor storage FIFO module" will be directly used for sending the message, and since the descriptor reading to the host driver is initiated only when the "descriptor storage RAM" is empty, step 8 and step 11 will not exist at the same time for the same queue;

[0131] Step 12, read the message in the "message storage RAM", send the message to the host side cache unit pointed by the descriptor, and then update the used descriptor to the descriptor ring table of the host driver;

[0132] Step 13, whenever a message is read from the "message storage RAM", the value in the "message number RAM" (the number of cached messages corresponding to the queue) is reduced by 1;

[0133] Step 14, whenever a descriptor is read from the "descriptor storage FIFO module", trigger reading the "descriptor index storage RAM", add 1 to the read descriptor index and write it back to the "descriptor index storage RAM" to update the descriptor index;

[0134] Step 15, if the messages in the "message storage RAM" have been read, but there are still descriptors in the "descriptor storage FIFO module", store these remaining descriptors in the "descriptor storage RAM", and whenever a descriptor is stored in the "descriptor storage RAM", add 1 to the write pointer of the "descriptor read-write pointer RAM" to indicate where to write.

[0135] Another embodiment of the present application provides a data processing unit (DPU) comprising:

[0136] a communication interface for communicating with other electronic devices;

[0137] a memory for storing computer program instructions;

[0138] a processor for executing the computer program instructions to support the data processing unit to implement the method as described in the above embodiments.

[0139] In this embodiment, the memory mainly includes a program storage area and a data storage area, wherein the program storage area can store application programs required by the operation device and at least one function, and the data storage area can store relevant data and the like. In addition, the memory can be a high-speed random access memory, and can also be a non-volatile memory such as a plug-in hard disk, a smart media card (SMC), a secure digital (SD) card, a flash card and the like, or can be other volatile solid-state storage devices.

[0140] The processor can be a central processing unit (CPU), and can also be other general-purpose processors, digital signal processors (DSPs), application specific integrated circuits (ASICs), field-programmable gate arrays (FPGAs) or other programmable logic devices, discrete gates or transistor logic devices, discrete hardware components, and the like. The general-purpose processor can be a microprocessor, or the processor can also be any conventional processor. The processor is the control center of the data processing unit, and connects various parts of the data processing unit through various interfaces and lines.

[0141] Another embodiment of the present application provides a computer program product including computer program instructions, which instruct a computer device to perform operations corresponding to the packet uploading method described in the above embodiments.

[0142] Specifically, the computer program product includes a series of computer program instructions, which are codes written in computer programs and define how to perform specific operations. The computer program instructions are designed to be loaded onto a computer device and guide the device to perform specific operations, which refer to the steps of the packet uploading method described in the above embodiments. In this way, the computer program product of the present embodiment provides a complete software solution, which can run on various computer devices to implement the packet uploading method of the above embodiments.

[0143] Having described various embodiments of the application, it is to be understood that the above description is meant not to be exhaustive or limited to the various embodiments disclosed. Many modifications and variations are possible in light of the above teachings without departing from the scope and spirit of the described embodiments. It is also to be understood that the terminology used herein is for the purpose of describing particular embodiments only, and is not intended to limit the scope of the various embodiments described herein, since the scope of the various embodiments is limited solely by the claims.

Claims

1. A message uploading method, applied to a data processing unit, characterized in that, The method includes: When a message is received from any queue, the message is cached in the data processing unit, and the number of cached messages in the queue is updated. Obtain the number of descriptors and the descriptor index of the queue cached in the data processing unit; wherein the descriptor index points to the position of the next descriptor to be read in the descriptor ring table; In the scenario where the number of descriptors is 0, the number of descriptors to be read, n1, is determined based on the descriptor index. m1 descriptors are read from the host-side descriptor ring table based on cache line alignment. Based on the m1 descriptors, the n1 descriptors to be read are obtained. The packets from the queue are written to the host-side cache unit pointed to by at least one of the n1 descriptors, and the cached packet count and descriptor index of the queue are updated. If the updated cached packet count of the queue is 0 and not all n1 descriptors are used, the unused descriptors are cached in the data processing unit. Wherein, m1 ≥ n1. In scenarios where the number of descriptors is greater than 0, the packets in the queue are written into the host-side cache unit pointed to by the descriptor of the data processing unit. If not all the packets in the queue are written into the host-side cache unit pointed to by the descriptor of the data processing unit, the number of descriptors to be read, n2, is determined according to the descriptor index. Based on the cache row alignment, m2 descriptors are read from the host-side descriptor ring table, and the n2 descriptors to be read are obtained according to the m2 descriptors. The remaining packets in the queue are written into the host-side cache unit pointed to by at least one of the n2 descriptors, and the number of cached packets in the queue and the descriptor index are updated. If the updated number of cached packets in the queue is 0 and not all of the n2 descriptors are used, the unused descriptors are cached in the data processing unit. Wherein, m2 ≥ n2.

2. The method according to claim 1, characterized in that, The method includes: In the scenario where the number of descriptors is 0, if the updated number of cached packets in the queue is not 0 and all n1 descriptors have been used, then the number of descriptors to be read, n3, is determined according to the updated descriptor index, and m3 descriptors are read from the host-side descriptor ring table based on cache line alignment. Based on the m3 descriptors, the n3 descriptors to be read are obtained, and the remaining packets in the queue are written to the host-side cache unit pointed to by at least one of the n3 descriptors. The number of cached packets in the queue and the descriptor index are updated; wherein, m3 ≥ n3.

3. The method according to claim 2, characterized in that, The steps to determine the number of descriptors n1, n2, or n3 to be read based on the descriptor index include: n=cache_bd_num-1-(bd_index+req_num-1)%cache_bd_num+req_num; Where n is the number of descriptors to be read (n1, n2, or n3), % is the modulo operator, cache_bd_num is the number of descriptors in a cacheline, bd_index is the descriptor index, and req_num is the number of descriptors required for prediction. A message processing request requires one descriptor according to the prediction method.

4. The method according to claim 2, characterized in that, The step of obtaining the n1 descriptors to be read based on the m1 descriptors includes: selecting n1 descriptors from the m1 descriptors according to the descriptor index as the n1 descriptors to be read; The step of obtaining the n2 descriptors to be read based on the m2 descriptors includes: selecting n2 descriptors from the m2 descriptors according to the descriptor index as the n2 descriptors to be read; The step of obtaining the n3 descriptors to be read based on the m3 descriptors includes: selecting n3 descriptors from the m3 descriptors according to the descriptor index as the n3 descriptors to be read.

5. A data processing unit, characterized in that, include: The message storage module is used to cache the message in the data processing unit and update the number of cached messages in the queue when a message from any queue is received. The descriptor query module is used to obtain the number of descriptors cached in the data processing unit by the queue; An index acquisition module is used to acquire a descriptor index; wherein, the descriptor index points to the position of the next descriptor to be read in the descriptor ring table; The descriptor reading module is used to determine the number of descriptors n1 to be read based on the descriptor index when the number of descriptors is 0, and to read m1 descriptors from the descriptor ring table on the host side based on the cache line alignment, and to obtain the n1 descriptors to be read based on the m1 descriptors; wherein, m1≥n1; The message uploading module is used to write the messages from the queue into the host-side buffer unit pointed to by the currently read descriptor, and update the number of buffered messages in the queue and the descriptor index; and The descriptor storage module is used to cache unused descriptors in the data processing unit if the updated number of cached messages in the queue is 0 and not all of the n1 descriptors are used. The message reporting module is also used to write the messages of the queue into the host-side cache unit pointed to by the descriptor of the data processing unit when the number of descriptors is greater than 0. The descriptor reading module is further configured to, if the messages in the queue are not all written into the host-side cache unit pointed to by the descriptor of the data processing unit, determine the number of descriptors n2 to be read according to the descriptor index, read m2 descriptors from the host-side descriptor ring table based on the cache line alignment, and obtain the n2 descriptors to be read based on the m2 descriptors; wherein, m2≥n2; The message reporting module is also used to write the remaining messages of the queue into the host-side cache unit pointed to by at least one of the n2 descriptors, and update the number of cached messages of the queue and the descriptor index; The descriptor storage module is further configured to cache unused descriptors in the data processing unit if the updated number of cached messages in the queue is 0 and not all of the n2 descriptors are used.

6. The data processing unit according to claim 5, characterized in that, The descriptor reading module is further configured to, in the scenario where the number of descriptors is 0, if the updated number of cached packets in the queue is not 0 and all n1 descriptors have been used, determine the number of descriptors n3 to be read based on the updated descriptor index, and read m3 descriptors from the host-side descriptor ring table based on the cache line alignment, and obtain the n3 descriptors to be read based on the m3 descriptors; wherein, m3≥n3; The message reporting module is also used to write the messages of the queue into the host-side cache unit pointed to by at least one of the n3 descriptors, and update the number of cached messages of the queue and the descriptor index.

7. The data processing unit according to claim 6, characterized in that, The descriptor reading module includes: The first descriptor number acquisition module is used to predict the required number of descriptors. A message requires one descriptor to process the request according to the prediction method. The second descriptor number acquisition module is used to determine the number of descriptors to be read, n1, n2 or n3, based on the descriptor index and the predicted number of descriptors required. The descriptor reading module is used to read the corresponding m1, m2, or m3 descriptors from the descriptor ring table on the host side based on the cache line alignment method, according to the number of descriptors n1, n2, or n3. The descriptor processing module is used to obtain the corresponding n1, n2, or n3 descriptors based on the m1, m2, or m3 descriptors.

8. The data processing unit according to any one of claims 5 to 7, characterized in that, The data processing unit includes: A message storage RAM is used to store messages from any of the queues. The message count RAM is used to store the number of buffered messages in any of the queues; The descriptor storage RAM is used to store the unused descriptors; The descriptor read / write pointer RAM is used to store the read pointer and the write pointer. The read pointer points to the position of the descriptor currently read from the descriptor storage RAM, and the write pointer points to the position of the descriptor currently written to the descriptor storage RAM. The descriptor FIFO module is used to store n1, n2, or n3 descriptors that are read; The descriptor index storage RAM is used to store the descriptor index; wherein, whenever a descriptor is read from the descriptor FIFO module, the value of the descriptor index is incremented by one.

9. A data processing unit, characterized in that, include: A communication interface used for communicating with other electronic devices; Memory is used to store computer program instructions; A processor for executing the computer program instructions to support the data processing unit in implementing the method as described in any one of claims 1 to 4.

10. A computer program product, characterized in that, It includes computer program instructions that instruct a computer device to perform an operation corresponding to the method described in any one of claims 1 to 4.

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