Semiconductor memory device and manufacturing method thereof

Abstract

A semiconductor memory device and a method of manufacturing the same are provided. The semiconductor memory device includes a first insulating layer including a cell region and an extension region, a channel structure penetrating the first insulating layer in the cell region, a memory layer extending along a sidewall of the channel structure, a conductive layer extending along the sidewall of the channel structure, an active pattern extending along the sidewall of the channel structure, and a gate electrode extending along the sidewall of the memory layer. The conductive layers are disposed to be spaced apart in a vertical direction along sidewalls of the memory layer over the first insulating layer, active patterns are coupled to corresponding ones of the conductive layers, and gate electrodes are disposed over the active patterns.

Description

[0001] Cross Reference to Related Applications

[0002] This application claims priority to Korean Patent Application No. 10-2024-0054125, filed on April 23, 2024, in the Korean Intellectual Property Office, the entire contents of which are incorporated herein by reference. TECHNICAL FIELD

[0003] Various embodiments of the present disclosure generally relate to a semiconductor memory device and a manufacturing method thereof, and more particularly to a three-dimensional semiconductor memory device and a manufacturing method thereof. BACKGROUND

[0004] Semiconductor memory devices can be applied not only to small electronic devices, but also to electronic devices in various fields such as automobiles, healthcare, and data centers. Accordingly, the demand for semiconductor memory devices is increasing.

[0005] A semiconductor memory device includes memory cells for storing data. A three-dimensional semiconductor memory device is more advantageous than a two-dimensional semiconductor memory device in implementing a large-capacity storage because the three-dimensional semiconductor memory device includes a plurality of memory cells arranged in three dimensions.

[0006] By increasing the number of stacked memory cells, the integration of memory cells in a three-dimensional semiconductor device can be improved. As the number of stacked memory cells increases, the number of stacked conductive layers coupled to the memory cells can also increase. As the number of stacked conductive layers increases, a connection structure between a peripheral circuit that controls the operation of the memory cells and the conductive layers can become more complex, and the operation reliability of the semiconductor memory device can decrease. SUMMARY

[0007] According to an embodiment, a semiconductor memory device can include a first insulating layer including a cell region and an extension region, a channel structure penetrating the first insulating layer in the cell region, a memory layer extending along a sidewall of the channel structure, a conductive layer disposed to be spaced apart in a vertical direction along a sidewall of the memory layer above the first insulating layer, a second insulating layer disposed to be alternated with the conductive layer in the vertical direction and extending above the extension region of the first insulating layer, an active pattern disposed in the second insulating layer between second insulating layers adjacent in the vertical direction and coupled to a corresponding one of the conductive layers, and a gate electrode disposed above the active pattern.

[0008] According to an embodiment, a semiconductor memory device can include a first insulating layer including a cell region and an extension region, a channel structure penetrating the first insulating layer in the cell region, a memory layer extending along a sidewall of the channel structure, a conductive layer and a second insulating layer disposed over the first insulating layer and alternately stacked along a sidewall of the memory layer, an active pattern respectively extending from the conductive layer and disposed in a stair structure over the extension region of the first insulating layer, and a gate electrode respectively disposed over the active pattern.

[0009] According to an embodiment, a method of manufacturing a semiconductor memory device can include forming a first insulating layer including a cell region and an extension region, stacking sub-structures over the first insulating layer, wherein each of the sub-structures is a stacked structure of a sacrificial layer and a second insulating layer, forming a stair structure and a preliminary gate electrode by etching the sub-structures, wherein the stair structure is disposed over the extension region of the first insulating layer, and the preliminary gate electrode is disposed over the stair structure and includes a portion of the sacrificial layer, forming a third insulating layer over the sub-structures to cover the stair structure and the preliminary gate electrode, forming a first opening and a second opening, the first and second openings respectively overlapping the stair structure on both sides of the preliminary gate electrode and penetrating the third insulating layer, replacing a portion of the sacrificial layer of the stair structure with an active pattern through the first and second openings, replacing the sacrificial layer with a conductive material, and forming a first contact plug and a second contact plug in the first and second openings, respectively. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a block diagram illustrating a semiconductor memory device according to an embodiment of the present disclosure;

[0011] Figure 2 is a circuit diagram illustrating a memory cell array and a transfer circuit according to an embodiment of the present disclosure;

[0012] Figure 3 is a diagram illustrating a gate stack structure of a memory cell array according to an embodiment of the present disclosure;

[0013] Figure 4A and Figure 4B is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the present disclosure;

[0014] Figure 5 is a cross-sectional view illustrating a transfer transistor according to an embodiment of the present disclosure;

[0015] Figure 6A , Figure 6B , Figure 6C and Figure 6D , Figure 7A , Figure 7B andFigure 7C , Figure 8A , Figure 8B and Figure 8C , and Figure 9A , Figure 9B , Figure 9C and Figure 9D are diagrams illustrating a method of manufacturing a semiconductor memory device according to an embodiment of the disclosure; and

[0016] Figure 10 is a block diagram illustrating an electronic system according to an embodiment of the disclosure. DETAILED DESCRIPTION

[0017] The specific structural or functional descriptions disclosed herein are merely meant to describe embodiments according to the concept of the disclosure. Embodiments according to the concept of the disclosure can be implemented in various forms, and should not be construed as being limited to the specific embodiments described herein.

[0018] Terms such as "first" and "second" are used to distinguish various elements, and do not indicate the size, order, priority, number, or importance of the elements. For example, in one example, a first element can be referred to as a second element, and in another example, a second element can be referred to as a first element. Terms such as "vertical," "horizontal," "above," "side," "lower," "outer," and other terms implying relative spatial relationships or orientations are used only for the purpose of facilitating description or reference to the drawings, and do not constitute other limitations. Cross-hatching in the entire figure shows corresponding or similar areas between figures, rather than indicating materials related to the areas. It should be understood that when one element or layer is referred to as "on," "connected to," or "coupled to" another element or layer, it can be directly on, connected to, or coupled to the other element or layer, or there can be an intermediate element or layer. In contrast, when one element is referred to as "directly on," "directly connected to," or "directly coupled to" another element or layer, there is no intermediate element or layer.

[0019] Various embodiments relate to a semiconductor memory device capable of improving operation reliability and a method of manufacturing the same.

[0020] Figure 1 is a block diagram illustrating a semiconductor memory device 50 according to an embodiment of the disclosure.

[0021] Referring to Figure 1 , the semiconductor memory device 50 includes a memory cell array 10, a transfer circuit 40, and a peripheral circuit structure PS.

[0022] The memory cell array 10 includes a plurality of memory blocks. Each of the memory blocks includes a plurality of memory cells. Each of the memory cells in the memory blocks can be a nonvolatile memory cell. In one embodiment, each of the memory cells in the memory blocks can be a NAND flash memory cell. Embodiments of the present disclosure will be described below based on the semiconductor memory device 50 including NAND flash memory cells, but the present disclosure is not limited thereto. In another embodiment, each of the memory cells can include a ferroelectric memory cell, a variable resistance memory cell, or the like.

[0023] The transfer circuit 40 is connected to the memory cell array 10 via the word lines WL, the source select lines SSL, and the drain select lines DSL.

[0024] The peripheral circuitry PS is configured to perform a program operation of storing data in the memory cell array 10, a read operation of outputting data stored in the memory cell array 10, and an erase operation of erasing data stored in the memory cell array 10. In one embodiment, the peripheral circuitry PS can include the input / output circuit 21, the control circuit 23, the voltage generation circuit 31, the block decoder 33, the column decoder 35, the page buffer 37, and the source line driver 39.

[0025] The input / output circuit 21 transfers a command CMD and an address ADD received from an external device (e.g., a memory controller) of the semiconductor memory device 50 to the control circuit 23. The input / output circuit 21 exchanges data DATA with the external device and the column decoder 35.

[0026] The control circuit 23 outputs an operation signal OP_S, a row address RADD, a source line control signal SL_S, a page buffer control signal PB_S, and a column address CADD in response to the command CMD and the address ADD.

[0027] The voltage generation circuit 31 generates and outputs various operation voltages for the program operation, the read operation, or the erase operation in response to the operation signal OP_S. The operation voltages output from the voltage generation circuit 31 are transferred to the transfer circuit 40 via a plurality of global lines GLL.

[0028] The block decoder 33 outputs a block selection signal in response to the row address RADD. The block selection signal output from the block decoder 33 is transferred to the transfer circuit 40 via a block selection line BSEL.

[0029] The transfer circuit 40 transfers the operation voltages transferred via the plurality of global lines GLL to the drain select lines DSL, the word lines WL, and the source select lines SSL in response to the block selection signal transferred to the block selection line BSEL.

[0030] The column decoder 35 transfers data DATA input from the input / output circuit 21 to the page buffer 37 or transfers data DATA stored in the page buffer 37 to the input / output circuit 21 in response to a column address CADD. The column decoder 35 exchanges data DATA with the input / output circuit 21 through a column line CL. Further, the column decoder 35 also exchanges data DATA with the page buffer 37 through a data line DL.

[0031] The page buffer 37 stores read data received through the bit line BL in response to a page buffer control signal PB_S. The page buffer 37 senses a voltage or a current of the bit line BL during a read operation. The page buffer 37 is connected to the memory cell array 10 through the bit line BL.

[0032] The source line driver 39 controls a voltage applied to the common source line CSL in response to a source line control signal SL_S. The source line driver 39 is connected to the memory cell array 10 through the common source line CSL.

[0033] Figure 2 is a circuit diagram illustrating the memory cell array 10 and the transfer circuit 40 according to an embodiment of the disclosure.

[0034] Reference Figure 2 The memory cell array 10 includes a plurality of memory cell strings CS. The plurality of memory cell strings CS is connected to a plurality of bit lines BL and a source layer SR. The plurality of memory cell strings CS is connected to Figure 1 a common source line CSL as shown.

[0035] Each memory cell string CS includes at least one source select transistor SST, a plurality of memory cells MC, and at least one drain select transistor DST.

[0036] The source select transistor SST controls an electrical connection between the plurality of memory cells MC and the source layer SR. The drain select transistor DST controls an electrical connection between the plurality of memory cells MC and the bit line BL.

[0037] One source select transistor SST or at least two source select transistors SST coupled in series can be provided between the source layer SR and the plurality of memory cells MC. In the corresponding memory cell string CS, one drain select transistor DST or at least two drain select transistors DST coupled in series can be provided between each bit line BL and the plurality of memory cells MC.

[0038] A plurality of gates of the plurality of memory cells MC is coupled to a plurality of word lines WL, respectively. A gate of the source select transistor SST is coupled to a source select line SSL. A gate of the drain select transistor DST is coupled to a drain select line DSL.

[0039] The source selection lines SSL, the drain selection lines DSL, and the plurality of word lines WL are connected to a transfer circuit 40. The transfer circuit 40 includes a transfer transistor group, and each transfer transistor group includes a plurality of transfer transistors PT connected to the same block selection line BSEL. The plurality of transfer transistors PT are connected to the source selection lines SSL, the drain selection lines DSL, and the plurality of word lines WL in a one-to-one manner.

[0040] The plurality of transfer transistors PT transfer a voltage applied to the plurality of global lines GLL to the source selection lines SSL, the drain selection lines DSL, and the plurality of word lines WL in response to a block selection signal applied to the block selection line BSEL. The plurality of global lines GLL includes a global source selection line GSSL, a global drain selection line GDSL, and a plurality of global word lines GWL corresponding to the source selection lines SSL, the drain selection lines DSL, and the plurality of word lines WL, respectively.

[0041] The conductive layers of the gate stack structure serve as the source selection lines SSL, the drain selection lines DSL, and the plurality of word lines WL. The plurality of transfer transistors PT include active patterns coupled to the conductive layers of the gate stack structure, respectively.

[0042] Figure 3 FIG. 1 is a diagram illustrating a gate stack structure GST of a memory cell array 10 according to an embodiment of the disclosure.

[0043] Referring to Figure 3 The gate stack structure GST includes a cell area CAR and an extension area EAR extending from the cell area CAR. The gate stack structure GST includes conductive layers and insulating layers extending in a horizontal direction. In one embodiment, the horizontal direction can correspond to a first direction DR1 or a second direction DR2. Figure 3 The first direction DR1 and the second direction DR2 shown in FIG. 1 are directions in which axes crossing each other face each other in a plane. The conductive layers and the insulating layers of the gate stack structure GST are alternately disposed in a vertical direction. Figure 3 The third direction DR3 shown in FIG. 1 is a vertical direction. In one embodiment, the first direction DR1, the second direction DR2, and the third direction DR3 can correspond to an X-axis direction, a Y-axis direction, and a Z-axis direction, respectively.

[0044] In one embodiment, the gate stack structure GST includes a plurality of stepped areas SAR1 to SARn (n is a natural number equal to or greater than 2) disposed in the extension area EAR. Figure 2 The plurality of transfer transistors PT overlap the plurality of stepped areas SAR1 to SARn of the gate stack structure GST, as shown in FIG. 1.

[0045] The gate stack structure GST can have a staircase structure in each of the plurality of staircase regions SAR1 to SARn. The staircase structures disposed in different staircase regions are disposed at different levels.

[0046] Figure 4A and Figure 4B is a cross-sectional view illustrating a semiconductor memory device according to an embodiment of the disclosure.

[0047] Referring to Figure 4A and Figure 4B , the semiconductor memory device includes a source layer SR, a bit line BL, a gate stack structure GST, a channel structure CH, a memory layer ML, a pass transistor PT, a global line (e.g., GWL), a block select line BSEL, and a peripheral circuit structure PS.

[0048] The source layer SR includes at least one doped semiconductor layer. The source layer SR includes N-type impurities as majority carriers. The region including the N-type impurities as the majority carriers is provided as a source region.

[0049] Referring to Figure 4A , in one embodiment, the source layer SR can include a first doped semiconductor layer L1, a second doped semiconductor layer L2, and a third doped semiconductor layer L3. One of the first doped semiconductor layer L1, the second doped semiconductor layer L2, and the third doped semiconductor layer L3 can include N-type impurities as majority carriers, and the other doped semiconductor layers can include N-type impurities or P-type impurities as majority carriers. In one embodiment, the second doped semiconductor layer L2 can include N-type impurities as majority carriers, and can be provided as a source region. The third doped semiconductor layer L3 can include N-type impurities or P-type impurities as majority carriers. According to an embodiment in which the third doped semiconductor layer L3 includes P-type impurities as majority carriers, the third doped semiconductor layer L3 can be provided as a well region. The first doped semiconductor layer L1 can include N-type impurities or P-type impurities as majority carriers.

[0050] Referring to Figure 4B , in one embodiment, the source layer SR can be formed as a single doped semiconductor layer. The single doped semiconductor layer can include a first conductivity type doped region including N-type impurities as majority carriers. The single doped semiconductor layer can further include a second conductivity type doped region including P-type impurities as majority carriers.

[0051] Referring to Figure 4A and Figure 4B , the source layer SR extends in a first direction DR1 and a second direction DR2. The bit line BL is spaced apart from the source layer SR in a third direction DR3, and a length of the bit line BL is defined in the second direction DR2.

[0052] The gate stack structure GST includes insulating layers and conductive layers CDL alternately arranged between a source layer SR and a bit line BL. The insulating layer of the gate stack structure GST is divided into a first insulating layer IL1 and a second insulating layer IL2. The first insulating layer IL1 is adjacent to the source layer SR and includes a cell area CAR and an extension area EAR extending from the cell area CAR. The second insulating layer IL2 is arranged above the first insulating layer IL1 and alternately with the conductive layers CDL in a third direction DR3. Each of the first insulating layer IL1 and the second insulating layer IL2 includes an insulating material such as a silicon oxide layer.

[0053] The conductive layers CDL of the gate stack structure GST are disposed on the first insulating layer IL1 and are spaced apart from each other in the third direction DR3. Each of the conductive layers CDL includes various conductive materials, such as a doped semiconductor layer, a metal layer, and the like. The doped semiconductor layer may include a doped silicon layer. The metal layer may include tungsten (W), copper (Cu), molybdenum (Mo), and the like. Each of the conductive layers CDL may also include a metal nitride layer provided as a barrier layer. The metal nitride layer may include titanium nitride (TiN), tantalum nitride (TaN), and the like.

[0054] The first insulating layer IL1 is penetrated by the channel structure CH in the cell region CAR. The channel structure CH is used as Figure 2 . The channel region of the memory cell string CS shown in . The channel structure CH includes a semiconductor material such as silicon (Si), germanium (Ge) or a mixture thereof. The channel structure CH extends in the third direction DR3 to penetrate the gate stack structure GST. In one embodiment, the channel structure CH has a tubular structure extending to a certain length in the third direction DR3. The core insulating layer CO is arranged in a central area defined by the tubular structure of the channel structure CH. The channel structure CH includes a cap portion. The cap portion of the channel structure CH forms one end of the channel structure CH facing the third direction DR3. The cap portion of the channel structure CH surrounds the end portion of the core insulating layer CO facing the bit line BL and includes at least one impurity of N-type impurities or P-type impurities. In one embodiment, the cap portion of the channel structure CH may include N-type impurities as majority carriers.

[0055] The memory layer ML extends along the sidewall of the channel structure CH. The memory layer ML is interposed between the channel structure CH and the first insulating layer IL1. The memory layer ML extends in the third direction DR3 to be interposed between each of the conductive layer CDL and the second insulating layer IL2 and the channel structure CH. The memory layer ML includes a barrier insulating layer between the gate stack structure GST and the channel structure CH, a data storage layer between the barrier insulating layer and the channel structure CH, and a tunnel insulating layer between the data storage layer and the channel structure CH. The tunnel insulating layer extends along the outer wall of the channel structure CH and includes an insulating material such as a silicon oxide layer. The data storage layer extends continuously along the outer wall of the tunnel insulating layer or is partitioned into data storage patterns spaced apart from each other in the third direction DR3. The data storage patterns are respectively provided at levels in which the conductive layers CDL are provided. The data storage layer can include a material layer capable of storing data that is changed using F-N tunneling (Fowler-Nordheim tunneling). In one embodiment, the data storage layer can include a charge trap insulating layer, a floating gate layer, or an insulating layer containing conductive nano dots. The charge trap insulating layer can include a silicon nitride layer. The barrier insulating layer can include at least one of a silicon dioxide (SiO2) layer and a high dielectric layer having a higher dielectric constant than the silicon dioxide (SiO2) layer. The high dielectric layer can include an aluminum oxide layer, a hafnium oxide layer, or the like.

[0056] The channel structure CH includes a contact surface in contact with the source layer SR. The contact surface can be defined at a portion of the sidewall of the channel structure CH, the other end of the channel structure CH, or the like. The other end of the channel structure CH faces the opposite direction of the cap portion described above.

[0057] Reference Figure 4A In one embodiment, the memory layer ML can be penetrated by the second doped semiconductor layer L2 of the source layer SR and can be partitioned into a first memory layer ML1 and a second memory layer ML2. The second doped semiconductor layer L2 of the source layer SR contacts a portion of the sidewall of the channel structure CH provided between the first memory layer ML1 and the second memory layer ML2. Accordingly, a contact surface between the channel structure CH and the source layer SR is defined. The first memory layer ML1 is interposed between the gate stack structure GST and the channel structure CH and extends between the third doped semiconductor layer L3 of the source layer SR and the channel structure CH. The second memory layer ML2 is interposed between the first doped semiconductor layer L1 of the source layer SR and the channel structure CH.

[0058] Reference Figure 4BIn one embodiment, the source layer SR can include a recess. The other end of the channel structure CH protrudes deeper into the source layer SR than the memory layer ML and is inserted into the recess of the source layer SR. The contact surface between the channel structure CH and the source layer SR is defined along the recess of the source layer SR.

[0059] Referring to Figure 4A and Figure 4B , the conductive layers CDL and the second insulating layers IL2 are disposed over the first insulating layers IL1. The conductive layers CDL and the second insulating layers IL2 are alternately disposed in the third direction DR3 along the sidewalls of the memory layers ML. The conductive layers CDL are spaced apart from each other in the third direction DR3 by the second insulating layers IL2. The conductive layers CDL and the second insulating layers IL2 surround the sidewalls of the memory layers ML over the cell areas CAR of the first insulating layers IL1 and extend over the extension areas EAR of the first insulating layers IL1.

[0060] At least one of the conductive layers CDL adjacent to the first insulating layers IL1 functions as a source select line SSL, at least one of the conductive layers CDL adjacent to the bit lines BL functions as a drain select line DSL, and the other conductive layers CDL function as word lines WL.

[0061] The second insulating layers IL2 have a stepped structure in the plurality of stepped areas SARI to SARn shown in Figure 3 . The stepped structure in different stepped areas includes the second insulating layers IL2 disposed at different levels. The second insulating layers IL2 are divided into a plurality of pairs, and each pair includes two second insulating layers IL2 adjacent to each other in the third direction DR3. Each pair of second insulating layers IL2 is adjacent to each other in the third direction DR3 with a corresponding conductive layer among the conductive layers CDL interposed therebetween and protrudes further in the horizontal direction than the corresponding conductive layer. In one embodiment, each pair of second insulating layers IL2 protrudes further in the first direction DR1 than the corresponding conductive layer.

[0062] The active patterns ACT are disposed between the second insulating layers IL2. Each of the active patterns ACT is disposed between consecutive second insulating layers IL2. Further, each of the active patterns ACT extends from a corresponding conductive layer among the conductive layers CDL. The active patterns ACT are disposed in a stepped structure over the extension areas EAR of the first insulating layers IL1. Each of the active patterns ACT is coupled to a corresponding conductive layer disposed in the same layer. The gate electrodes GE2 are disposed over and respectively overlap the active patterns ACT. Each of the gate electrodes GE2 is spaced apart from the active pattern ACT with a gate insulating region GI2 of a corresponding second insulating layer IL2 interposed therebetween.

[0063] Each of the active patterns ACT, the gate electrode GE2, the gate insulating region GI2 of the corresponding active pattern ACT and the second insulating layer forms a pass transistor PT.

[0064] The gate electrode GE2 serves as a gate of the pass transistor PT, and the gate insulating region GI2 of the second insulating layer serves as a gate insulating layer of the pass transistor PT. The gate electrode GE2 includes the same conductive material as the conductive layer CDL.

[0065] The active pattern ACT includes a doped semiconductor layer. In one embodiment, the active pattern ACT can include a P-type doped semiconductor layer, such as a P-type doped silicon layer. The active pattern ACT includes a channel region CHR that overlaps the gate electrode GE2. The channel region CHR of the active pattern ACT serves as a channel region of the pass transistor PT. The active pattern ACT includes a first junction JN21 and a second junction JN22 that are spaced apart from each other with the channel region CHR interposed therebetween. The first junction JN21 and the second junction JN22 are disposed on both sides of the channel region CHR. The first junction JN21 and the second junction JN22 serve as a source region and a drain region of the pass transistor PT. In one embodiment, the first junction JN21 and the second junction JN22 can include N-type impurities as majority carriers.

[0066] In one embodiment, the dummy pattern IL2’ can overlap the gate electrode GE2. The dummy pattern IL2’ is disposed at the same layer as one of the second insulating layers IL2, and includes the same material as the second insulating layers IL2. However, embodiments of the present disclosure are not limited thereto, and the dummy pattern IL2’ can be omitted.

[0067] The gate stack structure GST and the pass transistor PT are covered by a third insulating layer IL3. The third insulating layer IL3 is covered by a fourth insulating layer IL4. A bit line BL is formed in the fourth insulating layer IL4. The channel structure CH is electrically coupled to the bit line BL via a bit line contact structure BCT. The bit line contact structure BCT penetrates the third insulating layer IL3, and is coupled to the bit line BL and the channel structure CH.

[0068] A global line, such as a global word line GWL, is formed in the fourth insulating layer IL4. Each of the global lines is electrically coupled to a corresponding pass transistor PT via a first contact plug CT1. The first contact plug CT1 penetrates the third insulating layer IL3, and is coupled to the corresponding global line and the corresponding first junction JN21.

[0069] A third insulating layer IL3 is penetrated by a second contact plug CT2 coupled to the second junction JN22. The second contact plug CT2 includes a contact surface that contacts the second junction JN22 and extends in a third direction DR3 to penetrate the third insulating layer IL3. The third insulating layer IL3 and a fourth insulating layer IL4 block the rest of the second contact plug CT2 other than the contact surface. In one embodiment, the second contact plug CT2 as described above functions as a dummy plug. In some embodiments, the second contact plug CT2 can be referred to as a dummy contact plug.

[0070] Global lines such as the global word line GWL and the bit line BL are covered by a fifth insulating layer IL5, and the fifth insulating layer IL5 is covered by a sixth insulating layer IL6. The block select line BSEL is disposed in the sixth insulating layer IL6. The block select line BSEL is electrically coupled to the gate electrode GE2 via a third contact plug CT3. One block select line BSEL is coupled to the third contact plug CT3 and controls the gate electrode GE2 of the pass transistor PT.

[0071] Each of the third contact plugs CT3 extends from the corresponding gate electrode GE2 to the block select line BSEL and penetrates the dummy pattern IL2’, the third insulating layer IL3, the fourth insulating layer IL4, and the fifth insulating layer IL5.

[0072] The peripheral circuit structure PS includes a plurality of transistors TR. In one embodiment, the plurality of transistors TR can include Figure 1 The transistors of the page buffer 37 shown in FIG. 1. Each transistor TR is disposed in an active region of the semiconductor substrate SUB separated by an insulating layer ISO. Each of the transistors TR includes junctions JN11 and JN12, a gate insulating layer GIl, and a gate electrode GE1. The junctions JN11 and JN12 are disposed in the active region of the semiconductor substrate SUB spaced apart from each other. The gate insulating layer GIl and the gate electrode GE1 are stacked over the active region between the junctions JN11 and JN12.

[0073] The plurality of transistors TR is covered by a peripheral insulating structure PIL over the semiconductor substrate SUB. A plurality of interconnects IC is disposed in the peripheral insulating structure PIL. The plurality of interconnects IC includes at least one of a plurality of conductive lines and a plurality of conductive contacts for electrical connections.

[0074] Reference Figure 4A In one embodiment, the peripheral circuit structure PS can be disposed closer to the source layer SR than the bit line BL. The source layer SR can be disposed between the peripheral insulating structure PIL and the gate stack structure GST.

[0075] Reference Figure 4BIn one embodiment, the peripheral circuit structure PS can be disposed closer to the bit line BL than the source layer SR. The bit line BL can be disposed between the peripheral insulating structure PIL and the gate stack structure GST. The sixth insulating layer IL6 and the block select line BSEL are disposed between the bit line BL and the peripheral insulating structure PIL. The seventh insulating layer IL7 is interposed between each of the sixth insulating layer IL6 and the block select line BSEL and the peripheral insulating structure PIL.

[0076] A plurality of cell side junction patterns CBP are disposed in the seventh insulating layer IL7. A plurality of peripheral circuit side junction patterns PBP corresponding to the plurality of cell side junction patterns CBP are disposed in the peripheral insulating structure PIL. The plurality of cell side junction patterns CBP are joined to the plurality of peripheral circuit side junction patterns PBP.

[0077] A portion of the plurality of cell side junction patterns CBP can be electrically coupled to the bit line BL via at least one bit line connection structure. In one embodiment, a first cell side junction pattern among the plurality of cell side junction patterns CBP can be electrically coupled to the bit line BL via a first bit line connection structure BC1 and a second bit line connection structure BC2. The first bit line connection structure BC1 penetrates the fifth insulating layer IL5, and the second bit line connection structure BC2 penetrates the sixth insulating layer IL6.

[0078] A portion of the plurality of peripheral circuit side junction patterns PBP can be electrically coupled to a transistor of the page buffer via an interconnection IC. The peripheral circuit side junction pattern electrically coupled to the transistor of the page buffer can be joined to the first cell side junction pattern. Accordingly, the bit line BL can be electrically coupled to the page buffer via the first cell side junction pattern and the peripheral circuit side junction pattern.

[0079] Reference Figure 4A and Figure 4B In one embodiment, since the transfer transistor PT is disposed between the peripheral circuit structure PS and the gate stack structure GST, an area of the semiconductor substrate SUB allocated to the transfer transistor PT can be reduced. In one embodiment, the active pattern ACT of each of the transfer transistors PT is directly coupled to the corresponding conductive layer CDL, thereby reducing a bias loss between the transfer transistor PT and the conductive layer CDL. Accordingly, in one embodiment, an operating characteristic of the semiconductor memory device, such as a programming efficiency, can be improved.

[0080] Figure 5 is a cross-sectional view illustrating a transfer transistor PT according to an embodiment of the disclosure. Figure 5 is a cross-sectional view illustrating a transfer transistor PT according to an embodiment of the disclosure. Figure 4A or Figure 4B is an enlarged cross-sectional view of a first active pattern ACT1 of a first transfer transistor PT1 and surrounding components among the transfer transistors PT illustrated in FIG. 1A.

[0081] Referring to Figure 5 , Figure 4A or Figure 4B The second insulating layer IL2 shown in Figure 4A or Figure 4B has a stepped structure over the extension area EAR of the first insulating layer IL1 shown in

[0082] Figure 4A or Figure 4B The conductive layer CDL shown in

[0083] The first conductive layer CDL1 includes an area overlapping the first active pattern ACT1, and protrudes further than the first active pattern ACT1 in a horizontal direction. In one embodiment, the first conductive layer CDL1 protrudes further than the first active pattern ACT1 in the first direction DR1. In one embodiment, the horizontal direction is the first direction DR1.

[0084] The first intermediate layer IL2A is disposed between the first conductive layer CDL1 and the second conductive layer CDL2. The first active pattern ACT1 includes a first surface SU1 and a second surface SU2 opposite each other. The first surface SU1 faces Figure 4A or Figure 4B The first insulating layer IL1 shown in. The first intermediate layer IL2A extends along the first surface SU1 of the first active pattern ACT1. The first intermediate layer IL2A protrudes further than the first active pattern ACT1 in a horizontal direction to cover the first conductive layer CDL1. In one embodiment, the first intermediate layer IL2A protrudes further than the first active pattern ACT1 in the first direction DR1.

[0085] The first active pattern ACT1 extends from the second conductive layer CDL2, and is disposed between the first intermediate layer IL2A and the second intermediate layer IL2B adjacent in the third direction DR3. The first junction JN21 of the first active pattern ACT1 is spaced apart from the second conductive layer CDL2 with a channel region CHR interposed therebetween. The second junction JN22 of the first active pattern ACT1 contacts the second conductive layer CDL2.

[0086] The second intermediate layer IL2B extends along the second surface SU2 of the first active pattern ACT1. The second intermediate layer IL2B includes an interlayer insulating region IIA and a gate insulating region GI2. The interlayer insulating region IIA is interposed between the second conductive layer CDL2 and the third conductive layer CDL3. The gate insulating region GI2 extends from the interlayer insulating region IIA to cover the second surface SU2 of the first active pattern ACT1. The gate insulating region GI2 is interposed between the first gate electrode 1GE2 and the first active pattern ACT1.

[0087] The third conductive layer CDL3 and the third intermediate layer IL2C open the first active pattern ACT1. The third conductive layer CDL3 is disposed between the second intermediate layer IL2B and the third intermediate layer IL2C.

[0088] The first gate electrode 1GE2 is spaced apart from the third conductor layer CDL3 at the same level as the third conductive layer CDL3. The first gate electrode 1GE2 can be disposed between the second intermediate layer IL2B and a dummy pattern IL2C'. The dummy pattern IL2C' is disposed at the same level as the third intermediate layer IL2C and includes the same material as the third intermediate layer IL2C.

[0089] The first gate electrode 1GE2 is disposed between a first contact plug CT1 coupled with the first junction JN21 and a second contact plug CT2 coupled with the second junction JN22. A third contact plug CT3 coupled with the first gate electrode 1GE2 is disposed between the first contact plug CT1 and the second contact plug CT2. The second contact plug CT2 provided as a dummy plug extends in the third direction DR3 between the third conductive layer CDL3 and the first gate electrode 1GE2.

[0090] Hereinafter, a method of manufacturing a semiconductor memory device according to an embodiment of the disclosure will be described, which mainly focuses on a transfer transistor and a memory cell array of the semiconductor memory device.

[0091] Figure 6A to Figure 6D 、 Figure 7A to Figure 7C 、 Figure 8A to Figure 8C and Figure 9A to Figure 9D A method of manufacturing a semiconductor memory device according to various embodiments of the disclosure is illustrated.

[0092] Figure 6A to Figure 6D is a perspective view illustrating a process of forming a preliminary gate stack structure 100G, a preliminary gate electrode PG, and an active opening 125.

[0093] Referring to Figure 6A A first insulating layer 101 is formed on a lower structure (not shown). Although Figure 6A not shown in FIG. 1A, in one embodiment, the lower structure can includeFigure 4A a peripheral circuit structure PS and a preliminary source layer including Figure 4A a first doped semiconductor layer L1 as shown in Figure 4A a third doped semiconductor layer L3 as shown in, and a sacrificial structure between the first doped semiconductor layer L1 and the third doped semiconductor layer L3. In a subsequent process, the sacrificial structure of the preliminary source layer can be replaced with Figure 4A a second doped semiconductor layer L2 as shown in. In another embodiment, the lower structure can be a sacrificial substrate, such as a silicon wafer. In a subsequent process, the sacrificial substrate can be replaced with Figure 4B a source layer SR as shown in.

[0094] The first insulating layer 101 includes a cell area CAR and an extension area EAR extending from the cell area CAR. The first insulating layer 101 has a plate structure extending in a horizontal direction. Figure 6A The first direction DR1 and the second direction DR2 as shown in are directions facing each other in a plane with axes crossing each other. The plate structure of the first insulating layer 101 extends in the first direction DR1 and the second direction DR2.

[0095] A plurality of sub-structures SS1 to SSk (k is a natural number equal to or greater than 2) is disposed above the first insulating layer 101. The plurality of sub-structures SS1 to SSk is stacked in a vertical direction. Figure 6A The third direction DR3 as shown in is a vertical direction. In one embodiment, the first direction DR1, the second direction DR2, and the third direction DR3 can correspond to an X-axis direction, a Y-axis direction, and a Z-axis direction, respectively.

[0096] The plurality of sub-structures SS1 to SSk includes sacrificial layers 103 and second insulating layers 105 alternately stacked in the third direction DR3. The sacrificial layers 103 and the second insulating layers 105 form a plurality of pairs, and a stacked structure of the sacrificial layer 103 and the second insulating layer 105 of each pair forms a corresponding sub-structure.

[0097] The sacrificial layer 103 includes a material having etch selectivity with respect to the first insulating layer 101 and the second insulating layer 105. In one embodiment, the first insulating layer 101 and the second insulating layer 105 can include an insulating material, such as a silicon oxide layer, a silicon oxynitride layer, or the like. The sacrificial layer 103 can include a sacrificial insulating material, such as a silicon nitride layer, or the like.

[0098] Subsequently, a channel hole 110 is formed that penetrates the cell area CAR of the first insulating layer 101 and the plurality of sub-structures SS1 to SSk above the cell area CAR. Subsequently, a memory layer 111 is formed along a side wall of the channel hole 110. Further, a channel structure 113 is formed in the channel hole 110 that is opened through the memory layer 111.

[0099] The plurality of sub-structures SS1 to SSk are etched to form a preliminary staircase structure over the extended area EAR of the first insulating layer 101. The preliminary staircase structure includes a plurality of first pad portions 100P1 of the plurality of sub-structures SS1 to SSk. Each of the first pad portions 100P1 has a structure of a stack of a corresponding sacrificial layer 103 and a corresponding second insulating layer 105.

[0100] Reference is made to Figure 6B The plurality of sub-structures SS1 to SSk are etched to form a staircase structure and preliminary gate electrodes PG over the extended area EAR of the first insulating layer 101.

[0101] The staircase structure includes a plurality of second pad portions 100P2 of the plurality of sub-structures SS1 to SSk. Each of the plurality of second pad portions 100P2 is formed by etching a sub-structure under each of the plurality of first pad portions 100P1 shown in Figure 6A Figure 6A The plurality of second pad portions 100P2 respectively correspond to the plurality of first pad portions 100P1 shown in

[0102] Each of the preliminary gate electrodes PG is disposed over a portion of a corresponding second pad 100P2 among the plurality of second pads 100P2. The preliminary gate electrodes PG are formed by etching a portion of the plurality of first pad portions 100P1 shown in Figure 6A In other words, the etched first pad portions 100P1 form each of the preliminary gate electrodes PG. The second pad portions 100P2 disposed under each of the preliminary gate electrodes PG include areas that are open on both sides of each of the preliminary gate electrodes PG.

[0103] A portion of the plurality of first pad portions 100P1 can remain to form a first end portion EG1 of a corresponding sub-structure. The second pad portions 100P2 can not be open under the first pad portions 100P1 that form the first end portion EG1 and can be covered by the first pad portions 100P1.

[0104] Reference is made to Figure 6C A third insulating layer 121 is formed over the plurality of sub-structures SS1 to SSk to cover the preliminary gate electrodes PG and the plurality of second pad portions 100P2.

[0105] Subsequently, first openings 123A and second openings 123B that penetrate the third insulating layer 121 are formed. The first openings 123A and the second openings 123B overlap some areas of a corresponding second pad portion 100P2 and expose the sacrificial layer 103 of the corresponding second pad portion 100P2.​

[0106] Reference is made to Figure 6D The sacrificial layer 103 exposed through the first opening 123A and the second opening 123B is etched to form the active opening 125. The second pad portion 100P2 under the first pad portion 100P1 forming the first end portion EG1 is retained to form a second end portion EG2 of a corresponding substructure.

[0107] The sidewall of the first end portion EG1, the sidewall of the second end portion EG2, and the sidewall of the active opening 125 form part of the sidewall of the preliminary gate stack structure 100G. The preliminary gate stack structure 100G comprises the first insulating layer 101 (comprising the cell region CAR and the extension region EAR), and the sacrificial layer 103 and the second insulating layer 105 alternately stacked on the first insulating layer 101 in the third direction DR3. The sacrificial layer 103 and the second insulating layer 105 of the preliminary gate stack structure 100G are disposed on the cell region CAR of the first insulating layer 101, and extend over the extension region EAR of the first insulating layer 101. Part of the sacrificial layer 103 and the second insulating layer 105 form the first end portion EG1 and the second end portion EG2.

[0108] Figure 7A to Figure 7C Each shows a cross-section of the first insulating layer 101, the sacrificial layer 103 and the second insulating layer 105 of the preliminary gate stack structure 100G, the sacrificial layer 103 and the second insulating layer 105 of the preliminary gate electrode PG, and the third insulating layer 121 taken along the line I-I’ of Figure 6D Figure 7A is a cross-sectional view of the structure shown in Figure 6D Figure 7B and Figure 7C are cross-sectional views illustrating processes performed after the processes shown in Figure 6D

[0109] Reference is made to Figure 6D and Figure 7A The first opening 123A and the second opening 123B penetrate the third insulating layer 121 and the second insulating layer 105 of the corresponding second pad portion 100P2 on both sides of the corresponding preliminary gate electrode PG.

[0110] The active opening 125 overlaps the preliminary gate electrode PG between the first opening 123A and the second opening 123B. The first opening 123A and the second opening 123B are coupled through the active opening 125. One side of the active opening 125 is defined along the sacrificial layer 103 of the preliminary gate stack structure 100G in which the sacrificial layer 103 disposed at the same level as the active opening 125. The other side of the active opening 125 is defined along the third insulating layer 121.

[0111] Reference is made to Figure 7B ,​​​Figure 7A The active opening 125 shown in FIG. 1A is filled with an active pattern 133 through the first opening 123A and the second opening 123B. The active pattern 133 includes a doped semiconductor layer. In one embodiment, the active pattern 133 can include a P-type doped semiconductor layer, such as a P-type doped silicon layer.

[0112] Reference Figure 7C After the sacrificial layer 103 of the second pad portion 100P2 is replaced with the active pattern 133, conductive impurities can be doped into both ends of the active pattern 133 through the first opening 123A and the second opening 123B. Accordingly, a first junction 133J1 and a second junction 133J2 are respectively formed at both ends of the active pattern 133. The first junction 133J1 is spaced apart from the preliminary gate stack structure 100G, and the second junction 133J2 is in contact with the preliminary gate stack structure 100G.

[0113] A portion of the active pattern 133 between the first junction 133J1 and the second junction 133J2 can function as a channel region 133CH. In an embodiment in which the channel region 133CH includes a P-type doped semiconductor layer, the first junction 133J1 and the second junction 133J2 include N-type impurities.

[0114] As described above, the first junction 133J1 and the second junction 133J2 can be formed before the sacrificial layer 103 of the preliminary gate stack structure 100G and the sacrificial layer 103 of the preliminary gate electrode PG are replaced with conductive materials. However, embodiments of the present disclosure are not limited thereto. In another embodiment, the first junction 133J1 and the second junction 133J2 can be formed after the process described below with reference to Figure 9A

[0115] Figure 8A to Figure 8C is a perspective view illustrating a process of forming the conductive layer 153 and the gate electrode 153G.

[0116] Reference Figure 8A , Figure 7C The first opening 123A and the second opening 123B shown in FIG. 1C are respectively filled with a first sacrificial pillar 141A and a second sacrificial pillar 141B. The first sacrificial pillar 141A and the second sacrificial pillar 141B include a material having etch selectivity with respect to the first insulating layer 101, the second insulating layer 105, and the third insulating layer 121. In one embodiment, the first sacrificial pillar 141A and the second sacrificial pillar 141B can include a silicon nitride layer, an amorphous carbon layer, or the like.

[0117] Reference Figure 8B ​The slits 143 are formed to penetrate the third insulating layer 121, the preliminary gate stack structure 100G, and the preliminary gate electrode PG. The sidewalls of the preliminary gate stack structure 100G and the preliminary gate electrode PG are exposed by the slits 143. The slits 143 extend in a direction crossing the preliminary gate electrode PG and penetrate the active pattern 133.

[0118] refer to Figure 8C , after removing through slit 143 Figure 8B After removing the sacrificial layer of the preliminary gate stack structure 100G and the sacrificial layer of the preliminary gate electrode PG shown in FIG, the area where the sacrificial layer was removed is filled with a conductive material. The conductive material replacing each of the sacrificial layers of the preliminary gate stack structure 100G and the preliminary gate electrode PG is divided into a conductive layer 153 and a gate electrode 153G.

[0119] Conductive layer 153 replacement Figure 8B The sacrificial layer 103 of the preliminary gate stack structure 100G shown in FIG is alternately arranged with the second insulating layer 105 in the third direction DR3 over the first insulating layer 101. The conductive layer 153 and the second insulating layer 105 are arranged over the cell area CAR of the first insulating layer 101 and extend over the extension area EAR of the first insulating layer 101. The first insulating layer 101, the conductive layer 153, and the second insulating layer 105 form the gate stack structure 150. Each of the conductive layers 153 contacts the active pattern 133 disposed at the same level. Each of the conductive layers 153 contacts the second junction 133J2 of the active pattern 133 and is spaced apart from the first junction 133J1 of the active pattern 133, with the channel region 133CH and the second junction 133J2 of the active pattern 133 interposed therebetween.

[0120] Gate electrode 153G replacement Figure 8B The sacrificial layers 103 of the preliminary gate electrodes PG shown in FIG, and overlap with the active patterns 133, respectively.

[0121] According to one embodiment of the present invention, by replacing Figure 6A The conductive layer 153, the gate electrode 153G, and the active pattern 133 are formed using a sacrificial layer included in the stacked structure of the substructures SS1 to SSk shown in FIG. Therefore, the conductive layer 153, the gate electrode 153G, and the active pattern 133 may be self-aligned.

[0122] Figure 9A to Figure 9D Each shows the Figure 8C 1 and 2. A cross section of the gate stack structure 150, the gate electrode 153G, the active pattern 133, and the third insulating layer 121 taken along line II'. Figure 9A to Figure 9D It is shown in the figure Figure 8CA cross-sectional view of a process performed subsequent to the process shown.

[0123] refer to Figure 9A , remove Figure 8C The first sacrificial pillar 141A and the second sacrificial pillar 141B are shown. Therefore, the active pattern 133 is exposed through the first opening 123A and the second opening 123B. In one embodiment, when the first junction 133J1 and the second junction 133J2 are removed Figure 8C When the first sacrificial pillar 141A and the second sacrificial pillar 141B are previously formed, the first junction 133J1 and the second junction 133J2 can be exposed through the first opening 123A and the second opening 123B. In another embodiment, the first junction 133J1 and the second junction 133J2 can be exposed by removing Figure 8C The first and second sacrificial pillars 141A and 141B are shown and then conductive impurities are doped into the active pattern 133 through the first and second openings 123A and 123B.

[0124] The first junction 133J1 is exposed through the first opening 123A, and the second junction 133J2 is exposed through the second opening 123B.

[0125] refer to Figure 9B , by filling it with conductive material Figure 9A The first opening 123A and the second opening 123B shown in FIG. Figure 9A A first contact plug 161A and a second contact plug 161B are formed in the first opening 123A and the second opening 123B shown in FIG. The first contact plug 161A contacts the first junction 133J1, and the second contact plug 161B contacts the second junction 133J2.

[0126] refer to Figure 9C A fourth insulating layer 163 is formed over the third insulating layer 121. Subsequently, a global line 165 is formed in the fourth insulating layer 163. The global line 165 is coupled to the first contact plug 161A. The second contact plug 161B is covered by the fourth insulating layer 163 and can be insulated from external signal lines such as the global line 165 by the fourth insulating layer 163.

[0127] refer to Figure 9D , a fifth insulating layer 171 is formed over the fourth insulating layer 163. Subsequently, a third contact plug 173 is formed to penetrate the third insulating layer 121, the fourth insulating layer 163, and the fifth insulating layer 171.

[0128] The third contact plug 173 extends to contact the gate electrode 153G. Then, subsequent processes such as a process of forming a block selection line 175 coupled to the third contact plug 173 may be performed.

[0129] Figure 10 is a block diagram illustrating an electronic system 1000 according to an embodiment of the disclosure.

[0130] Referring to Figure 10 , the electronic system 1000 can be a computing system, a medical device, a communication device, a wearable device, a memory system, etc. The electronic system 1000 can include a host 1100 and a storage device 1200.

[0131] The host 1100 can store data in the storage device 1200 or can read data stored in the storage device 1200 based on an interface. Examples of the interface can include at least one of a double data rate (DDR), a universal serial bus (USB), a multimedia card (MMC), an embedded MMC (eMMC), a peripheral component interconnect (PCI), a high-speed PCI (PCI-E), an advanced technology attachment (ATA), a serial ATA (SATA), a parallel ATA (PATA), a small computer system interface (SCSI), an enhanced small disk interface (ESDI), an integrated drive electronics (IDE), FireWire, a universal flash memory (UFS), and a non-volatile memory express (NVMe) interface.

[0132] The storage device 1200 can include a memory controller 1210 and a semiconductor memory device 1220. In one embodiment, the storage device 1200 can be a storage medium such as a solid state drive (SSD) or a universal serial bus (USB) memory.

[0133] The memory controller 1210 can store data in or read data stored in the semiconductor memory device 1220 in response to a control of the host 1100.

[0134] The semiconductor memory device 1220 can include one memory chip or a plurality of memory chips. The semiconductor memory device 1220 can store data or output stored data in response to a control of the memory controller 1210.

[0135] The semiconductor memory device 1220 can be a non-volatile memory device. As described above with reference to Figure 4A or Figure 4B , in one embodiment, the semiconductor memory device 1220 can include a first insulating layer, a channel structure penetrating the first insulating layer and extending in a vertical direction, a memory layer extending along a sidewall of the channel structure, a conductive layer disposed to be spaced apart from each other in the vertical direction along the sidewall of the memory layer above the first insulating layer, an active pattern coupled with a corresponding one of the conductive layers, and a gate electrode disposed above the active pattern.

[0136] According to one embodiment of the present application, an active pattern and a gate electrode disposed above the active pattern can function as a pass transistor, and the active pattern can be directly coupled to a conductive layer of a gate stack structure including alternately stacked insulating layers and conductive layers. Accordingly, in one embodiment, a connection structure between the conductive layer and the pass transistor can be simplified, and a loss of bias transferred from the pass transistor to the conductive layer can be reduced, thereby improving operational reliability of a semiconductor memory device.

[0137] According to one embodiment of the present application, a region of an active pattern and a gate electrode provided with a pass transistor is provided by etching a stacked structure of a substructure, thereby improving arrangement efficiency of the pass transistor.

Claims

1. A semiconductor memory device, comprising: a first insulating layer including a cell region and an extension region, the extension region extending from the cell region; a channel structure penetrating the first insulating layer in the cell region, the channel structure extending in a vertical direction; a memory layer extending along a sidewall of the channel structure; a conductive layer disposed to be spaced apart in the vertical direction along a sidewall of the memory layer over the first insulating layer; a second insulating layer disposed to be alternated with the conductive layer in the vertical direction and extending over the extension region of the first insulating layer; an active pattern disposed between adjacent second insulating layers in the vertical direction in the second insulating layer and coupled to a corresponding conductive layer among the conductive layers; and a gate electrode disposed over the active pattern.

2. The semiconductor memory device of claim 1, wherein the adjacent second insulating layers in the vertical direction include a first intermediate layer and a second intermediate layer, the first intermediate layer and the second intermediate layer forming a stepped structure over the extension region of the first insulating layer, wherein the first intermediate layer extends along a first surface of the active pattern, the first surface facing the first insulating layer, and wherein the second intermediate layer extends along a second surface of the active pattern opposite the first surface, the second intermediate layer interposed between the active pattern and the gate electrode.

3. The semiconductor memory device of claim 1, further comprising a first junction and a second junction included in the active pattern, the first junction spaced apart from the second junction, wherein the gate electrode is disposed over a region between the first junction and the second junction of the active pattern.

4. The semiconductor memory device of claim 3, wherein the active pattern includes a P-type doped semiconductor layer, and wherein each of the first junction and the second junction includes an N-type impurity.

5. The semiconductor memory device of claim 3, wherein the first junction is spaced apart from the corresponding conductive layer, and wherein the second junction is in contact with the corresponding conductive layer.

6. The semiconductor memory device of claim 5, further comprising: a contact plug extending in the vertical direction from the first junction; and a global line coupled to the contact plug.

7. The semiconductor memory device of claim 5, further comprising a dummy contact plug extending in the vertical direction from the second junction.

8. The semiconductor memory device of claim 7, wherein the conductive layer includes a gate electrode level conductive layer disposed at a same level as the gate electrode, and wherein the dummy contact plug is disposed between the gate electrode level conductive layer and the gate electrode.

9. The semiconductor memory device of claim 1, further comprising: a contact plug extending in the vertical direction from the gate electrode; and a block selection line coupled to the contact plug.

10. A semiconductor memory device, comprising: a first insulating layer including a cell region and an extension region, the extension region extending from the cell region; ​ ​ ​ a channel structure penetrating the first insulating layer in the cell region, the channel structure extending in a vertical direction; a memory layer extending along a sidewall of the channel structure; a conductive layer and a second insulating layer alternately stacked over the first insulating layer and along a sidewall of the memory layer; an active pattern respectively extending from the conductive layer and disposed in a stepped structure over the extended region of the first insulating layer; and a gate electrode disposed over the active pattern.

11. The semiconductor memory device according to claim 10, wherein each of the active patterns includes a channel region overlapping a corresponding one of the gate electrodes and a first junction and a second junction respectively disposed on both sides of the channel region, wherein the first junction is spaced apart from a corresponding one of the conductive layers, and wherein the second junction is disposed between the corresponding conductive layer and the channel region, the second junction being in contact with the corresponding conductive layer.

12. The semiconductor memory device according to claim 11, wherein each of the active patterns includes a P-type doped semiconductor layer, and wherein each of the first and second junctions includes an N-type impurity.

13. The semiconductor memory device according to claim 10, wherein the conductive layer includes a first conductive layer, a second conductive layer, and a third conductive layer sequentially disposed in the vertical direction, wherein the second insulating layer includes a first intermediate layer between the first conductive layer and the second conductive layer and a second intermediate layer between the second conductive layer and the third conductive layer, wherein the active pattern includes a first active pattern extending from the second conductive layer, and wherein the gate electrode includes a first gate electrode disposed over the first active pattern.

14. The semiconductor memory device according to claim 13, wherein the first conductive layer extends to be disposed over the first active pattern, wherein the first intermediate layer extends between the first conductive layer and the first active pattern, wherein the second intermediate layer includes an interlayer insulating region between the second conductive layer and the third conductive layer and a gate insulating region extending from the interlayer insulating region to cover the first active pattern, and wherein the gate insulating region of the second intermediate layer is interposed between the first gate electrode and the first active pattern.

15. The semiconductor memory device according to claim 13, wherein the first gate electrode is disposed at the same level as the third conductive layer.

16. The semiconductor memory device according to claim 10, further comprising a first contact plug and a second contact plug respectively coupled to each of the active patterns on both sides of each of the gate electrodes, wherein each of the active patterns includes: a first junction coupled to the first contact plug; and a second junction coupled to a corresponding one of the conductive layers and the second contact plug, the second junction being spaced apart from the first junction. ​ ​ 17. The semiconductor memory device of claim 16, further comprising: a global line coupled to the first contact plug; and at least one insulating layer surrounding the second contact plug, wherein the second contact plug includes a contact surface that contacts the second junction, and wherein the at least one insulating layer surrounds surfaces of the second contact plug other than the contact surface of the second contact plug that contacts the second junction.

18. The semiconductor memory device of claim 10, further comprising: contact plugs respectively extending from the gate electrodes in the vertical direction; and a block select line coupled to the contact plugs.

19. A method of manufacturing a semiconductor memory device, the method comprising: forming a first insulating layer including a cell region and an extension region, the extension region extending from the cell region; stacking substructures over the first insulating layer, wherein each of the substructures is a stacked structure of a sacrificial layer and a second insulating layer; forming a staircase structure and a preliminary gate electrode by etching the substructures, wherein the staircase structure is disposed over the extension region of the first insulating layer, and the preliminary gate electrode is disposed over the staircase structure and includes a portion of the sacrificial layer; forming a third insulating layer over the substructures to cover the staircase structure and the preliminary gate electrode; forming first and second openings that overlap the staircase structure on both sides of the preliminary gate electrode and penetrate the third insulating layer, respectively; replacing a portion of the sacrificial layer of the staircase structure with an active pattern through the first and second openings; replacing the sacrificial layer with a conductive material; and forming first and second contact plugs in the first and second openings, respectively.

20. The method of claim 19, wherein forming the staircase structure and the preliminary gate electrode comprises: forming a preliminary staircase structure having first pad portions of the substructures by etching the substructures; forming the staircase structure having second pad portions of the substructures by etching the substructures under the first pad portions; and forming the preliminary gate electrode by etching at least one of the first pad portions, wherein the preliminary gate electrode includes the etched first pad portion and is disposed over a corresponding one of the second pad portions.

21. The method of claim 19, wherein the conductive material is divided into gate electrodes that replace the portion of the sacrificial layer of the preliminary gate electrode and conductive layers that are alternately disposed with the second insulating layers over the cell region of the first insulating layer, and wherein the conductive layers extend to contact the active pattern at a level at which the active pattern is disposed.

22. The method of claim 21, further comprising forming first and second junctions at both ends of the active pattern, respectively, by doping a conductive impurity through the first and second openings, wherein the first junction is spaced apart from the conductive layer, and the second junction is in contact with the conductive layer at the level at which the active pattern is disposed.

23. The method of claim 22, wherein the active pattern comprises a P-type doped semiconductor layer, and wherein each of the first and second junctions comprises an N-type impurity.

24. The method of claim 22, wherein the first contact plug is in contact with the first junction, and wherein the second contact plug is in contact with the second junction.

25. The method of claim 24, further comprising: forming at least one insulating layer over the third insulating layer to cover the first and second contact plugs; and forming a global line that penetrates the at least one insulating layer to couple to the first contact plug.

26. The method of claim 19, wherein replacing the sacrificial layer with the conductive material comprises: filling each of the first and second openings with a sacrificial post; forming a slit that penetrates the third insulating layer and the substructure and extends in a direction that intersects the preliminary gate electrode; removing the sacrificial layer through the slit; and filling the area where the sacrificial layer was removed with the conductive material, and wherein the method further comprises removing the sacrificial post prior to forming the first and second contact plugs.

27. The method of claim 19, further comprising: forming a channel hole in the cell region that penetrates the first insulating layer, the channel hole extending to penetrate the substructure; forming a memory layer on sidewalls of the channel hole; and forming a channel structure in the channel hole that opens through the memory layer.

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