Embedded flash memory and manufacturing method thereof
By optimizing the embedded flash memory structure, shortening the programming path, and enhancing the erase gate contact area and voltage stability, the problems of slow programming speed and unstable erasure in embedded flash memory have been solved, achieving higher programming speed and erase efficiency.
Patent Information
- Application Number
- CN202510996330.9
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-07-18
- Publication Date
- 2025-10-24
AI Technical Summary
Existing embedded flash memory has slow programming speed, unstable erasing process, insufficient erase gate driving capability, and easy fluctuation of erase voltage.
An embedded flash memory structure is designed by setting the width of the tunnel oxide layer and the floating gate layer to be greater than the width of the gate dielectric layer and the control gate layer, so that they protrude on both sides and are recessed in the word line gate, thereby shortening the programming path; a groove structure is set on the top of the erase gate to increase the contact area of the metal layer; and a thick insulating layer is covered on the source region to improve the stability of the erase voltage.
It improves the programming speed and erase operation stability of embedded flash memory, enhances the driving effect of the erase gate, reduces circuit design difficulty, and improves process compatibility and reliability.
Smart Images
Figure CN120835557A_ABST
Abstract
Description
TECHNICAL FIELD
[0001] The present application belongs to the field of semiconductor integrated circuit design and manufacturing, and particularly relates to an embedded flash memory and a manufacturing method thereof. BACKGROUND
[0002] In recent years, with the rapid development of the market of intelligent electronic products, various microcontrollers (MCU) and system on chip (SoC) chips have been used in various aspects of daily life such as automotive electronics, industrial control and medical products. High-performance MCU or SoC products cannot be separated from the support of high-performance embedded flash (eflash) cores. Whether from the chip area, system performance and power consumption, or from the manufacturing yield and design cycle, the leading role of embedded memory in SoC design is increasing. Embedded flash is to combine existing flash memory with existing logic modules in terms of physics or electricity, providing more performance.
[0003] Embedded flash (eFlash) as the core storage unit of system on chip (SoC) has a surge in demand in the fields of Internet of Things, automotive electronics and artificial intelligence. However, the existing embedded flash (eFlash) has the following problems:
[0004] 1) Due to the limitation of channel width, the hot electron injection path is long, which greatly limits the improvement of the programming speed of the embedded flash.
[0005] 2) The contact area of the planar erase gate is small, and the driving ability is easy to be insufficient, which easily leads to unstable erase process and fluctuation of the voltage actually applied to the erase gate.
[0006] It should be noted that the above introduction to the technical background is only for the convenience of clearly and completely describing the technical scheme of the present application, and for the convenience of understanding by those skilled in the art. The above technical scheme cannot be considered as known to those skilled in the art only because it is described in the background section of the present application. SUMMARY
[0007] In view of the above-mentioned shortcomings of the prior art, the purpose of the present application is to provide an embedded flash memory and a manufacturing method thereof, which is used to solve the problem of slow programming speed of the embedded flash memory in the prior art.
[0008] To achieve the above object and other related objects, the present application provides an embedded flash memory, which comprises: a semiconductor substrate; a gate stack layer formed on the semiconductor substrate, the gate stack layer comprising a tunneling oxide layer, a floating gate layer, a gate dielectric layer and a control gate layer stacked in sequence, the width of the tunneling oxide layer and the floating gate layer being greater than the width of the gate dielectric layer and the control gate layer, so that the tunneling oxide layer and the floating gate layer protrude from both sides of the gate dielectric layer and the control gate layer; an isolation side wall and a tunneling side wall covering the first side wall and the second side wall on both sides of the tunneling oxide layer, the floating gate layer, the gate dielectric layer and the control gate layer, the isolation side wall and the tunneling side wall having a corner at the top corner of the floating gate layer; a word line gate arranged on the side of the isolation side wall, the word line gate being recessed inward by a distance along the protruding tunneling oxide layer and floating gate layer; a drain region arranged in the semiconductor substrate and located on the side of the word line gate, the region between the drain region and the tunneling oxide layer and the floating gate layer being a channel region, the width of the channel region being reduced by controlling the distance of the word line gate recessed inward; a source region arranged in the semiconductor substrate on the side of the tunneling side wall, the source region being covered with an insulating layer; and an erase gate arranged on the side of the tunneling side wall and located on the insulating layer to be isolated from the source region.
[0009] Optionally, the material of the erase gate is polysilicon, a groove structure is formed on the top of the erase gate, and a metal layer is filled in the groove structure to form an ohmic contact with the polysilicon in the groove structure.
[0010] Optionally, the depth of the groove structure is 10% to 50% of the height of the erase gate.
[0011] Optionally, the groove structure comprises one of a rectangular groove, a V-shaped groove and a U-shaped groove.
[0012] Optionally, the width of the tunneling oxide layer and the floating gate layer protruding from any side of the gate dielectric layer and the control gate layer is 5 nm to 15 nm.
[0013] Optionally, the width of the tunneling oxide layer and the floating gate layer is 100 nm to 130 nm, and the width of the gate dielectric layer and the control gate layer is 80 nm to 110 nm.
[0014] Optionally, the thickness of the tunneling oxide layer is 90 angstroms to 120 angstroms, the thickness of the floating gate layer is 250 angstroms to 450 angstroms, the gate dielectric layer includes a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer, the thickness of the gate dielectric layer is 160 angstroms to 220 angstroms, the thickness of the control gate layer is 500 angstroms to 700 angstroms, and the gate stack layer also includes a hard mask arranged on the control gate layer, and the thickness of the hard mask is 500 angstroms to 1100 angstroms.
[0015] Optionally, the thickness of the isolation sidewall is 160 angstroms to 220 angstroms, and the thickness of the tunnel sidewall is 90 angstroms to 110 angstroms.
[0016] Optionally, the cross-section of the insulating layer on the source region is elliptical, and both ends of the ellipse are connected to the tunnel sidewall, wherein the thickness of the middle portion of the insulating layer is 380 angstroms to 450 angstroms, and the thickness at both ends is 150 angstroms to 190 angstroms.
[0017] The present invention also provides a method for manufacturing an embedded flash memory, the manufacturing method comprising the steps of: providing a semiconductor substrate; forming a gate stack layer on the semiconductor substrate, the gate stack layer comprising a tunneling oxide layer, a floating gate layer, a gate dielectric layer and a control gate layer stacked in sequence, the width of the tunneling oxide layer and the floating gate layer being greater than the width of the gate dielectric layer and the control gate layer, so that the tunneling oxide layer and the floating gate layer protrude from both sides of the gate dielectric layer and the control gate layer; forming an isolation sidewall and a tunneling sidewall, the isolation sidewall and the tunneling sidewall respectively covering a first sidewall and a second sidewall on both sides of the tunneling oxide layer, the floating gate layer, the gate dielectric layer and the control gate layer, the isolation sidewall and the tunneling sidewall having a corner at the top corner of the floating gate layer ; A source region is formed in the semiconductor substrate, the source region is arranged in the semiconductor substrate on the side of the tunnel side wall, and an insulating layer is covered on the source region; a word line gate is formed on the side of the isolation side wall, the word line gate protrudes along the tunneling oxide layer and the floating gate layer and is recessed a distance toward the inside of the word line gate; an erase gate is formed, the erase gate is arranged on the side of the tunneling side wall and is located on the insulating layer to be isolated from the source region; a drain region is formed in the semiconductor substrate, the drain region is arranged in the semiconductor substrate and is located on the side of the word line gate, the area between the drain region and the tunneling oxide layer and the floating gate layer is a channel region, and the width of the channel region is reduced by controlling the recessed distance of the word line gate toward the inside.
[0018] Optionally, forming a gate stack layer on the semiconductor substrate includes the steps of: sequentially forming a tunneling oxide layer, a floating gate layer, a gate dielectric layer, a control gate layer and a hard mask on the semiconductor substrate; patterning the hard mask, the control gate layer and the gate dielectric layer through a photolithography process and an etching process; forming a sidewall structure on the sidewalls of the patterned hard mask, the control gate layer and the gate dielectric layer; etching the floating gate layer and the tunneling oxide layer using the patterned hard mask, the control gate layer and the gate dielectric layer and the sidewall structure as a mask to pattern them, wherein the width of the tunneling oxide layer and the floating gate layer protruding from the gate dielectric layer and the control gate layer is controlled by controlling the width of the sidewall structure.
[0019] Optionally, forming an isolation sidewall and a tunneling sidewall includes the steps of: forming a first dielectric layer on the sidewalls of the sidewall structure, the tunneling oxide layer and the floating gate layer; removing the sidewall structure and the first dielectric layer on the tunneling oxide layer, the floating gate layer, the gate dielectric layer and the second sidewall of the control gate layer; forming a tunneling sidewall on the tunneling oxide layer, the floating gate layer, the gate dielectric layer and the second sidewall of the control gate layer. At this time, the tunneling oxide layer, the floating gate layer, the gate dielectric layer and the sidewall structure, the first dielectric layer and the tunneling oxide layer on the first sidewall of the control gate layer together constitute the isolation sidewall.
[0020] Optionally, forming a word line gate and an erase gate includes the following steps: forming a gate oxide layer on the surface of a semiconductor substrate through a thermal oxidation process; depositing a polysilicon layer on the semiconductor substrate and flattening it to remove excess polysilicon layer on the surface, wherein the polysilicon layer deposited on one side of the tunnel sidewall serves as the erase gate, and by controlling the deposition parameters of the polysilicon layer, a groove structure is formed on the top of the erase gate; the polysilicon layer deposited on one side of the isolation sidewall is the word line polysilicon; and etching the word line silicon to divide the word line polysilicon into two word line gates.
[0021] Optionally, the depth of the groove structure is 10% to 50% of the height of the erase gate, and the groove structure is also filled with a metal layer, which forms an ohmic contact with the polysilicon in the groove structure. The groove structure in the erase gate includes one of a rectangular groove, a V-shaped groove and a U-shaped groove.
[0022] Optionally, the forming of the word line gate and the erase gate comprises the following steps: forming a gate oxide layer on the surface of the semiconductor substrate by a thermal oxidation process; depositing a first polysilicon layer on the semiconductor substrate, wherein the first polysilicon layer deposited on one side of the tunneling side wall is used as the erase gate, and the first polysilicon layer deposited on one side of the isolation side wall is used as the word line polysilicon, and a groove structure is formed on the top of the erase gate and the top of the word line polysilicon; coating an organic medium layer on the erase gate and the word line polysilicon, and the organic medium layer fills the groove structure; etching the organic medium layer by plasma until the first polysilicon layer is exposed, and the organic medium layer is reserved in the groove structure; removing the excess first polysilicon layer on the surface by selectively etching the first polysilicon layer; removing the organic medium layer in the groove structure by wet etching; and etching the word line polysilicon so that the word line polysilicon is divided into two word line gates.
[0023] Optionally, the forming of the word line gate and the erase gate comprises the following steps: forming a gate oxide layer on the surface of the semiconductor substrate by a thermal oxidation process; depositing a first polysilicon layer on the semiconductor substrate, wherein the first polysilicon layer deposited on one side of the tunneling side wall is used as the erase gate, and the first polysilicon layer deposited on one side of the isolation side wall is used as the word line polysilicon, and a groove structure is formed on the top of the erase gate and the top of the word line polysilicon; depositing a second polysilicon layer on the erase gate and the word line polysilicon, and the second polysilicon layer fills the groove structure; removing the excess second polysilicon layer and the first polysilicon layer on the surface by planarization; and etching the word line polysilicon so that the word line polysilicon is divided into two word line gates.
[0024] Optionally, the width of the tunneling oxide layer and the floating gate layer protruding from any one side of the gate medium layer and the control gate layer is 5-15 nm; or the width of the tunneling oxide layer and the floating gate layer is 100-130 nm, and the width of the gate medium layer and the control gate layer is 80-110 nm.
[0025] Optionally, the thickness of the tunneling oxide layer is 90-120 angstroms, the thickness of the floating gate layer is 250-450 angstroms, the gate medium layer comprises a first silicon oxide layer, a silicon nitride layer on the first silicon oxide layer, and a second silicon oxide layer on the silicon nitride layer, the thickness of the gate medium layer is 130-170 angstroms, the thickness of the control gate layer is 500-700 angstroms, and the thickness of the hard mask is 500-1100 angstroms; the thickness of the isolation side wall is 160-220 angstroms, and the thickness of the tunneling side wall is 90-110 angstroms.
[0026] Optionally, an insulating layer is formed on the source region by a thermal oxidation process, the cross section of the insulating layer on the source region is in an oval shape, and the two ends of the oval shape are connected with the tunneling side wall, wherein the thickness of the middle part of the insulating layer is 380-450 angstroms, and the thickness of the two ends is 150-190 angstroms.
[0027] As described above, the embedded flash memory and the manufacturing method thereof have the following beneficial effects:
[0028] The width of the tunneling oxide layer and the floating gate layer of the embedded flash memory is set to be greater than the width of the gate dielectric layer and the control gate layer, so that the tunneling oxide layer and the floating gate layer protrude from the two sides of the gate dielectric layer and the control gate layer, the word line gate protrudes along the tunneling oxide layer and the floating gate layer, and the word line gate is recessed inward by a distance, the width of the channel region can be effectively reduced by controlling the distance of the inward recess of the word line gate, so that the path of electron injection into the floating gate layer during programming is greatly shortened, and the programming speed of the embedded flash memory is greatly improved. At the erase gate end, the floating gate layer protrusion can reduce the voltage required to pull electrons from the floating gate layer to the erase gate, and the insulating layer under the erase gate becomes very thick due to ion implantation and oxidation in the process, which allows the voltage applied to the erase gate to be increased without causing the insulating layer to break down, thereby greatly improving the process variation window. The embedded flash memory and the manufacturing method thereof combine the above-mentioned advantages, so that the embedded flash memory cell has better process compatibility, is more reliable, and has better performance.
[0029] The top of the erase gate is provided with a groove structure, and the groove structure forms an ohmic contact with the metal layer, which can greatly increase the contact area of the metal layer and the erase gate, improve the driving effect, and further improve the speed and stability of the erase operation of the erase gate.
[0030] The insulating layer with a large thickness is arranged on the source region, which can effectively increase the erase voltage that can be applied to the erase gate above the source region without causing damage to the device, thereby ensuring that the erase operation has very high erase efficiency and erase stability. Since the erase gate can apply a high enough voltage, no negative voltage needs to be applied to the control gate, which can greatly reduce the design difficulty of the applied circuit. BRIEF DESCRIPTION OF DRAWINGS
[0031] The accompanying drawings included to provide a further understanding of the embodiments of the present application, constitute a part of the specification and serve in conjunction with the text to explain the principles of the application. Obviously, the accompanying drawings in the following description are only some embodiments of the present application.
[0032] Figure 1 A structure schematic diagram of an embedded flash memory according to an embodiment of the present application is shown.
[0033] Figure 2 A structure diagram of another embedded flash memory according to an embodiment of the present application.
[0034] Figures 3-4 An example diagram of an operation method of an embedded flash memory according to an embodiment of the present application.
[0035] Figures 5-23 Structure diagrams of various steps of a manufacturing method of an embedded flash memory according to an embodiment of the present application.
[0036] Element Number Description
[0037] 101 semiconductor substrate
[0038] 102 tunnel oxide layer
[0039] 103 floating gate layer
[0040] 104 gate dielectric layer
[0041] 105 control gate layer
[0042] 106 hard mask
[0043] 107 isolation sidewall
[0044] 108 tunneling sidewall
[0045] 109 word line gate
[0046] 110 erase gate
[0047] 111 insulating layer
[0048] 112 source region
[0049] 113 drain region
[0050] 114 recessed structure
[0051] 115 gate oxide layer
[0052] 201 logic circuit region
[0053] 202 shallow trench isolation structure
[0054] 301 sidewall structure
[0055] 302 first dielectric layer
[0056] 303 first polysilicon layer
[0057] 304 second polysilicon layer
[0058] 305 organic dielectric layer DETAILED DESCRIPTION
[0059] Those skilled in the art will readily understand that the application is well adapted to carry out the objects and obtain the ends and advantages mentioned, as well as those inherent therein, and that the same can be readily carried out by others skilled in the art using the present description and the accompanying drawings, without departing from the spirit and scope of the application.
[0060] It should be emphasized that the term "comprises / comprising" when used in this specification is taken to mean the presence of stated features, integers, steps or components but does not preclude the presence or addition of one or more other features, integers, steps, components or groups thereof.
[0061] Features described and / or illustrated with respect to one implementation can be used in the same or similar manner in one or more other implementations, in combination with other features in the other implementations, or in place of other features in the other implementations.
[0062] As will be understood by those familiar with the art, the figures to be discussed are not drawn to scale and that actual implementation can include a three-dimensional aspect not apparent from the drawings.
[0063] To facilitate the description of the drawings, spatial terms, such as "beneath", "below", "lower", "under", "above", "upper" and the like, can be used herein for purposes of explanation and reference only. It will be understood that the spatial terms are intended to encompass different orientations of the device in use or operation, in addition to the orientations depicted in the drawings. For example, if the device described is turned over, elements described as "below" or "beneath" other elements or features would then be oriented "above" the other elements or features. Likewise, if the device is inverted, elements described as "above" other elements or features would then be oriented "below" the other elements or features. Therefore, the spatial terms are used herein only to facilitate the description of the drawings, and should not be construed as limiting the scope of the disclosure in any manner.
[0064] In the context of this application, structures described as being "on" or "above" a first feature and "on" or "below" a second feature can include embodiments where the first and second features are formed in direct contact, as well as embodiments where additional features are formed between the first and second features such that the first and second features can not be in direct contact.
[0065] It is noted that the drawings provided herein are merely schematic and are non-limiting examples of implementations of the application, and thus they are presented for illustrative purposes only. The drawings are not intended to limit the scope of the present application, and are not intended to limit the scope of the application to the embodiments depicted. In addition, the drawings provided herein are intended merely to simplify the drawings, and thus the shapes, numbers, and sizes of the components shown in the drawings can be changed arbitrarily, and the layout of the components can be more complex.
[0066] As Figure 1As shown, this embodiment provides an embedded flash memory, the embedded flash memory comprising: a semiconductor substrate 101; a gate stack layer formed on the semiconductor substrate 101, the gate stack layer comprising a tunneling oxide layer 102, a floating gate layer 103, a gate dielectric layer 104 and a control gate layer 105 stacked in sequence, the width of the tunneling oxide layer 102 and the floating gate layer 103 being greater than the width of the gate dielectric layer 104 and the control gate layer 105, so that the tunneling oxide layer 102 and the floating gate layer 103 protrude from both sides of the gate dielectric layer 104 and the control gate layer 105; an isolation sidewall 107 and a tunneling sidewall 108, respectively covering a first sidewall and a second sidewall on both sides of the tunneling oxide layer 102, the floating gate layer 103, the gate dielectric layer 104 and the control gate layer 105; a word line gate 101; a first sidewall and a second sidewall on both sides of the ... 09, arranged on the side of the isolation sidewall 107, the word line gate 109 protrudes along the tunneling oxide layer 102 and the floating gate layer 103 and is recessed a distance toward the inside of the word line gate 109; the drain region 113, arranged in the semiconductor substrate 101, and located on the side of the word line gate 109, the area between the drain region 113 and the tunneling oxide layer 102 and the floating gate layer 103 is a channel region, and the width of the channel region is reduced by controlling the recessed distance of the word line gate 109 toward the inside; the source region 112, arranged in the semiconductor substrate 101 on the side of the tunneling sidewall 108, and the source region 112 is covered with an insulating layer 111; the erase gate 110, arranged on the side of the tunneling sidewall 108, and located on the insulating layer 111 to be isolated from the source region 112.
[0067] In some embodiments, the semiconductor substrate 101 may be, for example, a silicon substrate, a germanium substrate, a silicon germanium substrate, a silicon carbide substrate, a III-V compound substrate, etc., and is not limited to the examples listed above. The semiconductor substrate 101 includes a core device region and a logic circuit region 201. The device region and the logic circuit region 201 are isolated by a shallow trench isolation structure 202.
[0068] like Figure 1 As shown, a gate stack layer is formed on the semiconductor substrate 101, and the gate stack layer includes a tunneling oxide layer 102, a floating gate layer 103, a gate dielectric layer 104 and a control gate layer 105 stacked in sequence. The width of the tunneling oxide layer 102 and the floating gate layer 103 is greater than the width of the gate dielectric layer 104 and the control gate layer 105, so that the tunneling oxide layer 102 and the floating gate layer 103 protrude from both sides of the gate dielectric layer 104 and the control gate layer 105.
[0069] In some embodiments, the material of the tunneling oxide layer 102 can be silicon dioxide, and the thickness of the tunneling oxide layer 102 can be 90 angstroms to 110 angstroms, for example, the thickness of the tunneling oxide layer 102 can be 90 angstroms, 100 angstroms, 110 angstroms, etc.; the material of the floating gate layer 103 can be polysilicon, and the thickness of the floating gate layer 103 can be 300 angstroms to 450 angstroms, for example, the thickness of the floating gate layer 103 can be 300 angstroms, 350 angstroms, 400 angstroms, 450 angstroms, etc.; the thickness of the gate dielectric layer 104 can be 130 angstroms to 170 angstroms, for example, the thickness of the gate dielectric layer 104 can be 130 angstroms, 140 angstroms, 150 angstroms, 160 angstroms, etc.; the gate dielectric layer 104 includes a first silicon oxide layer and a silicon nitride layer on the first silicon oxide layer, the thickness of the first silicon oxide layer can be 40 angstroms, 50 angstroms, 60 angstroms, etc., the thickness of the silicon nitride layer can be 40 angstroms, 50 angstroms, 60 angstroms, etc., and the thickness of the second silicon oxide layer can be 40 angstroms, 50 angstroms, 60 angstroms, etc.; the thickness of the control gate layer 105 can be 500 angstroms to 700 angstroms, and the material of the control gate layer 105 can be polysilicon, for example, the thickness of the control gate layer 105 can be 500 angstroms, 600 angstroms, 700 angstroms, etc.; the gate stack further includes a hard mask 106 disposed on the control gate layer 105, and the thickness of the hard mask 106 can be 500 angstroms to 1100 angstroms, for example, the thickness of the hard mask 106 can be 500 angstroms, 600 angstroms, 700 angstroms, 800 angstroms, 1000 angstroms, 1100 angstroms, etc.
[0070] In some embodiments, the width of the tunneling oxide layer 102 and the floating gate layer 103 protruding from any one side of the gate dielectric layer 104 and the control gate layer 105 can be 5 nanometers to 15 nanometers, for example, the width of the tunneling oxide layer 102 and the floating gate layer 103 protruding from any one side of the gate dielectric layer 104 and the control gate layer 105 can be 5 nanometers, 8 nanometers, 10 nanometers, 12 nanometers, 15 nanometers, etc.
[0071] In some embodiments, the width of the tunneling oxide layer 102 and the floating gate layer 103 can be 100 nanometers to 130 nanometers, for example, 110 nanometers, 120 nanometers, 130 nanometers, etc., and the width of the gate dielectric layer 104 and the control gate layer 105 can be 80 nanometers to 110 nanometers, for example, 90 nanometers, 100 nanometers, 110 nanometers, etc.
[0072] As shown in FIG. 1, the gate stack includes a tunneling oxide layer 102, a floating gate layer 103, a gate dielectric layer 104, a control gate layer 105, and a hard mask 106. Figure 1As shown, the isolation spacer 107 and the tunneling spacer 108 respectively cover the first sidewall and the second sidewall on both sides of the tunneling oxide layer 102, the floating gate layer 103, the gate dielectric layer 104, and the control gate layer 105. The isolation spacer 107 and the tunneling spacer 108 have corners at the top corners of the floating gate layer 103. In some embodiments, the thickness of the isolation spacer 107 is 160 angstroms to 220 angstroms, for example, 130 angstroms, 140 angstroms, 150 angstroms, 160 angstroms, 170 angstroms, etc.; the thickness of the tunneling spacer 108 is 90 angstroms to 110 angstroms, for example, 90 angstroms, 100 angstroms, 110 angstroms, etc. The material of the isolation sidewall 107 can be silicon dioxide, which is used to isolate the word line gate 109 from the gate stack structure. The material of the tunneling sidewall 108 can also be silicon dioxide, which is used to isolate the erase gate 110 from the gate stack structure. At the same time, by applying an appropriate voltage to the erase gate 110, the electrons in the floating gate layer 103 can be extracted through the tunneling effect of the tunneling sidewall 108 to remove the charge in the floating gate layer 103. The isolation sidewall 107 has a corner at the top corner of the floating gate layer 103, which can effectively ensure that the subsequent word line gate 109 protrudes along the tunneling oxide layer 102 and the floating gate layer 103 and is recessed a distance toward the inside of the word line gate 109. The tunneling sidewall 108 has a corner at the top corner of the floating gate layer 103, which can effectively ensure the uniformity of the thickness of the tunneling oxide layer 102 between the erase gate 110 and the floating gate layer 103, and ensure the stability of the erase gate 110 when extracting electrons in the floating gate layer 103 at the same voltage.
[0073] like Figure 1 As shown, a wordline gate 109 is disposed on a side of the isolation spacer 107. The wordline gate 109 protrudes along the tunneling oxide layer 102 and the floating gate layer 103 and is recessed a certain distance into the interior of the wordline gate 109. Specifically, one side of the wordline gate 109 is recessed a certain distance into the interior of the wordline gate 109, while the other side has a sidewall that is perpendicular or nearly perpendicular to the semiconductor substrate 101, such that the width of the lower portion of the wordline gate 109 is smaller than the width of the upper portion of the wordline gate 109. Generally speaking, the manufacturing process defines the morphology and size of the upper portion of the wordline gate 109. Therefore, when the upper size of the wordline gate 109 is the same as that of the conventional process, the lower width of the wordline gate 109 is smaller than that of the conventional process, thereby effectively shortening the width of the channel region. In some embodiments, the word line gate 109 may include a gate oxide layer located on the surface of the substrate and a polysilicon layer located on the gate oxide layer. The word line gate 109 is used to turn on the channel below it during programming, and to store electrons in the floating gate layer 103 through the tunneling oxide layer through the hot electron injection effect.
[0074] like Figure 1As shown, a drain region 113 is disposed in the semiconductor substrate 101 and is located lateral to the wordline gate 109. The region between the drain region 113, the tunneling oxide layer 102, and the floating gate layer 103 constitutes a channel region. By controlling the inward recess of the wordline gate 109, the width of the channel region is reduced, and the drain region 113 can be connected to a bit line of the embedded flash memory. In some embodiments, the drain region 113 can be N-type doped, and the shortened width of the channel region is equal to the inward recess of the wordline gate 109. Therefore, by controlling the width of the tunneling oxide layer 102 and the floating gate layer 103 protruding from both sides of the gate dielectric layer 104 and the control gate layer 105, the width of the channel region can be effectively controlled.
[0075] The present invention sets the width of the tunneling oxide layer 102 and the floating gate layer 103 of the embedded flash memory to be greater than the width of the gate dielectric layer 104 and the control gate layer 105, so that the tunneling oxide layer 102 and the floating gate layer 103 protrude from both sides of the gate dielectric layer 104 and the control gate layer 105, and the word line gate 109 protrudes along the tunneling oxide layer 102 and the floating gate layer 103 and is recessed a distance toward the interior of the word line gate 109. By controlling the recessed distance of the word line gate 109 toward the interior, the width of the channel region can be effectively reduced, thereby greatly shortening the path for electrons to be injected into the floating gate layer 103 during programming, thereby greatly improving the programming speed of the embedded flash memory.
[0076] like Figure 1 As shown, a source region 112 is disposed in the semiconductor substrate 101 on the side of the tunneling spacer 108 and is covered with an insulating layer 111. In some embodiments, the source region 112 may be N-type doped. The source region 112 can be connected to the source line of the embedded flash memory. The insulating layer 111 above the source region has an elliptical cross-section, with both ends of the ellipse contacting the tunneling spacer. The thickness of the insulating layer in the middle is 380 to 450 angstroms, and the thickness at both ends is 150 to 190 angstroms. The thicker insulating layer 111 disposed above the source region in the present invention effectively increases the ability to apply a higher erase voltage to the erase gate 110 above it without damaging the device, thereby ensuring extremely high erase efficiency and erase stability during the erase operation. For example, in this embodiment, during an erase operation, the erase gate 110 can apply an erase voltage in the range of 12V to 13V. Because the erase gate 110 can apply a sufficiently high voltage, there is no need to apply a negative voltage to the control gate, which greatly reduces the difficulty of applying circuit design. In addition, the insulating layer 111 is set to be an ellipse, and the electric field is usually concentrated in the middle of the erase gate 110. Therefore, the larger thickness of the middle part of the ellipse can prevent the risk of breakdown of the insulating layer 111 due to the concentration of the electric field in the middle. On the other hand, the thickness of the two ends of the ellipse is relatively small, which can ensure the stability of the distance between the two sides of the erase gate 110 and the floating gate layer 103, thereby ensuring the stability of the erase operation.
[0077] As shown in Figure 1 some embodiments, the erase gate 110 is disposed on the side of the tunneling sidewall 108 and is located on the insulating layer 111 to be isolated from the source region 112. In some embodiments, the material of the erase gate 110 can be polysilicon, and by applying a suitable voltage on the erase gate 110, the electrons in the floating gate layer 103 can be extracted by the tunneling effect of the tunneling sidewall 108 to perform the erase operation on the floating gate layer 103.
[0078] As shown in Figure 2 some embodiments, the material of the erase gate 110 is polysilicon, and the top of the erase gate 110 is formed with a groove structure 114, and the groove structure 114 is also filled with a metal layer, which forms an ohmic contact with the polysilicon in the groove structure 114. The metal layer can be, for example, a stack or alloy composed of one or more of titanium, nickel, tantalum, aluminum, tungsten, copper, gold, and the like, and is not limited to the examples listed here.
[0079] In some embodiments, the depth of the groove structure 114 is 10% to 50% of the height of the erase gate 110, for example, the depth of the groove structure 114 is 20%, 30%, 40%, 50%, 60%, etc. of the height of the erase gate 110. The metal layer can be deposited on the inner wall of the groove structure 114 or filled in the groove structure 114, and then form a metal silicide with the polysilicon of the erase gate 110 through an annealing process or the like. In some embodiments, the groove structure 114 includes one of a rectangular slot, a V-shaped slot, and a U-shaped slot. By forming an ohmic contact between the groove structure 114 and the metal layer, the contact area between the metal layer and the erase gate 110 can be greatly improved, the driving effect is improved, and the speed and stability of the erase operation of the erase gate 110 are improved.
[0080] As shown in Figure 3 and Figure 4 the embedded flash memory of the present embodiment includes a plurality of signal lines, including a bit line (BL, Bit line) connected to the drain region 113, a word line (WL, Word line / Select gate) connected to the word line gate 109, a control gate line (CG, Control gate) connected to the control gate layer 105, an erase gate line (EG, Erase gate) connected to the erase gate 110, and a source line (SL, Source line) connected to the source region 112.
[0081] The embodiment also provides an erasing method of the embedded flash memory, wherein during the erasing process, the bit line (BL) is applied with a voltage of 0V, the word line (WL) is applied with a voltage of 0V, the control gate line (CG) is applied with a voltage of 0V, the erase gate line (EG) is applied with a voltage of 11-13V, the source line (SL) is applied with a voltage of 0V, and the electronic path of erasing is to extract the electrons of the floating gate layer 103 to the erase gate 110.
[0082] The embodiment also provides a programming method of the embedded flash memory, wherein during the programming process, the bit line (BL) is applied with a hot current of 0.8-1.1μA, the word line (WL) is applied with a voltage of 0.9-1.1V, the control gate line (CG) is applied with a voltage of 9-12V, the erase gate line (EG) is applied with a voltage of 4-6V, the source line (SL) is applied with a voltage of 4-6V, and the electronic path of programming is to inject the electrons of the drain region 113 into the floating gate layer 103 by the hot electron injection method.
[0083] The embodiment also provides a reading method of the embedded flash memory, wherein during the reading process, the bit line (BL) is applied with a hot voltage of 0.9-1.2V, the word line (WL) is applied with a voltage of 0.8-2.5V, the control gate line (CG) is applied with a voltage of 0.9-3V, the erase gate line (EG) is applied with a voltage of 0V, the source line (SL) is applied with a voltage of 0V, and whether the floating gate layer 103 has the electronic charge is judged by the reading current.
[0084] As shown in Figures 5-19 The embodiment also provides a manufacturing method of the embedded flash memory, which can be used to manufacture the embedded flash memory of the above-mentioned embodiments, and some specific parameters of the embedded flash memory can refer to the above-mentioned embodiments. The manufacturing method of the embodiment comprises the following steps:
[0085] As shown in Figure 5 Firstly, step 1) is performed to provide the semiconductor substrate 101.
[0086] In some embodiments, the semiconductor substrate 101 can be a silicon substrate, a germanium substrate, a germanium-silicon substrate, a silicon carbide substrate, a ternary quaternary compound substrate, etc., and is not limited to the above-mentioned examples.
[0087] like Figures 5-10 As shown, step 2) is then performed to form a gate stack layer on the semiconductor substrate 101, wherein the gate stack layer includes a tunneling oxide layer 102, a floating gate layer 103, a gate dielectric layer 104 and a control gate layer 105 stacked in sequence, and the width of the tunneling oxide layer 102 and the floating gate layer 103 is greater than the width of the gate dielectric layer 104 and the control gate layer 105, so that the tunneling oxide layer 102 and the floating gate layer 103 protrude from both sides of the gate dielectric layer 104 and the control gate layer 105.
[0088] In some embodiments, the thickness of the tunneling oxide layer 102 is 90 angstroms to 110 angstroms, the thickness of the floating gate layer 103 is 300 angstroms to 450 angstroms, the gate dielectric layer 104 includes a first silicon oxide layer and a silicon nitride layer located on the first silicon oxide layer, the thickness of the gate dielectric layer 104 is 130 angstroms to 170 angstroms, the thickness of the control gate layer 105 is 500 angstroms to 700 angstroms, and the thickness of the hard mask 106 is 500 angstroms to 1100 angstroms; the thickness of the isolation sidewall 107 is 160 angstroms to 220 angstroms, and the thickness of the tunneling sidewall 108 is 90 angstroms to 110 angstroms.
[0089] In some embodiments, the width of the tunneling oxide layer 102 and the floating gate layer 103 protruding from any side of the gate dielectric layer 104 and the control gate layer 105 is 5 nanometers to 15 nanometers; or the width of the tunneling oxide layer 102 and the floating gate layer 103 is 100 nanometers to 130 nanometers, and the width of the gate dielectric layer 104 and the control gate layer 105 is 80 nanometers to 110 nanometers.
[0090] In one embodiment, forming a gate stack layer on the semiconductor substrate 101 includes the following steps:
[0091] like Figures 5-8 As shown, a tunneling oxide layer 102, a floating gate layer 103, a gate dielectric layer 104, a control gate layer 105 and a hard mask 106 are sequentially formed on the semiconductor substrate 101; the hard mask 106, the control gate layer 105 and the gate dielectric layer 104 are patterned by photolithography and etching processes;
[0092] like Figure 9 As shown, a spacer structure 301 is formed on the sidewalls of the patterned hard mask 106, the control gate layer 105 and the gate dielectric layer 104;
[0093] like Figure 10As shown, the hard mask 106, the control gate layer 105, the gate dielectric layer 104 and the side wall structure 301 are used as masks to etch the floating gate layer 103 and the tunnel oxide layer 102 to pattern them. The width of the side wall structure 301 controls the width of the floating gate layer 103 and the tunnel oxide layer 102 protruding from the gate dielectric layer 104 and the control gate layer 105.
[0094] As shown, the hard mask 106, the control gate layer 105, the gate dielectric layer 104 and the side wall structure 301 are used as masks to etch the floating gate layer 103 and the tunnel oxide layer 102 to pattern them. The width of the side wall structure 301 controls the width of the floating gate layer 103 and the tunnel oxide layer 102 protruding from the gate dielectric layer 104 and the control gate layer 105. Figures 11-13 As shown, then step 3) is performed to form the isolation side wall 107 and the tunnel side wall 108, which cover the first and second side walls of the tunnel oxide layer 102, the floating gate layer 103, the gate dielectric layer 104 and the control gate layer 105, respectively. The isolation side wall 107 and the tunnel side wall 108 have corners at the top corners of the floating gate layer 103.
[0095] In one embodiment, forming the isolation side wall 107 and the tunnel side wall 108 includes the steps of:
[0096] As shown, a first dielectric layer 302 is formed on the side walls of the side wall structure 301, the tunnel oxide layer 102 and the floating gate layer 103. Figure 11
[0097] As shown, the side wall structure 301 and the first dielectric layer 302 on the second side walls of the tunnel oxide layer 102, the floating gate layer 103, the gate dielectric layer 104 and the control gate layer 105 are removed. Figure 12 As shown, the tunnel side wall 108 is formed on the second side walls of the tunnel oxide layer 102, the floating gate layer 103, the gate dielectric layer 104 and the control gate layer 105. At this time, the side wall structure 301, the first dielectric layer 302 and the tunnel oxide layer on the first side walls of the tunnel oxide layer 102, the floating gate layer 103, the gate dielectric layer 104 and the control gate layer 105 together form the isolation side wall 107.
[0098] Figure 13 As shown, then step 4) is performed to form a source region 112 in the semiconductor substrate 101, which is disposed in the semiconductor substrate 101 at the side of the tunnel side wall 108, and an insulating layer 111 is formed on the source region 112. The insulating layer 111 on the source region 112 is formed by a thermal oxidation process. The cross section of the insulating layer 111 on the source region 112 is elliptical, and the two ends of the ellipse are connected to the tunnel side wall 108. The thickness of the middle part of the insulating layer 111 is 380-450 angstroms, and the thickness of the two ends is 150-190 angstroms.
[0099] As shown, then step 4) is performed to form a source region 112 in the semiconductor substrate 101, which is disposed in the semiconductor substrate 101 at the side of the tunnel side wall 108, and an insulating layer 111 is formed on the source region 112. The insulating layer 111 on the source region 112 is formed by a thermal oxidation process. The cross section of the insulating layer 111 on the source region 112 is elliptical, and the two ends of the ellipse are connected to the tunnel side wall 108. The thickness of the middle part of the insulating layer 111 is 380-450 angstroms, and the thickness of the two ends is 150-190 angstroms. Figure 13 As shown, then step 4) is performed to form a source region 112 in the semiconductor substrate 101, which is disposed in the semiconductor substrate 101 at the side of the tunnel side wall 108, and an insulating layer 111 is formed on the source region 112. The insulating layer 111 on the source region 112 is formed by a thermal oxidation process. The cross section of the insulating layer 111 on the source region 112 is elliptical, and the two ends of the ellipse are connected to the tunnel side wall 108. The thickness of the middle part of the insulating layer 111 is 380-450 angstroms, and the thickness of the two ends is 150-190 angstroms.
[0100] As shown, then step 4) is performed to form a source region 112 in the semiconductor substrate 101, which is disposed in the semiconductor substrate 101 at the side of the tunnel side wall 108, and an insulating layer 111 is formed on the source region 112. The insulating layer 111 on the source region 112 is formed by a thermal oxidation process. The cross section of the insulating layer 111 on the source region 112 is elliptical, and the two ends of the ellipse are connected to the tunnel side wall 108. The thickness of the middle part of the insulating layer 111 is 380-450 angstroms, and the thickness of the two ends is 150-190 angstroms. Figures 14-17 As shown, step 5 is then performed to form a wordline gate 109 on the side of the isolation spacer 107. The wordline gate 109 protrudes along the tunneling oxide layer 102 and the floating gate layer 103 and is recessed a distance toward the inside of the wordline gate 109. An erase gate 110 is formed. The erase gate 110 is disposed on the side of the tunneling spacer 108 and is located on the insulating layer 111 to be isolated from the source region 112.
[0101] In one embodiment, forming the word line gate 109 and the erase gate 110 includes the steps of:
[0102] like Figures 14-20 As shown, a gate oxide layer 115 is formed on the surface of the semiconductor substrate 101 by a thermal oxidation process; a first polysilicon layer 303 is deposited on the semiconductor substrate and planarized to remove excess first polysilicon layer 303 on the surface, wherein the polysilicon layer deposited on one side of the tunnel sidewall 108 serves as an erase gate 110, and a groove structure 114 can be formed on the top of the erase gate 110 by controlling the deposition parameters of the first polysilicon layer 303; the polysilicon layer deposited on one side of the isolation sidewall 107 is word line polysilicon; of course, the groove structure 114 can be naturally formed by deposition, or the erase gate 110 can be additionally etched to further form a groove structure 114 of the desired shape and depth.
[0103] In some instances, the depth of the groove structure 114 is 10% to 50% of the height of the erase gate 110. The groove structure 114 is also filled with a metal layer, and the metal layer forms an ohmic contact with the polysilicon in the groove structure 114. The groove structure 114 in the erase gate 110 includes one of a rectangular groove, a V-shaped groove, and a U-shaped groove.
[0104] Specifically, if Figures 14-20 As shown, forming the word line gate and the erase gate includes the steps of:
[0105] like Figure 14 As shown, a gate oxide layer is formed on the surface of the semiconductor substrate 101 through a thermal oxidation process.
[0106] like Figure 15 As shown, a first polysilicon layer 303 is deposited on the semiconductor substrate, wherein the first polysilicon layer 303 deposited on the tunneling spacer 108 side serves as the erase gate 110, and the first polysilicon layer 303 deposited on the isolation spacer 107 side serves as word line polysilicon. A groove structure 114 is formed on the top of the erase gate 110 and the top of the word line polysilicon.
[0107] like Figure 16 As shown, an organic dielectric layer 305 is spin-coated on the erase gate 110 and the word line polysilicon, and the organic dielectric layer 305 fills the groove structure 114 .
[0108] like Figure 17 As shown, the organic dielectric layer 305 is etched by plasma without a mask until the first polysilicon layer 303 is exposed, and the organic dielectric layer 305 is retained in the groove structure 114 .
[0109] like Figure 18 As shown, the first polysilicon layer is selectively etched to remove excess first polysilicon layer on the surface; wherein the selective etching has a higher selectivity for the first polysilicon layer 303 and a lower etching rate for the organic dielectric layer 305, so that the organic dielectric layer 305 is always maintained in the groove structure 114, thereby protecting the groove structure 114 from being etched and damaged.
[0110] like Figure 19 As shown, the organic dielectric layer 305 in the groove structure 114 is removed by wet etching, and the solution used in the wet etching may be, for example, an acidic solution.
[0111] This process method can use an etching process to remove the excess first polysilicon layer on the surface. During the etching process, the groove structure is filled with an organic dielectric layer, which can avoid damage caused by etching of the groove structure. Compared with the traditional planarization process, it can further avoid mechanical damage to the device, and the etching process has higher selectivity, which can effectively improve the process stability.
[0112] like Figure 20 As shown, the word line silicon is etched to separate the word line polysilicon into two word line gates 109 .
[0113] like Figure 20 As shown, step 6) is finally performed to form a drain region 113 in the semiconductor substrate 101 through an ion implantation process. The drain region 113 is arranged in the semiconductor substrate 101 and is located on the side of the word line gate 109. The area between the drain region 113 and the tunneling oxide layer 102 and the floating gate layer 103 is the channel region. The width of the channel region is reduced by controlling the inward concave distance of the word line gate 109.
[0114] like Figures 21-23 As shown, in another embodiment, forming the word line gate 109 and the erase gate 110 may also include the steps of:
[0115] like Figure 21As shown, a gate oxide layer is formed on the surface of the semiconductor substrate 101 by a thermal oxidation process; a first polysilicon layer 303 is deposited on the semiconductor substrate, wherein the first polysilicon layer 303 deposited on the side of the tunnel spacer 108 serves as the erase gate 110, and the first polysilicon layer 303 deposited on the side of the isolation spacer 107 serves as word line polysilicon, and a groove structure 114 is formed on the top of the erase gate 110 and the top of the word line polysilicon;
[0116] like Figure 22 As shown, a second polysilicon layer 304 is deposited on the erase gate 110 and the word line polysilicon, and the second polysilicon layer 304 fills the groove structure 114;
[0117] like Figure 23 As shown, the redundant second polysilicon layer 304 and the first polysilicon layer 303 on the surface are removed by planarization; and the word line polysilicon is etched to separate the word line polysilicon into two word line gates 109 .
[0118] In this embodiment, the second polysilicon layer 304 is deposited to fill the groove structure 114 in the first polysilicon layer 303 , which can greatly improve the stability of the subsequent planarization process and enhance the device yield.
[0119] As described above, the embedded flash memory and the manufacturing method thereof of the present invention have the following beneficial effects:
[0120] The present invention sets the width of the tunneling oxide layer 102 and the floating gate layer 103 of the embedded flash memory to be greater than the width of the gate dielectric layer 104 and the control gate layer 105, so that the tunneling oxide layer 102 and the floating gate layer 103 protrude from both sides of the gate dielectric layer 104 and the control gate layer 105, and the word line gate 109 protrudes along the tunneling oxide layer 102 and the floating gate layer 103 and is recessed a distance toward the interior of the word line gate 109. By controlling the recessed distance of the word line gate 109 toward the interior, the width of the channel region can be effectively reduced, thereby greatly shortening the path for electrons to be injected into the floating gate layer 103 during programming, thereby greatly improving the programming speed of the embedded flash memory. At the erase gate end, the protrusion of the floating gate layer 103 can reduce the voltage required to pull electrons from the floating gate layer 103 to the erase gate 110. At the same time, the insulating layer under the erase gate naturally becomes very thick due to ion implantation and oxidation during the process. This allows the voltage applied to the erase gate 110 to be increased without causing the insulating layer 111 to break down, thereby greatly improving the process variation window. Our embedded flash memory and its manufacturing method combine all of the above advantages, making this embedded flash memory unit more process-compatible, more reliable, and with better performance.
[0121] The top of the erasing grid 110 is provided with a groove structure 114, and the groove structure 114 forms an ohmic contact with the metal layer, so that the contact area of the metal layer and the erasing grid 110 can be greatly improved, the driving effect is improved, and the speed and stability of the erasing operation of the erasing grid 110 are improved.
[0122] The present application is provided with an insulating layer 111 with a large thickness on the source region, which can effectively increase the erasing voltage applied by the erasing grid 110 above it without causing damage to the device, thereby ensuring that the erasing operation has very high erasing efficiency and erasing stability. For example, in the present embodiment, the erasing voltage applied by the erasing grid 110 during the erasing operation is in the range of 12V-13V, and since the erasing grid 110 can apply a high enough voltage, it is not necessary to apply a negative voltage to the control grid, which can greatly reduce the design difficulty of the applied circuit.
[0123] Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.
[0124] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes completed by those skilled in the art without departing from the spirit and technical thought disclosed by the present application should be covered by the claims of the present application.
Claims
1. An embedded flash memory, characterized by, The embedded flash memory comprises: a semiconductor substrate; a gate stack formed on the semiconductor substrate, the gate stack comprising a tunneling oxide layer, a floating gate layer, a gate dielectric layer and a control gate layer stacked in sequence, the tunneling oxide layer and the floating gate layer having a width greater than that of the gate dielectric layer and the control gate layer, so that the tunneling oxide layer and the floating gate layer protrude on both sides of the gate dielectric layer and the control gate layer; an isolation sidewall and a tunneling sidewall covering the first sidewall and the second sidewall on both sides of the tunneling oxide layer, the floating gate layer, the gate dielectric layer and the control gate layer, the isolation sidewall and the tunneling sidewall having a corner at the top corner of the floating gate layer; a word line gate arranged on the side of the isolation sidewall, the word line gate being recessed inward by a distance along the protruding tunneling oxide layer and floating gate layer; a drain region arranged in the semiconductor substrate and located on the side of the word line gate, the region between the tunneling oxide layer and the floating gate layer being a channel region, and the width of the channel region being reduced by controlling the distance of the word line gate recessed inward; a source region arranged in the semiconductor substrate on the side of the tunneling sidewall, the source region being covered by an insulating layer; an erase gate arranged on the side of the tunneling sidewall and located on the insulating layer to be isolated from the source region.
2. The embedded flash memory of claim 1, wherein: The erase gate is made of polysilicon, a groove structure is formed on the top of the erase gate, and a metal layer is filled in the groove structure to form an ohmic contact with the polysilicon in the groove structure.
3. The embedded flash memory of claim 2, wherein: The depth of the groove structure is 10% to 50% of the height of the erase gate.
4. The embedded flash memory of claim 2, wherein: The groove structure comprises one of a rectangular groove, a V-shaped groove and a U-shaped groove.
5. The embedded flash memory of claim 1, wherein: The width of the tunneling oxide layer and the floating gate layer protruding on either side of the gate dielectric layer and the control gate layer is 5 nm to 15 nm.
6. The embedded flash memory of claim 1, wherein: The width of the tunneling oxide layer and the floating gate layer is 100 nm to 130 nm, and the width of the gate dielectric layer and the control gate layer is 80 nm to 110 nm.
7. The embedded flash memory of claim 1, wherein: The thickness of the tunneling oxide layer is 90 angstroms to 120 angstroms, the thickness of the floating gate layer is 250 angstroms to 450 angstroms, the gate dielectric layer comprises a first silicon oxide layer, a silicon nitride layer on the first silicon oxide layer and a second silicon oxide layer on the silicon nitride layer, the thickness of the gate dielectric layer is 130 angstroms to 170 angstroms, the thickness of the control gate layer is 500 angstroms to 700 angstroms, and the gate stack further comprises a hard mask arranged on the control gate layer, the thickness of the hard mask is 500 angstroms to 1100 angstroms.
8. The embedded flash memory of claim 1, wherein: The thickness of the isolation sidewall is 160 angstroms to 220 angstroms, and the thickness of the tunneling sidewall is 90 angstroms to 110 angstroms.
9. The embedded flash memory of claim 1, wherein: The cross section of the insulating layer on the source region is elliptical, the two ends of the ellipse are connected to the tunneling sidewall, the thickness of the middle part of the insulating layer is 380 angstroms to 450 angstroms, and the thickness of the two ends is 150 angstroms to 190 angstroms.
10. A method of fabricating an embedded flash memory, comprising: The method comprises the steps of: providing a semiconductor substrate; forming a gate stack on the semiconductor substrate, the gate stack comprising a tunneling oxide layer, a floating gate layer, a gate dielectric layer and a control gate layer stacked in sequence, the width of the tunneling oxide layer and the floating gate layer being greater than the width of the gate dielectric layer and the control gate layer, so that the tunneling oxide layer and the floating gate layer protrude on both sides of the gate dielectric layer and the control gate layer; forming an isolation sidewall and a tunneling sidewall, the isolation sidewall and the tunneling sidewall being respectively formed on the first sidewall and the second sidewall of the tunneling oxide layer, the floating gate layer, the gate dielectric layer and the control gate layer, the isolation sidewall and the tunneling sidewall having a corner at the top corner of the floating gate layer; forming a source region in the semiconductor substrate, the source region being formed in the semiconductor substrate on the side of the tunneling sidewall, and an insulating layer being formed on the source region; forming a word line gate on the side of the isolation sidewall, the word line gate being recessed inward by a distance along the protruding tunneling oxide layer and the floating gate layer; forming an erase gate on the side of the tunneling sidewall, the erase gate being formed on the insulating layer and being isolated from the source region; forming a drain region in the semiconductor substrate, the drain region being formed in the semiconductor substrate on the side of the word line gate, the region between the tunneling oxide layer and the floating gate layer being a channel region, and the width of the channel region being reduced by controlling the distance of the inward recess of the word line gate.
11. The method of claim 10, wherein: forming a gate stack on the semiconductor substrate comprises the steps of: forming a tunneling oxide layer, a floating gate layer, a gate dielectric layer, a control gate layer and a hard mask on the semiconductor substrate in sequence; patterning the hard mask, the control gate layer and the gate dielectric layer by a lithography process and an etching process; forming a sidewall structure on the sidewall of the patterned hard mask, the control gate layer and the gate dielectric layer; etching the floating gate layer and the tunneling oxide layer to pattern them by using the patterned hard mask, the control gate layer and the gate dielectric layer and the sidewall structure as a mask, wherein the width of the tunneling oxide layer and the floating gate layer protruding on the width of the gate dielectric layer and the control gate layer is controlled by controlling the width of the sidewall structure.
12. The method of claim 11, wherein: forming an isolation sidewall and a tunneling sidewall comprises the steps of: forming a first dielectric layer on the sidewall of the sidewall structure, the tunneling oxide layer and the floating gate layer; removing the sidewall structure and the first dielectric layer on the second sidewall of the tunneling oxide layer, the floating gate layer, the gate dielectric layer and the control gate layer; forming a tunneling sidewall on the second sidewall of the tunneling oxide layer, the floating gate layer, the gate dielectric layer and the control gate layer, wherein the sidewall structure, the first dielectric layer and the tunneling oxide layer on the first sidewall of the tunneling oxide layer, the floating gate layer, the gate dielectric layer and the control gate layer together form the isolation sidewall.
13. The method of claim 10, wherein: forming a word line gate and an erase gate comprises the steps of: forming a gate oxide layer on the surface of the semiconductor substrate by a thermal oxidation process; depositing a polysilicon layer on the semiconductor substrate and performing planarization to remove the excess polysilicon layer on the surface, wherein the polysilicon layer deposited on the side of the tunneling sidewall serves as the erase gate, and a groove structure is formed on the top of the erase gate by controlling the deposition parameters of the polysilicon layer; the polysilicon layer deposited on the side of the isolation sidewall serves as the word line polysilicon; The word line silicon is etched to separate the word line polysilicon into two word line gates.
14. The method of claim 13, wherein: The depth of the groove structure is 10% to 50% of the height of the erase gate. The groove structure is also filled with a metal layer, and the metal layer forms an ohmic contact with the polysilicon in the groove structure. The groove structure in the erase gate includes one of a rectangular groove, a V-shaped groove and a U-shaped groove.
15. The method of claim 10, wherein: Forming the word line gate and the erase gate includes the steps of: forming a gate oxide layer on the surface of the semiconductor substrate by a thermal oxidation process; Depositing a first polysilicon layer on the semiconductor substrate, wherein the first polysilicon layer deposited on one side of the tunnel sidewall serves as an erase gate, and the first polysilicon layer deposited on one side of the isolation sidewall serves as wordline polysilicon, and a groove structure is formed on the top of the erase gate and the top of the wordline polysilicon; Spin-coating an organic dielectric layer on the erase gate and the word line polysilicon, wherein the organic dielectric layer fills the groove structure; etching the organic dielectric layer by plasma until the first polysilicon layer is exposed, and the organic dielectric layer remains in the groove structure; selectively etching the first polysilicon layer to remove excess first polysilicon layer from the surface; removing the organic dielectric layer in the groove structure by wet etching; The word line polysilicon is etched to separate the word line polysilicon into two word line gates.
16. The method of claim 10, wherein: Forming the word line gate and the erase gate includes the steps of: forming a gate oxide layer on the surface of the semiconductor substrate by a thermal oxidation process; Depositing a first polysilicon layer on the semiconductor substrate, wherein the first polysilicon layer deposited on one side of the tunnel sidewall serves as an erase gate, and the first polysilicon layer deposited on one side of the isolation sidewall serves as wordline polysilicon, and a groove structure is formed on the top of the erase gate and the top of the wordline polysilicon; Depositing a second polysilicon layer on the erase gate and the word line polysilicon, wherein the second polysilicon layer fills the groove structure; removing the second polysilicon layer and the first polysilicon layer that are redundant on the surface by planarization; The word line polysilicon is etched to separate the word line polysilicon into two word line gates.
17. The method of claim 10, wherein: The width of the tunneling oxide layer and the floating gate layer protruding from any side of the gate dielectric layer and the control gate layer is 5 nanometers to 15 nanometers; or the width of the tunneling oxide layer and the floating gate layer is 100 nanometers to 130 nanometers, and the width of the gate dielectric layer and the control gate layer is 80 nanometers to 110 nanometers.
18. The method for manufacturing an embedded flash memory according to claim 10, wherein: The thickness of the tunneling oxide layer is 90 angstroms to 120 angstroms, the thickness of the floating gate layer is 250 angstroms to 450 angstroms, the gate dielectric layer includes a first silicon oxide layer, a silicon nitride layer located on the first silicon oxide layer, and a second silicon oxide layer located on the silicon nitride layer, the thickness of the gate dielectric layer is 130 angstroms to 170 angstroms, the thickness of the control gate layer is 500 angstroms to 700 angstroms, and the thickness of the hard mask is 500 angstroms to 1100 angstroms; the thickness of the isolation sidewall is 160 angstroms to 220 angstroms, and the thickness of the tunneling sidewall is 90 angstroms to 110 angstroms.
19. The method of claim 10, wherein: The insulating layer is covered on the source region by a thermal oxidation process, the cross section of the insulating layer on the source region is oval, and the two ends of the oval are connected with the tunneling side wall, wherein the thickness of the middle part of the insulating layer is 380-450 angstrom, and the thickness of the two ends is 150-190 angstrom.