Magnetic storage structure, magnetic memory and electronic equipment

By doping spin-orbit coupling materials into the orbital Hall layer and/or free layer, the problem of low orbit-spin conversion efficiency in the prior art is solved, and a high-efficiency, low-cost magnetic memory design is realized.

CN120835566APending Publication Date: 2025-10-24BEIJING SUPERSTRING ACAD OF MEMORY TECH +2
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Patent Information

Application Number
CN202410469414.2
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2024-04-18
Publication Date
2025-10-24

AI Technical Summary

Technical Problem

Existing technologies struggle to effectively improve orbital-spin-switching efficiency even with minor variations, leading to problems such as high memory production costs, low efficiency, and high power consumption.

Method used

By doping spin-orbit coupling materials into the orbital Hall layer and/or free layer, an orbital-spin-switching layer is formed, which enables efficient conversion of orbital flow to spin flow and reduces the need for additional film structures.

Benefits of technology

Without increasing the memory film structure, the orbital-spin switching efficiency is improved, production costs and power consumption are reduced, and the efficiency of the memory is increased.

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Abstract

A magnetic memory structure, a magnetic memory and an electronic device relate to the technical field of semiconductors, the magnetic memory structure comprises a magnetic tunnel junction, a track Hall layer and a track-spin conversion layer, the magnetic tunnel junction comprises a free layer; wherein the orbital Hall layer and / or the free layer are / is shared by the orbital-spin conversion layer; the orbital-spin conversion layer contains a spin-orbit coupling material, and the spin-orbit coupling material is doped in the orbital Hall layer and / or the free layer. The magnetic storage structure provided by the embodiment of the invention is simple in structure, and the conversion efficiency of orbital flow-spin flow is high.
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Description

TECHNICAL FIELD

[0001] Embodiments of the present application relate to the technical field of semiconductor technology, and in particular to a magnetic storage structure, a magnetic memory and an electronic device. BACKGROUND

[0002] With the development of integrated circuit technology, the critical dimension of devices is increasingly reduced, and the types and quantities of devices contained in a single chip are increased, so that a slight difference in process production can affect the performance of the devices.

[0003] In order to reduce the cost of products as much as possible, people want to make as many device units as possible on a limited substrate. Since the advent of Moore's Law, the industry has proposed various semiconductor structure designs and process optimizations to meet people's current product needs. SUMMARY

[0004] The following is a summary of the subject matter described in detail herein. This summary is not intended to limit the scope of protection of the present application.

[0005] Embodiments of the present application provide a magnetic storage structure, a magnetic memory and an electronic device, the magnetic storage structure has a simple structure, and the conversion efficiency of the orbit current-spin current is high.

[0006] Embodiments of the present application provide a magnetic storage structure, comprising: a magnetic tunnel junction, an orbit Hall layer and an orbit-spin conversion layer, the magnetic tunnel junction comprises a free layer; wherein the orbit Hall layer and / or the free layer are shared for the orbit-spin conversion layer; the orbit-spin conversion layer contains spin orbit coupling material, and the spin orbit coupling material is doped in the orbit Hall layer and / or the free layer.

[0007] In some embodiments of the present application, the spin orbit coupling material comprises a first metal having a spin orbit coupling effect.

[0008] In some embodiments of the present application, the first metal is selected from any one or more of ruthenium, rhodium, palladium, tantalum, tungsten, rhenium, osmium, platinum and gold.

[0009] In some embodiments of the present application, the doping amount of the spin orbit coupling material in the orbit Hall layer or the free layer is independently 25% to 75% by weight.

[0010] In some embodiments of the present application, the orbit Hall layer comprises a second metal having an orbit Hall effect.

[0011] In some embodiments of the present application, the second metal is selected from any one or more of titanium, manganese, chromium, vanadium, zinc and molybdenum.

[0012] In some embodiments of the present application, the magnetic tunnel junction further comprises an insulating barrier layer and a reference layer, the insulating barrier layer is located between the free layer and the reference layer.

[0013] In some embodiments of the present application, the magnetic tunnel junction further comprises an anti-ferromagnetic layer.

[0014] In some embodiments of the present application, the magnetic storage structure further comprises a protective layer, the protective layer at least surrounds the sidewall of the magnetic tunnel junction.

[0015] In some embodiments of the present application, the material of the protective layer comprises any one or more of SiN, SiO, AlO x , SiC and SiCN.

[0016] In some embodiments of the present application, the magnetic storage structure further comprises a top electrode connected with the magnetic tunnel junction.

[0017] Embodiments of the present application also provide a magnetic memory, comprising: a plurality of storage units arranged in an array on a substrate, each of the storage units comprising a magnetic storage structure as described above and two transistors, the two transistors being located between the substrate and the magnetic storage structure; the magnetic storage structure comprising a top electrode and a bottom electrode, the transistors comprising a first electrode, a second electrode, a semiconductor layer located between the first electrode and the second electrode, and a gate electrode, the semiconductor layer and the gate electrode having a gate insulating layer therebetween;

[0018] The top electrode is connected with a read bit line, the bottom electrode is connected with the first electrode of the two transistors, the second electrode of the two transistors is respectively connected with a write bit line and a source line, and the gate electrode of the two transistors is connected with a word line.

[0019] In some embodiments of the present application, the gate electrode at least partially surrounds the semiconductor layer.

[0020] Embodiments of the present application also provide an electronic device, comprising: a magnetic storage structure as described above, or comprising a magnetic memory as described above.

[0021] The magnetic storage structure of embodiments of the present application dopes spin-orbit coupling material in the orbital Hall layer and / or the free layer, so that the orbital-spin conversion layer capable of converting orbital flow into spin flow can be coupled with the orbital Hall layer or the free layer as one film layer, thereby eliminating the need for additional orbital-spin conversion layer, achieving the effect of improving orbital-spin conversion efficiency without increasing the film layer structure of the memory, and obtaining a magnetic memory with low production time, cost, high efficiency and low power consumption, such as Orbital Torque-MRAM memory.

[0022] Other features and advantages of the present application will be set forth in the following description, and in part will become apparent to those skilled in the art upon examination of the following or can be learned by practice of the present application. The features and advantages of the present application can be realized and obtained by means of the instruments and combinations particularly pointed out in the appended claims. BRIEF DESCRIPTION OF DRAWINGS

[0023] The accompanying drawings are included to provide a further understanding of the present application and are incorporated in and constitute a part of this specification, illustrate embodiments of the present application and together with the description serve to explain the principles of the present application. In the drawings:

[0024] Figure 1 A longitudinal sectional view in a vertical direction of a magnetic storage structure of an exemplary embodiment of the present application;

[0025] Figure 2 A longitudinal sectional view in a vertical direction of another magnetic storage structure of an exemplary embodiment of the present application;

[0026] Figure 3 A longitudinal sectional view in a vertical direction of still another magnetic storage structure of an exemplary embodiment of the present application;

[0027] Figure 4 A longitudinal sectional view in a vertical direction of still another magnetic storage structure of an exemplary embodiment of the present application;

[0028] Figure 5 A longitudinal sectional view in a vertical direction of a manufacturing method of an exemplary embodiment of the present application after forming a transistor and a bottom electrode in a substrate;

[0029] Figure 6 A longitudinal sectional view in a vertical direction of a manufacturing method of an exemplary embodiment of the present application after forming a mask layer;

[0030] Figure 7 A longitudinal sectional view in a vertical direction of a manufacturing method of an exemplary embodiment of the present application after forming a patterned protective layer;

[0031] Figure 8 A longitudinal sectional view in a vertical direction of a manufacturing method of an exemplary embodiment of the present application after depositing an insulating material on a substrate surface;

[0032] Figure 9 A longitudinal sectional view in a vertical direction of a magnetic storage structure obtained by a manufacturing method of an exemplary embodiment of the present application;

[0033] Figure 10 A longitudinal sectional view in a vertical direction of a magnetic storage structure of an exemplary embodiment of the present application;

[0034] The meanings of the reference symbols in the drawings are as follows:

[0035] 10 - magnetic tunnel junction; 11 - free layer; 12 - insulating barrier layer; 13 - reference layer; 14 - anti-ferromagnetic layer; 20 - orbital Hall layer; 30 - orbital-to-spin conversion layer; 31 - first orbital-to-spin conversion layer; 32 - second orbital-to-spin conversion layer; 40 - shield layer; 50 - mask layer; 60 - top electrode; 70 - protection layer; 80 - substrate; 81 - bottom electrode; 90 - transistor; 91 - first electrode; 92 - second electrode; 93 - semiconductor layer; 94 - gate electrode; 100 - memory cell; RBL - read bit line; WBL - write bit line; WL - word line; SL - source line. DETAILED DESCRIPTION

[0036] For the purpose of making the object, technical scheme and advantages of the present application more clear, the embodiments of the present application will be described in detail below with reference to the drawings. It should be noted that the embodiments in the present application and the features in the embodiments can be combined with each other as long as there is no conflict.

[0037] The embodiments of the present application are not necessarily limited to the sizes shown in the drawings, and the shapes and sizes of the components in the drawings are preferred embodiments, and other shapes and sizes can also be used. In addition, the drawings schematically show ideal examples, and the embodiments of the present application are not limited to the shapes or values shown in the drawings.

[0038] The size and proportion relationship between each film layer or component in the drawings of the present application can be used as a reference in the actual process, which is a better technical effect embodiment, but is not limited thereto. For example, the thickness and spacing of each film layer can be adjusted according to actual needs.

[0039] In the present application, for the convenience, the words indicating the orientation or position relationship such as "middle", "upper", "lower", "front", "rear", "vertical", "horizontal", "top", "bottom", "inner", "outer" and the like are used to describe the position relationship of the components with reference to the drawings, which are only for the convenience of describing the present specification and simplifying the description, and do not indicate or imply that the indicated device or element must have a particular orientation, be constructed and operated in a particular orientation, and therefore cannot be understood as a limitation on the present application. The position relationship of the components is appropriately changed according to the direction of describing each component. Therefore, it is not limited to the words described in the disclosure, and can be appropriately changed according to the situation.

[0040] In this application, unless otherwise explicitly specified and limited, the terms "mount", "connected", "connection" should be understood broadly. For example, it can be fixedly connected, or detachably connected, or integrally connected; it can be mechanically connected, or electrically connected; it can be directly connected, or indirectly connected through an intermediate piece, or the connection between two elements inside. For those skilled in the art, the specific meaning of the above terms in this application can be understood according to the specific circumstances.

[0041] In this application, a transistor refers to an element including at least three terminals of gate electrode, drain electrode and source electrode. The transistor has a channel region between the drain electrode (drain electrode terminal, drain region or drain electrode) and the source electrode (source electrode terminal, source region or source electrode), and current can flow through the drain electrode, the channel region and the source electrode. In this application, the channel region refers to the region through which current mainly flows.

[0042] In this application, "electrically connected" or "connected" includes the case where the constituent elements are connected together through an element having a certain electrical effect, such as electrical signal connection (coupled to), or physical direct connection. The element having a certain electrical effect is not particularly limited as long as it can perform the transmission and reception of electrical signals between the connected constituent elements. Examples of the element having a certain electrical effect include not only electrodes and wiring, but also switching elements such as transistors, resistors, inductors, capacitors, other elements having various functions, and the like.

[0043] In this application, "film" and "layer" can be exchanged with each other. For example, "protective layer" can be replaced by "protective film" sometimes.

[0044] In the description of this application, "orbital Hall layer" is defined as a film layer capable of generating orbital Hall effect; "orbital-spin conversion layer" is defined as a film layer capable of converting orbital flow into spin flow; "spin-orbit coupling material" is defined as a material having spin-orbit coupling effect.

[0045] Conventional spin orbit torque-magnetic random access memory (SOT-MRAM) relies on heavy metal materials with strong spin orbit coupling effect to generate spin current through spin Hall effect. However, recent studies have shown that many light metals have strong orbital Hall effect, which can also act on the ferromagnetic free layer to cause it to flip through orbital-spin conversion. However, only light metal layer cannot obtain high orbital-spin conversion efficiency.

[0046] The application aims to provide a magnetic storage structure (e.g., Orbital Torque-MRAM) with high orbital-spin conversion efficiency and a magnetic memory without increasing the film layer structure of the memory.

[0047] Specifically, the application provides a magnetic storage structure. Figure 1 A longitudinal sectional view in a vertical direction of a magnetic storage structure according to an exemplary embodiment of the application is shown in FIG. 1. Figure 2 A longitudinal sectional view in a vertical direction of another magnetic storage structure according to an exemplary embodiment of the application is shown in FIG. 2. Figure 3 A longitudinal sectional view in a vertical direction of still another magnetic storage structure according to an exemplary embodiment of the application is shown in FIG. 3. Figures 1 to 3 As shown in the figure, the magnetic storage structure comprises a magnetic tunnel junction 10, an orbital Hall layer 20 and an orbital-spin conversion layer 30.

[0048] The magnetic tunnel junction 10 comprises a free layer 11, which is in contact with the orbital Hall layer 20.

[0049] The orbital Hall layer 20 and / or the free layer 11 are shared as the orbital-spin conversion layer 30.

[0050] The orbital-spin conversion layer 30 contains spin-orbit coupling material, which is doped in the orbital Hall layer 20 and / or the free layer 11.

[0051] The magnetic storage structure according to the application dopes the spin-orbit coupling material in the orbital Hall layer and / or the free layer, so that the orbital-spin conversion layer capable of converting orbital flow into spin flow and the orbital Hall layer or the free layer can be coupled as one film layer, thereby achieving the effect of improving the orbital-spin conversion efficiency without increasing the film layer structure of the memory, and obtaining a magnetic memory with low production time, cost, high efficiency and low power consumption, such as an Orbital Torque-MRAM memory.

[0052] In some embodiments of the application, as shown in the figure, the spin-orbit coupling material can be doped only in the free layer 11, without doping in the orbital Hall layer 20, i.e., the orbital-spin conversion layer 30 and the free layer 11 are one film layer. Figure 1 Figure 2 ​As shown, the spin-orbit coupling material can be doped only in the orbit Hall layer 20, without doping in the free layer 11, i.e., the orbit-spin conversion layer 30 is the same film layer as the orbit Hall layer 20; in some other embodiments of the present application, the spin-orbit coupling material is doped in both the orbit Hall layer 20 and the free layer 11, and the orbit-spin conversion layer 30 is two layers, i.e., a first orbit-spin conversion layer 31 and a second orbit-spin conversion layer 32, wherein the first orbit-spin conversion layer 31 is the same film layer as the orbit Hall layer 20, and the second orbit-spin conversion layer 32 is the same film layer as the free layer 11.

[0053] In some embodiments of the present application, the spin-orbit coupling material can include a first metal having a spin-orbit coupling effect.

[0054] In some embodiments of the present application, the first metal can have a density > 5 g / cm 3 and a metal having a spin-orbit coupling effect.

[0055] In some embodiments of the present application, the first metal can have 5d atomic orbitals.

[0056] In some embodiments of the present application, the first metal can be selected from any one or more of ruthenium (Ru), rhodium (Rh), palladium (Pd), tantalum (Ta), tungsten (W), rhenium (Re), osmium (Os), platinum (Pt), and gold (Au).

[0057] In some embodiments of the present application, the spin-orbit coupling material can be doped in the orbit Hall layer or the free layer in an amount independently selected from 25 wt% to 75 wt%. When the spin-orbit coupling material is doped in the orbit Hall layer or the free layer in an amount ranging from 25 wt% to 75 wt%, the conversion efficiency of orbit current-spin current is higher, and the doping of the spin-orbit coupling material does not affect the performance of the orbit Hall layer or the free layer. For example, the spin-orbit coupling material can be doped in the orbit Hall layer or the free layer in an amount independently selected from 25 wt%, 30 wt%, 35 wt%, 40 wt%, 45 wt%, 50 wt%, 55 wt%, 60 wt%, 65 wt%, 70 wt%, or 75 wt%.

[0058] In some embodiments of the present application, the orbit Hall layer can include a second metal having an orbit Hall effect.

[0059] In some embodiments of the present application, the second metal can have a density < 5 g / cm 3In some embodiments of the present application, the second metal may be selected from any one or more of titanium (Ti), manganese (Mn), chromium (Cr), vanadium (V), zinc (Zn) and molybdenum (Mo).

[0060] In some embodiments of the present application, Figures 1 to 3 As shown, the magnetic tunnel junction may further include an insulating barrier layer 12 and a reference layer 13 , wherein the insulating barrier layer 12 is located between the free layer 11 and the reference layer 13 .

[0061] In some embodiments of the present application, Figures 1 to 3 As shown, the magnetic tunnel junction further includes an antiferromagnetic layer 14 .

[0062] In some embodiments of the present application, the magnetic tunnel junction may include multiple film layers; for example, the magnetic tunnel junction may include a reference layer (also called a pinned layer, a fixed layer), an insulating barrier layer and a free layer in sequence along the direction close to the substrate; for another example, the magnetic tunnel junction may include a synthetic antiferromagnetic layer, a reference layer, an insulating barrier layer and a free layer in sequence along the direction close to the substrate; for another example, the magnetic tunnel junction may include a synthetic antiferromagnetic layer, a ferromagnetic coupling layer, a reference layer, an insulating barrier layer and a free layer in sequence along the direction close to the substrate.

[0063] In some embodiments of the present application, the total thickness of the magnetic tunnel junction may be 10 nm to 20 nm, and have a top pinned structure.

[0064] In some embodiments of the present application, the reference layer has magnetic polarization invariance. The reference layer of the perpendicular MRAM (pSOT-MRAM) generally includes [Co / Ni] n Co / (Ru or Ir) / Co[Ni / Co] m 、[Co / Pd] n Co / (Ru or Ir) / Co[Pd / Co] m , or [Co / Pt] n Co / (Ru or Ir) / Co[Pt / Co] m The superlattice multilayer film structure has a value of 0≤m≤3 and 2≤n≤7, and can achieve ferromagnetic coupling with cobalt iron boron (CoFeB), cobalt iron (CoFe) / cobalt iron boron (CoFeB), cobalt iron (CoFe) / nickel iron alloy (NiFe), cobalt boride (CoB) or iron boride (FeB) through a lattice isolation layer; the total thickness of the reference layer can be 4nm to 15nm.

[0065] In some embodiments of the present application, the material of the barrier layer can be a non-magnetic metal oxide, for example, can be magnesium oxide (MgO), magnesium zinc oxide (MgZnO), magnesium boron oxide (MgBO), magnesium aluminum oxide (MgAlO), and preferably is magnesium oxide (MgO); the thickness of the insulating barrier layer can be 0.5 nm to 2.5 nm.

[0066] In some embodiments of the present application, the top electrode includes any one or more of Fe, Co, Ni, Cr, Cu, Zn, Si, Pt, Sm, Nd, C, N, B and O.

[0067] Figure 4 Another magnetic storage structure according to an exemplary embodiment of the present application is shown in a longitudinal cross-sectional view in the vertical direction. In some embodiments of the present application, as shown in FIG. 4, the magnetic storage structure further includes a shielding layer 40, a mask layer 50 and a top electrode 60 connected to the magnetic tunnel junction 10. The shielding layer 40 functions to prevent the reference layer 13 from contacting the top electrode. Figure 4

[0068] In some embodiments of the present application, the material of the shielding layer 40 can include any one or more of SiN, SiO, AlO x , SiC and SiCN.

[0069] In some embodiments of the present application, the mask layer 50 can be a hard mask layer (HM), and the material thereof can be tantalum (Ta), tantalum nitride (TaN) or tantalum (Ta) / tantalum nitride (TaN); the thickness of the hard mask layer can be 20 nm to 100 nm.

[0070] As shown in FIG. 6, in some embodiments of the present application, the magnetic storage structure further includes a protective layer 70, which at least surrounds the sidewall of the magnetic tunnel junction 10. Figure 4

[0071] The protective layer 70 can protect the magnetic tunnel junction 10 from being damaged in subsequent etching processes. For example, the magnetic tunnel junction is usually formed first and then the top electrode is formed. In the patterning and etching process of the top electrode, the magnetic tunnel junction is easily damaged. The presence of the protective layer 70 can avoid the damage of the magnetic tunnel junction.

[0072] As shown in FIG. 7, in some embodiments of the present application, the magnetic tunnel junction 10 includes the sidewall and the top surface of the track Hall layer 20, and the protective layer 70 can cover the sidewall of the magnetic tunnel junction 10 and extend to the top surface of the magnetic tunnel junction 10. Figure 4

[0073] As shown in FIG. 8, in some embodiments of the present application, the magnetic tunnel junction 10 includes the sidewall and the top surface of the track Hall layer 20, and the protective layer 70 can cover the sidewall of the magnetic tunnel junction 10 and extend to the top surface of the magnetic tunnel junction 10. Figure 4 ​​​As shown, the protection layer 70 may include an annular cap that covers the sidewalls of the magnetic tunnel junction 10 and extends to the top surface of the magnetic tunnel junction 10 .

[0074] In some embodiments of the present application, the protective layer includes SiN, SiO, AlO x , any one or more of SiC and SiCN.

[0075] In some embodiments of the present application, the magnetic storage structure may include a plurality of magnetic tunnel junctions distributed in an array, and the plurality of magnetic tunnel junctions may be located on the same side of a track Hall layer.

[0076] In some embodiments of the present application, Figure 4 As shown, the magnetic storage structure may be located on a substrate 80 , and the substrate 80 may include a plurality of bottom through holes, wherein bottom electrodes 81 , such as bottom metal wires, are disposed in the bottom through holes.

[0077] In some embodiments of the present application, Figure 1 As shown, the magnetic storage structure may further include a plurality of transistors 90 , one end of the bottom electrode 81 is electrically connected to the transistor 90 , and the other end of the bottom electrode 81 is electrically connected to the track Hall layer 20 .

[0078] In some embodiments of the present application, the transistor 90 may be a vertical channel transistor. Figures 5 to 9 As shown, in one exemplary embodiment, the magnetic memory structure described above can be obtained by the following manufacturing method.

[0079] S10: providing a substrate 80, and forming a plurality of spaced-apart transistors 90 in the substrate 80, for example, vertical channel transistors, wherein the transistors 90 are respectively connected to a write bit line WBL (Write Bit Line) and a source line SL (Source Line), and two transistors 90 are connected to the same word line WL (Word Line);

[0080] A bottom through hole is formed on the top of each transistor 90, and a bottom electrode 81 connected to the transistor 90 is provided in the bottom through hole. Figure 5 shown.

[0081] S20: Depositing the track Hall layer 20, various film layers of the magnetic tunnel junction, the shielding layer 40 and the mask layer 50 on the surface of the substrate 80, wherein the free layer 11, the insulating barrier layer 12, the reference layer 13 and the antiferromagnetic layer 14 of the magnetic tunnel junction can be deposited in sequence in the direction away from the track Hall layer 20, as shown in FIG. Figure 6 In this embodiment, the free layer 11 is doped with a spin-orbit coupling material, so the free layer 11 also functions as an orbit-spin conversion layer 30 .

[0082] S30: patterning and etching each film layer of the magnetic tunnel junction, the shielding layer 40 and the mask layer 50 to obtain an array of patterned magnetic tunnel junctions 10 on the track Hall layer 20; depositing a protective layer 70 covering the array of magnetic tunnel junctions 10 on the surface of the substrate 80, patterning and etching the protective layer 70 to form a cap structure around the sidewall of the magnetic tunnel junction 10, as shown in Figure 7 .

[0083] S40: depositing an insulating material covering the track Hall layer 20 and the protective layer 70 on the surface of the substrate 80, as shown in Figure 8 .

[0084] S50: forming a top electrode 60 connected with the patterned mask layer 50 on the top surface of each magnetic tunnel junction 10, as shown in Figure 9 .

[0085] The embodiments of the present application also provide a magnetic memory. Figure 10 Fig. 1 is a schematic diagram of a longitudinal section of a magnetic memory in the vertical direction according to an example embodiment of the present application.

[0086] As shown in Figure 10 , the magnetic memory comprises a plurality of memory cells 100, a read bit line RBL, a write bit line WBL, a word line WL and a source line SL;

[0087] The plurality of memory cells 100 are arranged in an array on a substrate 80, each memory cell 100 comprising one magnetic storage structure as described above and two transistors 90, the magnetic storage structure and the transistors 90 being stacked on the substrate 80, the two transistors 90 being between the substrate 80 and the magnetic storage structure;

[0088] Each magnetic storage structure comprises one top electrode 60 and two bottom electrodes 81;

[0089] The transistor 90 comprises a first electrode 91, a second electrode 92, a semiconductor layer 93 between the first electrode 91 and the second electrode 92, and a gate electrode 94, with a gate insulating layer (not shown in the figure) between the semiconductor layer 93 and the gate electrode 94;

[0090] The top electrode 60 is connected with the read bit line RBL, the two bottom electrodes 81 are respectively connected with the two first electrodes 91 of the two transistors 90, the second electrodes 92 of the two transistors 90 are respectively connected with the write bit line WBL and the source line SL, and the gate electrodes 94 of the two transistors 90 are connected with the same word line WL.

[0091] In some embodiments of the present application, the gate electrode 94 at least partially surrounds the semiconductor layer 93.

[0092] The application further provides an electronic device comprising the magnetic storage structure.

[0093] In some embodiments of the application, the electronic device can be a storage device, a smartphone, a computer, a tablet computer, an artificial intelligence device, a wearable device, a mobile power supply, or the like. The storage device can include a memory in a computer, and the like, which is not limited herein.

[0094] Although the embodiments disclosed in the present application are as above, the content described is only the embodiments adopted for the purpose of facilitating the understanding of the present application, and is not intended to limit the present application. Any person skilled in the art of the present application can make any modification and change in the form and details without departing from the spirit and scope of the present application. The protection scope of the present application shall be subject to the scope defined by the appended claims.

Claims

1. A magnetic storage structure, characterized by, The magnetic tunnel junction, the orbital Hall layer and the orbital-spin conversion layer, the magnetic tunnel junction comprising a free layer; wherein the orbital Hall layer and / or the free layer are shared as the orbital-spin conversion layer; The orbital-spin conversion layer contains a spin-orbit coupling material, the spin-orbit coupling material being doped in the orbital Hall layer and / or the free layer. The spin-orbit coupling material comprises a first metal having a spin-orbit coupling effect.

2. The magnetic storage structure of claim 1, wherein, The first metal is selected from any one or more of ruthenium, rhodium, palladium, tantalum, tungsten, rhenium, osmium, platinum and gold.

3. The magnetic storage structure of claim 2, wherein, The doping amount of the spin-orbit coupling material in the orbital Hall layer or the free layer is each independently 25 wt% to 75 wt%.

4. The magnetic storage structure of any one of claims 1 to 3, wherein, The orbital Hall layer comprises a second metal having an orbital Hall effect.

5. The magnetic storage structure of any one of claims 1 to 3, wherein, The second metal is selected from any one or more of titanium, manganese, chromium, vanadium, zinc and molybdenum.

6. The magnetic storage structure of claim 5, wherein, The magnetic tunnel junction further comprises an insulating barrier layer and a reference layer, the insulating barrier layer being located between the free layer and the reference layer.

7. The magnetic storage structure of any one of claims 1 to 3, wherein, The magnetic tunnel junction further comprises an anti-ferromagnetic layer; and / or, 8. The magnetic storage structure of claim 7, wherein, The magnetic storage structure further comprises a protective layer, the protective layer at least surrounding the sidewall of the magnetic tunnel junction; and / or, The magnetic storage structure further comprises a top electrode connected with the magnetic tunnel junction. The magnetic storage structure comprises:

9. The magnetic storage structure of claim 8, wherein, The material of the protective layer comprises any one or more of SiN, SiO, AlO x , SiC and SiCN.

10. A magnetic memory, comprising: An array of a plurality of memory cells on a substrate, each of the memory cells comprising a magnetic storage structure according to any one of claims 1 to 9 and two transistors between the substrate and the magnetic storage structure; the magnetic storage structure comprising a top electrode and a bottom electrode, the transistors comprising a first electrode, a second electrode, a semiconductor layer between the first electrode and the second electrode and a gate electrode, the semiconductor layer and the gate electrode having a gate insulating layer therebetween; The top electrode is connected with a read bit line, the bottom electrode is connected with the first electrode of the two transistors, the second electrode of the two transistors is respectively connected with a write bit line and a source line, and the gate electrode of the two transistors is connected with a word line. The gate electrode at least partially surrounds the semiconductor layer.

11. The magnetic memory of claim 10 wherein, The magnetic storage structure according to any one of claims 1 to 9, or the magnetic memory comprising the magnetic storage structure according to claim 10 or 11.

12. An electronic device, comprising: ​ ​