Semiconductor device

Abstract

A semiconductor device having improved device performance and reliability includes: a substrate; an active pattern including a plurality of channel patterns disposed on the substrate and vertically spaced apart from each other; a gate electrode surrounding the plurality of channel patterns; a lower source / drain pattern disposed on the substrate and disposed on one side of the plurality of channel patterns; an upper source / drain pattern spaced upward from the lower source / drain pattern; and sidewall spacers including a first sidewall spacer in contact with a first side surface of the lower source / drain pattern and defining the first side surface, and a second sidewall spacer in contact with a second side surface of the lower source / drain pattern and defining the second side surface, the first side surface and the second side surface are opposite side surfaces of the lower source / drain pattern.

Description

TECHNICAL FIELD

[0001] The disclosure relates to a semiconductor device. BACKGROUND

[0002] Semiconductor devices are core components for controlling or amplifying an electrical signal in an electronic device, and various types of semiconductor devices can be manufactured. For example, a memory device can be mainly used for storing and retrieving data, and a non-memory device can be used for controlling or amplifying an electrical signal. Semiconductor devices are core components of electronic devices and play an important role in various fields including computers, communication devices, consumer electronics, etc.

[0003] As industries develop, the performance and functionality of electronic devices are also increasing. Therefore, high performance characteristics of semiconductor devices are essentially required, and the integration of semiconductor devices is increasing to meet these requirements. Various methods for forming semiconductor devices with excellent performance and improved integration are being researched. SUMMARY

[0004] Embodiments of the disclosure provide a semiconductor device with improved electrical characteristics and reliability.

[0005] According to some aspects of the disclosure, a semiconductor device can include a substrate, an active pattern including a plurality of channel patterns disposed on the substrate and spaced apart vertically from each other, a gate electrode surrounding the plurality of channel patterns, a lower source / drain pattern disposed on the substrate and disposed on one side of the plurality of channel patterns, an upper source / drain pattern spaced apart upward from the lower source / drain pattern, and a sidewall spacer including a first sidewall spacer in contact with a first side surface of the lower source / drain pattern and a second sidewall spacer in contact with a second side surface of the lower source / drain pattern, wherein the first side surface and the second side surface can be opposite side surfaces of the lower source / drain pattern.

[0006] According to some aspects of the disclosure, a semiconductor device can include a substrate, an active pattern including a lower pattern disposed on the substrate and a plurality of channel patterns spaced apart from each other, wherein the plurality of channel patterns can include a lower channel pattern disposed on the lower pattern and a first upper channel pattern disposed on the lower channel pattern, a gate electrode surrounding the lower channel pattern and the first upper channel pattern, a lower source / drain pattern disposed on the lower pattern and disposed on one side of the lower channel pattern, an upper source / drain pattern disposed on one side of the first upper channel pattern, and a sidewall spacer disposed on two opposite side surfaces of the lower source / drain pattern, wherein at least one of the lower source / drain pattern and the upper source / drain pattern can include a plurality of epitaxial layers.

[0007] According to some aspects of the disclosure, a semiconductor device can include a substrate, an active pattern including a lower pattern extending in a first direction and disposed on the substrate and a plurality of channel patterns spaced apart from each other in a second direction perpendicular to the first direction, wherein each of the plurality of channel patterns can include a lower channel pattern disposed on the lower pattern and an upper channel pattern disposed on the lower channel pattern, a gate electrode surrounding each of the lower channel pattern and the upper channel pattern, a lower source / drain pattern disposed on the lower pattern and disposed at least one side of the lower channel pattern, an upper source / drain pattern disposed at least one side of the upper channel pattern, a dielectric spacer isolating the lower source / drain pattern and the upper source / drain pattern from each other such that the lower source / drain pattern and the upper source / drain pattern are spaced apart from each other, and a sidewall spacer including a first sidewall spacer in contact with and defining a first side surface of the lower source / drain pattern and a second sidewall spacer in contact with and defining a second side surface of the lower source / drain pattern, wherein the first side surface and the second side surface can be opposite side surfaces of the lower source / drain pattern, wherein the first sidewall spacer and the second sidewall spacer can be disposed such that a horizontal distance between the first sidewall spacer and the second sidewall spacer decreases in a direction approaching a top of the first sidewall spacer and the second sidewall spacer, the lower source / drain pattern and the upper source / drain pattern can have different conduction types, and at least one of the lower source / drain pattern and the upper source / drain pattern can include a plurality of epitaxial layers.

[0008] According to some aspects of the disclosure, the sidewall spacer is disposed at both sides of the lower source / drain pattern to limit a shape of the lower source / drain pattern to correspond to a channel width, thereby improving performance of the semiconductor device.

[0009] According to some aspects of the disclosure, by forming a heavily doped epitaxial layer of a constituent material capable of applying strain to a channel pattern, for example, germanium (Ge), around an outer side / surface of a lightly doped epitaxial layer of the same constituent material connecting adjacent channel patterns, defects caused by the heavily doped epitaxial layer contacting the channel pattern can be prevented, and performance of the semiconductor device can be improved. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above and other objects, features and advantages of the disclosure will become more clearly understood through detailed description of exemplary embodiments of the disclosure with reference to the attached drawings.

[0011] Figure 1 is provided to explain a plan view of a semiconductor device according to some aspects of the disclosure.

[0012] Figure 2 is a cross-sectional view taken along line A-A of Figure 1 .

[0013] Figure 3 is a sectional view taken along the line B-B of Figure 1

[0014] Figure 4 is a diagram provided to explain a semiconductor device according to some aspects of the present disclosure.

[0015] Figure 5 is a diagram provided to explain a dielectric isolation layer according to some aspects of the present disclosure.

[0016] Figure 6 is a diagram provided to explain a semiconductor device according to some aspects of the present disclosure.

[0017] Figure 7 is a diagram provided to explain a semiconductor device according to some aspects of the present disclosure.

[0018] Figure 8 is a diagram provided to explain a semiconductor device according to some aspects of the present disclosure.

[0019] Figure 9 is a diagram provided to explain a semiconductor device according to some aspects of the present disclosure.

[0020] Figure 10 is a diagram provided to explain a semiconductor device according to some aspects of the present disclosure.

[0021] Figure 11 is a diagram provided to explain a semiconductor device according to some aspects of the present disclosure.

[0022] Figure 12 is a diagram provided to explain a semiconductor device according to some aspects of the present disclosure.

[0023] Figure 13 is a diagram provided to explain Figure 12 a region R of

[0024] Figures 14 to 30 is a diagram showing intermediate stages provided to explain a method for manufacturing a semiconductor device according to some aspects of the present disclosure. DETAILED DESCRIPTION

[0025] Throughout this specification, unless the context clearly indicates otherwise, whenever a component is described as "comprising" a particular element or group of elements, it is understood that the component can only consist of that particular element or group of elements, or that particular element or group of elements can be combined with additional elements in order to create the component. On the other hand, the term "consisting of means that the component only consists of the listed elements.

[0026] ​Numerals such as "first," "second," "third," etc. can simply be used as labels to distinguish between particular elements, steps, etc. from one another. Terms of description that are not described using "first," "second," etc. in the specification can still be referred to as "first" or "second" in the claims. In addition, terms referenced using a particular numeral (e.g., "first" in a particular claim) can be described elsewhere using a different numeral (e.g., "second" in the specification or another claim).

[0027] It will be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element or intervening elements can be present. In contrast, when an element is referred to as being "directly connected" or "directly coupled" to another element, there are no intervening elements present. It will be understood that, although the terms "first," "second," etc. can be used herein to describe various elements, these elements should not be limited by these terms since such elements are commonly known with

[0028] To facilitate description, spatially relative terms such as "beneath," "below," "lower," "above," "upper," "top," "bottom," "front," "rear," and the like can be used herein to describe the position relationship between the elements shown in the drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in addition to the orientation depicted in the drawings.

[0029] Hereinafter, example details for practicing the present disclosure will be described in detail with reference to the accompanying drawings.

[0030] First, a semiconductor device according to some aspects of the present disclosure will be described with reference to Figures 1 to 3 A semiconductor device according to some aspects of the present disclosure will be described.

[0031] Figure 1 is a plan view provided to explain a semiconductor device according to some aspects of the present disclosure. Figure 2 is a cross-sectional view taken along line A-A of Figure 1 Figure 3 is a cross-sectional view taken along line B-B of Figure 1

[0032] With reference to Figures 1 to 3 , a semiconductor device according to some aspects can include a substrate 100, an active pattern AP, a gate electrode 120, a gate insulating film 130, source and drain patterns 150 and 250, a sidewall spacer 160_SW, a dielectric isolation layer 140, and a gate spacer 160_GS. As used herein, each of the source and drain patterns 150 and 250 can be a pattern that functions as a source pattern and / or a drain pattern of a transistor, and can also be denoted as a source / drain pattern in the claims and / or in other parts of the present disclosure. ​​

[0033] Semiconductor devices according to some aspects can include metal oxide semiconductor field effect transistors (MOSFETs), and for example, can include gate-all-around (GAA) transistors and three-dimensional multi-stacked semiconductor devices referred to as multi-bridge-channel FETs (MBCFETs). The three-dimensional multi-stacked semiconductor devices can be designed such that semiconductor channel regions of n-type FETs (nFETs) and semiconductor channel regions of p-type FETs (pFETs) are stacked by placing one on the other.

[0034] The substrate 100 can be bulk silicon or silicon-on-insulator (SOI). On the other hand, the substrate 100 can include silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimony, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimony, but is not limited thereto.

[0035] The active pattern AP can be disposed on the substrate 100. The active pattern AP can extend in a first direction D1 (e.g., longitudinally). The active pattern AP can be spaced apart from an adjacent active pattern AP in a second direction D2. In this case, the first direction D1 is a (e.g., perpendicular) direction crossing the second direction D2. Each of the first direction D1 and the second direction D2 can be a direction parallel to an upper surface of the substrate 100.

[0036] The active pattern AP can be a multi-channel active pattern. The active pattern AP can include a lower pattern BP and a plurality of channel patterns CP.

[0037] The lower pattern BP can protrude from the substrate 100. The lower pattern BP can extend in the first direction D1 (e.g., longitudinally). The lower pattern BP can be spaced apart from an adjacent lower pattern BP in the second direction D2. The lower patterns BP adjacent to each other can be divided by a field trench FT. The field trench FT can be defined by an upper surface of the substrate 100 and a side surface of the lower pattern BP.

[0038] The plurality of channel patterns CP can be disposed on the lower pattern BP. The plurality of channel patterns CP can be spaced apart from the lower pattern BP in a third direction D3. Each of the channel patterns CP can be spaced apart from each other in the third direction D3. The third direction D3 can be a (e.g., perpendicular) direction crossing each of the first direction D1 and the second direction D2. The third direction D3 can be a direction perpendicular to the upper surface of the substrate 100. The third direction D3 can be a thickness direction of the substrate 100. Accordingly, the plurality of channel patterns CP can be disposed on the lower pattern BP on the substrate 100 and vertically spaced apart from each other. Each channel pattern CP can have a nanosheet shape.

[0039] The plurality of channel patterns CP can include a lower channel pattern CP_B and an upper channel pattern CP_U. The lower channel pattern CP_B can be disposed on the lower pattern BP, and the upper channel pattern CP_U can be disposed on the lower channel pattern CP_B. The lower channel pattern CP_B and the upper channel pattern CP_U can be opposite conductive types, but according to design, the lower channel pattern CP_B and the upper channel pattern CP_U can also be the same conductive type. In Figure 2 two layers (e.g., the lower channel pattern CP_B and the upper channel pattern CP_U) are shown, but the inventive concept is not limited thereto. Also, in Figure 2 two lower channel patterns CP_B and two upper channel patterns CP_U are shown, but the inventive concept is not limited thereto.

[0040] The lower pattern BP can be formed by etching a portion of the substrate 100. However, the inventive concept is not limited thereto. For example, the lower pattern BP can include an epitaxial layer grown from the substrate 100. The lower pattern BP can include an elemental semiconductor material such as silicon (Si) or germanium (Ge). In certain embodiments, the lower pattern BP can include a compound semiconductor. For example, the lower pattern BP can include a group IV-IV compound semiconductor or a group III-V compound semiconductor.

[0041] For example, the group IV-IV compound semiconductor can be a binary compound or a ternary compound including at least two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn).

[0042] For example, the group III-V compound semiconductor can be one of a binary compound, a ternary compound, and a quaternary compound formed by a combination of at least one of aluminum (Al), gallium (Ga), and indium (In) as a group III element and one of phosphorus (P), arsenic (As), and antimony (Sb) as a group V element.

[0043] The channel pattern CP can include one of an elemental semiconductor material such as silicon (Si) or silicon germanium (SiGe), a group IV-IV compound semiconductor, and a group III-V compound semiconductor. Each of the plurality of channel patterns CP can include the same material as the lower pattern BP, or can include a different material from the lower pattern BP.

[0044] The lower pattern BP and the plurality of channel patterns CP can include silicon (Si). In some embodiments, the lower pattern BP and the plurality of channel patterns CP can include silicon germanium (SiGe). In certain embodiments, the lower pattern BP can include silicon (Si), and the plurality of channel patterns CP can include silicon germanium (SiGe).

[0045] A field insulating film 105 can be disposed on the substrate 100. The field insulating film 105 can fill a portion of the field trench FT. The field insulating film 105 can be disposed between the lower patterns BP adjacent to each other. The field insulating film 105 can extend in the first direction D1 (e.g., longitudinally). The field insulating film 105 can be formed on an upper surface of the substrate 100. The field insulating film 105 can cover a portion of the sidewall of the lower pattern BP. For example, as shown in FIG. 1B, the field insulating film 105 can cover the sidewall of the lower pattern BP, but can not be disposed on an upper surface of the lower pattern BP. For example, the field insulating film 105 can not be disposed between the upper surface of the lower pattern BP and the lower channel pattern CP_B. Figure 3 The field insulating film 105 can be formed of an oxide, a nitride, an oxynitride, or a combination thereof. Although the field insulating film 105 is shown as a single layer in

[0046] For example, the field insulating film 105 can include an oxide, a nitride, an oxynitride, or a combination thereof. Although the field insulating film 105 is shown as a single layer in Figure 3 The field insulating film 105 can be formed of an oxide, a nitride, an oxynitride, or a combination thereof. Although the field insulating film 105 is shown as a single layer in

[0047] The source and drain patterns 150 and 250 can include a lower source and drain pattern 150 and an upper source and drain pattern 250. The lower source and drain pattern 150 and the upper source and drain pattern 250 can have opposite conductive types. For example, the lower source and drain pattern 150 can have n-type conductivity, and the upper source and drain pattern 250 can have p-type conductivity. On the other hand, the lower source and drain pattern 150 can have p-type conductivity, and the upper source and drain pattern 250 can have n-type conductivity. In another example, the lower source and drain pattern 150 and the upper source and drain pattern 250 can have the same conductive type.

[0048] The source and drain patterns 150 and 250 can be disposed in source and drain trenches 150_R extending along the third direction D3 (e.g., longitudinally). As used herein, the source and drain trenches 150_R can be trenches that form one or more source / drain patterns, and the source and drain trenches 150_R can be denoted as source / drain trenches in claims and / or in other portions of the present disclosure. The source and drain patterns 150 and 250 can fill at least a portion of the source and drain trenches 150_R. For example, the lower source and drain patterns 150 and the upper source and drain patterns 250 can fill lower and upper portions of the source and drain trenches 150_R, respectively. A dielectric isolation layer 140 isolating the lower source and drain patterns 150 and the upper source and drain patterns 250 from each other can be included / forming between the lower source and drain patterns 150 and the upper source and drain patterns 250. For example, the dielectric isolation layer 140 can be disposed between the lower source / drain patterns 150 and the upper source / drain patterns 250 such that the lower source / drain patterns 150 and the upper source / drain patterns 250 are isolated (e.g., spaced apart) from each other.

[0049] A lower / bottom surface of the source and drain trenches 150_R can be defined by the lower pattern BP. Side surfaces or sidewalls of the source and drain trenches 150_R on the first direction D1 can be defined by the lower pattern BP, the channel pattern CP, and sidewalls or side surfaces of the gate insulating film 130. Side surfaces or sidewalls of the source and drain trenches 150_R on the second direction D2 can be defined by the sidewall spacers 160_SW.

[0050] The source and drain patterns 150 and 250 can be disposed on and at least one side of the active pattern AP.

[0051] For example, the lower source and drain patterns 150 can be disposed on the lower pattern BP. The lower source and drain patterns 150 can be disposed at least one side of the lower channel patterns CP_B and electrically connected to the lower channel patterns CP_B. A portion of the lower source and drain patterns 150 can be in contact with the channel pattern CP. Another portion of the lower source and drain patterns 150 can be in contact with the gate insulating film 130. The lower source and drain patterns 150 can be disposed between the lower channel patterns CP_B spaced apart from each other along the first direction D1. The lower source and drain patterns 150 can connect the lower channel patterns CP_B of the channel pattern CP spaced apart from each other on the first direction D1. As used herein, components described as being “electrically connected” are configured such that an electrical signal can be transferred from one component to another (although such an electrical signal can attenuate in strength as it is transferred and can be selectively transferred).

[0052] The upper source and drain pattern 250 can be disposed at least on one side of the upper channel pattern CP_U and electrically connected to the upper channel pattern CP_U. A portion of the upper source and drain pattern 250 can be in contact with the upper channel pattern CP_U. Another portion of the upper source and drain pattern 250 can be in contact with the gate insulating film 130. The upper source and drain pattern 250 can be disposed between the upper channel patterns CP_U spaced apart from each other in the first direction D1. The upper source and drain pattern 250 can connect the upper channel patterns CP_U of the channel patterns CP spaced apart from each other in the first direction D1.

[0053] The source and drain patterns 150 and 250 can be disposed at least on one side of the gate electrode 120. The source and drain patterns 150 and 250 can be disposed between the gate electrodes 120 adjacent in the first direction D1. For example, the source and drain patterns 150 and 250 can be disposed on both sides of the lower gate electrode 120_B. Unlike as illustrated, the source and drain patterns 150 and 250 can be disposed on one side of the gate electrode 120 and can not be disposed on the other side of the gate electrode 120.

[0054] The source and drain patterns 150 and 250 can be epitaxial patterns formed by a selective epitaxial growth process using the active pattern AP as a seed. The source and drain patterns 150 and 250 can function as sources and drains of transistors using the channel patterns CP as channel regions. For example, the lower source and drain pattern 150 can function as a source or a drain of a transistor using the lower channel pattern CP_B as a channel region, and the upper source and drain pattern 250 can function as a source or a drain of a transistor using the upper channel pattern CP_U as a channel region.

[0055] The source and drain patterns 150 and 250 can include a semiconductor material. For example, the source and drain patterns 150 and 250 can include an elemental semiconductor material such as silicon (Si) or germanium (Ge). In some embodiments, the source and drain patterns 150 and 250 can include, for example, a binary compound or a ternary compound including at least two or more of carbon (C), silicon (Si), germanium (Ge), tin (Sn), and a compound doped with a group IV element. For example, the source and drain pattern 150 can include silicon (Si), silicon germanium (SiGe), germanium (Ge), silicon carbide (SiC), etc., but is not limited thereto.

[0056] The source and drain patterns 150 and 250 can include impurities doped into a semiconductor material. The doped impurities can include at least one of boron (B), phosphorus (P), carbon (C), arsenic (As), antimony (Sb), bismuth (Bi), and oxygen (O), but the inventive concepts are not limited thereto. The lower source and drain patterns 150 and the upper source and drain patterns 250 can have opposite conductivity types and can include the same or different semiconductor materials. For example, source and drain patterns having p-type conductivity can include silicon germanium (SiGe), boron-doped silicon germanium (SiGe:B), carbon-doped silicon germanium (SiGe:C), carbon and boron-doped silicon germanium (SiGe:C:B), boron-doped silicon (Si:B), and silicon (Si). Source and drain patterns having n-type conductivity can include phosphorus-doped silicon (Si:P), arsenic-doped silicon (Si:As), carbon-doped silicon (Si:C), arsenic and carbon-doped silicon (Si:As:C), arsenic and phosphorus-doped silicon (Si:As:P), and silicon (Si). However, the inventive concepts are not limited thereto.

[0057] Although the source and drain patterns 150 and 250 are shown as a single layer in Figure 2 , this is for ease of description only, and the inventive concepts are not limited thereto. For example, each source and drain pattern can include multiple layers including different materials. In some embodiments, the source and drain patterns can include the same material and can include multiple layers having different concentrations of the constituent material (e.g., different concentrations of germanium (Ge)). Examples will be described in detail below with reference to Figures 6 to 13 .

[0058] The sidewall spacers 160_SW can be disposed on two opposite side surfaces of the lower source and drain patterns 150 in the second direction D2. For example, the sidewall spacers 160_SW can include first sidewall spacers 162_SW and second sidewall spacers 164_SW. The first sidewall spacers 162_SW can be in contact with and define a first side surface of the lower source and drain patterns 150. In addition, the second sidewall spacers 164_SW can be in contact with and define a second side surface of the lower source and drain patterns 150. The first and second side surfaces can be opposite sides of the lower source and drain patterns 150, and the first and second side surfaces can not be connected to each other. For example, the first and second side surfaces can be spaced apart from each other and can form opposite side surfaces of the lower source and drain patterns 150.

[0059] The first sidewall spacer 162_SW and the second sidewall spacer 164_SW may be independent structures. For example, each of the first sidewall spacer 162_SW and the second sidewall spacer 164_SW may be arranged to contact a corresponding one of the two sides of the lower source and drain pattern 150 and may not be connected to each other. For example, the first sidewall spacer 162_SW and the second sidewall spacer 164_SW may be spaced apart from each other in the second direction D2. Therefore, the first sidewall spacer 162_SW and the second sidewall spacer 164_SW may not be formed in the upper region of the upper surface including the lower source and drain pattern 150. For example, the first sidewall spacer 162_SW and the second sidewall spacer 164_SW may be arranged to contact the first side and the second side of the lower source and drain pattern 150, respectively, and the dielectric isolation layer 140 may be arranged to contact the upper region of the upper surface including the lower source and drain pattern 150.

[0060] like Figure 3 , the heights of the first and second sidewall spacers 162_SW and 164_SW may be lower than or equal to the height of the lower source and drain pattern 150. For example, the uppermost portions / topmost surfaces of the first and second sidewall spacers 162_SW and 164_SW may have a vertical height lower than or equal to the uppermost / topmost surface of the lower source and drain pattern 150.

[0061] Figure 4 Shown along Figure 1 Another example of a cross-sectional view taken along line BB. Figure 4The first sidewall spacer 162_SW and the second sidewall spacer 164_SW can be disposed / formed with the same inclination as that of the side surface of the lower pattern BP. For example, the side surface of the first sidewall spacer 162_SW and the side surface of the second sidewall spacer 164_SW can have the same angle with respect to (e.g., in a cross-sectional view) a horizontal plane / line as that of the side surface of the lower pattern BP disposed under the corresponding side surface of the first sidewall spacer 162_SW and the second sidewall spacer 164_SW. The first sidewall spacer 162_SW and the second sidewall spacer 164_SW can be disposed inwardly inclined such that the width (e.g., horizontal distance) between the first sidewall spacer 162_SW and the second sidewall spacer 164_SW (e.g., in a horizontal direction) decreases in a direction approaching the top of the first sidewall spacer 162_SW and the second sidewall spacer 164_SW. In this case, the first side surface of the lower source and drain pattern 150 can be formed to have the same inclination as that of the side surface (e.g., the side surface contacting the lower source and drain pattern 150) of the first sidewall spacer 162_SW and to be formed along the sidewall (e.g., the side surface) of the first sidewall spacer 162_SW (e.g., the side surface contacting the lower source and drain pattern 150). In addition, the second side surface of the lower source and drain pattern 150 can be formed with the same inclination as that of the side surface (e.g., the side surface contacting the lower source and drain pattern 150) of the second sidewall spacer 164_SW and to be formed along the sidewall (e.g., the side surface) of the second sidewall spacer 164_SW (e.g., the side surface contacting the lower source and drain pattern 150).

[0062] As described above, in the semiconductor device according to some aspects of the present disclosure, the sidewall spacers are disposed on both sides of the lower source and drain pattern to limit the shape of the side surface of the lower source and drain pattern to correspond to the channel width of the corresponding transistor and / or to correspond to the lower channel pattern CP_B, thereby improving the integration and performance of the semiconductor device.

[0063] Figure 5 is provided to explain the dielectric isolation layer according to some aspects of the present disclosure. Referring to Figure 2 , Figure 3 and Figure 5The dielectric isolation layer 140 can be provided between the lower source and drain pattern 150 and the upper source and drain pattern 250 to separate and insulate the lower source and drain pattern 150 from the upper source and drain pattern 250. The dielectric isolation layer 140 can include first to fifth regions 140_1, 140_2, 140_3, 140_4, and 140_5. The first region 140_1 can face (e.g., contact) an upper surface of the lower source and drain pattern 150. The second region 140_2 can extend upward from a first end of the first region 140_1, and the third region 140_3 can extend upward from a second end spaced apart from the first end in the first direction D1. Outer sides / surfaces of the second region 140_2 and the third region 140_3 can be in contact with the gate insulating film 130, and inner sides / surfaces of the second region 140_2 and the third region 140_3 can be in contact with the etching stop film 170. The fourth region 140_4 can extend downward from a third end connected to the first end and the second end of the first region 140_1. In addition, the fifth region 140_5 can extend downward from a fourth end opposite the third end. Inner sides / surfaces of the fourth region 140_4 and the fifth region 140_5 can be in contact with the sidewall spacers 160_SW, and outer sides / surfaces of the fourth region 140_4 and the fifth region 140_5 can be in contact with the etching stop film 170.

[0064] Figure 5 The fourth region 140_4 and the fifth region 140_5 are shown as extending from the first region 140_1 in the vertical direction, but the inventive concept is not limited thereto. For example, the fourth region 140_4 and the fifth region 140_5 can be formed to extend obliquely along the sidewalls (e.g., side surfaces) of the first sidewall spacer 162_SW and the second sidewall spacer 164_SW.

[0065] The dielectric isolation layer 140 can be formed such that portions thereof are provided between the lower source and drain pattern 150 and the upper source and drain pattern 250 to support the upper source and drain pattern 250. The second region 140_2 and the third region 140_3 can extend from both ends (e.g., opposite ends) of the first region 140_1 along the lower gate electrode 120_B in the third direction D3, such that upper surfaces of the second region 140_2 and the third region 140_3 support (e.g., contact) the upper source and drain pattern 250.

[0066] The dielectric isolation layer 140 can be formed such that a portion thereof isolates the lower source and drain pattern 150 and the upper source and drain pattern 250 from each other. For example, a portion of the dielectric isolation layer 140 can be disposed between the lower source and drain pattern 150 and the upper source and drain pattern 250. As described above, a lower surface of the lower source and drain pattern 150 can be in contact with the lower pattern BP. In addition, two sides of the lower source and drain pattern 150 opposite each other in the first direction D1 can be in contact with the lower channel pattern CP_B and the lower gate electrode 120_B. In this case, an upper surface and two sides of the lower source and drain pattern 150 opposite each other in the second direction D2 are formed to be surrounded by (e.g., in contact with) the dielectric isolation layer 140, such that the lower source and drain pattern 150 and the upper source and drain pattern 250 can be electrically isolated / insulated from each other.

[0067] The dielectric isolation layer 140 can include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon oxynitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbon oxide (SiOC), and combinations thereof. The dielectric isolation layer 140 can include a material different from that of the sidewall spacer 160_SW. Although it is shown that the dielectric isolation layer 140 is a single layer, this is merely for ease of description, and the inventive concept is not limited thereto. In some embodiments, the sidewall spacer 160_SW can include at least one of silicon nitride (SiN), silicon carbon oxynitride (SiOCN), and silicon carbon oxide (SiOC).

[0068] Referring again to Figures 1 to 3 The gate electrode 120 can extend longitudinally along the second direction D2 on the substrate 100. The gate electrode 120 can intersect the active pattern AP. The gate electrode 120 can be disposed on the lower pattern BP. The gate electrode 120 can be spaced apart from an adjacent gate electrode 120 in the first direction D1. The gate electrode 120 can surround the plurality of channel patterns CP. The gate electrode 120 can surround four surfaces of the channel pattern CP. For example, the gate electrode 120 can surround an upper surface, a lower surface, and two (e.g., opposite) side surfaces of the channel pattern CP. The upper surface and the lower surface of the channel pattern CP can represent surfaces perpendicular to the third direction D3, and the two side surfaces / opposite side surfaces of the channel pattern CP can represent surfaces perpendicular to the second direction D2.

[0069] The gate electrode 120 can include an upper gate electrode 120_U and a lower gate electrode 120_B. The lower gate electrode 120_B can be disposed between the channel patterns CP adjacent in the third direction D3. The lower gate electrode 120_B can be disposed between the lower pattern BP and the channel pattern CP disposed at the bottom of the plurality of channel patterns CP. The upper gate electrode 120_U can be disposed on the channel pattern CP disposed at the top of the plurality of channel patterns CP.

[0070] According to some aspects, the active pattern AP can include a plurality of channel patterns CP, and the gate electrode 120 can include a plurality of lower gate electrodes 120_B. In this case, the number of the lower gate electrodes 120_B can be proportional to the number of the channel patterns CP included in the active pattern AP. The number of the lower gate electrodes 120_B can be equal to the number of the channel patterns CP. For example, as shown in FIG. 1B, the number of the lower gate electrodes 120_B can be 4, and the number of the lower gate electrodes 120_B can be the same as the number of the channel patterns CP. However, the inventive concept is not limited thereto. Figure 2

[0071] The gate electrode 120 can include at least one of a metal, a metal alloy, a conductive metal nitride, a metal silicide, a doped semiconductor material, a conductive metal oxide, and a conductive metal oxynitride. For example, the gate electrode 120 can include titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), and combinations thereof, but is not limited thereto. The conductive metal oxide and the conductive metal oxynitride can include oxidized forms of the above materials, but are not limited thereto.

[0072] ​The gate insulating film 130 can be disposed between the gate electrode 120 and the plurality of channel patterns CP and between the gate electrode 120 and the source and drain patterns 150. For example, the gate insulating film 130 can be disposed between the upper gate electrode 120_U and a channel pattern CP disposed on top of the plurality of channel patterns CP (e.g., a top channel pattern of the upper channel pattern CP_U). The gate insulating film 130 can be disposed between the lower gate electrode 120_B and the channel pattern CP.

[0073] The gate insulating film 130 can extend in the first direction D1 along the upper and lower surfaces of the channel pattern CP. The sidewall of the gate insulating film 130 can extend in the third direction D3 along the sidewall of the source and drain patterns 150 and 250. The sidewall of the gate insulating film 130 can be defined as a portion in contact with the source and drain patterns 150 and 250. The sidewall of the source and drain patterns 150 and 250 can be defined as a portion in contact with the gate insulating film 130 and the channel pattern CP.

[0074] The gate insulating film 130 can include one or more of silicon oxide, boron nitride, hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0075] The gate spacer 160_GS can be disposed on the upper gate electrode 120_U. For example, the gate spacer 160_GS can extend along the side surface of the upper gate electrode 120_U and the side surface of a gate cap pattern (not shown) disposed on the upper gate electrode 120_U (e.g., longitudinally). The gate spacer 160_GS can not be formed on / located between the lower pattern BP and the channel pattern CP. The gate spacer 160_GS can not be formed on / located between adjacent channel patterns CP in the third direction D3.

[0076] For example, the gate spacer 160_GS can include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof. Although the gate spacer 160_GS is shown as a single layer, this is merely for ease of description, and the inventive concept is not limited thereto.

[0077] In some aspects, the gate insulating film 130 can be disposed between the upper gate electrode 120_U and the channel pattern CP, and can not be disposed on the gate spacers 160 GS. For example, the gate insulating film 130 can not be disposed between the gate spacers 160 GS and the upper gate electrode 120_U, nor between the gate spacers 160 GS and the gate cap pattern. However, the inventive concepts are not limited thereto.

[0078] Although not shown, a gate cap pattern can be disposed on the upper gate electrode 120_U. The gate cap pattern can cover an upper surface of the upper gate electrode 120_U. The gate cap pattern can be stacked on the upper gate electrode 120_U in the third direction D3. The gate cap pattern can be disposed between the gate spacers 160 GS. Side surfaces of the gate cap pattern can be in contact with the gate spacers 160 GS. An upper surface of the gate cap pattern can be disposed to be flush with (e.g., at the same height as) an upper surface of the interlayer insulating film 180. However, the inventive concepts are not limited thereto.

[0079] For example, the gate cap pattern can include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. The gate cap pattern can include a material having etch selectivity with respect to the interlayer insulating film 180.

[0080] The etch stop film 170 can extend along the contours of the side walls of the gate spacers 160 GS, the upper source and drain patterns 250, and the dielectric isolation layer 140. In addition, the etch stop film 170 can be disposed on an upper surface of the field insulating film 105.

[0081] The etch stop film 170 can include a material having etch selectivity with respect to the interlayer insulating film 180. For example, the etch stop film 170 can include at least one of silicon nitride (SiN), silicon oxide (SiO), silicon oxynitride (SiON), silicon oxycarbonitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon oxycarbide (SiOC), and combinations thereof.

[0082] The interlayer insulating film 180 can be disposed on the etch stop film 170. The interlayer insulating film 180 can be disposed on the source and drain patterns 150 and 250. The interlayer insulating film 180 can be disposed on one side (or both sides) of the upper gate electrode 120_U. The interlayer insulating film 180 can be disposed between the upper gate electrode 120_U. In addition, the interlayer insulating film 180 can be disposed on an upper surface of the field insulating film 105.

[0083] For example, the interlayer insulating film 180 can include at least one of silicon oxide (SiO), silicon nitride (SiN), silicon oxynitride (SiON), and a low dielectric constant material. For example, the low dielectric constant material can include fluorinated tetraethyl orthosilicate (FTEOS), hydrogen silsesquioxane (HSQ), bisbenzocyclobutene (BCB), tetramethyl orthosilicate (TMOS), octamethylcyclotetrasiloxane (OMCTS), hexamethyldisiloxane (HMDS), trimethylsilyl borate (TMSB), diacetoxyditertiarybutylsilane (DADBS), trimethylsilyl phosphate (TMSP), polytetrafluoroethylene (PTFE), TOSZ, fluorosilicate glass (FSG), polyimide nanocellulose foam (such as polypropylene oxide), carbon-doped silicon oxide (CDO), organosilicate glass (OSG), SiLK, amorphous fluorocarbon, silica aerogel, silica xerogel, mesoporous silica, or a combination thereof, but is not limited thereto.

[0084] Although not shown, the semiconductor device according to some aspects can also include source and drain contacts. The source and drain contacts can be disposed on the lower source and drain pattern 150 and / or can be disposed on the upper source and drain pattern 250. The source and drain contacts can extend through the interlayer insulating film 180 and the etch stop film 170. The source and drain contacts can be electrically connected to the lower source and drain pattern 150 and / or can be electrically connected to the upper source and drain pattern 250.

[0085] The source and drain contacts can include an electrically conductive material. For example, the source and drain contacts can include at least one of a metal, a metal nitride, a metal carbonitride, a two-dimensional (2D) material, and an electrically conductive semiconductor material.

[0086] Figures 6 to 13 is provided to explain a semiconductor device according to some embodiments of the present disclosure. For ease of explanation, a configuration different from the configuration described with reference to Figures 1 to 5 In the semiconductor device according to some embodiments, the lower source and drain pattern 150 and the upper source and drain pattern 250 can have different conductive types. Additionally, at least one of the lower source and drain pattern 150 and the upper source and drain pattern 250 can include a plurality of epitaxial layers.

[0087] Reference is made to Figures 6 to 9In the semiconductor device according to some embodiments, the lower source and drain pattern 150 can be an n-type lower source and drain pattern 150_N having n-type conductivity. The n-type lower source and drain pattern 150_N can include at least one of phosphorus-doped silicon (Si:P), arsenic-doped silicon (Si:As), carbon-doped silicon (Si:C), arsenic and carbon-doped silicon (Si:As:C), arsenic and phosphorus-doped silicon (Si:As:P), and silicon (Si). However, the inventive concept is not limited thereto. On the other hand, the upper source and drain pattern 250 can be a p-type upper source and drain pattern 250_P having p-type conductivity.

[0088] The p-type upper source and drain pattern 250_P can include at least one of silicon germanium (SiGe), boron-doped silicon germanium (SiGe:B), carbon-doped silicon germanium (SiGe:C), carbon and boron-doped silicon germanium (SiGe:C:B), boron-doped silicon (Si:B), and silicon (Si). However, the inventive concept is not limited thereto.

[0089] Referring to Figure 6 and Figure 7 , the p-type upper source and drain pattern 250_P can include a first epitaxial layer 252_P and a second epitaxial layer 254_P. The second epitaxial layer 254_P can extend along the profile of the first epitaxial layer 252_P. For example, the first epitaxial layer 252_P can be formed on and in contact with the upper channel pattern CP_U on both sides / opposite sides (left and right sides) of the first epitaxial layer 252_P, and the second epitaxial layer 254_P can be disposed to surround the first epitaxial layer 252_P not in contact with the upper channel pattern CP_U. In this case, the second epitaxial layer 254_P can extend along the outer surface of the first epitaxial layer 252_P so as not to be in contact with the adjacent upper channel pattern CP_U, but the inventive concept is not limited thereto. For example, in a cross-section of Figure 6 , the first epitaxial layer 252_P can be in contact with the upper channel pattern CP_U on both sides / opposite sides of the first epitaxial layer 252_P, and the central region can have a concave cross-section and / or a ribbon-like cross-section, and the second epitaxial layer 254_P can be disposed on the upper and lower surfaces of the first epitaxial layer 252_P. In Figure 7In a cross-section of the second epitaxial layer 254_P, the second epitaxial layer 254_P can be disposed to surround all of the upper and lower surfaces of the first epitaxial layer 252_P, and both of the side surfaces. The first epitaxial layer 252_P and the second epitaxial layer 254_P can include the same constituent material, and can have different concentrations of the constituent material. For example, each of the first epitaxial layer 252_P and the second epitaxial layer 254_P can include silicon germanium (SiGe), and the concentration of germanium (Ge) in the second epitaxial layer 254_P can be greater than the concentration of germanium (Ge) in the first epitaxial layer 252_P.

[0090] Referring to Figure 8 and Figure 9 , the n-type lower source and drain pattern 150_N can include a third epitaxial layer 152_N and a fourth epitaxial layer 154_N. The fourth epitaxial layer 154_N can be disposed on the third epitaxial layer 152_N. The third epitaxial layer 152_N can be disposed to surround / contact the lower surface of the fourth epitaxial layer 154_N, and at least a portion of the side surface of the fourth epitaxial layer 154_N. In this case, the third epitaxial layer 152_N and the fourth epitaxial layer 154_N can include the same constituent material, and can have different concentrations of the constituent material. For example, the third epitaxial layer 152_N and the fourth epitaxial layer 154_N can include silicon (Si) doped with arsenic (As) or phosphorus (P), and the concentration of arsenic (As) or phosphorus (P) included in the fourth epitaxial layer 154_N can be greater than the concentration of arsenic (As) or phosphorus (P) included in the third epitaxial layer 152_N.

[0091] Although Figure 8 and Figure 9 show that both the upper source and drain pattern 250_P and the lower source and drain pattern 150_N have a plurality of epitaxial layers, this is only for ease of description, and the inventive concept is not limited thereto. For example, only one of the upper source and drain pattern 250_P and the lower source and drain pattern 150_N can have a plurality of epitaxial layers.

[0092] Referring to Figures 10 to 13 , in the semiconductor device according to some aspects, the lower source and drain pattern 150 can be a p-type lower source and drain pattern 150_P having p-type conductivity. The p-type lower source and drain pattern 150_P can include at least one of silicon germanium (SiGe), boron-doped silicon germanium (SiGe:B), carbon-doped silicon germanium (SiGe:C), carbon and boron-doped silicon germanium (SiGe:C:B), boron-doped silicon (Si:B), and silicon (Si). However, the inventive concept is not limited thereto.

[0093] On the other hand, the upper source and drain pattern 250 can be an n-type upper source and drain pattern 250_N having n-type conductivity. The n-type upper source and drain pattern 250_N can include at least one of phosphorus-doped silicon (Si:P), arsenic-doped silicon (Si:As), carbon-doped silicon (Si:C), arsenic and carbon-doped silicon (Si:As:C), arsenic and phosphorus-doped silicon (Si:As:P), and silicon (Si). However, the inventive concept is not limited thereto.

[0094] Referring to Figure 10 and Figure 11 , the p-type lower source and drain pattern 150_P can include a fifth epitaxial layer 152_P and a sixth epitaxial layer 154_P. The fifth epitaxial layer 152_P can be disposed in contact with the lower channel pattern CP_B and the lower pattern BP on both sides / opposite sides (left and right sides) of the fifth epitaxial layer 152_P, and the sixth epitaxial layer 154_P can be disposed on the fifth epitaxial layer 152_P. The fifth epitaxial layer 152_P can be disposed to surround a lower surface of the sixth epitaxial layer 154_P and at least a portion of a side surface of the sixth epitaxial layer 154_P. In addition, at least a portion of the side surface of the fifth epitaxial layer 152_P can be in contact with the sidewall spacer 160_SW, and at least a portion of the side surface of the sixth epitaxial layer 154_P can also be in contact with the sidewall spacer 160_SW. In this case, as shown in a cross-section of Figure 11 , the uppermost portion of the fifth epitaxial layer 152_P can have a vertical level corresponding to (e.g., the same as) a middle point between the uppermost portion and the lowermost portion of the sidewall spacer 160_SW. The fifth epitaxial layer 152_P and the sixth epitaxial layer 154_P can include the same constituent material, and can have different constituent material ratios (or concentrations). For example, the fifth epitaxial layer 152_P and the sixth epitaxial layer 154_P can include silicon germanium (SiGe), and the concentration of germanium (Ge) in the sixth epitaxial layer 154_P can be greater than the concentration of germanium (Ge) in the fifth epitaxial layer 152_P.

[0095] Referring to Figure 12 , the n-type upper source and drain pattern 250_N can include a seventh epitaxial layer 252_N and an eighth epitaxial layer 254_N. Figure 13 is Figure 12 an enlarged view of the region R of Figure 13The seventh epitaxial layer 252_N can include a (7-1)th epitaxial layer 252_1_N adjacent to the first upper channel pattern CA_U1 and a (7-2)th epitaxial layer 252_2_N adjacent to the second upper channel pattern CA_U2. The first upper channel pattern CA_U1 and the second upper channel pattern CA_U2 can be included in adjacent channel patterns, respectively. An eighth epitaxial layer 254_N can be disposed between the (7-1)th epitaxial layer 252_1_N and the (7-2)th epitaxial layer 252_2_N. The seventh epitaxial layer 252_N and the eighth epitaxial layer 254_N can include the same constituent material, and can have different concentrations of the constituent material. For example, the seventh epitaxial layer 252_N and the eighth epitaxial layer 254_N can include silicon (Si) doped with arsenic (As) or phosphorus (P), and the concentration of arsenic (As) or phosphorus (P) in the eighth epitaxial layer 254_N can be greater than the concentration of arsenic (As) or phosphorus (P) in the seventh epitaxial layer 252_N.

[0096] Although Figure 13 The (7-1)th epitaxial layer 252_1_N and the (7-2)th epitaxial layer 252_2_N are shown as not being connected to each other, in certain embodiments, the (7-1)th epitaxial layer 252_1_N and the (7-2)th epitaxial layer 252_2_N can be connected to each other, and can form a ribbon-like cross-section similar to the shape of the first epitaxial layer 252_P of Figure 6 Additionally, although Figure 12 Both the upper source and drain pattern 250_N and the lower source and drain pattern 150_P are shown as having multiple epitaxial layers, this is merely for ease of description, and the inventive concept is not limited thereto. For example, only one of the upper source and drain pattern 250_N and the lower source and drain pattern 150_P can have multiple epitaxial layers.

[0097] As described above, in a semiconductor device according to some aspects of the present disclosure, a heavily doped epitaxial layer of a constituent material that applies strain to a channel pattern is formed to surround the outer side / surface of a lightly doped epitaxial layer of the same constituent material connecting adjacent channel patterns, so that defects caused by the heavily doped epitaxial layer contacting the channel pattern can be prevented, and the performance of the semiconductor device can be improved.

[0098] Figures 14 to 30 FIGS. 1 to 6 are diagrams illustrating intermediate stages provided to explain a method for manufacturing a semiconductor device according to some aspects of the present disclosure. Figure 14 , Figure 16 and Figure 18 are top views illustrating intermediate stages of manufacturing a semiconductor device. Figure 15 , Figure 17 and Figures 19 to 30 include Figure 15 (a), Figure 17 (a),Figure 19 (a) to Figure 30 (a), (b), (c), and (d) Figure 15 (b), (c), and (d) Figure 17 (b) and (c) Figure 19 (b) to (d) Figure 30 (b). Figure 15 (a), (b), (c), and (d) Figure 17 (a) and (b) Figure 19 (a) to (c) Figure 30 (a) is a partial cross-sectional view of a semiconductor device in a length direction of a channel of the semiconductor device (e.g., A-A of FIG. 1) in an intermediate stage of manufacturing the semiconductor device. Figure 1 , Figure 14 , Figure 16 and Figure 18 of FIG. 1, Figure 15 (b), (c), and (d) Figure 17 (b) and (c) Figure 19 (b) to (d) Figure 30 (b) is a partial cross-sectional view of a semiconductor device in a width direction of a channel of the semiconductor device (e.g., B-B of FIG. 1) in an intermediate stage of manufacturing the semiconductor device. Figure 1 , Figure 14 , Figure 16 and Figure 18 of FIG. 1.

[0099] Referring to Figure 14 and Figure 15 , a method for manufacturing a semiconductor device according to some aspects can include forming a stack structure S_ST on a substrate 100.

[0100] The substrate 100 can be a silicon substrate, or can include other materials such as silicon germanium (SiGe), silicon germanium on insulator (SGOI), indium antimony, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimony, but is not limited thereto.

[0101] A stack structure S_ST can be formed on the base 100. The stack structure S_ST can include sacrificial semiconductor layers SC_L and active semiconductor layers ACT_L which can be alternately stacked. As shown, the stack structure S_ST can include an upper stack structure US_ST, an intermediate sacrificial semiconductor layer SC_ML, and a lower stack structure BS_ST. The upper stack structure US_ST can be defined as a stack structure of some active semiconductor layers ACT_L and some sacrificial semiconductor layers SC_L disposed on an upper portion of the intermediate sacrificial semiconductor layer SC_ML. The lower stack structure BS_ST can be defined as a stack structure of some other active semiconductor layers ACT_L and some other sacrificial semiconductor layers SC_L disposed on a lower portion of the intermediate sacrificial semiconductor layer SC_ML. The active semiconductor layers ACT_L and the sacrificial semiconductor layers SC_L can be formed of materials having different etching rates from each other in a subsequent etching process. For example, the active semiconductor layers ACT_L and the sacrificial semiconductor layers SC_L can have etching selectivity with respect to an etchant used in the subsequent etching process.

[0102] Referring to Figure 16 and Figure 17 A method for manufacturing a semiconductor device according to some aspects can include patterning the stack structure S_ST. A mask pattern MP extending in a first direction D1 can be formed on the stack structure S_ST, and the stack structure S_ST can be patterned (i.e., selectively removing the stack structure S_ST using the mask pattern MP as a mask). For example, the mask pattern MP can expose a portion of an upper surface of the stack structure S_ST. The field trench FT and the lower pattern BP can be formed by selectively removing regions not covered by the mask pattern MP. The patterned stack structure S_ST can be spaced apart from each other in a second direction D2.

[0103] A field insulating film 105 can be formed on the field trench FT. The field insulating film 105 can fill the field trench FT. It is shown that the field insulating film 105 is a single layer, but the inventive concept is not limited thereto.

[0104] Referring to Figure 18 and Figure 19A dummy gate stack DGS can be formed on the stack structure S_ST. The dummy gate stack DGS can include a gate sacrificial pattern 120_SC and a hard mask pattern 120_HM. To form the dummy gate stack DGS, polysilicon can be formed on the stack structure S_ST, and the hard mask pattern 120_HM can be formed on the polysilicon. The gate sacrificial pattern 120_SC can be formed by patterning the polysilicon using the hard mask pattern 120_HM as a mask. In this case, the hard mask pattern 120_HM on the gate sacrificial pattern 120_SC can not be removed. The gate sacrificial pattern 120_SC can intersect (e.g., in a plan view) the stack structure S_ST. For example, the gate sacrificial pattern 120_SC can cross (e.g., vertically) the stack structure S_ST. For example, the gate sacrificial pattern 120_SC can extend in the second direction D2, and the patterned stack structure S_ST can extend in the first direction D1.

[0105] A pre-spacer layer 160_P can be formed on the dummy gate stack DGS and the stack structure S_ST. The pre-spacer layer 160_P can be formed along the top and side surfaces of the hard mask pattern 120_HM, the side surfaces of the gate sacrificial pattern 120_SC, and the upper surface of the stack structure S_ST.

[0106] Referring to Figure 20 An intermediate source and drain trench 150_R1 for forming a sidewall spacer 160_SW can be formed. For example, the intermediate source and drain trench 150_R1 can be formed by selectively etching portions of the upper stack structure US_ST and the intermediate sacrificial semiconductor layer SC_ML between adjacent dummy gate stacks DGS until an upper end of the bottom stack structure BS_ST (e.g., by selectively etching portions of the upper stack structure US_ST and the intermediate sacrificial semiconductor layer SC_ML between adjacent dummy gate stacks DGS to expose a portion of the bottom stack structure BS_ST).

[0107] The active semiconductor layers ACT_L of the upper stack structure US_ST can be separated by the intermediate source and drain trench 150_R1 to form an upper channel pattern CP_U. The intermediate source and drain trench 150_R1 can expose the upper channel pattern CP_U, the sacrificial semiconductor layers SC_L disposed between the upper channel pattern CP_U, and the intermediate sacrificial semiconductor layer SC_ML.

[0108] A thickness of the hard mask pattern 120_HM in the third direction D3 can decrease while the etching process is performed. In addition, a portion of the pre-spacer layer 160_P can be removed to form a gate spacer 160_GS and the sidewall spacer 160_SW.

[0109] Referring toFigure 21 and Figure 22 A first trench insulating film TIF_1 can be formed on the stack structure S_ST and the dummy gate stack DGS, and a second trench insulating film TIF_2 can be formed on the first trench insulating film TIF_1. The first trench insulating film TIF_1 can be a dielectric isolation layer (e.g., silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon oxynitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbon oxide (SiOC), or a combination thereof) for isolating the upper source and drain patterns and the lower source and drain patterns from each other. Figure 3 The second trench insulating film TIF_2 can be formed to protect the first trench insulating film TIF_1 in a process of forming the first trench insulating film TIF_1 as a dielectric isolation layer.

[0110] A material of the first trench insulating film TIF_1 can include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon oxynitride (SiOCN), silicon boron nitride (SiBN), silicon boron oxynitride (SiOBN), silicon carbon oxide (SiOC), or a combination thereof. However, the inventive concept is not limited thereto.

[0111] Referring to Figure 23 A source and drain trench 150_R in which the source and drain patterns are to be disposed in a later step can be formed. For example, the source and drain trench 150_R can be formed by further etching the already-formed intermediate source and drain trench 150_R1 to a lower end of the lower stack structure BS_ST (e.g., by further etching the already-formed intermediate source and drain trench 150_R1 to expose a portion of the lower pattern BP).

[0112] The etching can include chemical oxide removal (COR) or pulsed dry cleaning (PDC). For example, for dry etching, ion beam etching (IBE), carbon tetrafluoride (CF4) treatment, or chemical oxide removal (COR) can be used.

[0113] During the etching, portions of the second trench insulating film TIF_2 and the first trench insulating film TIF_1 can be removed. As a result of the etching, the first trench insulating film TIF_1 can remain on the upper surface and the side surface of the dummy gate stack DGS, and on the side surface of the upper stack structure US_ST and the intermediate sacrificial semiconductor layer SC_ML. In addition, the lower stack structure BS_ST between adjacent dummy gate stacks DGS can be removed by the etching, but the sidewall spacer 160_SW disposed on the side surface of the lower stack structure BS_ST and the first trench insulating film TIF_1 can be remained.

[0114] The active semiconductor layer ACT_L of the lower stack structure BS_ST can be separated by the source and drain trenches 150_R to form a lower channel pattern CP_B. The source and drain trenches 150_R can expose the lower channel pattern CP_B and the sacrificial semiconductor layer SC_L disposed between the lower channel pattern CP_B.

[0115] Referring to Figure 24 The lower source and drain pattern 150 can be formed in the source and drain trenches 150_R. For example, the lower source and drain pattern 150 can be formed using an epitaxial growth method. The upper surface of the lower pattern BP and the sidewall of the lower channel pattern CP_B exposed by the source and drain trenches 150_R can be used as seeds.

[0116] In Figure 24 The lower source and drain pattern 150 is shown as a single layer in FIG. 15, but in certain embodiments, the lower source and drain pattern 150 can include multiple epitaxial layers. When the lower source and drain pattern 150 includes multiple epitaxial layers, first, a lightly doped epitaxial layer including a constituent material such as germanium (Ge), arsenic (As), or phosphorus (P) that is bonded to silicon or doped into silicon at a low concentration can be formed using the upper surface of the lower pattern BP and the sidewall of the lower channel pattern CP_B exposed by the source and drain trenches 150_R as seeds, and thereafter, a heavily doped epitaxial layer of the same constituent material can be formed using the lightly doped epitaxial layer as seeds.

[0117] In some aspects, the lower source and drain pattern 150 can be formed by using a raw material including an elemental semiconductor precursor via at least one of a low pressure chemical vapor deposition (LPCVD) process, a selective epitaxial growth (SEG) process, and a cyclic deposition and etching (CDE) process.

[0118] Referring to Figure 25 The dielectric isolation layer 140 can be formed on the first trench insulating film TIF_1. In some aspects, the first trench insulating film TIF_1 and the dielectric isolation layer 140 can include the same or similar materials. In this case, as shown in Figure 25 the first trench insulating film TIF_1 and the dielectric isolation layer 140 can be formed / integrated as a single layer. The dielectric isolation layer 140 can be formed on the upper and side surfaces of the dummy gate stack DGS, the side surfaces of the upper stack structure US_ST and the intermediate sacrificial semiconductor layer SC_ML, and the upper surface of the lower source and drain pattern 150.

[0119] Referring to Figure 26A buried insulating layer 190a may be formed on the dielectric isolation layer 140. For example, the buried insulating layer 190a may fill the source and drain trenches 150_R. The buried insulating layer 190a may be formed on the upper surface of the dielectric isolation layer 140 disposed on the dummy gate stack DGS. After forming the buried insulating layer 190a, an annealing process may be performed, and a planarization process such as chemical mechanical polishing (CMP) may be performed to remove excess material. The material of the buried insulating layer 190a may include silicon oxide (SiO) and tosyl silazane (TOSZ). However, the inventive concept is not limited thereto.

[0120] Reference Figure 27 The buried insulating layer 190b may be formed by etching the buried insulating layer 190a to the upper end height of the middle sacrificial semiconductor layer SC_ML. A pulsed dry clean (PDC) may be used for the etching process of the buried insulating layer 190b, but the inventive concept is not limited thereto. The buried insulating layer 190b may include silicon oxide, but is not limited thereto.

[0121] Reference Figure 28 , the dielectric isolation layer 140 can be etched to the height of the upper end of the middle sacrificial semiconductor layer SC_ML. In this case, the upper surface of the etched dielectric isolation layer 140 can be substantially flush with the upper surface of the etched buried insulating layer 190b (for example, at the same height). Wet etching can be used for the etching process of the dielectric isolation layer 140. Through wet etching, the dielectric isolation layer 140 can be isotropically etched. Figure 28 , the dielectric isolation layer 140 disposed on the field insulating film 105 is removed by an etching process, but the inventive concept is not limited thereto. As used herein, terms such as "same," "equal," "planar," "coplanar," "parallel," and "perpendicular" encompass equivalence or near equivalence, including variations that may occur (e.g., due to manufacturing processes). Unless the context or other statements indicate otherwise, the term "substantially" may be used herein to emphasize this meaning.

[0122] Reference Figure 29 , an upper source and drain pattern 250 may be formed in the source and drain trench 150_R. For example, the upper source and drain pattern 250 may be formed using an epitaxial growth method. Sidewalls of the upper channel pattern CP_U exposed by the source and drain trench 150_R may serve as seeds.

[0123] Despite Figure 29The upper source and drain pattern 250 is shown as a single layer in the middle, but in certain embodiments, the upper source and drain pattern 250 can include multiple epitaxial layers. When the upper source and drain pattern 250 includes multiple epitaxial layers, first, a lightly doped epitaxial layer including a low concentration of a constituent material can be formed using the sidewalls of the upper channel pattern CP_U exposed by the source and drain trenches 150_R as seeds, and thereafter, a heavily doped epitaxial layer including a high concentration of the same constituent material can be formed using the lightly doped epitaxial layer as seeds.

[0124] The lightly doped epitaxial layers grown on the sidewalls of two adjacent upper channel patterns CP_U can be connected to each other, and the heavily doped epitaxial layer of the same constituent material can be formed using the lightly doped epitaxial layers as seeds. The heavily doped epitaxial layer can be grown to extend along the outer surfaces of the lightly doped epitaxial layers. As a result, the heavily doped epitaxial layer can be formed to surround the outer surfaces of the lightly doped epitaxial layers.

[0125] In some aspects, the upper source and drain pattern 250 can be formed by using a raw material including an elemental semiconductor precursor via at least one of a low pressure chemical vapor deposition (LPCVD) process, a selective epitaxial growth (SEG) process, and a cyclic deposition and etching (CDE) process.

[0126] Referring to Figure 30 The buried insulating layer 190c can be formed by partially or completely removing the buried insulating layer 190b through a pre-cleaning process. For example, when the buried insulating layer 190b is gradually removed through a pre-cleaning process occurring in a semiconductor device manufacturing process, the buried insulating layer 190c can be formed. In this case, unlike Figure 29 The buried insulating layer 190c can be completely removed, or the height of the buried insulating layer 190c can be lower than the height of the upper surface of the dielectric isolation layer 140.

[0127] The etching stop film 170 (see Figure 29 ) and the interlayer insulating film 180 (see Figure 2 ) can be formed on the upper surfaces of the source and drain patterns 150 and 250 (see Figure 2 ). The etching stop film 170 can be formed along the upper surface of the field insulating film 105 of Figure 3 and the upper surface and side surface of the dielectric isolation layer 140 of Figure 3 . The interlayer insulating film 180 can be formed on the etching stop film 170.

[0128] The gate sacrificial pattern 120_SC of Figure 29 can be removed, and the sacrificial semiconductor layers SC_L and SC_ML of Figure 29 can be removed to form a gate trench. The gate trench can expose the channel pattern (see Figure 29and source and drain patterns 150 and 250. A gate insulating film 130 can be formed on the source and drain patterns 150 and 250 exposed by the gate trenches, the side surfaces of the dielectric separation layer 140, and the outer surfaces of the channel patterns CP. Figure 2 A gate electrode 120 (see Figure 2 ) can be formed around the channel patterns CP. The gate electrode 120 can be disposed on the gate insulating film 130.

[0129] The gate electrode can include an upper gate electrode (120_U of Figure 2 ) and a lower gate electrode (120_B of Figure 2 ). For example, the upper gate electrode can be formed on the gate spacers 160_GS (see Figure 2 ). The upper gate electrode can fill the space between adjacent gate spacers 160_GS. The lower gate electrode can be formed on the insulating film structure (e.g., on the gate insulating film 130). The lower gate electrode can fill the space between adjacent channel patterns CP.

[0130] A gate cap pattern can be formed on the upper gate electrode. For example, a portion of the upper gate electrode can be recessed and the gate cap pattern can be formed on the upper surface of the upper gate electrode.

[0131] Each of the source and drain patterns 150 and 250 can be electrically connected to a power supply rail by a source contact and / or a drain contact. For example, a lower source contact, a lower drain contact, an upper source contact, and an upper drain contact can be formed on the source and drain patterns 150 and 250. Each contact can be electrically connected to the power supply rail by a contact via. The via can be formed in the lower pattern (BP of Figure 2 ) to electrically connect the source and drain patterns 150 or 250 to the source contact or the drain contact, but the location where the via is formed is not limited thereto.

[0132] As a result, a semiconductor device as described in the above Figures 1 to 13 can be provided.

[0133] Even though different drawings show variations of example embodiments and different embodiments disclose features that differ from each other, these drawings and embodiments are not necessarily meant to be mutually exclusive of one another. Rather, when the relevant descriptions of the drawings and embodiments are considered as a whole, features depicted in different drawings and / or described above in different embodiments can be combined with other features from other drawings / embodiments to result in additional variations of embodiments. For example, components and / or features of different embodiments described above can be combined interchangeably or additionally with components and / or features of other embodiments to form additional embodiments, and the present disclosure includes the additional embodiments, unless the context clearly indicates otherwise.

[0134] Although the present disclosure has been described above through specific aspects and drawings, the inventive concept is not limited thereto, and it is obvious that those of ordinary skill in the art can make various changes and modifications within the technical idea of the present disclosure and the equivalent scope of the appended claims.

Claims

1. A semiconductor device comprising: a substrate; an active pattern including a plurality of channel patterns disposed on the substrate and spaced apart from each other vertically; a gate electrode surrounding the plurality of channel patterns; a lower source / drain pattern disposed on the substrate and disposed on one side of the plurality of channel patterns; an upper source / drain pattern disposed above and spaced apart from the lower source / drain pattern; and a sidewall spacer including a first sidewall spacer in contact with a first side surface of the lower source / drain pattern and a second sidewall spacer in contact with a second side surface of the lower source / drain pattern, wherein the first side surface and the second side surface are opposite side surfaces of the lower source / drain pattern.

2. The semiconductor device according to claim 1, wherein The first sidewall spacer and the second sidewall spacer are disposed such that a horizontal distance between the first sidewall spacer and the second sidewall spacer decreases in a direction approaching a top portion of the first sidewall spacer and the second sidewall spacer.

3. The semiconductor device according to claim 1, wherein The first sidewall spacer and the second sidewall spacer are spaced apart from each other in a horizontal direction.

4. The semiconductor device according to claim 1, wherein The first sidewall spacer and the second sidewall spacer are not connected to each other.

5. The semiconductor device according to claim 1, wherein An uppermost portion of the first sidewall spacer and an uppermost portion of the second sidewall spacer have a vertical level lower than or equal to an uppermost portion of the lower source / drain pattern.

6. The semiconductor device according to claim 1, further comprising: a dielectric isolation layer isolating the lower source / drain pattern and the upper source / drain pattern from each other, wherein the dielectric isolation layer is disposed on and in contact with an upper surface of the lower source / drain pattern, the first sidewall spacer, and the second sidewall spacer.

7. The semiconductor device according to claim 6, further comprising: an interlayer insulating film disposed on the dielectric isolation layer and formed to fill a space between the lower source / drain pattern and the upper source / drain pattern.

8. The semiconductor device according to claim 1, wherein The sidewall spacer includes at least one of silicon nitride, silicon carbon oxynitride, and silicon carbon oxide.

9. The semiconductor device according to claim 6, wherein The sidewall spacer and the dielectric isolation layer include different materials.

10. The semiconductor device according to claim 1, wherein The lower source / drain pattern and the upper source / drain pattern have different conductive types.

11. The semiconductor device according to claim 1, wherein At least one of the lower source / drain pattern and the upper source / drain pattern has a plurality of epitaxial layers.

12. A semiconductor device comprising: a substrate; an active pattern including a lower pattern disposed on the substrate and a plurality of channel patterns spaced apart from each other, wherein the plurality of channel patterns include a lower channel pattern disposed on the lower pattern, and an upper channel pattern disposed on the lower channel pattern; a gate electrode surrounding the lower channel pattern and the upper channel pattern; a lower source / drain pattern disposed on the lower pattern and disposed on one side of the lower channel pattern; an upper source / drain pattern disposed on one side of the upper channel pattern; and a sidewall spacer disposed on two opposite side surfaces of the lower source / drain pattern, wherein at least one of the lower source / drain pattern and the upper source / drain pattern includes a plurality of epitaxial layers.

13. The semiconductor device according to claim 12, wherein The lower source / drain pattern and the upper source / drain pattern have different conductive types from each other.

14. The semiconductor device according to claim 13, wherein The lower source / drain pattern has n-type conductivity, The upper source / drain pattern has p-type conductivity, The upper source / drain pattern includes a first epitaxial layer and a second epitaxial layer, and the first epitaxial layer has a first conductivity type, and the second epitaxial layer has a second conductivity type different from the first conductivity type. The first epitaxial layer contacts the upper channel pattern on both sides of the upper source / drain pattern, and the second epitaxial layer extends along an outer surface of the first epitaxial layer that does not contact the upper channel pattern.

15. The semiconductor device according to claim 13, wherein The lower source / drain pattern has n-type conductivity, The upper source / drain pattern has p-type conductivity, The lower source / drain pattern includes a first epitaxial layer and a second epitaxial layer, The second epitaxial layer is disposed on the first epitaxial layer, and The first epitaxial layer is disposed to surround at least a portion of a side surface of the second epitaxial layer and a lower surface of the second epitaxial layer.

16. The semiconductor device according to claim 13, wherein The lower source / drain pattern has p-type conductivity, The upper source / drain pattern has n-type conductivity, The lower source / drain pattern includes a first epitaxial layer and a second epitaxial layer, The first epitaxial layer is formed to contact the upper channel pattern on both sides of the lower source / drain pattern and to contact the lower pattern, The second epitaxial layer is disposed on the first epitaxial layer, The first epitaxial layer is disposed to surround at least a portion of a side surface of the second epitaxial layer and a lower surface of the second epitaxial layer, and At least a portion of a side surface of the first epitaxial layer contacts the sidewall spacer, and another portion of a side surface of the second epitaxial layer contacts the sidewall spacer.

17. The semiconductor device according to claim 13, wherein The lower source / drain pattern has p-type conductivity, The upper source / drain pattern has n-type conductivity, The upper source / drain pattern includes a first epitaxial layer, a second epitaxial layer, and a third epitaxial layer, The upper channel pattern includes a first upper channel pattern and a second upper channel pattern spaced apart from each other in a horizontal direction, the first epitaxial layer contacts the first upper channel pattern, and the second epitaxial layer contacts the second upper channel pattern, and The third epitaxial layer is disposed between the first epitaxial layer and the second epitaxial layer.

18. The semiconductor device of claim 13, further comprising: A dielectric isolation layer is disposed between the lower source / drain pattern and the upper source / drain pattern.

19. The semiconductor device according to claim 18, wherein The dielectric isolation layer includes: a first region facing an upper surface of the lower source / drain pattern; a second region extending upward from a first end of the first region; a third region extending upward from a second end of the first region opposite the first end; a fourth region extending downward from a third end of the first region connected to the first end and the second end; and a fifth region extending downward from a fourth end of the first region opposite the third end, and an upper surface of each of the second region and the third region faces a lower surface of the upper source / drain pattern. 20.A semiconductor device comprising: a substrate; an active pattern including a lower pattern extending in a first direction and disposed on the substrate, and a plurality of channel patterns spaced apart from each other in a second direction perpendicular to the first direction, wherein each of the plurality of channel patterns includes a lower channel pattern disposed on the lower pattern, and an upper channel pattern disposed on the lower channel pattern; a gate electrode surrounding each of the lower channel pattern and the upper channel pattern; a lower source / drain pattern disposed on the lower pattern and disposed on at least one side of the lower channel pattern; an upper source / drain pattern disposed on at least one side of the upper channel pattern; a dielectric isolation layer isolating the lower source / drain pattern and the upper source / drain pattern from each other such that the lower source / drain pattern and the upper source / drain pattern are spaced apart from each other; and a sidewall spacer comprising a first sidewall spacer in contact with and defining a first side surface of the lower source / drain pattern, and a second sidewall spacer in contact with and defining a second side surface of the lower source / drain pattern, wherein the first side surface and the second side surface are opposite side surfaces of the lower source / drain pattern, wherein the first sidewall spacer and the second sidewall spacer are arranged such that a horizontal distance between the first sidewall spacer and the second sidewall spacer decreases in a direction towards a top of the first sidewall spacer and the second sidewall spacer, the lower source / drain pattern and the upper source / drain pattern have different conductivity types, and at least one of the lower source / drain pattern and the upper source / drain pattern comprises a plurality of epitaxial layers.

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