Silicon carbide trench MOSFET device and preparation method thereof

Abstract

The invention belongs to the technical field of semiconductor device design, and discloses a silicon carbide trench MOSFET device and a preparation method thereof, the MOSFET device comprises a plurality of gate trenches and source electrode contact layers, the source electrode contact layers are arranged between two adjacent gate trenches, the depth of the source electrode contact layers is lower than that of the gate trenches, and the source electrode contact layers are arranged between the gate trenches. The bottom end of each gate trench is provided with a first thick P + structure and a shielding structure, the upper end of the first thick P + structure is exposed out of the bottom of the gate trench, and the shielding structure wraps the first thick P + structure. The bottom end of each gate trench is provided with the shielding structure and the first thick P + structure to form a full-surrounding gate oxide shielding layer at the bottom of the trench, so that the gate oxide can be better protected from being damaged by a high electric field, and the reliability and the performance of the device are improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of power semiconductors, and particularly relates to a silicon carbide trench MOSFET device and a preparation method. BACKGROUND

[0002] At present, with the increasing cost requirements of silicon carbide-based power semiconductor devices, device design manufacturers are continuously improving the power density of the devices. Using a trench structure, forming a gate oxide layer on the bottom and sidewall of the trench structure, and filling the inside of the trench structure with a material such as polysilicon to form a gate electrode is a common and effective improvement measure. For example, the existing Infineon semi-enclosed trench structure and the Rohm double-trench structure. However, the gate oxide layer of the silicon carbide device needs to be protected from high electric field breakdown to affect the reliability of the device.

[0003] Therefore, it is necessary to design a silicon carbide trench MOSFET device with a gate oxide layer protection structure.

[0004] At the same time, in the patent document with the publication number CN118737815A, a trench manufacturing method with a bottom shielding structure is proposed, which forms a P-type shielding layer by vertically injecting P-type impurities at the bottom of the trench and performing annealing treatment. This scheme describes from the perspective of process and structure, eliminating the redundant design amount of the shielding layer injection photolithography to the trench photolithography in the process, which can protect the gate oxide, but the floating shielding layer will cause the dynamic characteristics of the device to deteriorate during high-frequency switching. Moreover, due to the introduction of the shielding layer, the resistance between the source and the drain is also increased, which reduces the current density of the MOSFET device and negatively affects the performance of the device. SUMMARY

[0005] In view of the above technical problems, the present application provides a silicon carbide trench MOSFET device and a preparation method, which forms a fully-enclosed gate oxide shielding layer at the bottom of the trench by setting a shielding structure and a first dense P+ structure at the bottom end of each gate trench, thereby better protecting the gate oxide from high electric field damage and improving the reliability of the device.

[0006] To achieve the above technical purposes, the application adopts the following technical scheme: A silicon carbide trench MOSFET device, characterized in that: it comprises a plurality of gate trenches and a source contact layer, the source contact layer is arranged between two adjacent gate trenches, the depth of the source contact layer is lower than the depth of the gate trench, and the bottom end of each gate trench is provided with a first dense P+ structure and a shielding structure, the shielding structure covers the first dense P+ structure, and the upper end of the first dense P+ structure is exposed at the bottom of the gate trench.

[0007] Further, a connection trench is arranged between the at least two gate trenches, and a second dense P+ structure is arranged at the bottom of the connection trench and connected to the first dense P+ structures on both sides.

[0008] Further, the MOSFET device comprises, from bottom to top, a substrate, a first N-type epitaxial layer, a first N-type JFET implantation layer, a second N-type epitaxial layer, and a second N-type JFET implantation layer, the bottom end of the gate trench passes through the second N-type JFET implantation layer and the second N-type epitaxial layer and is located in the first N-type JFET implantation layer.

[0009] Further, the source contact layer comprises a P+ source contact region, two N+ source contact regions, and a P-well structure, the P+ source contact region is located between the two N+ source contact regions, the two N+ source contact regions are respectively adjacent to the gate trench on the corresponding side, the top of the P-well structure is in contact with the bottom of the P+ source contact region and the N+ source contact region, and the bottom of the P-well structure is in contact with the top of the second N-type JFET implantation layer.

[0010] Further, the N-type impurity concentration of the first N-type epitaxial layer is 6e15-1.5e16, and the thickness is 6 ~11 The N-type impurity concentration of the second N-type epitaxial layer is 6e15-2e18, and the thickness is 2 ~4 The depth of the gate trench is 1.0 ~1.5 .

[0011] A preparation method of a silicon carbide trench MOSFET device, characterized by comprising the following steps: An early-stage process: generating an epitaxial layer on a substrate and a source contact layer on the epitaxial layer; Trench etching: opening a plurality of gate trenches passing through the source contact layer and extending into the epitaxial layer by an etching process, and the depth of the source contact layer is lower than the depth of the gate trench; Impurity implantation: implanting P-type impurities in a preset range of the epitaxial layer at the bottom end of each gate trench to form a shielding structure; implanting P-type impurities in the corresponding shielding structure directly below the bottom of each gate trench to form a first dense P+ structure covered by the shielding structure, and the upper end of the first dense P+ structure is exposed from the bottom of the gate trench.

[0012] Further, the epitaxial layer comprises a first N-type epitaxial layer, and the early-stage process specifically comprises: Implanting N-type impurities on the surface of the first N-type epitaxial layer to form a first N-type JFET implantation layer; Manufacturing a second N-type epitaxial layer on the surface of the first N-type JFET implantation layer; The first preset region of the surface of the second N-type epitaxial layer is injected with N-type impurities to form an N+ source contact region, and the second preset region of the surface of the second N-type epitaxial layer is injected with P-type impurities to form a P+ source contact region; the first preset depth of the interior of the second N-type epitaxial layer is injected with P-type impurities to form a P well structure, the top of the P well structure being in contact with the bottom of the N+ source contact region and the P+ source contact region; the second preset depth of the interior of the second N-type epitaxial layer is injected with N-type impurities to form a second N-type JFET injection layer, the top of the second N-type JFET injection layer being in contact with the bottom of the P well structure, and the N+ source contact region, the P+ source contact region and the P well structure constituting the source contact layer; Further, the trench etching process specifically comprises: A mask layer is covered on the top of the N+ source contact region and the P+ source contact region, and a plurality of first trenches passing through the N+ source contact region are formed by a mask etching process, the bottom of the first trench being located in the P well structure; P-type impurities are injected into a preset range below the first trench to form a shielding structure, the top of the shielding structure being in contact with the bottom of the second N-type JFET injection layer and the bottom of the first N-type JFET injection layer; The depth of the first trench is deepened by a mask etching process to obtain a second trench, the bottom of the second trench being located in the shielding structure, and the first trench and the second trench constituting the gate trench; P-type impurities are injected into a preset range below the second trench to form a first dense P+ structure covered by the shielding structure, the upper end of the first dense P+ structure being exposed from the bottom of the gate trench.

[0013] Further, in the trench etching process, at least a connecting trench is opened between two gate trenches when the depth of the first trench is deepened by a mask etching process; P-type impurities are injected into a preset range below the connecting trench to form a second dense P+ structure, the second dense P+ structure being connected with the first dense P+ structure at the bottom of the gate trench on both sides.

[0014] Further, the depth of the first trench is 0.4 ~0.8 , the depth of the shielding structure is 1.0 ~2.5 , and the total depth of the gate trench formed by the first trench and the second trench is 1.0 ~1.5 .

[0015] Thanks to the above technical scheme, the present application has the following technical effects: (1) The present invention proposes a silicon carbide trench MOSFET device, which forms a fully surrounding gate oxide shielding layer at the bottom of each gate trench by arranging a shielding structure and a first concentrated P+ structure at the bottom of each gate trench. This can better protect the gate oxide from damage by high electric fields and improve the reliability of the device.

[0016] A connecting trench is provided between at least two gate trenches, and a second concentrated P+ structure is provided at the bottom of the connecting trench. The second concentrated P+ structure is connected to the first concentrated P+ structures on both sides. The P+ structure in the shielding layer is used for grounding. The potential is stabilized by grounding the shielding layer, effectively optimizing the compromise relationship between grounding resistance and on-resistance, and conveniently obtaining an appropriate compromise between current density and robustness by adjusting the layout and grounding method.

[0017] (2) The present invention proposes a silicon carbide trench MOSFET device, which suppresses the JFET resistance caused by the newly added shielding structure and improves the current density through a double JFET layer injection design below the source contact layer.

[0018] (3) The silicon carbide trench MOSFET device proposed in the present invention eliminates the redundant design of the trench lithography due to the shielding layer injection lithography by using the shielding layer self-aligned injection technology. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] Figure 1 Schematic diagram of the cross-sectional structure of the silicon carbide trench MOSFET device proposed in Example 1; Figure 2 for Figure 1 Schematic diagram of the MOSFET device preparation process from Step 1 to Step 2; Figure 3 for Figure 1 Schematic diagram of the MOSFET device preparation process from Step 3 to Step 4; Figure 4 for Figure 1 Schematic diagram of Step 5 of the preparation process of the MOSFET device shown; Figure 5 for Figure 1 Schematic diagram of Step 6 of the MOSFET device preparation process shown Figure 1 ; Figure 6 for Figure 1 Schematic diagram of Step 6 of the MOSFET device preparation process shown Figure 2 ; Figure 7 Schematic diagram of Step 5 of the fabrication process for the silicon carbide trench MOSFET device proposed in Example 2; Figure 8The layout design of the stripe structure of the silicon carbide trench MOSFET device proposed in Example 2; Figure 9 Layout design 1 of the square structure of the silicon carbide trench MOSFET device proposed in Example 2; Figure 10 Layout design 2 of the square structure of the silicon carbide trench MOSFET device proposed in Example 2; Figure 11 This is the layout design 3 of the square structure of the silicon carbide trench MOSFET device proposed in Example 2.

[0020] Among them, 100, substrate; 1, first N-type epitaxial layer; 2, first N-type JFET injection layer; 3, second N-type epitaxial layer; 4, N+ source contact region; 5, P+ source contact region; 6, P-well structure; 7, second N-type JFET injection layer; 8, mask layer; 9, first trench; 10, shielding structure; 11, second trench; 12, first concentrated P+ structure; 13, second concentrated P+ structure; 14, first via; 15, second via; 16, connecting trench. DETAILED DESCRIPTION

[0021] In order to further illustrate the technical means and effects adopted by the present invention to achieve the predetermined purpose of the invention, the specific implementation methods, structures, features and effects of the present invention are described in detail below in conjunction with the accompanying drawings and preferred embodiments.

[0022] Example 1 The present invention proposes a silicon carbide trench MOSFET device, including multiple gate trenches and source contact layers. The source contact layer is arranged between two adjacent gate trenches. The depth of the source contact layer is lower than the depth of the gate trench. The bottom end of each gate trench is provided with a first concentrated P+ structure 12 and a shielding structure 10. The upper end of the first concentrated P+ structure 12 is exposed at the bottom of the gate trench. The shielding structure 10 covers the first concentrated P+ structure 10, forming a structure that fully shields the bottom of the trench.

[0023] like Figure 1 In the example shown, the MOSFET device includes a substrate 100, a first N-type epitaxial layer 1, a first N-type JFET injection layer 2, a second N-type epitaxial layer 3, and a second N-type JFET injection layer 7 arranged from bottom to top, wherein the bottom end of the gate trench passes through the second N-type JFET injection layer 7 and the second N-type epitaxial layer 3, and is located in the first N-type JFET injection layer 2.

[0024] The source contact layer comprises a P+ source contact region 5, two N+ source contact regions 4 and a P well structure 6, the P+ source contact region 5 is located between the two N+ source contact regions 4, the two N+ source contact regions 4 are respectively adjacent to the corresponding side gate trench, the top of the P well structure 6 is in contact with the bottom of the P+ source contact region 5 and the N+ source contact region 4, and the bottom of the P well structure 6 is in contact with the top of the second N type JFET injection layer 7.

[0025] In the embodiment, the N type impurity concentration of the first N type epitaxial layer 1 is 6e15-1.5e16, and the thickness is 6 ~11 The N type impurity concentration of the second N type epitaxial layer 3 is 6e15-2e18, and the thickness is 2 ~4 The depth of the gate trench is 1.0 ~1.5 .

[0026] In combination Figures 2 to 6 Taking a 1200V MOSFET device as an example, the preparation process is introduced as follows: Step 1, injecting N type impurities on the surface of the first N type epitaxial layer 1 to form a first N type JFET injection layer 2, the purpose of injecting N type impurities is to reduce the JFET resistance at the first JFET position; the N type impurity concentration of the first N type epitaxial layer 1 is 6e15-1.5e16, and the thickness is 6 ~11 .

[0027] Step 2, making a second N type epitaxial layer 3 on the surface of the first N type JFET injection layer 2, the N type impurity concentration of the second N type epitaxial layer is 6e15-2e18, and the thickness is 2 ~4 The concentration range of the second N type epitaxial layer is wide, which is convenient for adjusting the final concentration by subsequent doping.

[0028] Step 3, injecting N type impurities on the first preset area of the surface of the second N type epitaxial layer 3 to form an N+ source contact region 4, and injecting P type impurities on the second preset area of the surface of the second N type epitaxial layer 3 to form a P+ source contact region 5; injecting P type impurities at a first preset depth inside the second N type epitaxial layer 3 to form a P well structure 6, the top of the P well structure 6 is in contact with the bottom of the N+ source contact region 4 and the P+ source contact region 5; injecting N type impurities at a second preset depth inside the second N type epitaxial layer 3 to form a second N type JFET injection layer 7, the top of the second N type JFET injection layer 7 is in contact with the bottom of the P well structure 6, and the N+ source contact region 4, the P+ source contact region 5 and the P well structure 6 constitute a source contact layer.

[0029] Step 4: Cover the top of the N+ source contact region 4 and the P+ source contact region 5 with a mask layer 8, and form a plurality of first trenches 9 through the N+ source contact region 4 by a mask etching process. The bottom of the first trench 9 is located in the P well structure 6. The depth of the first trench 9 is 0.4 ~10.8 ; The preset depth 1.0 below the first groove 9 ~2.5 P-type impurities are implanted into the range to form a shielding structure 10 , the top of the shielding structure 10 contacts the bottom of the second N-type JFET injection layer 7 , and the bottom contacts the bottom of the first N-type JFET injection layer 2 .

[0030] Step 5: Deepen the first trench 9 (depth 1.0) by mask etching process. ~1.5 ), obtaining a second trench 11, the bottom of the second trench 11 is located in the shielding structure 10, and the first trench 9 and the second trench 11 constitute a gate trench; P-type impurities are injected into a preset range below the second trench 11 to form a first concentrated P+ structure 12 covered by the shielding structure 10. The purpose is to form an ohmic contact to achieve a grounding effect of the shielding layer. The upper end of the first concentrated P+ structure 12 is exposed at the bottom of the gate trench.

[0031] Step 6: After high temperature activation of impurities, gate oxide is generated and poly silicon is deposited to make the gate electrode.

[0032] Step 7, make emitter contact on the front and lead it out with metal; Figure 5 and Figure 6 As shown, a double JFET is formed directly below the source contact layer. This design can suppress the JFET resistance caused by the shielding layer structure and effectively improve the current density. According to the layout design, holes are drilled at appropriate locations, such as the first via 14 and the second via 15, and then filled with metal to form metal vias connected to the source potential.

[0033] The depth of the first groove 9 is preferably 0.4 ~0.8 , the depth of the shielding structure 10 is 1.0 ~2.5 The total depth of the gate trench formed by the first trench 9 and the second trench 11 is 1.0 ~1.5 .

[0034] Example 2 like Figure 7As shown, the embodiment proposes a silicon carbide trench MOSFET device, which is different from the MOSFET device in the first embodiment only in that a connecting trench 16 is arranged between the at least two gate trenches, and the bottom of the connecting trench 16 is provided with a second dense P+ structure 13, which is connected with the first dense P+ structures 12 on both sides.

[0035] The embodiment proposes a silicon carbide trench MOSFET device, which is different from the MOSFET device in the first embodiment only in that a connecting trench 16 is arranged between the at least two gate trenches, and the bottom of the connecting trench 16 is provided with a second dense P+ structure 13, which is connected with the first dense P+ structures 12 on both sides. In the trench etching process, when the depth of the first trench 9 is deepened by the mask etching process, the connecting trench 16 is opened between the at least two gate trenches, that is, by removing part of the hard mask, the positions between part of the first trenches 9 are also etched.

[0036] When the P-type impurities are injected into the preset range below the first trench 9, the bottom of the connecting trench 16 can also obtain dense P+ injection to form the second dense P+ structure 13, and by adjusting the P+ injection setting and etching depth, the second dense P+ structure 13 can be connected with the first dense P+ structures 12 at the bottom of the gate trenches on both sides.

[0037] Figure 8 The layout design of the strip structure of the silicon carbide trench MOSFET device of the second embodiment is shown. In the layout example, the dark stripes are the positions of the first etching, that is, the positions of the first trenches 9, and the light stripes are the positions of the second etching, that is, the positions of the connecting trenches 16. After the P-type impurities are injected into the preset range below the trenches, the P+ structure is formed, which is also the position of the shield layer grounding. In the layout example, the first trenches 9 of the device are parallel to each other without intersection. Figures 9 to 11 The layout design of the strip structure of the silicon carbide trench MOSFET device of the second embodiment is shown. In the layout example, the dark stripes are the positions of the first etching, that is, the positions of the first trenches 9, and the light stripes are the positions of the second etching, that is, the positions of the connecting trenches 16. After the P-type impurities are injected into the preset range below the trenches, the P+ structure is formed, which is also the position of the shield layer grounding. In the layout example, the first trenches 9 of the device are parallel to each other without intersection.

[0038] The application designs a unique shielding layer grounding mode, which does not affect the voltage resistance, and is convenient to adjust the number of groundings through the layout, and effectively optimizes the compromise relationship between the grounding resistance and the on-resistance Ron. The principle is to reduce the layout light color etching area, which can obtain more current channels, thereby effectively improving the chip current density. At the same time, the local position is far away from the light color grounding position, which directly leads to the increase of the grounding resistance of the local position. When the device is in high frequency switching, the larger grounding resistance will affect the dynamic characteristics of the remote local position, therefore, under a specific frequency working condition, the distribution of the light color area of the layout can be adjusted to obtain a better compromise between the current density and the robustness. Increasing the light color etching area can adapt to the actual production process.

[0039] In addition to the bar and square design, the application scheme is also applicable to hexagonal and other shape designs.

[0040] The above is only the preferred embodiment of the application, and does not limit the application in any form. Although the application has been disclosed as above, it is not intended to limit the application. Any person skilled in the art can make some changes or modifications to the above disclosed technical content without departing from the scope of the application, and any modification, change and modification of the above embodiment according to the technical essence of the application are still within the scope of the application.

Claims

1. A silicon carbide trench MOSFET device, characterized by: The invention comprises a plurality of gate trenches and a source contact layer, wherein the source contact layer is arranged between two adjacent gate trenches, the depth of the source contact layer is lower than the depth of the gate trench, and the bottom end of each gate trench is provided with a first concentrated P+ structure (12) and a shielding structure (10), wherein the shielding structure (10) covers the first concentrated P+ structure (12), and the upper end of the first concentrated P+ structure (12) is exposed at the bottom of the gate trench.

2. The silicon carbide trench MOSFET device of Claim 1, wherein: A connecting trench (16) is provided between at least two gate trenches, a second concentrated P+ structure (13) is provided at the bottom of the connecting trench (16), and the second concentrated P+ structure (13) is connected to the first concentrated P+ structures (12) on both sides.

3. The silicon carbide trench MOSFET device of Claim 1, wherein: The MOSFET device comprises a substrate (100), a first N-type epitaxial layer (1), a first N-type JFET injection layer (2), a second N-type epitaxial layer (3) and a second N-type JFET injection layer (7) arranged from bottom to top, wherein the bottom end of the gate trench passes through the second N-type JFET injection layer (7) and the second N-type epitaxial layer (3) and is located in the first N-type JFET injection layer (2).

4. The silicon carbide trench MOSFET device of Claim 3, wherein: The source contact layer comprises a P+ source contact region (5), an N+ source contact region (4) and a P-well structure (6); the P+ source contact region (5) is located between the two N+ source contact regions (4); the two N+ source contact regions (4) are respectively adjacent to the gate trenches on the corresponding sides; the top of the P-well structure (6) contacts the bottoms of the P+ source contact region (5) and the N+ source contact region (4); and the bottom of the P-well structure (6) contacts the top of the second N-type JFET injection layer (7).

5. The silicon carbide trench MOSFET device of Claim 3, wherein: The N-type impurity concentration of the first N-type epitaxial layer (1) is 6e15-1.5e16, and the thickness is 6 ~1 The N-type impurity concentration of the second N-type epitaxial layer (3) is 6e15-2e18, and the thickness is 2 ~3 The depth of the gate trench is 1.0 ~1.5 .

6. A method of fabricating a silicon carbide trench MOSFET device, the method comprising: Including process: Preliminary process: generating an epitaxial layer and a source contact layer located on the epitaxial layer on a substrate (100); Trench etching: Multiple gate trenches are created through the source contact layer and into the epitaxial layer through an etching process. The depth of the source contact layer is lower than the depth of the gate trenches. Impurity injection: P-type impurities are injected into a preset range of the epitaxial layer where the bottom of each gate trench is located to form a shielding structure (10); P-type impurities are injected into the corresponding shielding structure (10) just below the bottom of each gate trench to form a first concentrated P+ structure (12) covered by the shielding structure (10), and the upper end of the first concentrated P+ structure (12) is exposed at the bottom of the gate trench.

7. The method of producing a silicon carbide trench MOSFET device according to Claim 6, wherein The epitaxial layer includes a first N-type epitaxial layer (1), and the preliminary process specifically includes: Injecting N-type impurities into the surface of the first N-type epitaxial layer (1) to form a first N-type JFET injection layer (2); Fabricating a second N-type epitaxial layer (3) on the surface of the first N-type JFET injection layer (2); A first preset region on the surface of the second N-type epitaxial layer (3) is injected with N-type impurities to form an N+ source contact region (4), and a second preset region on the surface of the second N-type epitaxial layer (3) is injected with P-type impurities to form a P+ source contact region (5); a first preset depth inside the second N-type epitaxial layer (3) is injected with P-type impurities to form a P-well structure (6), the top of the P-well structure (6) being in contact with the bottom of the N+ source contact region (4) and the P+ source contact region (5); a second preset depth inside the second N-type epitaxial layer (3) is injected with N-type impurities to form a second N-type JFET injection layer (7), the top of the second N-type JFET injection layer (7) being in contact with the bottom of the P-well structure (6), and the N+ source contact region (4), the P+ source contact region (5) and the P-well structure (6) forming the source contact layer.

8. The method of producing a silicon carbide trench MOSFET device according to Claim 7, wherein The trench etching process specifically comprises: A mask layer (8) is covered on the top of the N+ source contact region (4) and the P+ source contact region (5), and a plurality of first trenches (9) passing through the N+ source contact region (4) are formed by a mask etching process, the bottom of the first trench (9) being located in the P-well structure (6); P-type impurities are injected into a preset range below the first trench (9) to form a shielding structure (10), the top of the shielding structure (10) being in contact with the bottom of the second N-type JFET injection layer (7) and the bottom of the shielding structure (10) being in contact with the bottom of the first N-type JFET injection layer (2); The depth of the first trench (9) is deepened by a mask etching process to obtain a second trench (11), the bottom of the second trench (11) being located in the shielding structure (10), and the first trench (9) and the second trench (11) forming the gate trench; P-type impurities are injected into a preset range below the second trench (11) to form a first dense P+ structure (12) covered by the shielding structure (10), the upper end of the first dense P+ structure (12) being exposed from the bottom of the gate trench.

9. The method of producing a silicon carbide trench MOSFET device according to Claim 8, wherein In the trench etching process, at least a connecting trench (16) is opened between two gate trenches when the depth of the first trench (9) is deepened by a mask etching process; P-type impurities are injected into a preset range below the connecting trench (16) to form a second dense P+ structure (13), the second dense P+ structure (13) being connected with the first dense P+ structure (12) at the bottom of the gate trench on both sides.

10. The method of producing a silicon carbide trench MOSFET device of claim 8, wherein The depth of the first trench (9) is 0.4 ~0.8 The depth of the shielding structure (10) is 1.0 ~2.5 The total depth of the gate trench formed by the first trench (9) and the second trench (11) is 1.0 ~1.5 .

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