Three-dimensional semiconductor device and method of manufacturing same

Abstract

A three-dimensional semiconductor device may include: a lower active region on a substrate, including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; an upper active region on the lower active region, including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a gate electrode disposed on the lower channel pattern and the upper channel pattern and extending in the first direction; and an insulating structure disposed on one side of the lower active region and the upper active region and extending in a second direction, the first direction and the second direction being parallel to the top surface of the substrate. The insulating structure may include a first portion adjacent to the lower active region, and a second portion disposed on the first portion and adjacent to the upper active region. A side surface of the insulating structure may have a stepped structure at a boundary between the first portion and the second portion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0051672 filed on April 17, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0003] The present disclosure relates to a three-dimensional semiconductor device and a method of manufacturing the same, and particularly, to a three-dimensional semiconductor device including a field effect transistor and a method of manufacturing the same. Background Art

[0004] A semiconductor device includes an integrated circuit composed of metal oxide semiconductor field effect transistors (MOS-FETs). To meet the growing demand for semiconductor devices with small pattern sizes and reduced design rules, MOS-FETs are being actively scaled down. Scaling down MOS-FETs can lead to degradation of the operating properties of the semiconductor device. Various research efforts are underway to overcome the technical limitations associated with scaling down semiconductor devices and achieve high-performance semiconductor devices. Summary of the Invention

[0005] Embodiments of the inventive concept provide a three-dimensional semiconductor device having increased integration density and improved electrical characteristics.

[0006] Embodiments of the inventive concept provide a method of fabricating a three-dimensional semiconductor device having increased integration density and improved electrical characteristics.

[0007] According to an embodiment of the present invention, a three-dimensional semiconductor device may include: a lower active region located on a substrate, the lower active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; an upper active region located on the lower active region, the upper active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a gate electrode disposed on the lower and upper channel patterns and extending in a first direction; and an insulating structure disposed on one side of the lower and upper active regions and extending in a second direction, the first and second directions being parallel to the top surface of the substrate and intersecting each other. The insulating structure may include a first portion adjacent to the lower active region and a second portion disposed on the first portion and adjacent to the upper active region. A side surface of the insulating structure may have a stepped structure at a boundary between the first and second portions.

[0008] According to embodiments of the inventive concept, a three-dimensional semiconductor device can include a lower active region on a substrate, the lower active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; an upper active region stacked on the lower active region, the upper active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a gate electrode disposed on the lower channel pattern and the upper channel pattern and extending in a first direction; and an insulating structure disposed on a side of the lower active region and the upper active region and extending in a second direction, the first direction and the second direction being parallel to a top surface of the substrate and crossing each other. The insulating structure can include a first portion adjacent to the lower active region and a second portion disposed on the first portion and adjacent to the upper active region. A side surface of the first portion can protrude in the first direction with respect to a side surface of the second portion. The first portion can have a stepped surface connecting the side surface of the first portion to the side surface of the second portion.

[0009] According to embodiments of the inventive concept, a three-dimensional semiconductor device can include lower active regions spaced apart from each other in a first direction on a substrate, each of the lower active regions including a lower channel pattern and a lower source / drain pattern, the lower channel patterns being spaced apart from each other in a second direction crossing the first direction, the lower source / drain pattern being connected to the lower channel pattern; upper active regions respectively stacked on the lower active regions, each of the upper active regions including an upper channel pattern and an upper source / drain pattern, the upper channel patterns being spaced apart from each other in the second direction, the upper source / drain pattern being connected to the upper channel pattern; a gate electrode respectively disposed on the lower channel pattern and the upper channel pattern, the gate electrode extending in the first direction and being spaced apart from each other in the second direction; an insulating structure disposed between the lower active regions and the upper active regions and extending in a vertical direction from the lower active regions to the upper active regions; a cut pattern spaced apart from the insulating structure in the first direction, one of the lower active regions and one of the upper active regions being interposed between the cut pattern and the insulating structure, and extending in the vertical direction from the lower active regions to the upper active regions; and a vertical via member penetrating the cut pattern in the vertical direction. The insulating structure can include a first portion adjacent to the lower active regions and a second portion disposed on the first portion and adjacent to the upper active regions. A side surface of the insulating structure can have a boundary between the first portion and the second portion, the boundary having a stepped structure. The boundary can be located at a level higher than a bottom surface of the upper source / drain pattern and lower than a top surface of the upper source / drain pattern. BRIEF DESCRIPTION OF DRAWINGS

[0010] Figure 1 is a conceptual view illustrating a logic unit of a semiconductor device according to a comparative example.

[0011] Figure 2 is a conceptual view illustrating a logic unit of a semiconductor device according to embodiments of the inventive concept.

[0012] Figure 3 is a plan view showing a three-dimensional semiconductor device according to an embodiment of the present inventive concept.

[0013] Figures 4A-4D are cross-sectional views taken along lines A-A', B-B', C-C', and D-D' of Figure 3 , respectively.

[0014] Figure 5 is an enlarged cross-sectional view showing a portion "M" of Figure 4B .

[0015] Figures 6A-6C are enlarged cross-sectional views each showing a portion "M" of Figure 4B .

[0016] Figures 7A-19D are cross-sectional views showing a method of manufacturing a semiconductor device according to an embodiment of the present inventive concept.

[0017] Figure 20A and Figure 20B are cross-sectional views taken along lines A-A' and B-B' of Figure 3 , respectively. DETAILED DESCRIPTION

[0018] Figure 1 is a conceptual view showing a logic cell of a semiconductor device according to a comparative example. In detail, Figure 1 a logic cell of a two-dimensional device according to a comparative example can be shown.

[0019] Referring to Figure 1 , a single-height cell SHC' can be provided. For example, a first power line POR1 and a second power line POR2 can be disposed on the substrate 100. A drain voltage (e.g., a power supply voltage (VDD)) can be applied to one of the first power line POR1 and the second power line POR2. A source voltage (e.g., a ground voltage (VSS)) can be applied to the other of the first power line POR1 and the second power line POR2. In an embodiment, the source voltage can be applied to the first power line POR1, and the drain voltage can be applied to the second power line POR2.

[0020] A single-height cell SHC' can be defined between the first power line POR1 and the second power line POR2. The single-height cell SHC' can include a lower active region LAR and an upper active region UAR. One of the lower active region LAR and the upper active region UAR can be a PMOSFET region, and the other of the lower active region LAR and the upper active region UAR can be an NMOSFET region. For example, the lower active region LAR can be an NMOSFET region, and the upper active region UAR can be a PMOSFET region. For example, the single-height cell SHC' can include a CMOS structure disposed between the first power line POR1 and the second power line POR2.

[0021] The semiconductor device according to the comparative example can be a two-dimensional device in which transistors of a front-end-of-line (FEOL) layer are arranged two-dimensionally. For example, the NMOSFET of the lower active region LAR can be spaced apart from the PMOSFET of the upper active region UAR in the first direction D1.

[0022] Each of the lower active region LAR and the upper active region UAR can have a first width W1 in the first direction D1. In the comparative example, a length of the single-height cell SHC' in the first direction D1 can be defined as a first height HE1. The first height HE1 can be substantially equal to a distance (e.g., a pitch) between the first power line POR1 and the second power line POR2.

[0023] The single-height cell SHC' can constitute a single logic cell. In this specification, a logic cell can denote a logic device (e.g., AND, OR, XOR, XNOR, inverter, etc.) configured to perform a specific function. In other words, a logic cell can include transistors constituting a logic device and interconnection lines connecting the transistors to each other. The logic device can be a CMOS device.

[0024] In the comparative example, since the single-height cell SHC' includes a two-dimensional device, the lower active region LAR and the upper active region UAR can not overlap each other in a plane of Figure 1 (e.g., in a plane of the two-dimensional device), and can be spaced apart from each other in the first direction D1. Accordingly, the first height HE1 of the single-height cell SHC' should be defined as spanning the lower active region LAR and the upper active region UAR spaced apart from each other in the first direction D1. As a result, the first height HE1 of the single-height cell SHC' in the comparative example can have a relatively increased value. For example, the single-height cell SHC' in the comparative example can have a relatively large area.

[0025] Figure 2 is a conceptual diagram illustrating a logic cell of a semiconductor device according to an embodiment of the inventive concept. Figure 2 illustrates a logic cell of a three-dimensional device according to an embodiment of the inventive concept.

[0026] Referring to Figure 2 A single-height cell SHC can be provided that includes a three-dimensional device having stacked transistors, such as three-dimensional (3D) field effect transistors (FETs), complementary FETs (CFETs), and / or stacked FETs (SFETs). In detail, a first power line POR1 and a second power line POR2 can be disposed on a substrate 100. The single-height cell SHC can be defined between the first power line POR1 and the second power line POR2.

[0027] The single-height cell SHC can include a lower active region LAR and an upper active region UAR. One of the lower active region LAR and the upper active region UAR can be a PMOSFET region, and the other of the lower active region LAR and the upper active region UAR can be an NMOSFET region. Thus, the single-height cell SHC can be a CMOS device.

[0028] In the present embodiment, the semiconductor device can be a three-dimensional device in which transistors of a FEOL layer are stacked vertically. Thus, the semiconductor device can be a 3D FET, a CFET, and / or a SFET. A lower active region LAR serving as a bottom layer can be disposed on the substrate 100, and an upper active region UAR serving as a top layer can be stacked on the lower active region LAR in a vertical direction (e.g., along a third direction D3). For example, an NMOSFET of the lower active region LAR can be disposed on the substrate 100, and a PMOSFET of the upper active region UAR can be stacked on the NMOSFET. The lower active region LAR and the upper active region UAR can be spaced apart from each other in the vertical direction (e.g., in the third direction D3).

[0029] Each of the lower active region LAR and the upper active region UAR can have a first width W1 in the first direction D1. In the present embodiment, a length of the single-height cell SHC in the first direction D1 can be defined as a second height HE2.

[0030] Since the single-height cell SHC according to the present embodiment includes a three-dimensional device (e.g., stacked transistors), the lower active region LAR and the upper active region UAR can overlap each other in a plane of Figure 2 (e.g., in a plane of the first direction D1 and the second direction D2). Thus, the second height HE2 of the single-height cell SHC can have a dimension that spans a single active region, or can be only moderately greater than the first width W1. As a result, as noted above, the second height HE2 of the single-height cell SHC according to the present three-dimensional embodiment can be less than the first height HE1 of a single-height cell SHC' in a two-dimensional device. Figure 1 (e.g., in a plane of the first direction D1 and the second direction D2). Thus, the second height HE2 of the single-height cell SHC can have a dimension that spans a single active region, or can be only moderately greater than the first width W1. As a result, as noted above, the second height HE2 of the single-height cell SHC according to the present three-dimensional embodiment can be less than the first height HE1 of a single-height cell SHC' in a two-dimensional device. Figure 2The plane (e.g., the D1-D2 plane) may have a relatively small area. Therefore, in a three-dimensional semiconductor device according to this embodiment, the integration density of the device can be increased by reducing the area of ​​the logic cell in the plane shown. However, adjacent cells in such a three-dimensional semiconductor device may suffer from short circuit problems, which can be prevented by the disclosed embodiments, as described below.

[0031] Figure 3 is a plan view illustrating a three-dimensional semiconductor device according to an embodiment of the inventive concept. Figures 4A-4D are along Figure 3 Cross-sectional views taken along lines AA', BB', CC' and DD'. Figure 3 and Figures 4A-4D The three-dimensional semiconductor device can be Figure 2 A specific example of a single-height unit.

[0032] Reference Figure 3 and Figures 4A-4D , a single height cell SHC may be provided on a substrate 100. The substrate 100 may include a top surface 100a and a bottom surface 100b opposite to each other. The top surface 100a may be the front surface of the substrate 100, and the bottom surface 100b may be the back surface of the substrate 100. In an embodiment, the substrate 100 may be an insulating substrate formed of or including a silicon-based insulating material (e.g., silicon oxide and / or silicon nitride). In an embodiment, the substrate 100 may be a semiconductor substrate made of silicon, germanium, or silicon germanium.

[0033] The device isolation layer 107 may be provided in the substrate 100. In the case where the single-height cells SHC are spaced apart from each other by a relatively large distance, the device isolation layer 107 may be provided between adjacent single-height cells in the single-height cells SHC. A cutting pattern CTP, which will be described below, may be provided to penetrate a portion of the device isolation layer 107. In embodiments, the device isolation layer 107 may be formed of or include at least one of a silicon-based insulating material (e.g., silicon oxide, silicon oxynitride, and silicon nitride).

[0034] A first lower insulating layer 101 may be disposed on the substrate 100. When viewed in a plan view, the first lower insulating layer 101 may overlap with a lower channel pattern LCH and an upper channel pattern UCH, which will be described below. When viewed in a plan view, the first lower insulating layer 101 may not overlap with a lower source / drain pattern LSD and an upper source / drain pattern USD, which will be described below. The first lower insulating layer 101 may be formed of or include at least one of a silicon-based insulating material (e.g., silicon oxide) and / or a semiconductor material (e.g., Si or SiGe).

[0035] Each of the single height cells SHC may be a logic cell constituting a logic circuit. Each of the single height cells SHC may be a logic cell, for example, as previously described with reference to Figure 2 The three-dimensional device described herein. The single height cells (SHCs) may be arranged in a first direction D1. In this specification, the first direction D1 and the second direction D2 may be parallel to the top surface 100a of the substrate 100 and may not be parallel to each other. The third direction D3 may be a vertical direction D3 perpendicular to the top surface 100a of the substrate 100. The first direction D1, the second direction D2, and the third direction D3 may not be parallel to each other.

[0036] The first, second, and third single height cells SHC1, SHC2, and SHC3 may be spaced apart from each other in the first direction D1. The second single height cell SHC2 may be disposed between the first and third single height cells SHC1 and SHC3.

[0037] The first single-height cell SHC1 and the second single-height cell SHC2 may be spaced apart from each other by a first distance INT1 in the first direction D1. The second single-height cell SHC2 and the third single-height cell SHC3 may be spaced apart from each other by a second distance INT2 in the first direction D1. The first distance INT1 may be greater than the second distance INT2. The second single-height cell SHC2 may be closer to the third single-height cell SHC3 than to the first single-height cell SHC1.

[0038] Each of the single-height cells SHC can include a lower active region LAR and an upper active region UAR that are sequentially stacked on the substrate 100. One of the lower active region LAR and the upper active region UAR can be a PMOSFET region, and the other of the lower active region LAR and the upper active region UAR can be an NMOSFET region. The lower active region LAR can be disposed as a bottom layer of the FEOL layers, and the upper active region UAR can be disposed as a top layer of the FEOL layers. The NMOSFET and PMOSFET of the lower active region LAR and the upper active region UAR can be vertically stacked to constitute a three-dimensional stacked transistor. In an embodiment, the lower active region LAR can be an NMOSFET region, and the upper active region UAR can be a PMOSFET region.

[0039] Each of the lower active region LAR and the upper active region UAR can be a strip or line-shaped region extending in the second direction D2. One of the cut pattern CTP or the insulating structure IS can be disposed between the single-height cells SHC adjacent to each other. In some examples, the insulating structure IS can function as a wall to separate the single-height cells SHC (e.g., NMOSFET and PMOSFET) from each other, for example, to form a CMOS device such as a 3D FET, a CFET, and / or a SFET. In some examples, the insulating structure IS can additionally be configured as a wall-like, such as vertically oriented, having opposite faces, etc. For example, the insulating structure IS can be disposed between the lower active regions LAR and between the upper active regions UAR of adjacent single-height cells SHC. The cut pattern CTP can be spaced apart from the insulating structure IS in the first direction D1 with one of the lower active regions LAR interposed between the cut pattern CTP and the insulating structure IS. The cut pattern CTP can be spaced apart from the insulating structure IS in the first direction D1 with one of the upper active regions UAR interposed between the cut pattern CTP and the insulating structure IS. The cut pattern CTP and the insulating structure IS can be alternately disposed between the single-height cells SHC. For example, the insulating structure IT can be disposed on one side of the single-height cells SHC, and the cut pattern CTP can be disposed on the opposite side of the single-height cells SHC. In other words, the insulating structure IS can be disposed on one side of the lower active regions LAR and the upper active regions UAR, and the cut pattern CTP can be disposed on the opposite side of the lower active regions LAR and the upper active regions UAR. Accordingly, the single-height cells SHC can have an asymmetric structure.

[0040] According to embodiments of the inventive concepts, the cut pattern CTP can be disposed between a first single-height cell SHC1 and a second single-height cell SHC2. The insulating structure IS can be disposed between the second single-height cell SHC2 and a third single-height cell SHC3. The cut pattern CTP can be disposed in a case where a distance between the single-height cells SHC is relatively large. The insulating structure IS can be disposed in a case where a distance between the single-height cells SHC is relatively small.

[0041] The cut pattern CTP can be arranged to separate the single-height cells SHC from each other. Adjacent single-height cells SHC in the single-height cells SHC can be spaced apart from each other in the first direction D1 via the cut pattern CTP. The cut pattern CTP can be a strip or line pattern extending in the second direction D2.

[0042] The insulating structure IS can be arranged to separate the single-height cells SHC from each other. Adjacent single-height cells SHC in the single-height cells SHC can be spaced apart from each other in the first direction D1 via the insulating structure IS. The insulating structure IS can be a strip or line structure extending in the second direction D2.

[0043] The lower active region LAR can include a lower channel pattern LCH and a lower source / drain pattern LSD. The lower channel pattern LCH can be interposed between a pair of lower source / drain patterns LSD. The lower channel pattern LCH can connect the pair of lower source / drain patterns LSD to each other. The lower channel pattern LCH can be spaced apart from the substrate 100 in the vertical direction D3, with the first lower insulating layer 101 interposed between the lower channel pattern LCH and the substrate 100.

[0044] The cut pattern CTP and the insulating structure IS can be alternately arranged between the lower channel patterns LCH, which are spaced apart from each other in the first direction D1. In a case where a distance between the lower channel patterns LCH spaced apart from each other in the first direction D1 is relatively small, the insulating structure IS can be arranged to separate the lower channel patterns LCH from each other. In a case where a distance between the lower channel patterns LCH spaced apart from each other in the first direction D1 is relatively large, the cut pattern CTP can be arranged between the lower channel patterns LCH. According to an embodiment of the inventive concept, the cut pattern CTP can be arranged between the lower channel pattern LCH in the first single-height cell SHC1 and the lower channel pattern LCH in the second single-height cell SHC2. The insulating structure IS can be arranged between the lower channel pattern LCH in the second single-height cell SHC2 and the lower channel pattern LCH in the third single-height cell SHC3. The lower channel pattern LCH in the second single-height cell SHC2 and the lower channel pattern LCH in the third single-height cell SHC3 can be spaced apart from each other in the first direction D1 via the insulating structure IS.

[0045] The lower channel pattern LCH can include a first semiconductor pattern SP1 and a second semiconductor pattern SP2 stacked to be spaced apart from each other in the vertical direction D3. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be formed of or include at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). In an embodiment, each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be formed of or include crystalline silicon. Each of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be a nanosheet. As an example, the lower channel pattern LCH can further include one or more semiconductor patterns stacked and spaced apart from the second semiconductor pattern SP2. The first semiconductor pattern SP1 can be a lowermost semiconductor pattern.

[0046] The lower source / drain pattern LSD can be disposed on the substrate 100. Each of the lower source / drain patterns LSD can be an epitaxial pattern formed through a selective epitaxial growth (SEG) process. In an embodiment, a top surface of the lower source / drain pattern LSD can be higher than a top surface of the second semiconductor pattern SP2 of the lower channel pattern LCH.

[0047] The lower source / drain pattern LSD can be doped with an impurity to have a first conductivity type. The first conductivity type can be an n-type or a p-type. In the present embodiment, the first conductivity type can be an n-type. The lower source / drain pattern LSD can be formed of or include silicon (Si) and / or silicon germanium (SiGe).

[0048] The first interlayer insulating layer 110 can be disposed on the lower source / drain pattern LSD. The first interlayer insulating layer 110 can cover the lower source / drain pattern LSD. The first interlayer insulating layer 110 can cover a top surface 100a of the substrate 100 and a top surface of the device isolation layer 107. A top surface of the first interlayer insulating layer 110 can be located at a higher level than a top surface of the lower source / drain pattern LSD. In the present specification, a level can indicate a distance measured in the vertical direction D3 from the top surface 100a of the substrate 100. The liner layer LIN can be disposed to conformingly cover the top surface of the first interlayer insulating layer 110. The liner layer LIN can be interposed between the first interlayer insulating layer 110 and a second interlayer insulating layer 120 to be described below.

[0049] A lower active contact LAC can be disposed under the lower source / drain pattern LSD. The lower active contact LAC can be electrically connected to the lower source / drain pattern LSD. The lower active contact LAC can vertically extend from the bottom surface 100b of the substrate 100 to the top surface 100a. A top surface of the lower active contact LAC can extend to a level higher than the top surface 100a of the substrate 100, and can be in direct contact with the lower source / drain pattern LSD. The lower active contact LAC can be formed of or include a metallic material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0050] An upper active region UAR can be disposed on the first interlayer insulating layer 110 and the liner layer LIN. The upper active region UAR can include an upper channel pattern UCH and an upper source / drain pattern USD. The upper channel pattern UCH can vertically overlap the lower channel pattern LCH, respectively. The upper source / drain pattern USD can vertically overlap the lower source / drain pattern LSD, respectively. The upper channel pattern UCH can be interposed between a pair of upper source / drain patterns USD. The upper channel pattern UCH can connect the pair of upper source / drain patterns USD to each other.

[0051] The cutting pattern CTP and the insulating structure IS can be alternately disposed between the upper channel patterns UCH spaced apart from each other in the first direction D1. In a case where a distance between the upper channel patterns UCH spaced apart from each other in the first direction D1 is relatively small, the insulating structure IS can be disposed to separate the upper channel patterns UCH from each other. In a case where a distance between the upper channel patterns UCH spaced apart from each other in the first direction D1 is relatively large, the cutting pattern CTP can be disposed between the upper channel patterns UCH. According to an embodiment of the inventive concept, the cutting pattern CTP can be disposed between the upper channel pattern UCH in the first single-height cell SHC1 and the upper channel pattern UCH in the second single-height cell SHC2. The insulating structure IS can be disposed between the upper channel pattern UCH in the second single-height cell SHC2 and the upper channel pattern UCH in the third single-height cell SHC3. The upper channel pattern UCH in the second single-height cell SHC2 can be spaced apart from the upper channel pattern UCH in the third single-height cell SHC3 in the first direction D1 via the insulating structure IS.

[0052] The upper channel pattern UCH can include a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 stacked to be spaced apart from each other in the vertical direction D3. The third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 of the upper channel pattern UCH can include the same semiconductor material as the first semiconductor pattern SP1 and the second semiconductor pattern SP2 of the lower channel pattern LCH. Each of the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4 can be a nanosheet. In an embodiment, the fourth semiconductor pattern SP4 can be an uppermost semiconductor pattern. In an embodiment, the upper channel pattern UCH can further include one or more semiconductor patterns stacked to be spaced apart from the fourth semiconductor pattern SP4.

[0053] At least one dummy channel pattern DSP can be interposed between the lower channel pattern LCH and the upper channel pattern UCH thereon. A seed layer SDL can be interposed between the dummy channel pattern DSP and the upper channel pattern UCH.

[0054] The dummy channel pattern DSP can be spaced apart from the lower source / drain pattern LSD and the upper source / drain pattern USD. In other words, the dummy channel pattern DSP can not be connected to any source / drain pattern. The dummy channel pattern DSP can be formed of or include a semiconductor material (e.g., silicon (Si), germanium (Ge), or silicon germanium (SiGe)) or a silicon-based insulating material (e.g., silicon oxide or silicon nitride). In an embodiment, the dummy channel pattern DSP can be formed of or include a silicon-based insulating material.

[0055] The upper source / drain pattern USD can be disposed on a top surface of the liner layer LIN. Each of the upper source / drain pattern USD can be an epitaxial pattern formed through a selective epitaxial growth (SEG) process. In an embodiment, a top surface of the upper source / drain pattern USD can be higher than a top surface of the fourth semiconductor pattern SP4 of the upper channel pattern UCH.

[0056] The upper source / drain pattern USD can be doped with an impurity to have a second conductivity type. The second conductivity type can be different from the first conductivity type of the lower source / drain pattern LSD. The second conductivity type can be a p-type. The upper source / drain pattern USD can be formed of or include at least one of silicon germanium (SiGe) and / or silicon (Si).

[0057] A plurality of gate electrodes GE may be disposed on the single-height cell SHC. Specifically, the gate electrodes GE may be disposed on the stacked lower channel pattern LCH and upper channel pattern UCH. When viewed in a plan view, the gate electrodes GE may be stripe-shaped patterns extending in a first direction D1. The gate electrodes GE may vertically overlap the stacked lower channel pattern LCH and upper channel pattern UCH.

[0058] The gate electrode GE may extend from the substrate 100 in a vertical direction D3 to a gate capping pattern GP, ​​which will be described below. The gate electrode GE may extend from the top surface of the device isolation layer 107 and the top surface of the first lower insulating layer 101 in the vertical direction D3 to the gate capping pattern GP, ​​which will be described below. The gate electrode GE may extend from the lower channel pattern LCH of the lower active region LAR to the upper channel pattern UCH of the upper active region UAR in a third direction D3. The gate electrode GE may extend along the third direction D3 from the lowermost semiconductor pattern (e.g., the first semiconductor pattern SP1) to the uppermost semiconductor pattern (e.g., the fourth semiconductor pattern SP4).

[0059] The gate electrode GE may be provided on the top surface, the bottom surface, and the opposite side surfaces of each of the first to fourth semiconductor patterns SP1 to SP4. For example, the transistor according to this embodiment may include a three-dimensional field effect transistor (e.g., a multi-bridge channel FET (MBCFET) or a gate-all-around FET (GAAFET)) in which the gate electrode GE is provided to three-dimensionally surround a channel pattern.

[0060] The gate electrode GE may include a lower gate electrode LGE disposed in a bottom layer of the FEOL layer (e.g., the lower active region LAR), and an upper gate electrode UGE disposed in a top layer of the FEOL layer (e.g., the upper active region UAR). The lower gate electrode LGE and the upper gate electrode UGE may vertically overlap each other. In an embodiment, the lower gate electrode LGE and the upper gate electrode UGE may be connected to each other. For example, the gate electrode GE according to this embodiment may be a common gate electrode in which the lower gate electrode LGE on the lower channel pattern LCH and the upper gate electrode UGE on the upper channel pattern UCH are connected to each other.

[0061] The lower gate electrode LGE may include a first internal electrode PO1 interposed between the first lower insulating layer 101 and the first semiconductor pattern SP1 , a second internal electrode PO2 interposed between the first and second semiconductor patterns SP1 and SP2 , and a third internal electrode PO3 interposed between the second semiconductor pattern SP2 and the dummy channel pattern DSP.

[0062] The upper gate electrode UGE can include a fourth inner electrode PO4 interposed between the dummy channel pattern DSP (or seed layer SDL) and a third semiconductor pattern SP3, a fifth inner electrode PO5 interposed between the third semiconductor pattern SP3 and a fourth semiconductor pattern SP4, and an outer electrode PO6 on the fourth semiconductor pattern SP4.

[0063] A pair of gate spacers GS can be respectively disposed on opposite side surfaces of the gate electrode GE. The pair of gate spacers GS can be respectively disposed on opposite side surfaces of the outer electrode PO6. The gate spacer GS can extend along the gate electrode GE and in the first direction D1. A top surface of the gate spacer GS can be higher than a top surface of the gate electrode GE. The top surface of the gate spacer GS can be coplanar with a top surface of a gate cap pattern GP to be described hereinafter. The top surface of the gate spacer GS can be coplanar with a top surface of the insulating structure IS. The gate spacer GS can be formed of or include at least one of SiCN, SiCON, and SiN. In an embodiment, the gate spacer GS can be a multi-layer structure including at least two different materials selected from SiCN, SiCON, and SiN.

[0064] The gate cap pattern GP can be disposed on a top surface of the gate electrode GE. The gate cap pattern GP can extend along the gate electrode GE or in the first direction D1. In an embodiment, the gate cap pattern GP can be formed of or include at least one of SiON, SiCN, SiCON, and SiN.

[0065] The gate insulating layer GI can be interposed between the gate electrode GE and the first to fourth semiconductor patterns SP1 to SP4. The gate insulating layer GI can be formed of or include at least one of silicon oxide, silicon oxynitride, and / or a high-k dielectric material. In an embodiment, the gate insulating layer GI can include a silicon oxide layer formed to directly cover the semiconductor patterns SP1 to SP4 and a high-k dielectric layer formed on the silicon oxide layer. In other words, the gate insulating layer GI can be a multi-layer structure including the silicon oxide layer and the high-k dielectric layer.

[0066] The high-k dielectric layer can be formed of or include at least one of a high-k dielectric material having a dielectric constant higher than that of silicon oxide. For example, the high-k dielectric material can include at least one of hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0067] The lower gate electrode LGE can include a first work function metal pattern on the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The upper gate electrode UGE can include a second work function metal pattern on the third semiconductor pattern SP3 and the fourth semiconductor pattern SP4. Each of the first work function metal pattern and the second work function metal pattern can be formed of a material including at least one metal element selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo) and nitrogen (N). The first work function metal pattern and the second work function metal pattern can have different work functions from each other. The gate electrode GE can include at least one of a low-resistance metal (e.g., tungsten (W), ruthenium (Ru), aluminum (Al), titanium (Ti), and tantalum (Ta)) on the first work function metal pattern and the second work function metal pattern. In an embodiment, the outer electrode PO6 can include the second work function metal pattern as well as the low-resistance metal.

[0068] A second interlayer insulating layer 120 can be disposed on the upper source / drain pattern USD and the gate electrode GE. The second interlayer insulating layer 120 can cover the upper source / drain pattern USD. The second interlayer insulating layer 120 can cover a top surface of the liner layer LIN. A top surface of the second interlayer insulating layer 120 can be coplanar with a top surface of an upper active contact UAC to be described below. A third interlayer insulating layer 130 can cover the second interlayer insulating layer 120.

[0069] The upper active contact UAC can be disposed to penetrate the second interlayer insulating layer 120 and can be electrically connected to the upper source / drain pattern USD, respectively. The upper active contact UAC can be in direct contact with the upper source / drain pattern USD. The upper active contacts UAC can be spaced apart from each other in the first direction D1 via the insulating structure IS.

[0070] The upper gate contact UGC can be disposed to penetrate the third interlayer insulating layer 130 and the gate cap pattern GP and can be electrically connected to the upper gate electrode UGE. Each of the upper active contact UAC and the upper gate contact UGC can be formed of or include a metal material selected from the group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0071] The cut pattern CTP and the insulating structure IS can be alternately arranged between the gate electrodes GE adjacent to each other in the first direction D1. The cut pattern CTP and the insulating structure IS can separate the adjacent gate electrodes GE among the gate electrodes GE from each other. The adjacent gate electrodes GE among the gate electrodes GE can be spaced apart from each other in the first direction D1 by the cut pattern CTP and the insulating structure IS. According to an embodiment of the inventive concept, the cut pattern CTP can be arranged to cut the gate electrodes GE crossing the first single-height cell SHC1 and the second single-height cell SHC2 in the first direction D1. The insulating structure IS can also be arranged to cut the gate electrodes GE crossing the second single-height cell SHC2 and the third single-height cell SHC3 in the first direction D1.

[0072] The cut pattern CTP can extend from the lower active region LAR to the upper active region UAR in the vertical direction D3. The cut pattern CTP can penetrate the gate cap pattern GP and the gate electrode GE, and can penetrate a portion of the device isolation layer 107. A top surface of the cut pattern CTP can be coplanar with a top surface of the gate cap pattern GP. A bottom surface of the cut pattern CTP can be disposed in the device isolation layer 107. The bottom surface of the cut pattern CTP can be located at a higher level than a bottom surface of the insulating structure IS. The cut pattern CTP can be a strip or line pattern extending in the second direction D2. The cut pattern CTP can be a single insulating layer or a plurality of insulating layers.

[0073] The vertical via member VT can be disposed in the cut pattern CTP. The vertical via member VT can penetrate the cut pattern CTP in the vertical direction D3. The cut pattern CTP can cover opposite side surfaces of the vertical via member VT. The cut pattern CTP can extend in the first direction D1 along a bottom surface of the vertical via member VT. A top surface of the vertical via member VT can be coplanar with a top surface of the cut pattern CTP. A bottom surface of the vertical via member VT can be located at a higher level than a bottom surface of the insulating structure IS. A width of the vertical via member VT can increase as a distance from the bottom surface of the vertical via member VT in the vertical direction D3 increases.

[0074] The vertical via member VT can connect the upper active contact member UAC to the lower active contact member LAC. The vertical via member VT can be disposed at a side of the upper active contact member UAC and the lower active contact member LAC. The upper active contact member UAC can extend in the first direction D1 and can be connected to an upper portion of the vertical via member VT. The lower active contact member LAC can extend in the first direction D1 and can be connected to a lower portion of the vertical via member VT.

[0075] The vertical via member VT can include a metallic material. For example, the vertical via member VT can be formed of or include at least one of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0076] The insulating structure IS can be a strip or line pattern extending in the second direction D2. The insulating structure IS can include an insulating material. For example, the insulating structure IS can be formed of or include at least one of SiON, SiCN, SiCON, and SiN.

[0077] The insulating structure IS can be spaced apart from the vertical via member VT and the cut pattern CTP in the first direction D1, one of the upper source / drain patterns USD being interposed between the insulating structure IS and the vertical via member VT and the cut pattern CTP. The insulating structure IS can be spaced apart from the vertical via member VT and the cut pattern CTP in the first direction D1, one of the lower source / drain patterns LSD being interposed between the insulating structure IS and the vertical via member VT and the cut pattern CTP.

[0078] A level of a top surface of the insulating structure IS can be equal to or higher than a level of a top surface of the gate electrode GE. A level of a bottom surface of the insulating structure IS can be equal to or lower than a level of a bottom surface of the gate electrode GE. The insulating structure IS can penetrate the gate electrode GE in the vertical direction D3.

[0079] The insulating structure IS can extend in the vertical direction D3 to span the lower active region LAR and the upper active region UAR. The insulating structure IS can extend in the vertical direction D3 from the lower active contact LAC to the upper active contact UAC.

[0080] The insulating structure IS can be interposed between adjacent ones of the upper source / drain patterns USD. The insulating structure IS can be interposed between adjacent ones of the lower source / drain patterns LSD. Side surfaces of the insulating structure IS can be in direct contact with the upper source / drain patterns USD and the lower source / drain patterns LSD. A top surface of the insulating structure IS can be located at a level higher than top surfaces of the upper source / drain patterns USD.

[0081] A top surface of the insulating structure IS can be higher or equal in level to a top surface of the upper active contact UAC. The insulating structure IS can separate adjacent ones of the upper active contacts UAC from each other. A bottom surface of the insulating structure IS can be equal or lower in level to a bottom surface of the lower active contact LAC. A length of the insulating structure IS in the third direction D3 can be greater than a length of the cut pattern CTP and a length of the vertical via VT.

[0082] A third interlayer insulating layer 130 can be disposed on the second interlayer insulating layer 120. A first metal layer M1 can be disposed in the third interlayer insulating layer 130. The first metal layer M1 can include an upper interconnect line 135. The first metal layer M1 can also include an upper via element UVI. The upper via element UVI can electrically connect the upper interconnect line 135 to the upper active contact UAC. Each of the upper interconnect line 135 and the upper via element UVI can be formed of or include a metal material selected from a group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0083] Additional metal layers (e.g., M2, M3, M4, etc.) can be stacked on the first metal layer M1. The first metal layer M1 and the additional metal layers (e.g., M2, M3, M4, etc.) thereon can constitute back end of line (BEOL) layers of the semiconductor device. The additional metal layers (e.g., M2, M3, M4, etc.) on the first metal layer M1 can include wiring lines for connecting logic cells to each other.

[0084] A lower interlayer insulating layer 200 can be disposed below the bottom surface 100b of the substrate 100. A backside metal layer BSM can be disposed in the lower interlayer insulating layer 200. The backside metal layer BSM can include a lower interconnect line 235. The backside metal layer BSM can also include a lower via element LVI. The lower via element LVI can electrically connect the lower active contact LAC to the lower interconnect line 235. Each of the lower interconnect line 235 and the lower via element LVI can be formed of or include a metal material selected from a group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0085] A lower metal layer can also be stacked below the backside metal layer BSM. In an embodiment, the lower metal layer can include a power delivery network. The power delivery network can include a wiring network for applying a source voltage and a drain voltage to the backside metal layer BSM.

[0086] A source voltage and a drain voltage can be applied to the backside metal layer BSM through the power delivery network. One of the source voltage and the drain voltage can be applied to the lower source / drain pattern LSD through the lower interconnect line 235, the lower via member LVI, and the lower active contact member LAC. The other one of the source voltage and the drain voltage can be applied to the first metal layer M1 from the backside metal layer BSM through the power tap unit. The voltage applied to the first metal layer M1 through the power tap unit can be applied to the upper source / drain pattern USD through the upper interconnect line 135, the upper via member UVI, and the upper active contact member UAC. The power tap unit can be inserted between single-height units SHC adjacent to each other.

[0087] Figure 5 is an enlarged cross-sectional view illustrating a portion "M" of Figure 4B . Hereinafter, the insulating structure IS according to an embodiment of the inventive concept will be described in more detail with reference to Figure 5 .

[0088] With reference to Figure 4D and Figure 5 , the insulating structure IS can include a first portion P1 and a second portion P2 and a protruding portion PRT disposed on the first portion P1. The first portion P1 can extend from the bottom surface 100b of the substrate 100 to the upper active region UAR in the vertical direction D3. The first portion P1 can be disposed to penetrate the substrate 100, the lower active region LAR, the first interlayer insulating layer 110, and the liner layer LIN, and to penetrate a portion of the upper active region UAR. A top surface of the first portion P1 can be located at a level higher than a bottom surface of the upper source / drain pattern USD and lower than a top surface of the upper source / drain pattern USD. The first portion P1 can be adjacent to the lower active region LAR.

[0089] The second portion P2 can be disposed on the first portion P1 between the upper source / drain patterns USD adjacent to each other in the first direction D1. A top surface of the second portion P2 can be coplanar with top surfaces of the second interlayer insulating layer 120, the gate cap pattern GP, the gate spacer GS, and the upper active contact member UAC. The second portion P2 can be adjacent to the upper active region UAR. The second portion P2 can be spaced apart from the lower active region LAR. The second portion P2 can not be connected to the lower active region LAR. In an embodiment, a plurality of second portions P2 can be disposed. The second portions P2 can be spaced apart from each other on the first portion P1 in the second direction D2.

[0090] The protruding portion PRT can be disposed on the first portion P1 between the gate electrodes GE adjacent to each other in the first direction D1. A top surface of the protruding portion PRT can be coplanar with top surfaces of the second portion P2, the second interlayer insulating layer 120, the gate cap pattern GP, the gate spacers GS, and the upper active contact UAC. In an embodiment, a plurality of protruding portions PRT can be disposed. The protruding portions PRT can be spaced apart from each other on the first portion P1 in the second direction D2. When viewed in a plan view, the protruding portions PRT can not overlap the second portion P2. For example, the protruding portions PRT on the first portion P1 and the second portion P2 can be alternately disposed in the second direction D2.

[0091] The gate spacers GS can be interposed between the protruding portion PRT and the second portion P2. The protruding portion PRT can extend along a bottom surface of the gate spacers GS and can be connected to the second portion P2.

[0092] An upper portion of the protruding portion PRT can be disposed between a pair of gate spacers GS. A lower portion of the protruding portion PRT can extend along bottom surfaces of the pair of gate spacers GS. The protruding portion PRT can extend in the vertical direction D3 from a top surface of the first portion P1 to bottom surfaces of the pair of gate spacers GS and can extend in the vertical direction D3 through an area between the pair of gate spacers GS to a bottom surface of the third interlayer insulating layer 130.

[0093] Each of the first portion P1 and the second portion P2 can have side surfaces opposite to each other in the first direction D1. The side surface of the first portion P1 and the side surface of the second portion P2 can form a stepped (e.g., shape similar to a tread or a stair) structure boundary between the first portion P1 and the second portion P2. The first portion P1 can include a first lower side surface S1a and a second lower side surface S1b. The second portion P2 can include a first upper side surface S2a and a second upper side surface S2b. The first lower side surface S1a can be spaced apart from the first upper side surface S2a in the first direction D1. The second lower side surface S1b can be spaced apart from the second upper side surface S2b in the first direction D1. In other words, the side surface of the first portion P1 can protrude in the first direction D1 with respect to the side surface of the second portion P2. The side surface of the insulating structure IS can have a stepped (e.g., shape similar to a tread or a stair) structure at a boundary between the first portion P1 and the second portion P2.

[0094] The first portion P1 can have a first width WD1 in the first direction D1. The second portion P2 can have a second width WD2 in the first direction D1. Each of the first width WD1 and the second width WD2 can increase as a distance from a bottom surface of the insulating structure IS in the vertical direction D3 increases. The first width WD1 can have a maximum value at a highest level of the first portion P1. The second width WD2 can have a maximum value at a highest level of the second portion P2. The second width WD2 can have a minimum value at a lowest level of the second portion P2.

[0095] At a boundary between the first portion P1 and the second portion P2, the first width WD1 can be greater than the second width WD2. The maximum value of the first width WD1 can be greater than the minimum value of the second width WD2. In detail, the width of the first portion P1 at its highest level can be greater than the width of the second portion P2 at its lowest level. Accordingly, the width of the insulating structure IS can discontinuously change at the boundary between the first portion P1 and the second portion P2. At the boundary between the first portion P1 and the second portion P2, the width of the insulating structure IS can abruptly change from the first width WD1 to the second width WD2.

[0096] The outer side surface of the first portion P1 can include a stepped (e.g., a shape similar to a stair or a tread thereof) surface SP. The stepped surface SP can be a top surface of the first portion P1 that is not covered by the second portion P2. The stepped surface SP can be horizontally flat, and can connect a side surface of the first portion P1 to a side surface of the second portion P2 at a boundary of the first portion P1 and the second portion P2. The stepped surface SP can be located at the same level as the boundary between the first portion P1 and the second portion P2. The stepped surface SP of the first portion P1 can be configured to change the width of the insulating structure IS from the first width WD1 to the second width WD2. Due to the stepped surface SP, the width of the insulating structure IS can abruptly change at the boundary between the first portion P1 and the second portion P2. The stepped surface SP can include two portions spaced apart from each other in the first direction D1, with the second portion P2 interposed therebetween.

[0097] The stepped surface SP can be a horizontally flat surface connecting the first lower side surface S1a to the first upper side surface S2a. The stepped surface SP can be a surface connecting the second lower side surface S1b to the second upper side surface S2b.

[0098] The stepped surface SP can be located at a level higher than a bottom surface of the upper source / drain pattern USD and lower than a top surface of the upper source / drain pattern USD. In other words, the boundary between the first portion P1 and the second portion P2 can be located at a level higher than the bottom surface of the upper source / drain pattern USD and lower than the top surface of the upper source / drain pattern USD.

[0099] Figures 6A-6C are each a magnified cross-sectional view of the portion "M". For the sake of concise description, elements previously described with reference to Figure 4B may be identified by the same reference numerals without repeating overlapping description thereof. Figure 5

[0100] With reference to Figure 6A , a third portion P3 can be disposed between the first portion P1 and the second portion P2. The third portion P3 can be located at a level higher than a bottom surface of the upper source / drain pattern USD and lower than a top surface of the upper source / drain pattern USD. The third portion P3 can have a third width WD3 in the first direction D1. The third width WD3 can be smaller than a maximum value of the first width WD1 and can be greater than a minimum value of the second width WD2. The third width WD3 can decrease as a distance from the first portion P1 increases in a direction toward the second portion P2. The third width WD3 can decrease as the distance from the first portion P1 increases and the distance from the second portion P2 decreases.

[0101] A side surface CW of the third portion P3 can have a curved surface. The side surface CW of the third portion P3 can be configured to change a width of the insulating structure IS from the first width WD1 to the second width WD2. The side surface CW of the third portion P3 can include two portions spaced apart from each other in the first direction D1, between which the second portion P2 is interposed. Due to the side surface CW of the third portion P3, in some examples, the width of the insulating structure IS can gradually change from the first width WD1 to the second width WD2.

[0102] With reference to Figure 6B ​, the centerline CL1 of the first portion P1 may be spaced apart from the centerline CL2 of the second portion P2 in the first direction D1. The centerline CL1 of the first portion P1 and the centerline CL2 of the second portion P2 may be offset from each other in the first direction D1. For example, the first lower surface S1a of the first portion P1 may protrude from the first upper surface S2a of the second portion P2 in the first direction D1. The first lower surface S1a of the first portion P1 and the first upper surface S2a of the second portion P2 may be spaced apart from each other in the first direction D1. The second lower surface S1b of the first portion P1 may be aligned with the second upper surface S2b of the second portion P2 in the vertical direction D3. At the boundary between the first portion P1 and the second portion P2, the first lower surface S1a and the first upper surface S2a may form a stepped structure. At the boundary between the first portion P1 and the second portion P2, the second lower surface S1b and the second upper surface S2b may not form a stepped structure. When viewed in a plan view, a center line CL1 of the first portion P1 may be defined as an imaginary line passing through the center of the first portion P1 in the second direction D2. When viewed in a plan view, a center line CL2 of the second portion P2 may be defined as an imaginary line passing through the center of the second portion P2 in the second direction D2.

[0103] Reference Figure 6C , the insulating pattern IP may be inserted between the first portion P1 and the second portion P2. The insulating pattern IP may be in contact with the top surface of the first portion P1 and may be in contact with the bottom surface of the second portion P2. The insulating pattern IP may cover at least a portion of the side surface of the second portion P2. The insulating pattern IP may extend from the bottom surface of the second portion P2 in the vertical direction D3 along the first upper side surface S2a and the second upper side surface S2b. The insulating pattern IP may cover at least a portion of the top surface of the first portion P1. Due to the insulating pattern IP, the second width WD2 of the second portion P2 may be smaller than Figure 5 Therefore, the distance between the upper active contacts UAC adjacent to each other can be reduced. As a result, the reliability and electrical characteristics of the three-dimensional semiconductor device can be improved.

[0104] The insulating pattern IP may include an oxide material. The insulating pattern IP may be a single oxide layer or a plurality of oxide layers. The insulating pattern IP may include a material having a different etch selectivity from the insulating structure IS. For example, the insulating structure IS may be formed of or include SiN, and the insulating pattern IP may be formed of or include SiON.

[0105] According to embodiments of the inventive concept, the insulating structure IS can include two separate portions (e.g., a first portion P1 and a second portion P2). At a boundary between the first portion P1 and the second portion P2, a first width WD1 of the first portion P1 in the first direction D1 can be greater than a second width WD2 of the second portion P2 in the second direction D2. A stepped surface SP can be formed between the first portion P1 and the second portion P2. This can be because the first portion P1 and the second portion P2 of the insulating structure IS can be formed separately in a manufacturing process described later. Since the insulating structure IS separates adjacent cells from each other, a short circuit problem can be prevented from occurring between adjacent cells, and a total area of a logic cell can be reduced. Accordingly, the disclosed semiconductor device and manufacturing method can be improved over other semiconductor devices by preventing or reducing short circuits and / or reducing device size. In some examples, the stepped surface SP of the insulating structure IS can be formed via a two-step process, thereby preventing a short circuit problem that can occur when the insulating structure is formed by a single process. In addition, in a process of forming the insulating structure IS, which will be described later, the first portion P1 can be formed before a source / drain pattern and a channel pattern are formed, and in this case, uniformity of a channel length can be improved. The second portion P2 can be formed after an upper source / drain pattern USD is formed, and in this case, a patterning margin can be ensured and a skirt issue can be prevented at intersections of several structures. Furthermore, since the second portion P2 is formed after the upper source / drain pattern USD is formed, the upper source / drain pattern USD can easily grow and can be formed to have an increased area. Accordingly, using the disclosed semiconductor device and manufacturing method, process difficulty in a subsequent process of forming contacts can be reduced.

[0106] In addition, since the vertical via is formed in the cut pattern, a width of the insulating structure can be reduced. As a result, according to embodiments of the inventive concept, electrical and reliability characteristics of a three-dimensional semiconductor device can be improved. In addition, a cell height can be reduced and integration density of the three-dimensional semiconductor device can be increased.

[0107] Figures 7A-19D FIG. 1 is a cross-sectional view illustrating a method of manufacturing a semiconductor device according to embodiments of the inventive concept. In detail, Figure 7A Figure 9A Figure 10A Figure 11A Figure 12A Figure 13A Figure 14A Figure 18A and Figure 19A are cross-sectional views corresponding to line A-A' of Figure 3 Figure 9B Figure 10B Figure 11B Figure 12B ,​​​​​​​​​​​Figure 13B 、 Figure 14B 、 Figure 15A 、 Figure 16A 、 Figure 17A 、 Figure 18B and Figure 19B is with Figure 3 The cross-sectional view corresponding to the line BB'. Figure 7B 、 Figure 8 、 Figure 9C 、 Figure 14C 、 Figure 15B 、 Figure 18C and Figure 19C is with Figure 3 The cross-sectional view corresponding to the line CC'. Figure 9D 、 Figure 10C 、 Figure 13C 、 Figure 14D 、 Figure 16B 、 Figure 17B 、 Figure 18D and Figure 19D is with Figure 3 The cross-sectional view corresponding to the line D-D'.

[0108] Reference Figure 7A and Figure 7B , a semiconductor substrate 105 may be provided. The semiconductor substrate 105 may be formed of or include at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe). For example, the semiconductor substrate 105 may be a single crystal silicon wafer.

[0109] A first lower insulating layer 101 may be formed on the semiconductor substrate 105. The first lower insulating layer 101 may be formed of or include at least one of a silicon-based insulating material (e.g., silicon oxide) and / or a semiconductor material (Si or SiGe).

[0110] First sacrificial layers SAL1 and first active layers ACL1 may be alternately stacked on the first lower insulating layer 101. The first sacrificial layers SAL1 and the first active layer ACL1 may be formed of or include at least one of silicon (Si), germanium (Ge), and silicon germanium (SiGe), and may be formed of different materials. For example, the first sacrificial layers SAL1 may be formed of or include silicon germanium (SiGe), and the first active layer ACL1 may be formed of or include silicon (Si). The concentration of germanium (Ge) in each of the first sacrificial layers SAL1 may be in a range of 10 at% to 30 at%.

[0111] A separation layer DSL can be formed on the uppermost one of the first sacrificial layers SAL1. In embodiments, the thickness of the separation layer DSL can be greater than the thickness of the first sacrificial layers SAL1. The separation layer DSL can be formed of or include silicon (Si) or silicon germanium (SiGe). In cases where the separation layer DSL includes silicon germanium (SiGe), the germanium concentration of the separation layer DSL can be higher than the germanium concentration of the first sacrificial layers SAL1. For example, the germanium concentration of the separation layer DSL can range from 40 at% to 90 at%.

[0112] A seed layer SDL can be formed on the separation layer DSL. The seed layer SDL can include the same material as the first active layers ACL1. The second sacrificial layers SAL2 and the second active layers ACL2 can be alternately stacked on the seed layer SDL. Each of the second sacrificial layers SAL2 can be formed of or include the same material as the first sacrificial layers SAL1, and each of the second active layers ACL2 can be formed of or include the same material as the first active layers ACL1. The separation layer DSL can be interposed between the first sacrificial layers SAL1 and the seed layer SDL.

[0113] A third sacrificial layer SAL3 can be formed on the uppermost one of the second active layers ACL2. The thickness of the third sacrificial layer SAL3 can be greater than the thickness of the second active layers ACL2 and the thickness of the second sacrificial layers SAL2. The third sacrificial layer SAL3 can be formed of or include the same material as the second sacrificial layers SAL2.

[0114] A stack pattern STP can be formed by patterning the first to third sacrificial layers SAL1, SAL2, and SAL3, the first and second active layers ACL1 and ACL2, the seed layer SDL, and the separation layer DSL. The formation of the stack pattern STP can include forming a hard mask pattern on the third sacrificial layer SAL3, etching the layers SAL1, SAL2, SAL3, ACL1, ACL2, SDL, and DSL stacked on the semiconductor substrate 105 using the hard mask pattern as an etching mask, and removing the hard mask pattern. During the formation of the stack pattern STP, the upper portion of the semiconductor substrate 105 can be patterned to form the trenches TR1 and TR2. The stack pattern STP can be a bar-shaped or line-shaped pattern extending in the second direction D2.

[0115] The stack pattern STP can include a lower stack pattern STPl on the first lower insulating layer 101, an upper stack pattern STP2 on the lower stack pattern STPl, and a separation layer DSL between the lower stack pattern STPl and the upper stack pattern STP2. The lower stack pattern STPl can include first sacrificial layers SAL1 and first active layers ACL1 that are alternately stacked. The upper stack pattern STP2 can include a seed layer SDL and second sacrificial layers SAL2 and second active layers ACL2 that are alternately stacked on the seed layer SDL. The upper stack pattern STP2 can further include a third sacrificial layer SAL3 that is stacked on an uppermost one of the second active layers ACL2.

[0116] The trenches can include a first trench TR1 and a second trench TR2. According to embodiments of the inventive concepts, the first trench TR1 can be formed between the second single-height cell SHC2 and the third single-height cell SHC3. The second trench TR2 can be formed between the first single-height cell SHCl and the second single-height cell SHC2. A width TR2 W of the second trench TR2 in the first direction Dl can be greater than a width TR1 W of the first trench TR1 in the first direction Dl. The width TR1 W of the first trench TR1 can increase as a distance from the semiconductor substrate 105 in the vertical direction D3 increases. The width of the first trench TR1 at an uppermost level can be greater than the width at a lowermost level. A distance between the stack pattern STP on the first single-height cell SHCl and the stack pattern STP on the second single-height cell SHC2 can be greater than a distance between the stack pattern STP on the second single-height cell SHC2 and the stack pattern on the third single-height cell SHC3.

[0117] Referring to Figure 8 An initial insulating structure PIS can be formed on the semiconductor substrate 105 to fill the first trench TR1. For example, the formation of the initial insulating structure PIS can include forming a mask layer (not shown) on the semiconductor substrate 105 to expose the first trench TR1, filling the first trench TR1 with an insulating material, recessing the insulating material to expose a top surface of the third sacrificial layer SAL3, and removing the mask layer. The recessing of the insulating material can be performed by a wet etching process.

[0118] A device isolation layer 107 can be formed on the semiconductor substrate 105 to fill a lower portion of the second trench TR2. In embodiments, the formation of the device isolation layer 107 can include forming an insulating layer (not shown) on the semiconductor substrate 105 to cover the stack pattern STP, and recessing the insulating layer to expose the stack pattern STP. The recessing of the insulating layer can be performed using a wet etching process. A top surface of the device isolation layer 107 can be coplanar with a top surface of the semiconductor substrate 105.

[0119] Referring to Figures 9A-9DA plurality of first sacrificial patterns PP1 can be formed to cross the stack pattern STP. The first sacrificial patterns PP1 can be spaced apart from each other in the second direction D2. Each of the first sacrificial patterns PP1 can be a linear pattern extending in the first direction D1. In an embodiment, the formation of the first sacrificial patterns PP1 can include forming a sacrificial layer (not shown) on the semiconductor substrate 105, forming a hard mask pattern MP on the sacrificial layer, and patterning the sacrificial layer using the hard mask pattern MP as an etching mask. The sacrificial layer can be formed of or include amorphous silicon and / or polysilicon. In an embodiment, the patterning process can be performed using an anisotropic etching process. During the patterning process, a portion of the third sacrificial layer SAL3 and a portion of the initial insulating structure PIS that are not shielded by the hard mask pattern MP can also be etched. Accordingly, the initial insulating structure PIS can have portions protruding in the vertical direction D3. The protruding portions can be spaced apart from each other in the second direction D2 and can extend in the first direction D1. The protruding portions can vertically overlap the first sacrificial patterns PP1.

[0120] A pair of gate spacers GS can be formed on opposite side surfaces of the first sacrificial patterns PP1, respectively. The gate spacers GS can extend to cover side surfaces of the protruding portions of the initial insulating structure PIS. In an embodiment, the formation of the gate spacers GS can include conformally forming a spacer layer (not shown) on the semiconductor substrate 105 and anisotropically etching the spacer layer. The spacer layer can cover the first sacrificial patterns PP1 and the hard mask pattern MP. For example, the spacer layer can be formed of or include at least one of SiCN, SiCON, and SiN.

[0121] Referring to Figures 10A-10C An etching process can be performed on the stack pattern STP using the gate spacers GS and the hard mask pattern MP as etching masks. As a result of the etching process, recesses RS can be formed between the first sacrificial patterns PP1 adjacent to each other in the second direction D2. Due to the recesses RS, the stack pattern STP can be formed to have a shape of a vertical bar.

[0122] The etching process can be performed to partially remove an upper portion of the initial insulating structure PIS, and as a result, a first portion P1 and a protruding portion PRT on the first portion P1 can be formed. When viewed in a plan view, the protruding portion PRT can vertically overlap the first sacrificial patterns PP1 and the gate spacers GS. The protruding portions PRT on the first portion P1 can be spaced apart from each other in the second direction D2. A top surface of the first portion P1 can be located at a higher level than a bottom surface of the upper stack pattern STP2. The top surface of the first portion P1 can be located at a lower level than a top surface of the upper stack pattern STP2.

[0123] In case the separation layer DSL includes silicon germanium (SiGe), a dummy trench DSP can be formed by replacing the separation layer DSL with a silicon-based insulating material. For example, the separation layer DSL exposed by the recesses RS can be selectively removed to form a vacant region, and then the silicon-based insulating material (e.g., silicon nitride) can be formed to fill the vacant region. The top surface of the first portion P1 can be located at a higher level than the top surface of the dummy trench DSP.

[0124] Referring to Figure 11A and Figure 11B A sacrificial contact pattern PLH can be formed in the semiconductor substrate 105 exposed by the recesses RS. The sacrificial contact pattern PLH can be formed to have a contact shape. The sacrificial contact pattern PLH can be arranged along the second direction D2. The sacrificial contact pattern PLH can include a material (e.g., silicon germanium (SiGe)) having etch selectivity with respect to the semiconductor substrate 105. The sacrificial contact pattern PLH can be formed by an epitaxial growth process. The recesses RS can be formed to expose the sacrificial contact pattern PLH.

[0125] A second lower insulating layer 102 can be formed on the sacrificial contact pattern PLH. A top surface of the second lower insulating layer 102 can be coplanar with a top surface of the first lower insulating layer 101. The second lower insulating layer 102 can be formed of a silicon-based insulating material (e.g., silicon oxide, silicon oxynitride, or silicon nitride). In an embodiment, the second lower insulating layer 102 can be formed of the same material as the device isolation layer 107.

[0126] A lower source / drain pattern LSD can be formed on the second lower insulating layer 102. In detail, a first SEG process can be performed to form the lower source / drain pattern LSD, in which the exposed side surfaces of the lower stack pattern STP1 serve as a seed layer. The first active layer ACL1 exposed by the recesses RS can be used as a seed layer to grow the lower source / drain pattern LSD. In an embodiment, the first SEG process can include a chemical vapor deposition (CVD) process or a molecular beam epitaxy (MBE) process.

[0127] As an example, impurities can be implanted into the lower source / drain pattern LSD in an in-situ manner during the first SEG process. As another example, impurities can be implanted into the lower source / drain pattern LSD after the lower source / drain pattern LSD is formed. The lower source / drain pattern LSD can be doped to have a first conductivity type (e.g., n-type).

[0128] The lower source / drain pattern LSD can be formed to completely fill the space between the pair of lower stack patterns STP1. For example, the first SEG process can be performed for a sufficient time until the lower source / drain pattern LSD is grown to fill the space between the pair of lower stack patterns STP1 and connect the pair of lower stack patterns STP1 to each other.

[0129] Referring to Figure 12A and Figure 12B A first interlayer insulating layer 110 can be formed to cover the lower source / drain patterns LSD. The first interlayer insulating layer 110 can cover side surfaces of the upper stack patterns STP2. Next, an upper portion of the first interlayer insulating layer 110 can be removed to re-expose the side surfaces of the upper stack patterns STP2. A liner layer LIN can be formed to conformally cover the first interlayer insulating layer 110. The liner layer LIN can be a single insulating layer or a plurality of insulating layers.

[0130] Referring to Figures 13A-13C An upper source / drain pattern USD can be formed on the exposed side surfaces of the upper stack patterns STP2. The upper source / drain pattern USD can cover the top surfaces of the first portions P1. In detail, the upper source / drain pattern USD can be formed by a second SEG process using the exposed side surfaces of the upper stack patterns STP2 as seed layers. The upper source / drain pattern USD can be grown using the exposed second active layer ACL2 as seed layers. The upper source / drain pattern USD can be doped to have a second conductivity type (e.g., p-type) different from the first conductivity type.

[0131] The second SEG process can also be performed for a sufficient time until the upper source / drain pattern USD is grown to completely fill the spaces between the pair of upper stack patterns STP2.

[0132] Referring to Figures 14A-14D The first active layer ACL1 interposed between the pair of lower source / drain patterns LSD can constitute a lower channel pattern LCH. For example, a first semiconductor pattern SP1 and a second semiconductor pattern SP2 of the lower channel pattern LCH can be formed from the first active layer ACL1. The lower channel pattern LCH and the lower source / drain patterns LSD can constitute a lower active region LAR serving as a bottom layer of the three-dimensional device. The second active layer ACL2 interposed between the pair of upper source / drain patterns USD can constitute an upper channel pattern UCH. For example, a third semiconductor pattern SP3 and a fourth semiconductor pattern SP4 of the upper channel pattern UCH can be formed from the second active layer ACL2. The upper channel pattern UCH and the upper source / drain patterns USD can constitute an upper active region UAR serving as a top layer of the three-dimensional device.

[0133] A second interlayer insulating layer 120 can be formed to cover the upper source / drain pattern USD. In an embodiment, the second interlayer insulating layer 120 can include a silicon oxide layer.

[0134] A planarization process can be performed on the second interlayer insulating layer 120 to expose a top surface of the first sacrificial pattern PP1. The planarization of the second interlayer insulating layer 120 can be performed using an etch-back process or a chemical mechanical polishing (CMP) process. During the planarization process, the hard mask pattern MP on the first sacrificial pattern PP1 can be completely removed. As a result, the top surface of the second interlayer insulating layer 120 can be coplanar with the top surface of the first sacrificial pattern PP1 and the top surface of the gate spacers GS.

[0135] The exposed first sacrificial pattern PP1 can be selectively removed. The removal of the first sacrificial pattern PP1 can include a wet etching process using an etching solution capable of selectively etching polysilicon. As the first sacrificial pattern PP1 is removed, the first to third sacrificial layers SAL1, SAL2, and SAL3 can be exposed.

[0136] An etching process selected to selectively etch the first to third sacrificial layers SAL1, SAL2, and SAL3 can be performed to leave the first to fourth semiconductor patterns SP1 to SP4 and the dummy channel pattern DSP and remove only the first to third sacrificial layers SAL1, SAL2, and SAL3. An etching process having a high etching rate for silicon germanium can be selected. For example, an etching process having a high etching rate for a silicon germanium layer having a germanium concentration higher than 10 at% can be selected.

[0137] A gate insulating layer GI can be conformally formed in the empty space formed by removing the first sacrificial pattern PP1 and the first to third sacrificial layers SAL1, SAL2, and SAL3. A gate electrode GE can be formed on the gate insulating layer GI. The formation of the gate electrode GE can include forming first to fifth inner electrodes PO1 to PO5 between the first to fourth semiconductor patterns SP1 to SP4 and forming an outer electrode PO6 in an empty region formed by removing the third sacrificial layer SAL3 and the first sacrificial pattern PP1.

[0138] The gate electrode GE can be vertically recessed to have a reduced height. A gate capping pattern GP can be formed on the recessed gate electrode GE. A planarization process can be performed on the gate capping pattern GP such that a top surface of the gate capping pattern GP is coplanar with a top surface of the second interlayer insulating layer 120.

[0139] Referring to Figure 15A and Figure 15BA second sacrificial pattern PP2 can be formed on an opposite side of the lower active region LAR and the upper active region UAR. The second sacrificial pattern PP2 can be spaced apart from the insulating structure IS in the first direction D1 with one of the lower active region LAR and one of the upper active region UAR interposed between the second sacrificial pattern PP2 and the insulating structure IS. The second sacrificial pattern PP2 can penetrate the gate capping pattern GP, the second interlayer insulating layer 120, the liner layer LIN, the first interlayer insulating layer 110, and the gate electrode GE, and can extend into the device isolation layer 107. According to embodiments of the inventive concepts, the second sacrificial pattern PP2 can be formed between the first single-height cell SHC1 and the second single-height cell SHC2. The formation of the second sacrificial pattern PP2 can include forming a cut mask pattern (not shown) on the gate capping pattern GP and the second interlayer insulating layer 120, forming cut holes that expose the device isolation layer 107 using the cut mask pattern as an etching mask, and forming a sacrificial material in the cut holes.

[0140] Referring to Figure 16A and Figure 16B A third trench TR3 can be formed on the first portion P1 between the upper source / drain patterns USD that are adjacent to each other in the first direction D1. In embodiments, the formation of the third trench TR3 can include forming a mask pattern (not shown) on the second interlayer insulating layer 120, etching the second interlayer insulating layer 120 using the mask pattern as an etching mask, etching a portion of the upper source / drain patterns USD using the mask pattern as an etching mask to expose a top surface of the first portion P1, and removing the mask pattern. As a result of the partial removal of the upper source / drain patterns USD, the upper source / drain patterns USD can be divided into two portions that are spaced apart from each other in the first direction D1.

[0141] Referring to Figure 17A and Figure 17B A second portion P2 can be formed to fill the third trench TR3. The insulating structure IS can include the first portion P1, the second portion P2, and the protruding portion PRT.

[0142] Referring to Figures 18A-18D The second sacrificial pattern PP2 can be selectively removed. The removal of the second sacrificial pattern PP2 can include a wet etching process using an etching solution capable of selectively etching the sacrificial material.

[0143] After the second sacrificial pattern PP2 is removed, a cut pattern CTP can be formed in the exposed trench. The cut pattern CTP can be formed to penetrate the gate capping pattern GP and the gate electrode GE, and can extend into the device isolation layer 107. The cut pattern CTP can be formed by forming an insulating material to conformally cover the exposed trench.

[0144] A vertical via VT can be formed in the cut pattern CTP. The formation of the vertical via VT can include filling an exposed trench conformally covered with an insulating material with a metallic material. For example, the metallic material can include a metallic material selected from a group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0145] An upper active contact UAC can be formed to penetrate the second interlayer insulating layer 120, and the upper active contact UAC can be coupled to the upper source / drain pattern USD, respectively. The upper active contact UAC can extend in the first direction D1 to contact an upper portion of the vertical via VT. To this end, a portion of the cut pattern CTP can be removed. An upper gate contact UGC can be formed to penetrate the second interlayer insulating layer 120 and the gate cap pattern GP, and can be coupled to the gate electrode GE. For example, each of the upper active contact UAC and the upper gate contact UGC can be formed of or include a metallic material selected from a group consisting of copper (Cu), aluminum (Al), ruthenium (Ru), cobalt (Co), tungsten (W), and molybdenum (Mo).

[0146] A third interlayer insulating layer 130 can be formed to cover the second interlayer insulating layer 120. A first metal layer M1 including an upper interconnection line 135 can be formed in the third interlayer insulating layer 130. An upper via UVI can be formed to electrically connect the upper interconnection line 135 to the upper active contact UAC. BEOL layers including additional metal layers (e.g., M2, M3, M4, etc.) can be formed on the first metal layer M1.

[0147] Referring to Figures 19A-19D The semiconductor substrate 105 can be flipped such that the back surface of the semiconductor substrate 105 is exposed to the outside. An etching process can be performed on the back surface of the semiconductor substrate 105 to reduce the height of the semiconductor substrate 105. A planarization process can be performed on the back surface of the semiconductor substrate 105 to expose a top surface of the sacrificial contact pattern PLH.

[0148] Referring back to Figures 4A-4D The sacrificial contact pattern PLH can be replaced with a lower active contact LAC. In detail, the sacrificial contact pattern PLH can be selectively removed. An etching process can be further performed on an area formed by the removal of the sacrificial contact pattern PLH to expose a lower source / drain pattern LSD. The lower active contact LAC can be formed to be coupled to the exposed lower source / drain pattern LSD. The lower active contact LAC can be formed in a self-aligned manner using the sacrificial contact pattern PLH. The lower active contact LAC can extend in the first direction D1 and can contact a lower portion of the vertical via VT. To this end, a portion of the cut pattern CTP can be removed.

[0149] A substrate 100 can replace the semiconductor substrate 105. The substrate 100 can be an insulating substrate including silicon-based insulating materials (e.g., silicon oxide and / or silicon nitride). In an embodiment, the semiconductor substrate 105 can not be replaced by the substrate 100.

[0150] A lower interlayer insulating layer 200 can be formed on the substrate 100. A backside metal layer BSM can be formed in the lower interlayer insulating layer 200. The backside metal layer BSM can include a lower interconnection line 235. In addition, a lower via member LVI can be formed to electrically connect a lower active contact member LAC to the lower interconnection line 235. A backside metal layer can be additionally formed on the backside metal layer BSM. In an embodiment, the backside metal layer can include a power delivery network.

[0151] Figure 20A and Figure 20B are cross-sectional views taken along lines A-A' and B-B' of Figure 3 , respectively. For a clear description, previously described elements can be identified by the same reference numerals without repeating their repetitive descriptions.

[0152] Referring to Figure 20A and Figure 20B , a first insulating layer 111 can be disposed on the lower source / drain pattern LSD. The first insulating layer 111 can be a single insulating layer or a plurality of insulating layers. A second insulating layer 121 can be disposed on the upper source / drain pattern USD. The second insulating layer 121 can be a single insulating layer or a plurality of insulating layers.

[0153] In a three-dimensional semiconductor device according to an embodiment of the inventive concept, a cut pattern and an insulating structure can be disposed on opposite sides of a logic cell, respectively. A width of an upper portion of the insulating structure at a bottom level thereof can be smaller than a width of a lower portion of the insulating structure at a top level thereof. For example, the width of the insulating structure can discontinuously change at a boundary between the upper portion and the lower portion thereof. Since the upper portion and the lower portion of the insulating structure are separately and sequentially formed, a short problem can be prevented from occurring in a process of forming the insulating structure. In some examples, a stepped surface of the insulating structure can be formed via a two-step process, thereby preventing a short problem that can occur when the insulating structure is formed via a single process. Accordingly, the disclosed semiconductor device and manufacturing method can improve other semiconductor devices by preventing or reducing shorts. In addition, a vertical via member can be formed in the cut pattern, and in this case, the width of the insulating structure can be reduced and the integration density of the logic cell can be increased. Furthermore, since the upper portion of the insulating structure is formed after the source / drain pattern is formed, the source / drain pattern can be easily grown and can be formed to have an increased area. Accordingly, the process difficulty in a subsequent step of forming a contact structure can be reduced. Accordingly, the reliability and electrical characteristics of the three-dimensional semiconductor device can be improved using the disclosed semiconductor device and manufacturing method.

[0154] While example embodiments of the inventive concept have been particularly shown and described, ordinary skilled in the art will understand that changes can be made in form and details without departing from the spirit and scope of the appended claims.

Claims

1. A three-dimensional semiconductor device comprising: a lower active region on a substrate, the lower active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; an upper active region on the lower active region, the upper active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a gate electrode disposed on the lower channel pattern and the upper channel pattern and extending in a first direction; and an insulating structure disposed on one side of the lower active region and the upper active region and extending in a second direction, the first direction and the second direction being parallel to a top surface of the substrate and crossing each other, wherein: the insulating structure includes a first portion adjacent to the lower active region, and a second portion disposed on the first portion and adjacent to the upper active region, and a side surface of the insulating structure has a stepped structure at a boundary between the first portion and the second portion. the boundary between the first portion and the second portion is located at a level higher than a bottom surface of the upper source / drain pattern and lower than a top surface of the upper source / drain pattern.

2. The three-dimensional semiconductor device of claim 1, wherein, 3. The three-dimensional semiconductor device of claim 2, wherein: the first portion of the insulating structure has a first width, the second portion of the insulating structure has a second width, and at the boundary between the first portion and the second portion, the first width is greater than the second width. the first width and the second width increase as a distance from the top surface of the substrate in a vertical direction perpendicular to the top surface of the substrate increases.

4. The three-dimensional semiconductor device of claim 3, wherein, 5. The three-dimensional semiconductor device of claim 2, wherein: the insulating structure further includes a third portion between the first portion and the second portion, the first portion has a first width, the first width being variable, the second portion has a second width, the second width being variable, the third portion has a third width, and the third width is smaller than a maximum value of the first width and greater than a minimum value of the second width. a side surface of the third portion is curved, and 6. The three-dimensional semiconductor device of claim 5, wherein, the third width decreases as a distance from the first portion increases and as a distance from the second portion decreases. center lines of the first portion and the second portion are offset from each other in the first direction when viewed in a plan view.

7. The three-dimensional semiconductor device of claim 2, wherein, 8. The three-dimensional semiconductor device of claim 2, further comprising an insulating pattern interposed between the first portion and the second portion, the insulating pattern includes a material having a different etching selectivity from that of the insulating structure. wherein, the insulating pattern extends along a side surface of the second portion from a bottom surface of the second portion in a vertical direction perpendicular to the top surface of the substrate.

9. The three-dimensional semiconductor device of claim 8, wherein, a top surface of the insulating structure is located at a level higher than a top surface of the upper source / drain pattern and a top surface of the gate electrode.

10. The three-dimensional semiconductor device of Claim 2, wherein, 11. The three-dimensional semiconductor device of claim 2, further comprising: ​ a cut pattern disposed on opposite sides of the lower active region and the upper active region, extending from the lower active region to the upper active region in a vertical direction perpendicular to a top surface of the substrate, and extending in the second direction; a lower active contact coupled to the lower source / drain pattern; an upper active contact coupled to the upper source / drain pattern; and a vertical via connecting the lower active contact to the upper active contact, wherein the vertical via is disposed to penetrate the cut pattern. The three-dimensional semiconductor device includes one or more of a complementary field effect transistor, a stacked field effect transistor, and a three-dimensional field effect transistor.

12. The three-dimensional semiconductor device of Claim 1, wherein, 13. A three-dimensional semiconductor device, comprising: a lower active region on a substrate, the lower active region including a lower channel pattern and a lower source / drain pattern connected to the lower channel pattern; an upper active region stacked on the lower active region, the upper active region including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern; a gate electrode disposed on the lower channel pattern and the upper channel pattern and extending in a first direction; and an insulating structure disposed on one side of the lower active region and the upper active region and extending in a second direction, the first direction and the second direction being parallel to a top surface of the substrate and crossing each other, wherein: the insulating structure includes a first portion adjacent to the lower active region and a second portion disposed on the first portion and adjacent to the upper active region, a side surface of the first portion protrudes in the first direction with respect to a side surface of the second portion, and the first portion has a stepped surface connecting the side surface of the first portion to the side surface of the second portion. The stepped surface is located at a level higher than a bottom surface of the upper source / drain pattern and lower than a top surface of the upper source / drain pattern.

14. The three-dimensional semiconductor device of claim 13, wherein, The insulating structure further includes a third portion between the first portion and the second portion, 15. The three-dimensional semiconductor device of claim 14, wherein, the first portion has a first width, the first width being variable, the second portion has a second width, the second width being variable, the third portion has a third width, and the third width is smaller than a maximum value of the first width and larger than a minimum value of the second width. A side surface of the third portion is curved, and 16. The three-dimensional semiconductor device of claim 15, wherein, the third width decreases as a distance from the first portion increases and as a distance from the second portion decreases. When viewed in a plan view, a center line of the first portion and a center line of the second portion are offset from each other in the first direction.

17. The three-dimensional semiconductor device of Claim 14, wherein, A top surface of the insulating structure is located at a level higher than a top surface of the upper source / drain pattern and a top surface of the gate electrode.

18. The three-dimensional semiconductor device of Claim 14, wherein, 19. A three-dimensional semiconductor device, comprising: lower active regions on a substrate, the lower active regions being spaced apart from each other in a first direction, each of the lower active regions including a lower channel pattern and a lower source / drain pattern, the lower channel patterns being spaced apart from each other in a second direction crossing the first direction, the lower source / drain pattern being connected to the lower channel pattern; ​ upper active regions each including an upper channel pattern and an upper source / drain pattern connected to the upper channel pattern, which are stacked on the lower active regions, respectively, in the second direction; gate electrodes each provided on the lower channel pattern and the upper channel pattern, the gate electrodes extending in the first direction and being spaced apart from each other in the second direction; an insulating structure provided between the lower active regions and the upper active regions and extending in a vertical direction from the lower active regions to the upper active regions; a cut pattern spaced apart from the insulating structure in the first direction, one of the lower active regions and one of the upper active regions being interposed between the cut pattern and the insulating structure, and the cut pattern extending in the vertical direction from the lower active regions to the upper active regions; and a vertical via member penetrating the cut pattern in the vertical direction, wherein: the insulating structure includes a first portion adjacent to the lower active regions, and a second portion provided on the first portion and adjacent to the upper active regions, a side surface of the insulating structure has a boundary between the first portion and the second portion, the boundary has a stepped structure, and the boundary is located at a level higher than a bottom surface of the upper source / drain pattern and lower than a top surface of the upper source / drain pattern. the first portion of the insulating structure has a first width, 20. The three-dimensional semiconductor device of Claim 19, wherein, the second portion of the insulating structure has a second width, and at the boundary between the first portion and the second portion, the first width is greater than the second width. the first portion of the insulating structure has a first width, the second portion of the insulating structure has a second width, and at the boundary between the first portion and the second portion, the first width is greater than the second width.

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