Semiconductor device

Abstract

A semiconductor device includes: a substrate; an active pattern on the bottom and extending in a first horizontal direction; at least one first nanosheet stacked on the active pattern and spaced apart from each other in a vertical direction; at least one second nanosheet stacked on the active pattern and spaced apart from each other in the vertical direction; a trench formed on the active pattern between the at least one first nanosheet and the at least one second nanosheet; a lower spacer disposed along a bottom surface of the trench; a source / drain region within the trench on the lower spacer; and a void formed within the trench between the lower spacer and the source / drain region. An uppermost surface of the lower spacer is formed lower than an uppermost surface of the active pattern. The uppermost surface of the void is formed higher than the uppermost surface of the active pattern.

Description

[0001] This application claims the benefit of priority to Korean Patent Application No. 10-2024-0053623, filed on April 22, 2024, in the Korean Intellectual Property Office, the disclosure of which is incorporated herein in its entirety by reference. TECHNICAL FIELD

[0002] The present disclosure relates generally to a semiconductor device, and more particularly, to a semiconductor device including a multi-bridge channel field effect transistor (MBCFET™). BACKGROUND

[0003] A multi-gate transistor can have been proposed as a scaling technique for increasing the density of integrated circuit devices. A multi-gate transistor can refer to a transistor in which a silicon body in the form of a fin and / or a nanowire can be formed on a substrate and a gate can be formed on a surface of the silicon body.

[0004] As such, a multi-gate transistor can utilize its three-dimensional (3D) channel, thereby allowing for easy scaling (e.g., increasing and / or decreasing) in the vertical direction. Further, a multi-gate transistor can provide improved control of current flowing through the transistor when compared to a related transistor without the need to increase the gate length. Additionally, a multi-gate transistor can mitigate and / or reduce short channel effects (SCE), which can refer to a phenomenon in which the potential of a channel region can be affected by a drain voltage. SUMMARY

[0005] One or more example embodiments of the present disclosure provide a semiconductor device that can reduce leakage current between adjacent source / drain regions by forming a lower spacer and a void under the source / drain regions.

[0006] However, aspects of the present disclosure are not limited to those set forth herein. The above and other aspects of the present disclosure can become more apparent to one of ordinary skill in the art from the following detailed description of the present disclosure given by reference to the accompanying drawings.

[0007] According to an aspect of the disclosure, a semiconductor device includes a substrate; an active pattern on the substrate and extending in a first horizontal direction; at least one first nanosheet stacked on the active pattern and spaced apart from each other in a vertical direction; at least one second nanosheet stacked on the active pattern and spaced apart from each other in the vertical direction; a trench formed on the active pattern between the at least one first nanosheet and the at least one second nanosheet; a lower spacer disposed along a bottom surface of the trench; a source / drain region on the lower spacer within the trench; and a void formed within the trench between the lower spacer and the source / drain region. The at least one second nanosheet is spaced apart from the at least one first nanosheet in the first horizontal direction. The trench extends into the active pattern. An uppermost surface of the lower spacer is formed at a first level lower than a second level of an uppermost surface of the active pattern. An uppermost surface of the void is formed at a third level higher than the second level of the uppermost surface of the active pattern.

[0008] According to an aspect of the disclosure, a semiconductor device includes a substrate; an active pattern on the substrate and extending in a first horizontal direction on the substrate; a first gate electrode extending on the active pattern in a second horizontal direction different from the first horizontal direction; a second gate electrode extending on the active pattern in the second horizontal direction; a gate insulating layer disposed on a sidewall of the first gate electrode in the first horizontal direction; a trench formed on the active pattern between the first gate electrode and the second gate electrode; a lower spacer disposed along a bottom surface of the trench; a source / drain region on the lower spacer within the trench; and a void formed within the trench between the lower spacer and the source / drain region. The second gate electrode is spaced apart from the first gate electrode in the first horizontal direction. The trench extends into the active pattern. An uppermost surface of the lower spacer is formed at a first level lower than a second level of an uppermost surface of the active pattern. An uppermost surface of the void is formed at a third level higher than the second level of the uppermost surface of the active pattern. The source / drain region includes a first layer, a second layer on the first layer, and a third layer on the second layer. At least a portion of the second layer is exposed through the void. At least a portion of the third layer is exposed through the void.

[0009] According to an aspect of the present disclosure, a semiconductor device includes a substrate; an active pattern on the substrate and extending in a first horizontal direction; a first plurality of nanosheets stacked on the active pattern and spaced apart from each other in a vertical direction; a second plurality of nanosheets stacked on the active pattern and spaced apart from each other in the vertical direction; a first gate electrode on the active pattern and extending in a second horizontal direction different from the first horizontal direction; a second gate electrode on the active pattern and extending in the second horizontal direction; a first gate insulating layer disposed on a sidewall of the first gate electrode in the first horizontal direction; a second gate insulating layer disposed on a sidewall of the second gate electrode in the first horizontal direction; a trench formed on the active pattern between the first plurality of nanosheets and the second plurality of nanosheets; a lower spacer disposed along a bottom surface of the trench; a source / drain region on the lower spacer within the trench; and a void formed within the trench between the lower spacer and the source / drain region. The second plurality of nanosheets is spaced apart from the first plurality of nanosheets in the first horizontal direction. The first gate electrode at least partially surrounds the first plurality of nanosheets. The second gate electrode is spaced apart from the first gate electrode in the first horizontal direction. The second gate electrode at least partially surrounds the second plurality of nanosheets. The trench extends into the active pattern. An uppermost surface of the lower spacer is formed at a first level lower than a second level of an uppermost surface of the active pattern. An uppermost surface of the void is formed at a third level higher than the second level of the uppermost surface of the active pattern. A lowermost surface of the void is formed at a fourth level lower than the first level of the uppermost surface of the lower spacer. The upper surface of the void is convexly formed toward the source / drain region. The source / drain region includes a first layer, a second layer, and a third layer, the first layer being in contact with a sidewall of each of the first gate insulating layer and the second gate insulating layer in the first horizontal direction and the uppermost surface of the lower spacer, the second layer being on the first layer, and the third layer being on the second layer. At least a portion of the second layer is exposed through the void. At least a portion of the third layer is exposed through the void.

[0010] It should be noted that the effects of the present disclosure are not limited to those described above and that other effects of the present disclosure can become more apparent from the following description. BRIEF DESCRIPTION OF DRAWINGS

[0011] The above and other aspects, features, and advantages of certain embodiments of the present disclosure can be more apparent from the following description taken in conjunction with the accompanying drawings, in which:

[0012] Figure 1 is a schematic layout diagram illustrating a semiconductor device according to some embodiments of the present disclosure.

[0013] Figure 2 is a cross-sectional view taken along line A-A' of Figure 1 .

[0014] Figure 3 is a cross-sectional view taken along line B-B' of Figure 1

[0015] Figures 4 to 15 is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0016] Figures 16 to 21 is a cross-sectional view showing a semiconductor device according to some embodiments of the present disclosure. DETAILED DESCRIPTION

[0017] The following description with reference to the accompanying drawings is provided to assist in a comprehensive understanding of embodiments of the present disclosure as defined by the claims and their equivalents. Various specific details are included to assist in understanding, but these details are to be considered in the context of the disclosure and exemplary implementations. Accordingly, those who work in the art will recognize that various modifications and

[0018] With regard to the description of the drawings, like reference numerals can be used to refer to like or similar elements. It is to be understood that the singular forms "a," "an," and "the" include one or more of one or more things unless the context clearly dictates otherwise. As used herein, each of the phrases such as "A or B," "at least one of A and B," "at least one of A or B," "A, B, or C," "at least one of A, B, and C," and "at least one of A, B, or C," can include any one of or all possible combinations of the items enumerated in the phrase. As used herein, terms such as "1st" and "2nd" or "first" and "second" can be used to simply distinguish a corresponding component from another, without otherwise limiting the component in importance or order. It will be understood that if an element (for example, a first element) is termed to be "associated with" or "associated with" another element (for example, a second element) or "connected with" or "connected to" another element (for example, a second element), it means that the element can be directly (for example, wiredly), wirelessly, or via a third element associated with the other element.

[0019] ​It will be understood that when an element or layer is referred to as being "on" or "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers can be present. In contrast, when an element is referred to as being "directly on," or "directly connected to" or "directly coupled to" another element or layer, there are no intervening elements or layers present. It will also be understood that, when a device or component is referred to as being "configured to" perform a task or process, that device or component is not unconditionally programmed to perform the task or process, but rather, is capable of performing the task or process when appropriately configured or activated.

[0020] The terms "upper," "middle," "lower," and the like can be used to describe relative positions of elements. The terms "first," "second," "third," and the like can be used to describe various elements, however, these elements should not be limited by the terminology. For example, a "first" element could be termed a "second" element without departing from the scope of the present disclosure. Alternatively or additionally, the terms "first," "second," "third," and the like can be used to distinguish between components of the same type, and not necessarily in order of precedence or numerical order.

[0021] As used herein, when an element or layer is referred to as being "on," "over," or "around" another element or layer, it can cover at least a portion of the other element or layer, where the portion can include a portion of the other element or can include the entire dimension (e.g., length, width, depth) of the other element. Similarly, when an element or layer is referred to as "penetrating" another element or layer, it can penetrate at least a portion of the other element or layer, where the portion can include a portion of the other element or can include the entire dimension (e.g., length, width, depth) of the other element.

[0022] Reference throughout this disclosure to "one embodiment," "an embodiment," "exemplary embodiment," or similar language can indicate that a particular feature, structure, or characteristic described in connection with the indicated embodiment is included in at least one embodiment of the solution. Thus, appearances of the phrases "in one embodiment," "in an embodiment," "in an exemplary embodiment," and similar language throughout this disclosure can (but not necessarily) all refer to the same embodiment. The embodiments described herein are exemplary embodiments, and the disclosure is not limited to them. The disclosure can be implemented in various other forms.

[0023] It will be understood that the particular sequence or hierarchy of operations in the processes disclosed is an example of a method that can be implemented. It is understood that the particular sequence or hierarchy of operations in the processes disclosed can be re-arranged, or that some operations can be omitted, without changing the outcome of the method. The elements of the attached claims are not meant to be interpreted in a literal sense unless the context clearly indicates otherwise.

[0024] As used herein, each of the terms "Al2O3", "AIN", "BaSrTiO", "BaTiO", "HfAlO", "HfO2", "HfSiO", "HfZrO", "La2O3", "LaAlO", "MoC", "MoN", "NbC", "NbN", "Ni-Pt", "PbScTaO", "PbTiZrO5", "PZN", "SiBC", "SiBCN", "SiBN", "SiCN", "SiN", "SiO2", "SiOBN", "SiOC", "SiOCN", "SiON", "SrTiO", "Ta2O5", "TaAIN", "TaCN", "TaTiN", "Ti", "TiAl", "TiAlC", "TiAlC-N", "TiAIN", "TiC", "TiO2", "WC", "WN", "Y2O3", "ZrO2", "ZrSiO", and the like can refer to a material made of the elements included in each of the terms, and is not a chemical formula that represents a stoichiometric relationship.

[0025] Referring to Figures 1 to 3 Semiconductor devices according to some embodiments of the disclosure are described.

[0026] Figure 1 is a schematic layout diagram illustrating a semiconductor device according to some embodiments of the disclosure. Figure 2 is a cross-sectional view taken along line A-A' of Figure 1 according to some embodiments of the disclosure. Figure 3 is a cross-sectional view taken along line B-B' of Figure 1 according to some embodiments of the disclosure.

[0027] Referring to Figures 1 to 3A semiconductor device according to some embodiments of the present disclosure includes a substrate 100, an active pattern 101, at least one first nanowire NW1, at least one second nanowire NW2, a first gate electrode G1, a second gate electrode G2, a first gate spacer 111, a second gate spacer 112, a first gate insulating layer 121, a second gate insulating layer 122, a first capping pattern 131, a second capping pattern 132, a lower spacer 140, a source / drain region 150, a void 160, a first etch stop layer 170, a first interlayer insulating layer 175, a source / drain contact CA, a silicide layer SL, a gate contact CB, a second etch stop layer 180, a second interlayer insulating layer 185, a first via V1, and a second via V2.

[0028] The substrate 100 can be and / or can include a silicon (Si) substrate, a silicon-on-insulator (SOI), etc. Alternatively or additionally, the substrate 100 can be and / or can include a silicon germanium (SiGe), a SiGe-on-insulator (SGOI), an indium antimonide (InSb), a lead telluride (PbTe) compound, an indium arsenide (InAs), an indium phosphide (InP), a gallium arsenide (GaAs), a gallium antimonide (GaSb), etc. However, the present disclosure is not limited thereto.

[0029] The first horizontal direction DR1 and the second horizontal direction DR2 can refer to a direction parallel to an upper surface of the substrate 100. The second horizontal direction DR2 can refer to a direction different from the first horizontal direction DR1. The vertical direction DR3 can refer to a direction perpendicular to both the first horizontal direction DR1 and the second horizontal direction DR2. That is, the vertical direction DR3 can refer to a direction perpendicular to the upper surface of the substrate 100.

[0030] The active pattern 101 can extend on the substrate 100 in the first horizontal direction DR1. The active pattern 101 can protrude from the upper surface of the substrate 100 in the vertical direction DR3. For example, the active pattern 101 can be a portion of the substrate 100, and can include an epitaxial layer grown from the substrate 100.

[0031] The field insulating layer 105 can be disposed on the upper surface of the substrate 100. The field insulating layer 105 can surround a sidewall of the active pattern 101. For example, the upper surface of the active pattern 101 can protrude from the upper surface of the field insulating layer 105 in the vertical direction DR3, however, the present disclosure is not limited thereto. Alternatively or additionally, the upper surface of the active pattern 101 can be formed on a substantially similar and / or identical plane as the upper surface of the field insulating layer 105. The field insulating layer 105 can include, for example, but is not limited to, an oxide layer, a nitride layer, an oxynitride layer, or a combination thereof.

[0032] In some embodiments, the at least one first nanowire NW1 can include a first plurality of nanowires. The first plurality of nanowires NW1 can be stacked on the active pattern 101 and can be spaced apart from each other in the vertical direction DR3. For example, the first plurality of nanowires NW1 can include a first nanowire NW1_1, a second nanowire NW1_2, and a third nanowire NW1_3 that can be sequentially stacked on the active pattern 101 and can be spaced apart from each other in the vertical direction DR3. That is, the first nanowire NW1_1 can be spaced apart from the active pattern 101 in the vertical direction DR3, the second nanowire NW1_2 can be spaced apart from the first nanowire NW1_1 in the vertical direction DR3, and the third nanowire NW1_3 can be spaced apart from the second nanowire NW1_2 in the vertical direction DR3.

[0033] In some embodiments, the at least one second nanowire NW2 can include a second plurality of nanowires. The second plurality of nanowires NW2 can be stacked on the active pattern 101 and can be spaced apart from each other in the vertical direction DR3. For example, the second plurality of nanowires NW2 can include a fourth nanowire NW2_1, a fifth nanowire NW2_2, and a sixth nanowire NW2_3 that can be sequentially stacked on the active pattern 101 and can be spaced apart from each other in the vertical direction DR3. That is, the fourth nanowire NW2_1 can be spaced apart from the active pattern 101 in the vertical direction DR3, the fifth nanowire NW2_2 can be spaced apart from the fourth nanowire NW2_1 in the vertical direction DR3, and the sixth nanowire NW2_3 can be spaced apart from the fifth nanowire NW2_2 in the vertical direction DR3.

[0034] The second plurality of nanowires NW2 can be spaced apart from the first plurality of nanowires NW1 in the first horizontal direction DR1. For example, the first nanowire NW1_1 can be disposed at a substantially similar and / or identical vertical level as the fourth nanowire NW2_1. The second nanowire NW1_2 can be disposed at a substantially similar and / or identical vertical level as the fifth nanowire NW2_2. The third nanowire NW1_3 can be disposed at a substantially similar and / or identical vertical level as the sixth nanowire NW2_3. Figure 2 and Figure 3 It is shown that the first plurality of nanowires NW1 and the second plurality of nanowires NW2 each include three (3) vertically spaced and stacked nanowires, however, the present disclosure is not limited thereto. Alternatively or additionally, the first plurality of nanowires NW1 and the second plurality of nanowires NW2 can each include four (4) or more vertically spaced and stacked nanowires. In some embodiments, the first plurality of nanowires NW1 and the second plurality of nanowires NW2 can each include silicon (Si), however, the present disclosure is not limited thereto. Alternatively or additionally, in some embodiments, the first plurality of nanowires NW1 and the second plurality of nanowires NW2 can each include, but are not limited to, silicon germanium (SiGe), etc.

[0035] The first gate electrode G1 can extend over the active pattern 101 and the field insulating layer 105 in the second horizontal direction DR2. The first gate electrode G1 can surround the first plurality of nanosheets NW1. The second gate electrode G2 can extend over the active pattern 101 and the field insulating layer 105 in the second horizontal direction DR2. The second gate electrode G2 can be spaced apart from the first gate electrode G1 in the first horizontal direction DR1. The second gate electrode G2 can surround the second plurality of nanosheets NW2.

[0036] Each of the first gate electrode G1 and the second gate electrode G2 can include, for example, but not limited to, titanium nitride (TiN), tantalum carbide (TaC), tantalum nitride (TaN), titanium silicon nitride (TiSiN), tantalum silicon nitride (TaSiN), tantalum titanium nitride (TaTiN), titanium aluminum nitride (TiAlN), tantalum aluminum nitride (TaAlN), tungsten nitride (WN), ruthenium (Ru), titanium aluminum (TiAl), titanium aluminum carbonitride (TiAlC-N), titanium aluminum carbide (TiAlC), titanium carbide (TiC), tantalum carbonitride (TaCN), tungsten (W), aluminum (Al), copper (Cu), cobalt (Co), titanium (Ti), tantalum (Ta), nickel (Ni), platinum (Pt), nickel-platinum (Ni-Pt), niobium (Nb), niobium nitride (NbN), niobium carbide (NbC), molybdenum (Mo), molybdenum nitride (MoN), molybdenum carbide (MoC), tungsten carbide (WC), rhodium (Rh), palladium (Pd), iridium (Ir), osmium (Os), silver (Ag), gold (Au), zinc (Zn), vanadium (V), or a combination thereof. Each of the first gate electrode G1 and the second gate electrode G2 can include, but not limited to, a conductive metal oxide and / or a conductive metal oxynitride, and / or can include an oxidized form of the aforementioned materials.

[0037] The first gate spacer 111 may be disposed on the upper surface of the uppermost nanosheet in the first plurality of nanosheets NW1 and the field insulating layer 105. For example, the first gate spacer 111 may be disposed on the upper surface of the third nanosheet NW1_3 and the field insulating layer 105. The first gate spacer 111 may extend in the second horizontal direction DR2 on both sidewalls of the first gate electrode G1 in the first horizontal direction DR1. The second gate spacer 112 may be disposed on the upper surface of the uppermost nanosheet in the second plurality of nanosheets NW2 and the field insulating layer 105. For example, the second gate spacer 112 may be disposed on the upper surface of the sixth nanosheet NW2_3 and the field insulating layer 105. The second gate spacer 112 may extend in the second horizontal direction DR2 on both sidewalls of the second gate electrode G2 in the first horizontal direction DR1. Each of the first gate spacer 111 and the second gate spacer 112 may include, for example, at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxyboronitride (SiOBN), silicon borocarbide (SiBC), silicon boron carbonitride (SiBCN), silicon oxycarbide (SiOC), and combinations thereof. However, the present disclosure is not limited thereto.

[0038] The trench T may be formed between the first gate electrode G1 and the second gate electrode G2 on the active pattern 101. The trench T may be formed between the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 on the active pattern 101. For example, the trench T may extend into the active pattern 101. That is, the bottom surface of the trench T may be lower than the uppermost surface of the active pattern 101. For example, the bottom surface of the trench T may be lower than the upper surface of the field insulating layer 105, however, the present disclosure is not limited thereto. For example, the sidewalls and bottom surface of the trench T may be defined by the sidewalls of the first plurality of nanosheets NW1 in the first horizontal direction DR1, the sidewalls of the second plurality of nanosheets NW2 in the first horizontal direction DR1, the first gate insulating layer 121 and the second gate insulating layer 122, and the active pattern 101.

[0039] The lower spacer 140 may be provided along the bottom surface of the trench T. For example, the lower spacer 140 may be provided in a liner shape. Figure 2 In a cross-sectional view taken along the first horizontal direction DR1 in FIG. , the lower spacer 140 may have a semicircular shape. Alternatively or additionally, a lower surface of the lower spacer 140 may contact the active pattern 101. In some embodiments, an upper surface of the lower spacer 140 may be recessed toward the active pattern 101. An uppermost surface 140 a of the lower spacer 140 may be lower than an uppermost surface of the active pattern 101. Figure 2It is shown that the uppermost surface 140a of the lower spacer 140 is formed in parallel with the first horizontal direction DR1, however, the present disclosure is not limited thereto. Alternatively or additionally, the uppermost surface 140a of the lower spacer 140 can be inclined with respect to the first horizontal direction DR1.

[0040] For example, the lower spacer 140 can be formed as a single layer, however, the present disclosure is not limited thereto. In some embodiments, the thickness of the lower spacer 140 at the lowermost portion of the trench T in the vertical direction DR3 can be in a range of about 2 nanometers (nm) to about 10 nm. For example, the height difference between the uppermost surface 140a of the lower spacer 140 and the uppermost surface of the active pattern 101 can be in a range of about 2 nm to about 4 nm. The lower spacer 140 can include an insulating material. For example, the lower spacer 140 can include at least one of silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), silicon boronitride (SiBN), silicon oxoboronitride (SiOBN), silicon borocarbide (SiBC), silicon boron carbonitride (SiBCN), silicon oxycarbide (SiOC), and combinations thereof. However, the present disclosure is not limited thereto.

[0041] The source / drain region 150 can be disposed on the lower spacer 140 within the trench T. For example, the source / drain region 150 can be in contact with the sidewall of the first plurality of nanosheets NW1 in the first horizontal direction DR1. The source / drain region 150 can be in contact with the sidewall of the second plurality of nanosheets NW2 in the first horizontal direction DR1. For example, the source / drain region 150 can be in contact with the uppermost surface 140a of the lower spacer 140. In some embodiments, at least a portion of the source / drain region 150 can be in contact with the active pattern 101 on the uppermost surface 140a of the lower spacer 140. For example, the uppermost surface of the source / drain region 150 can be formed higher than the upper surface of the third nanosheet NW1_3 and the upper surface of the sixth nanosheet NW2_3.

[0042] In some embodiments, at least a portion of the source / drain region 150 can be disposed between the active pattern 101 and the first nanosheet NW1_1. At least a portion of the source / drain region 150 can be disposed between adjacent nanosheets in the first plurality of nanosheets NW1. For example, at least a portion of the source / drain region 150 can be disposed between the first nanosheet NW1_1 and the second nanosheet NW1_2. Alternatively or additionally, at least a portion of the source / drain region 150 can be disposed between the second nanosheet NW1_2 and the third nanosheet NW1_3. For example, at least a portion of the source / drain region 150 can be disposed between the active pattern 101 and the fourth nanosheet NW2_1. Alternatively or additionally, at least a portion of the source / drain region 150 can be disposed between adjacent nanosheets in the second plurality of nanosheets NW2. For example, at least a portion of the source / drain region 150 can be disposed between the fourth nanosheet NW2_1 and the fifth nanosheet NW2_2. As another example, at least a portion of the source / drain region 150 can be disposed between the fifth nanosheet NW2_2 and the sixth nanosheet NW2_3.

[0043] In some embodiments, the source / drain region 150 can include a first layer 151, a second layer 152, and a third layer 153. The first layer 151 can be disposed on the uppermost surface 140a of the lower spacer 140 along sidewalls of the trench T. For example, the first layer 151 can be in contact with sidewalls of the first plurality of nanosheets NW1 in the first horizontal direction DR1. The first layer 151 can be in contact with sidewalls of the second plurality of nanosheets NW2 in the first horizontal direction DR1. For example, the first layer 151 can be in contact with the uppermost surface 140a of the lower spacer 140. As another example, at least a portion of the first layer 151 can be in contact with the active pattern 101 on the uppermost surface 140a of the lower spacer 140.

[0044] In some embodiments, at least a portion of the first layer 151 can be disposed between the active pattern 101 and the first nanosheet NW1_1. Alternatively or additionally, at least a portion of the first layer 151 can be disposed between the first nanosheet NW1_1 and the second nanosheet NW1_2. As another example, at least a portion of the first layer 151 can be disposed between the second nanosheet NW1_2 and the third nanosheet NW1_3. As another embodiment, at least a portion of the first layer 151 can be disposed between the active pattern 101 and the fourth nanosheet NW2_1. As yet another example, at least a portion of the first layer 151 can be disposed between the fourth nanosheet NW2_1 and the fifth nanosheet NW2_2. As yet another example, at least a portion of the first layer 151 can be disposed between the fifth nanosheet NW2_2 and the sixth nanosheet NW2_3.

[0045] In some embodiments, the first layer 151 can extend to a lower surface of the first gate spacer 111 disposed on an upper surface of the third nanosheet NW1_3. Optionally or additionally, the first layer 151 can extend to a lower surface of the second gate spacer 112 disposed on an upper surface of the sixth nanosheet NW2_3. In some embodiments, the first layer 151 can include undoped silicon (Si), undoped silicon germanium (SiGe), carbon (C) doped silicon (Si), C doped silicon germanium (SiGe), or the like. However, the present disclosure is not limited thereto.

[0046] The second layer 152 can be disposed on the first layer 151 within the trench T. For example, the second layer 152 can be disposed along sidewalls of the first layer 151. That is, the second layer 152 can be in contact with the sidewalls of the first layer 151. For example, in a cross-sectional view of FIG. 1A taken along the first horizontal direction DR1, the second layer 152 can be disposed on the first layer 151. Figure 2

[0047] In some embodiments, the second layer 152 can extend to a lower surface of the first gate spacer 111 disposed on an upper surface of the third nanosheet NW1_3. Optionally or additionally, the second layer 152 can extend to a lower surface of the second gate spacer 112 disposed on an upper surface of the sixth nanosheet NW2_3. For example, the second layer 152 can include a different material from the first layer 151. In such an example, the second layer 152 can include silicon (Si) doped with arsenic (As), silicon (Si) doped with phosphorus (P), silicon (Si) doped with both arsenic (As) and phosphorus (P), or silicon (Si) doped with antimony (Sb), or the like. However, the present disclosure is not limited thereto.

[0048] The third layer 153 can be disposed on the second layer 152 within the trench T. For example, the third layer 153 can fill the entire trench T except for the lower spacer 140, the first layer 151, the second layer 152, and the void 160. As another example, the third layer 153 can be in contact with sidewalls of the second layer 152. For example, in a cross-sectional view of FIG. 1A taken along the first horizontal direction DR1, the third layer 153 can be disposed on the second layer 152. Figure 2 Figure 2 In a cross-sectional view of FIG. 1A taken along the first horizontal direction DR1, the third layer 153 can be spaced apart from the lower spacer 140 in the vertical direction DR3. The third layer 153 can include, but is not limited to, silicon (Si) doped with P. For example, if the second layer 152 includes silicon (Si) doped with both arsenic (As) and phosphorus (P) or silicon (Si) doped with only phosphorus (P), a concentration of phosphorus (P) doped in the third layer 153 can be greater than a concentration of phosphorus (P) doped in the second layer 152. The concentrations can be defined in atomic percentage (at%) values.​​

[0049] The void 160 can be formed in the trench T between the lower spacer 140 and the source / drain region 150. For example, a portion of the lower spacer 140 can be exposed by the void 160. That is, a lower surface of the void 160 can be defined by the lower spacer 140. For example, an uppermost surface 140a of the lower spacer 140 can not be exposed by the void 160, however, the present disclosure is not limited thereto. Alternatively or additionally, at least a portion of the uppermost surface 140a of the lower spacer 140 can be exposed by the void 160. For example, the second layer 152 and the third layer 153 can be exposed by the void 160. That is, an upper surface of the void 160 can be defined by the second layer 152 and the third layer 153. For example, the first layer 151 can not be exposed by the void 160, however, the present disclosure is not limited thereto. Alternatively or additionally, at least a portion of the first layer 151 can be exposed by the void 160.

[0050] In some embodiments, an upper surface of the void 160 can be convexly formed toward the source / drain region 150. Alternatively or additionally, a lower surface of the void 160 can be convexly formed toward the active pattern 101. For example, a lowermost surface of the void 160 can be formed lower than the uppermost surface 140a of the lower spacer 140. As another example, an uppermost surface 160a of the void 160 can be formed higher than the uppermost surface 140a of the lower spacer 140. As yet another example, the uppermost surface 160a of the void 160 can be formed higher than an upper surface of the active pattern 101. Alternatively or additionally, the uppermost surface 160a of the void 160 can be formed lower than a lower surface of the first nanosheet NW1_1, which can refer to a lowermost nanosheet among the first plurality of nanosheets NW1. Alternatively or additionally, the uppermost surface 160a of the void 160 can be formed lower than a lower surface of the fourth nanosheet NW2_1, which can refer to a lowermost nanosheet among the second plurality of nanosheets NW2. In such embodiments, a ratio of a volume of the void 160 to a combined volume of the void 160 and the source / drain region 150 can be in a range of about 2% to about 5%.

[0051] The first gate insulating layer 121 can be disposed on both sidewalls of the first gate electrode G1 in the first horizontal direction DR1. For example, the first gate insulating layer 121 can be disposed between the first gate electrode G1 and the first gate spacer 111. The first gate insulating layer 121 can be disposed between the first gate electrode G1 and the active pattern 101. The first gate insulating layer 121 can be disposed between the first gate electrode G1 and the field insulating layer 105. The first gate insulating layer 121 can be disposed between the first gate electrode G1 and the first plurality of nanosheets NW1. The first gate insulating layer 121 can be disposed between the first gate electrode G1 and the source / drain region 150. That is, the first gate insulating layer 121 can be disposed between the first gate electrode G1 and the first layer 151. For example, the first gate insulating layer 121 can be in contact with the source / drain region 150. That is, the first gate insulating layer 121 can be in contact with the first layer 151.

[0052] The second gate insulating layer 122 can be disposed on both sidewalls of the second gate electrode G2 in the first horizontal direction DR1. For example, the second gate insulating layer 122 can be disposed between the second gate electrode G2 and the second gate spacer 112. The second gate insulating layer 122 can be disposed between the second gate electrode G2 and the active pattern 101. The second gate insulating layer 122 can be disposed between the second gate electrode G2 and the field insulating layer 105. The second gate insulating layer 122 can be disposed between the second gate electrode G2 and the second plurality of nanosheets NW2. The second gate insulating layer 122 can be disposed between the second gate electrode G2 and the source / drain region 150. That is, the second gate insulating layer 122 can be disposed between the second gate electrode G2 and the first layer 151. For example, the second gate insulating layer 122 can be in contact with the source / drain region 150. That is, the second gate insulating layer 122 can be in contact with the first layer 151.

[0053] The first gate insulating layer 121 and the second gate insulating layer 122 can include, but are not limited to, at least one of silicon oxide (SiO2), silicon oxynitride (SiON), silicon nitride (SiN), a high-k material having a larger dielectric constant than silicon oxide (SiO2), etc. The high-k material can include, for example, but is not limited to, at least one of hafnium oxide (HfO2), hafnium silicon oxide (HfSiO), hafnium aluminum oxide (HfAlO), lanthanum oxide (La2O3), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO), tantalum oxide (Ta2O5), titanium oxide (TiO2), barium strontium titanium oxide (BST) (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (Y2O3), aluminum oxide (Al2O3), lead scandium tantalum oxide (PST) (PbScTaO), lead zinc niobate (PZN), etc.

[0054] A semiconductor device according to some embodiments of the present disclosure can include a negative capacitance (NC) field effect transistor (FET) using a negative capacitor. For example, each of the first gate insulating layer 121 and the second gate insulating layer 122 can include a ferroelectric material film having ferroelectric properties and a paraelectric material film having paraelectric properties.

[0055] The ferroelectric material film can have a negative capacitance, and the paraelectric material film can have a positive capacitance. For example, if two (2) or more capacitors are connected in series and have a positive capacitance, a total capacitance of the two (2) or more capacitors can be lower than a capacitance of each of the two (2) or more capacitors. Alternatively, if at least one (1) of the two (2) or more capacitors has a negative capacitance, a total capacitance of the two (2) or more capacitors can have a positive value and can be greater than an absolute value of the capacitance of each of the two (2) or more capacitors.

[0056] If the ferroelectric material film having a negative capacitance is connected in series with the paraelectric material film having a positive capacitance, a total capacitance of the ferroelectric material film and the paraelectric material film can increase. Accordingly, a transistor having the ferroelectric material film can have a sub-threshold swing (SS) of less than 60 mV / decade at room temperature.

[0057] The ferroelectric material film can have ferroelectric properties. The ferroelectric material film can include, for example, but not limited to, at least one of hafnium oxide (HfO2), hafnium zirconium oxide (HfZrO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), lead zirconium titanium oxide (PbTiZrO5), etc. For example, the hafnium zirconium oxide (HfZrO) can be and / or can include a material obtained by doping hafnium oxide (HfO2) with zirconium (Zr). In another example, the hafnium zirconium oxide (HfZrO) can be and / or can include a compound of hafnium (Hf), zirconium (Zr), and oxygen (O).

[0058] The ferroelectric material film can further include a dopant. For example, the dopant can include, but not limited to, at least one of aluminum (Al), titanium (Ti), niobium (Nb), lanthanum (La), yttrium (Y), zirconium (Zr), magnesium (Mg), silicon (Si), calcium (Ca), cerium (Ce), dysprosium (Dy), erbium (Er), gadolinium (Gd), germanium (Ge), scandium (Sc), strontium (Sr), tin (Sn), etc. The type of the dopant can vary according to the type of the material of the ferroelectric material film.

[0059] If the ferroelectric material film includes hafnium oxide (HfO2), the dopant of the ferroelectric material film can include, for example, at least one of gadolinium (Gd), silicon (Si), zirconium (Zr), aluminum (Al), and yttrium (Y).

[0060] If the dopant of the ferroelectric material film is aluminum (Al), the ferroelectric material film can include about 3 at% to about 8 at% of aluminum (Al). As used herein, the ratio of the dopant in the ferroelectric material film can refer to the ratio of the amount of aluminum (Al) in the ferroelectric material film to the sum of the amount of hafnium (Hf) and the amount of aluminum (Al).

[0061] If the dopant of the ferroelectric material film is silicon (Si), the ferroelectric material film can include about 2 at% to about 10 at% of silicon (Si). If the dopant of the ferroelectric material film is yttrium (Y), the ferroelectric material film can include about 2 at% to about 10 at% of yttrium (Y). If the dopant of the ferroelectric material film is gadolinium (Gd), the ferroelectric material film can include about 1 at% to about 7 at% of gadolinium (Gd). If the dopant of the ferroelectric material film is zirconium (Zr), the ferroelectric material film can include about 50 at% to about 80 at% of zirconium (Zr).

[0062] The paraelectric material film can include paraelectric properties. The paraelectric material film can include, for example, but not limited to, at least one of silicon oxide (SiO2), high-k metal oxide, etc. The high-k metal oxide can include, for example, at least one of hafnium oxide (HfO2), zirconium oxide (ZrO2), and aluminum oxide (Al2O3). However, the present disclosure is not limited thereto.

[0063] The ferroelectric material film and the paraelectric material film can include substantially similar and / or identical materials. The ferroelectric material film can have ferroelectric properties. Alternatively or additionally, the paraelectric material film can not have ferroelectric properties. For example, if the ferroelectric material film and the paraelectric material film include hafnium oxide (HfO2), the hafnium oxide (HfO2) included in the ferroelectric material film can have a different crystal structure than the hafnium oxide (HfO2) included in the paraelectric material film.

[0064] The ferroelectric material film can be thick enough to exhibit ferroelectric properties. The ferroelectric material film can have, for example, a thickness of about 0.5 nm to about 10 nm. However, the present disclosure is not limited thereto. The critical thickness at which ferroelectric properties can be exhibited can vary depending on the type of ferroelectric material, and thus, the thickness of the ferroelectric material film can vary depending on the type of ferroelectric material included in the ferroelectric material film.

[0065] For example, each of the first gate insulating layer 121 and the second gate insulating layer 122 can include a single ferroelectric material film. As another example, each of the first gate insulating layer 121 and the second gate insulating layer 122 can include a plurality of ferroelectric material films that can be spaced apart from each other. Each of the first gate insulating layer 121 and the second gate insulating layer 122 can include a stack of a plurality of ferroelectric material films and a plurality of paraelectric material films, which can be alternately stacked with the ferroelectric material films.

[0066] The first etch stop layer 170 can be disposed on sidewalls of the first gate spacers 111 and the second gate spacers 112 in the first horizontal direction DR1. Alternatively or additionally, the first etch stop layer 170 can be disposed on an upper surface of the source / drain region 150. In some embodiments, the first etch stop layer 170 can be disposed on sidewalls of the source / drain region 150 in the second horizontal direction DR2. For example, the first etch stop layer 170 can be conformally formed. The first etch stop layer 170 can include at least one of, for example, aluminum oxide (Al2O3), aluminum nitride (AlN), hafnium oxide (HfO2), zirconium oxide (ZrO2), silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a low-k material, etc. However, the present disclosure is not limited thereto.

[0067] The first cover pattern 131 can extend over each of the first gate spacers 111, the first gate insulating layer 121, and the first gate electrode G1 in the second horizontal direction DR2. The second cover pattern 132 can extend over each of the second gate spacers 112, the second gate insulating layer 122, and the second gate electrode G2 in the second horizontal direction DR2. For example, a lower surface of the first cover pattern 131 and the second cover pattern 132 can be in contact with the first etch stop layer 170, however, the present disclosure is not limited thereto. Alternatively or additionally, sidewalls of the first cover pattern 131 and the second cover pattern 132 can be in contact with the first etch stop layer 170. The first cover pattern 131 and the second cover pattern 132 can include at least one of, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbonitride (SiCN), silicon oxycarbonitride (SiOCN), and combinations thereof. However, the present disclosure is not limited thereto.

[0068] The first interlayer insulating layer 175 can be disposed on the first etch stop layer 170. The first interlayer insulating layer 175 can be disposed on sidewalls of each of the first cover pattern 131 and the second cover pattern 132. The first interlayer insulating layer 175 can cover the source / drain region 150 on the field insulating layer 105. For example, an upper surface of the first interlayer insulating layer 175 can be formed on a plane substantially similar to and / or identical to an upper surface of the first cover pattern 131 and the second cover pattern 132. The first interlayer insulating layer 175 can include at least one of, for example, silicon oxide (SiO2), silicon nitride (SiN), silicon oxynitride (SiON), a low-k material, etc. However, the present disclosure is not limited thereto.

[0069] The source / drain contact CA can be disposed between the first gate electrode G1 and the second gate electrode G2. The source / drain contact CA can be disposed over the source / drain region 150. The source / drain contact CA can extend into the source / drain region 150 by penetrating the first interlayer insulating layer 175 and the first etch stop layer 170 in the vertical direction DR3. The source / drain contact CA can be electrically connected to the source / drain region 150. In Figure 2 In the embodiment, the source / drain contact CA is illustrated as being formed as a single layer, however, the present disclosure is not limited thereto. Alternatively or additionally, the source / drain contact CA can be formed as a plurality of layers. For example, an upper surface of the source / drain contact CA can be formed on a plane substantially similar to and / or identical to an upper surface of the first interlayer insulating layer 175, however, the present disclosure is not limited thereto. Alternatively or additionally, the upper surface of the source / drain contact CA can be formed higher than the upper surface of the first interlayer insulating layer 175. The source / drain contact CA can be and / or can include an electrically conductive material. A silicide layer SL can be disposed between the source / drain contact CA and the source / drain region 150. The silicide layer SL can be disposed along a boundary between the source / drain contact CA and the source / drain region 150. For example, the silicide layer SL can include a metal silicide material. However, the present disclosure is not limited thereto.

[0070] The gate contact CB can be located over the first gate electrode G1. The gate contact CB can be connected to the first gate electrode G1 by penetrating the first cover pattern 131 in the vertical direction DR3. In Figure 3 In the embodiment, the gate contact CB is illustrated as being formed as a single layer, however, the present disclosure is not limited thereto. Alternatively or additionally, the gate contact CB can be formed as a plurality of layers. For example, an upper surface of the gate contact CB can be formed on a plane substantially similar to and / or identical to upper surfaces of the source / drain contact CA and the first interlayer insulating layer 175, however, the present disclosure is not limited thereto. The gate contact CB can include an electrically conductive material. However, the present disclosure is not limited thereto.

[0071] The second etch stop layer 180 can be disposed on an upper surface of the source / drain contact CA, the first and second cover patterns 131 and 132, and the first interlayer insulating layer 175. In Figure 2 and Figure 3In some embodiments, the second etch stop layer 180 is shown as being formed as a single layer, however, the present disclosure is not limited thereto. Alternatively or additionally, the second etch stop layer 180 can be formed as multiple layers. The second etch stop layer 180 can include, for example, at least one of aluminum oxide (AI2O3), aluminum nitride (AIN), hafnium oxide (Hf02), zirconium oxide (Zr02), silicon oxide (Si02), silicon nitride (SiN), silicon oxynitride (SiON), low-k materials, etc. However, the present disclosure is not limited thereto. A second interlayer insulating layer 185 can be disposed on the second etch stop layer 180. The second interlayer insulating layer 185 can include, but is not limited to, at least one of silicon oxide (Si02), silicon nitride (SiN), silicon oxynitride (SiON), low-k materials, etc.

[0072] The first via V1 can be connected to the source / drain contact CA by penetrating the second interlayer insulating layer 185 and the second etch stop layer 180 in the vertical direction DR3. Similarly, the second via V2 can be connected to the gate contact CB by penetrating the second interlayer insulating layer 185 and the second etch stop layer 180 in the vertical direction DR3. In Figure 2 and Figure 3 In some embodiments, the first via V1 and the second via V2 are shown as being formed as a single layer, however, the present disclosure is not limited thereto. Alternatively or additionally, the first via V1 and the second via V2 can be formed as multiple layers. The first via V1 and the second via V2 can include a conductive material. However, the present disclosure is not limited thereto.

[0073] A semiconductor device according to some embodiments of the present disclosure can have a lower spacer 140 under the source / drain region 150, thereby potentially reducing leakage current with a nearby source / drain region. Alternatively or additionally, a semiconductor device according to some embodiments of the present disclosure can have an air gap 160 between the lower spacer 140 and the source / drain region 150, thereby potentially reducing leakage current with a nearby source / drain region.

[0074] Referring to Figures 4 to 15 A method of manufacturing a semiconductor device according to some embodiments of the present disclosure is described.

[0075] Figures 4 to 15 is a cross-sectional view showing an intermediate step of a method of manufacturing a semiconductor device according to some embodiments of the present disclosure.

[0076] Referring to Figure 4 and Figure 5A stack structure 10 can be formed on the substrate 100. The stack structure 10 can include first semiconductor layers 11 and second semiconductor layers 12 which can be stacked on an upper surface of the substrate 100, the second semiconductor layers 12 being alternated with the first semiconductor layers 11. For example, the first semiconductor layers 11 can be formed at a bottom of the stack structure 10 (e.g., as a lowermost layer of the stack structure 10), and the second semiconductor layers 12 can be formed at a top of the stack structure 10 (e.g., as an uppermost layer of the stack structure 10). However, the present disclosure is not limited thereto. Alternatively or additionally, the first semiconductor layers 11 can be formed at the top of the stack structure 10. The first semiconductor layers 11 can include, for example, silicon germanium (SiGe). The second semiconductor layers 12 can include, for example, silicon (Si), or the like. However, the present disclosure is not limited thereto.

[0077] Subsequently, the stack structure 10 can be partially etched. During etching of the stack structure 10, the substrate 100 can be partially etched. By the etching process, an active pattern 101 can be defined on the upper surface of the substrate 100 under the stack structure 10. The active pattern 101 can extend in a first horizontal direction DR1. Subsequently, a field insulating layer 105 can be formed on the upper surface of the substrate 100. The field insulating layer 105 can surround sidewalls of the active pattern 101. For example, an upper surface of the active pattern 101 can be formed higher than an upper surface of the field insulating layer 105. Subsequently, a pad oxide layer 20 can be formed to cover the upper surface of the field insulating layer 105, exposed sidewalls of the active pattern 101, and sidewalls and an upper surface of the stack structure 10. For example, the pad oxide layer 20 can be formed conformally. The pad oxide layer 20 can include, for example, silicon oxide (SiO2), or the like. However, the present disclosure is not limited thereto.

[0078] Referring to Figure 6 and Figure 7 On the stack structure 10 and the field insulating layer 105, first and second dummy gates DG1 and DG2 and first and second dummy cover patterns DC1 and DC2 can be formed on the pad oxide layer 20, the first and second dummy gates DG1 and DG2 can extend in a second horizontal direction DR2, and the first and second dummy cover patterns DC1 and DC2 can extend in the second horizontal direction DR2. The first dummy cover pattern DC1 can be formed on the first dummy gate DG1. The second dummy cover pattern DC2 can be formed on the second dummy gate DG2. The second dummy gate DG2 and the second dummy cover pattern DC2 can be spaced apart from the first dummy gate DG1 and the first dummy cover pattern DC1, respectively, in the first horizontal direction DR1. During formation of the first and second dummy gates DG1 and DG2 and the first and second dummy cover patterns DC1 and DC2, the entire pad oxide layer 20 except for a portion which can be overlapped with the first and second dummy gates DG1 and DG2 in a vertical direction DR3 can be etched.

[0079] Subsequently, a spacer material layer SM can be formed to cover the sidewalls of the first dummy gate DG1 and the second dummy gate DG2, the sidewalls and the upper surfaces of the first dummy coverage pattern DC1 and the second dummy coverage pattern DC2, the exposed upper surface of the stack structure 10, and the upper surface of the field insulating layer 105. For example, the spacer material layer SM can be formed conformally. The spacer material layer SM can include, for example, silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon nitride (SiCN), silicon oxygen carbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxygen boron nitride (SiOBN), silicon boron carbon (SiBC), silicon boron carbon nitride (SiBCN), silicon carbon oxide (SiOC), or a combination thereof. However, the present disclosure is not limited thereto.

[0080] Referring to Figure 8 The stack structure 10 can be etched using the first dummy coverage pattern DC1 and the second dummy coverage pattern DC2 and the first dummy gate DG1 and the second dummy gate DG2 as masks, thereby forming a trench T. For example, the trench T can extend into the active pattern 101. During the formation of the trench T, portions of the spacer material layer SM formed on the upper surfaces of the first dummy coverage pattern DC1 and the second dummy coverage pattern DC2 and portions of the first dummy coverage pattern DC1 and the second dummy coverage pattern DC2 can be etched. Portions of the spacer material layer SM remaining on the sidewalls of the first dummy cap coverage pattern DC1 and the first dummy gate DG1 can be defined as a first gate spacer 111. Similarly, portions of the spacer material layer SM remaining on the sidewalls of the second dummy coverage pattern DC2 and the second dummy gate DG2 can be defined as a second gate spacer 112.

[0081] After the formation of the trench T, the second semiconductor layer 12 remaining under the first dummy gate DG1 can be defined as a first plurality of nanosheets NW1. Alternatively or additionally, after the formation of the trench T, the second semiconductor layer 12 remaining under the second dummy gate DG2 can be defined as a second plurality of nanosheets NW2. For example, during the formation of the trench T, the sidewalls of the first semiconductor layer 11 in the first horizontal direction DR1 can be etched more than the sidewalls of the second semiconductor layer 12 in the first horizontal direction DR1. As a result, the sidewalls of the first semiconductor layer 11 in the first horizontal direction DR1 can be recessed more than the sidewalls of the first plurality of nanosheets NW1 and the second plurality of nanosheets NW2 in the first horizontal direction DR1.

[0082] Referring to Figure 9 A lower spacer 140 can be formed along the bottom surface of the trench T. For example, the lower spacer 140 can be disposed in a liner shape. For example, in the case where the trench T extends into the active pattern 101, the lower spacer 140 can be formed on the sidewalls of the trench T and the bottom surface of the trench T. Figure 9In a cross-sectional view taken along the first horizontal direction DR1, the lower spacer 140 can have a semi-circular shape. For example, a lower surface of the lower spacer 140 can be in contact with the active pattern 101. In some embodiments, an upper surface of the lower spacer 140 can be concavely formed toward the active pattern 101. For example, an uppermost surface 140a of the lower spacer 140 can be formed lower than an uppermost surface of the active pattern 101. A trench formed on the upper surface of the lower spacer 140 within the trench T can be defined as a first source / drain trench ST1. For example, at least a portion of the active pattern 101 can be exposed through the first source / drain trench ST1 on the uppermost surface 140a of the lower spacer 140.

[0083] Referring to Figure 10 A first layer 151 can be formed along a sidewall of the first source / drain trench ST1. For example, the first layer 151 can be disposed along the sidewall of the first source / drain trench ST1 on the uppermost surface 140a of the lower spacer 140. That is, the first layer 151 can be in contact with a sidewall of the first plurality of nanosheets NW1 in the first horizontal direction DR1. The first layer 151 can be in contact with a sidewall of the second plurality of nanosheets NW2 in the first horizontal direction DR1. For example, the first layer 151 can be in contact with a sidewall of the first semiconductor layer 11 in the first horizontal direction DR1. As another example, the first layer 151 can be in contact with the uppermost surface 140a of the lower spacer 140. As still another example, at least a portion of the first layer 151 can be in contact with the active pattern 101 on the uppermost surface 140a of the lower spacer 140.

[0084] As Figure 10 In a cross-sectional view taken along the first horizontal direction DR1, the first layer 151 can not be formed on an upper surface of the lower spacer 140 that can be concavely formed toward the active pattern 101. A trench formed between portions of the first layer 151 within the first source / drain trench ST1 can be defined as a second source / drain trench ST2. For example, the upper surface of the lower spacer 140 that is concavely formed toward the active pattern 101 can be exposed through the second source / drain trench ST2.

[0085] Referring to Figure 11 A second layer 152 can be formed along a sidewall of the second source / drain trench ST2. For example, the second layer 152 can be in contact with a sidewall of the first layer 151. As Figure 11As shown in FIG. 1A, in a cross-sectional view taken along the first horizontal direction DR1, the second layer 152 can not be formed on an upper surface of the lower spacer 140 that can be recessively formed toward the active pattern 101. A trench formed within the second source / drain trench ST2 between portions of the second layer 152 can be defined as a third source / drain trench ST3. For example, the upper surface of the lower spacer 140 that is recessively formed toward the active pattern 101 can be exposed by the third source / drain trench ST3. For example, a sidewall of the second layer 152 that overlaps the upper surface of the lower spacer 140 in the vertical direction DR3 can have a sloped profile.

[0086] Referring to Figure 12 A third layer 153 can be formed on the second layer 152 within the third source / drain trench ST3. As a result, a source / drain region 150 including the first layer 151 to the third layer 153 can be formed. As shown in FIG. 1A, in a cross-sectional view taken along the first horizontal direction DR1, a lower surface of the third layer 153 can be recessively formed toward an upper surface of the third layer 153. For example, after the third layer 153 is formed, a void 160 can be formed between the upper surface of the lower spacer 140 that can be recessively formed toward the active pattern 101 and the lower surface of the source / drain region 150. Figure 12

[0087] For example, a lower surface of the void 160 can be defined by the lower spacer 140. Alternatively or additionally, an upper surface of the void 160 can be defined by the second layer 152 and the third layer 153. For example, the upper surface of the void 160 can be convexly formed toward the source / drain region 150. Alternatively or additionally, the lower surface of the void 160 can be convexly formed toward the active pattern 101. For example, a lowermost surface of the void 160 can be formed lower than an uppermost surface 140a of the lower spacer 140. For example, an uppermost surface 160a of the void 160 can be formed higher than the uppermost surface 140a of the lower spacer 140. As another example, the uppermost surface 160a of the void 160 can be formed higher than an uppermost surface of the active pattern 101. As yet another example, the uppermost surface 160a of the void 160 can be formed lower than a lower surface of the first nanowire NW1_1 and a lower surface of the fourth nanowire NW2_1.

[0088] Referring to Figure 13 A first etch stop layer 170 can be formed on the exposed upper surface of the field insulating layer 105, the exposed sidewalls of the first gate spacer 111 and the second gate spacer 112, the exposed upper surfaces of the first dummy cover pattern DC1 and the second dummy cover pattern DC2, and the exposed surfaces of the source / drain region 150. Subsequently, a first interlayer insulating layer 175 can be formed on the first etch stop layer 170. Subsequently, a planarization process can be performed, thereby exposing upper surfaces of the first dummy gate DG1 and the second dummy gate DG2. ​

[0089] Referring to Figure 14 The first dummy gate DG1 and the second dummy gate DG2, the pad oxide layer 20, and the first semiconductor layer 11 can be etched. The region in which the first dummy gate DG1, the pad oxide layer 20, and the first semiconductor layer 11 have been etched can be defined as the first gate trench GT1. Alternatively or additionally, the region in which the second dummy gate DG2, the pad oxide layer 20, and the first semiconductor layer 11 have been etched can be defined as the second gate trench GT2.

[0090] Referring to Figure 15 The first gate insulating layer 121, the first gate electrode G1, and the first cap pattern 131 can be sequentially formed within the first gate trench GT1. Alternatively or additionally, the second gate insulating layer 122, the second gate electrode G2, and the second cap pattern 132 can be sequentially formed within the second gate trench GT2. For example, the first gate electrode G1 can surround the first plurality of nanosheets NW1. The second gate electrode G2 can surround the second plurality of nanosheets NW2.

[0091] Referring to Figure 2 and Figure 3 A source / drain contact CA can be formed on the source / drain region 150. The source / drain contact CA can penetrate the first interlayer insulating layer 175 and the first etch stop layer 170 in the vertical direction DR3, thereby extending into the source / drain region 150. Alternatively or additionally, a silicide layer SL can be formed between the source / drain region 150 and the source / drain contact CA. In addition, a gate contact CB can be formed to penetrate the first cap pattern 131 in the vertical direction DR3 and to be connected to the first gate electrode G1.

[0092] Subsequently, a second etch stop layer 180 and a second interlayer insulating layer 185 can be sequentially formed on the upper surfaces of the first interlayer insulating layer 175, the first cap pattern 131 and the second cap pattern 132, and the source / drain contact CA. Subsequently, a first via V1 can be formed to penetrate the second etch stop layer 180 and the second interlayer insulating layer 185 in the vertical direction DR3 and to be connected to the source / drain contact CA. Alternatively or additionally, a second via V2 can be formed to penetrate the second etch stop layer 180 and the second interlayer insulating layer 185 in the vertical direction DR3 and to be connected to the gate contact CB. In this way, the semiconductor device shown in FIG. 1 can be manufactured. Figure 2 and Figure 3 The semiconductor device shown in FIG. 1 can be manufactured.

[0093] Referring to Figure 16 The semiconductor device according to some embodiments of the disclosure is described, focusing on the differences from the semiconductor device depicted in FIG. 1. Figures 1 to 3

[0094] Figure 16 ​is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 16 The semiconductor device of Figures 1 to 3 may include and / or can be similar in many respects to the semiconductor device described above with reference to Figures 1 to 3 may include additional features not mentioned above. Thus, for the sake of brevity, repetitive description of the semiconductor device described above with reference to Figure 16 may be omitted.

[0095] Referring to Figure 16 , at least a portion of the void 260 can overlap the uppermost surface 140a of the lower spacer 140 in the vertical direction DR3.

[0096] For example, the source / drain region 250 can include a first layer 251, a second layer 252, and a third layer 153. Alternatively or additionally, at least a portion of the void 260 can be formed on the uppermost surface 140a of the lower spacer 140. For example, the first layer 251 to the third layer 153 can be exposed through the void 260. That is, an upper surface of the void 260 can be defined by the first layer 251 to the third layer 153. As shown in Figure 16 in a cross-sectional view taken along the first horizontal direction DR1, the second layer 252 can be spaced apart from the uppermost surface 140a of the lower spacer 140 in the vertical direction DR3.

[0097] Referring to Figure 17 describing a semiconductor device according to some embodiments of the present disclosure, focus is placed on differences from the semiconductor device depicted in Figures 1 to 3 .

[0098] Figure 17 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 17 The semiconductor device of Figures 1 to 3 may include and / or can be similar in many respects to the semiconductor device described above with reference to Figures 1 to 3 may include additional features not mentioned above. Thus, for the sake of brevity, repetitive description of the semiconductor device described above with reference to Figure 17 may be omitted.

[0099] Referring to Figure 17 , a sidewall of the first gate insulating layer 321 in contact with the source / drain region 350 in the first horizontal direction DR1 can be aligned with a sidewall of the first plurality of nanosheets NW1 in the first horizontal direction DR1. Alternatively or additionally, a sidewall of the second gate insulating layer 322 in contact with the source / drain region 350 in the first horizontal direction DR1 can be aligned with a sidewall of the second plurality of nanosheets NW2 in the first horizontal direction DR1.

[0100] For example, a sidewall of the first gate insulating layer 321 disposed between the first gate electrode G31 and the first layer 351 in the first horizontal direction DR1 can be aligned with a sidewall of the first plurality of nanosheets NW1 in the first horizontal direction DR1. Alternatively or additionally, a sidewall of the second gate insulating layer 322 disposed between the second gate electrode G32 and the first layer 351 in the first horizontal direction DR1 can be aligned with a sidewall of the second plurality of nanosheets NW2 in the first horizontal direction DR1. As used herein, the term aligned can refer to having a continuous sloped profile.

[0101] Referring to Figure 18 semiconductor devices depicted in Figures 1 to 3 differ from the semiconductor devices depicted in

[0102] Figure 18 is a cross-sectional view illustrating a semiconductor device according to some embodiments of the present disclosure. Figure 18 The semiconductor device of Figures 1 to 3 may include and / or can be similar in many respects to the semiconductor devices described above with reference to Figures 1 to 3 and can include additional features not mentioned above. Thus, for the sake of brevity, repetitive description of the semiconductor devices described above with reference to Figure 18 may be omitted.

[0103] Referring to Figure 18 , the fourth layer 454 can be disposed between the first layer 151 and the second layer 152.

[0104] For example, the source / drain region 450 can include the first layer 151, the second layer 152, the third layer 153, and the fourth layer 454. In some embodiments, the fourth layer 454 can be disposed along an interface between the first layer 151 and the second layer 152. That is, the fourth layer 454 can separate the first layer 151 and the second layer 152. For example, the fourth layer 454 can be in contact with the uppermost surface 140a of the lower spacer 140. The fourth layer 454 can include silicon (Si) doped with carbon (C), silicon (Si) doped with both carbon (C) and arsenic (As), or silicon (Si) doped with both carbon (C) and phosphorus (P), etc. However, the present disclosure is not limited thereto.

[0105] Referring to Figure 19 semiconductor devices depicted in Figures 1 to 3 differ from the semiconductor devices depicted in

[0106] Figure 19 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present disclosure. Figure 19 The semiconductor device of may include and / or can be similar in many respects to the semiconductor devices described above with reference toFigures 1 to 3 The semiconductor device described, and can include additional features not mentioned above. Thus, to the extent that the above description refers to a semiconductor device, it should be read as a reference to a semiconductor device that can include additional features not mentioned above. For the sake of brevity, the above description will not repeat descriptions of a semiconductor device that are described above with reference to Figures 1 to 3 The semiconductor device described above with reference to Figure 19 Repetitive description of a semiconductor device described above with reference to

[0107] With reference to Figure 19 The fourth layer 554 can be disposed between the second layer 152 and the third layer 153.

[0108] For example, the source / drain region 550 can include the first layer 151, the second layer 152, the third layer 153, and the fourth layer 554. In some embodiments, the fourth layer 554 can be disposed along an interface between the second layer 152 and the third layer 153. That is, the fourth layer 554 can separate the second layer 152 and the third layer 153. For example, the fourth layer 554 can be exposed by the void 160. The fourth layer 554 can include silicon (Si) doped with C, silicon (Si) doped with both carbon (C) and arsenic (As), or silicon (Si) doped with both carbon (C) and phosphorus (P), etc. However, the present disclosure is not limited thereto.

[0109] With reference to Figure 20 The semiconductor device described above with reference to Figures 1 to 3 differ from the semiconductor device depicted in

[0110] Figure 20 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present disclosure. Figure 20 The semiconductor device described above with reference to Figures 1 to 3 The semiconductor device described above with reference to Figures 1 to 3 The semiconductor device described above with reference to Figure 20 Repetitive description of a semiconductor device described above with reference to

[0111] With reference to Figure 20 The sidewalls of the second layer 652 and the third layer 653 in the first horizontal direction DR1 can have a tilted profile.

[0112] For example, a pitch in the first horizontal direction DR1 between the sidewalls of the first nanowire NW1_1 and the sidewalls of the second layer 652 can be greater than a pitch in the first horizontal direction DR1 between the sidewalls of the second nanowire NW1_2 and the sidewalls of the second layer 652. Alternatively or additionally, a pitch in the first horizontal direction DR1 between the sidewalls of the second nanowire NW1_2 and the sidewalls of the second layer 652 can be greater than a pitch in the first horizontal direction DR1 between the sidewalls of the third nanowire NW1_3 and the sidewalls of the second layer 652.

[0113] As another example, a pitch in the first horizontal direction DR1 between sidewalls of the fourth nanowire NW2_1 and sidewalls of the second layer 652 can be greater than a pitch in the first horizontal direction DR1 between sidewalls of the fifth nanowire NW2_2 and sidewalls of the second layer 652. Alternatively or additionally, a pitch in the first horizontal direction DR1 between sidewalls of the fifth nanowire NW2_2 and sidewalls of the second layer 652 can be greater than a pitch in the first horizontal direction DR1 between sidewalls of the sixth nanowire NW2_3 and sidewalls of the second layer 652.

[0114] In some embodiments, a thickness in the first horizontal direction DR1 of the first layer 651 in contact with sidewalls of the first nanowire NW1_1 can be greater than a thickness in the first horizontal direction DR1 of the first layer 651 in contact with sidewalls of the second nanowire NW1_2. Alternatively or additionally, a thickness in the first horizontal direction DR1 of the first layer 651 in contact with sidewalls of the second nanowire NW1_2 can be greater than a thickness in the first horizontal direction DR1 of the first layer 651 in contact with sidewalls of the third nanowire NW1_3.

[0115] As another example, a thickness in the first horizontal direction DR1 of the first layer 651 in contact with sidewalls of the fourth nanowire NW2_1 can be greater than a thickness in the first horizontal direction DR1 of the first layer 651 in contact with sidewalls of the fifth nanowire NW2_2. Alternatively or additionally, a thickness in the first horizontal direction DR1 of the first layer 651 in contact with sidewalls of the fifth nanowire NW2_2 can be greater than a thickness in the first horizontal direction DR1 of the first layer 651 in contact with sidewalls of the sixth nanowire NW2_3.

[0116] Referring to Figure 21 semiconductor devices according to some embodiments of the present disclosure, focusing on differences from the semiconductor devices depicted in Figures 1 to 3

[0117] Figure 21 is a cross-sectional view illustrating a semiconductor device according to some other embodiments of the present disclosure. Figure 21 The semiconductor device of Figures 1 to 3 may include and / or can be similar in many respects to the semiconductor devices described above with reference to Figures 1 to 3 Figure 21 repetitive description of the semiconductor devices of

[0118] Referring to Figure 21 , the lower spacer 740 can be formed as a bilayer.

[0119] ​​For example, the lower spacers 740 can include a first lower spacer 741 and a second lower spacer 742. In some embodiments, the first lower spacer 741 can be disposed along a bottom surface of the trench T. For example, the first lower spacer 741 can be arranged in a liner shape. As shown in FIG. 7B, in a cross-sectional view taken along the first horizontal direction DR1, the first lower spacer 741 can have a semi-circular shape. Figure 21 As shown in FIG. 7B, in a cross-sectional view taken along the first horizontal direction DR1, the first lower spacer 741 can have a semi-circular shape. The second lower spacer 742 can be disposed between the first lower spacer 741 and the void 160. The second lower spacer 742 can be exposed through the void 160. For example, the second lower spacer 742 can be arranged in a liner shape. As shown in FIG. 7B, in a cross-sectional view taken along the first horizontal direction DR1, the second lower spacer 742 can have a semi-circular shape. Figure 21 As shown in FIG. 7B, in a cross-sectional view taken along the first horizontal direction DR1, the first lower spacer 741 can have a semi-circular shape. The second lower spacer 742 can be disposed between the first lower spacer 741 and the void 160. The second lower spacer 742 can be exposed through the void 160. For example, the second lower spacer 742 can be arranged in a liner shape. As shown in FIG. 7B, in a cross-sectional view taken along the first horizontal direction DR1, the second lower spacer 742 can have a semi-circular shape.

[0120] In some embodiments, uppermost surfaces 740a of the first lower spacer 741 and the second lower spacer 742 can be formed on substantially similar and / or the same planes. For example, the uppermost surfaces 740a of the first lower spacer 741 and the second lower spacer 742 can be in contact with the first layer 151. Each of the first lower spacer 741 and the second lower spacer 742 can include an insulating material. For example, the first lower spacer 741 and the second lower spacer 742 can include different materials. As another example, the first lower spacer 741 and the second lower spacer 742 can include silicon nitride (SiN), silicon oxynitride (SiON), silicon oxide (SiO2), silicon carbon nitride (SiCN), silicon oxygen carbon nitride (SiOCN), silicon boron nitride (SiBN), silicon oxygen boron nitride (SiOBN), silicon boron carbon (SiBC), silicon boron carbon nitride (SiBCN), silicon oxygen carbon (SiOC), a combination thereof, or the like. However, the present disclosure is not limited thereto.

[0121] Although embodiments according to the technical concept of the present disclosure have been described with reference to the accompanying drawings, the present disclosure is not limited to these embodiments and can be manufactured in various different forms. It will be understood by those skilled in the art that the technical concept of the present disclosure and essential features can be implemented in other specific forms without changing them. Therefore, the embodiments described above should be understood in all aspects to be illustrative rather than restrictive.

Claims

1. A semiconductor device comprising: a substrate; an active pattern extending in a first horizontal direction on the substrate; at least one first nanosheet stacked on the active pattern; at least one second nanosheet stacked on the active pattern, the at least one second nanosheet being spaced apart from the at least one first nanosheet in the first horizontal direction; a trench forming the active pattern between the at least one first nanosheet and the at least one second nanosheet, the trench extending into the active pattern; a lower spacer disposed along a bottom surface of the trench, an uppermost surface of the lower spacer being formed at a first level lower than a second level of an uppermost surface of the active pattern; a source / drain region on the lower spacer within the trench; and a void formed within the trench between the lower spacer and the source / drain region, an uppermost surface of the void being formed at a third level higher than the second level of the uppermost surface of the active pattern. the source / drain region includes:

2. The semiconductor device according to claim 1, wherein a first layer in contact with a sidewall of each of the at least one first nanosheet and the at least one second nanosheet in the first horizontal direction and the uppermost surface of the lower spacer; a second layer on the first layer, at least a portion of the second layer being exposed through the void, and a third layer on the second layer, at least a portion of the third layer being exposed through the void. the source / drain region further includes a fourth layer disposed between the first layer and the second layer.

3. The semiconductor device according to claim 2, wherein the source / drain region further includes a fourth layer arranged between the second layer and the third layer.

4. The semiconductor device according to claim 2, wherein 5. The semiconductor device of claim 1, further comprising: a gate electrode on the active pattern and extending in a second horizontal direction different from the first horizontal direction, the gate electrode at least partially surrounding the at least one first nanosheet; and a gate insulating layer disposed between the gate electrode and the source / drain region, the gate insulating layer being in contact with the source / drain region. a sidewall of the gate insulating layer in the first horizontal direction that is in contact with the source / drain region is aligned with a sidewall of the at least one first nanosheet in the first horizontal direction. at least a portion of the source / drain region is in contact with the active pattern on the uppermost surface of the lower spacer.

6. The semiconductor device according to claim 5, wherein the at least one first nanosheet includes a plurality of first nanosheets spaced apart from each other in a vertical direction, and 7. The semiconductor device according to claim 1, wherein wherein the third level of the uppermost surface of the void is lower than a fourth level of a lower surface of a lowermost nanosheet of the plurality of first nanosheets.

8. The semiconductor device according to claim 1, wherein a lowermost surface of the void is formed at a fourth level lower than the first level of the uppermost surface of the lower spacer. an upper surface of the void is convexly formed toward the source / drain region.

9. The semiconductor device according to claim 1, wherein the at least one first nanosheet includes a plurality of first nanosheets spaced apart from each other in a vertical direction, and 10. The semiconductor device according to claim 1, wherein wherein at least a portion of the source / drain region is between adjacent nanosheets of the plurality of first nanosheets.

11. The semiconductor device according to claim 1, wherein the lower spacer includes: a first lower spacer in contact with the active pattern, and 12. The semiconductor device according to any one of Claims 1 to 11, wherein a second lower spacer between the first lower spacer and the void, the second lower spacer including a material different from a material of the first lower spacer.

13. A semiconductor device comprising: a substrate; an active pattern on the substrate and extending in a first horizontal direction; ​ ​ a first gate electrode extending over the active pattern in a second horizontal direction different from the first horizontal direction; a second gate electrode extending over the active pattern in the second horizontal direction, the second gate electrode being spaced apart from the first gate electrode in the first horizontal direction; a gate insulating layer provided on a sidewall of the first gate electrode in the first horizontal direction; a trench formed over the active pattern between the first gate electrode and the second gate electrode, the trench extending into the active pattern; a lower spacer provided along a bottom surface of the trench, an uppermost surface of the lower spacer being formed at a first level lower than a second level of an uppermost surface of the active pattern; a source / drain region on the lower spacer within the trench; and a gap formed within the trench between the lower spacer and the source / drain region, an uppermost surface of the gap being formed at a third level higher than the second level of the uppermost surface of the active pattern, wherein the source / drain region includes: a first layer in contact with the sidewall of the gate insulating layer in the first horizontal direction and the uppermost surface of the lower spacer; a second layer on the first layer, at least a portion of the second layer being exposed through the gap; and a third layer on the second layer, at least a portion of the third layer being exposed through the gap. The third layer is not in contact with the lower spacer.

14. The semiconductor device according to claim 13, wherein A ratio of a volume of the gap to a combined volume of the gap and the source / drain region is in a range of 2% to 5%.

15. The semiconductor device according to claim 13, wherein A lowermost surface of the gap is formed at a fourth level lower than the first level of the uppermost surface of the lower spacer.

16. The semiconductor device according to claim 13, wherein 17. The semiconductor device according to claim 13, further comprising: a first plurality of nanosheets stacked on the active pattern and spaced apart from each other in a vertical direction, the first plurality of nanosheets being at least partially surrounded by the first gate electrode, the first plurality of nanosheets being in contact with the first layer; and a second plurality of nanosheets stacked on the active pattern and spaced apart from each other in the vertical direction, the second plurality of nanosheets being at least partially surrounded by the second gate electrode, the second plurality of nanosheets being spaced apart from the first plurality of nanosheets in the first horizontal direction, the second plurality of nanosheets being in contact with the first layer. The first plurality of nanosheets includes a first nanosheet provided on an upper surface of the active pattern and a second nanosheet provided on an upper surface of the first nanosheet, and 18. The semiconductor device according to claim 17, wherein wherein a first pitch in the first horizontal direction between a sidewall of the first nanosheet in the first horizontal direction and the second layer is greater than a second pitch in the first horizontal direction between a sidewall of the second nanosheet in the first horizontal direction and the second layer. At least a portion of the gap at least partially overlaps the uppermost surface of the lower spacer in the vertical direction.

19. The semiconductor device according to any one of Claims 13 to 18, wherein 20. A semiconductor device comprising: a substrate; an active pattern on the substrate and extending in a first horizontal direction; a first plurality of nanosheets stacked on the active pattern and spaced apart from each other in a vertical direction; a second plurality of nanosheets stacked on the active pattern and spaced apart from each other in the vertical direction, the second plurality of nanosheets being spaced apart from the first plurality of nanosheets in the first horizontal direction. ​ a first gate electrode on the active pattern and extending in a second horizontal direction different from the first horizontal direction, the first gate electrode at least partially surrounding the first plurality of nanosheets; a second gate electrode on the active pattern and extending in the second horizontal direction, the second gate electrode spaced apart from the first gate electrode in the first horizontal direction, the second gate electrode at least partially surrounding the second plurality of nanosheets; a first gate insulating layer disposed on a sidewall of the first gate electrode in the first horizontal direction; a second gate insulating layer disposed on a sidewall of the second gate electrode in the first horizontal direction; a trench formed on the active pattern between the first plurality of nanosheets and the second plurality of nanosheets, the trench extending into the active pattern; a lower spacer disposed along a bottom surface of the trench, an uppermost surface of the lower spacer being formed at a first level lower than a second level of an uppermost surface of the active pattern; a source / drain region on the lower spacer within the trench; and a void formed within the trench between the lower spacer and the source / drain region, an uppermost surface of the void being formed at a third level higher than the second level of the uppermost surface of the active pattern, a lowermost surface of the void being formed at a fourth level lower than the first level of the uppermost surface of the lower spacer, the upper surface of the void being convexly formed toward the source / drain region, wherein the source / drain region includes: a first layer in contact with the sidewall of each of the first gate insulating layer and the second gate insulating layer in the first horizontal direction and the uppermost surface of the lower spacer; a second layer on the first layer, at least a portion of the second layer being exposed through the void; and a third layer on the second layer, at least a portion of the third layer being exposed through the void. ​

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