Methods for fabricating CMOS devices based on doping two-dimensional semiconductor materials and CMOS devices

Abstract

The application discloses a kind of based on doping preparation two-dimensional semiconductor material CMOS device and method and CMOS device, in which preparation method includes preparing the source and drain of nMOSFET and pMOSFET on two-dimensional semiconductor surface, then sequentially define two-dimensional semiconductor channel region, define p-doped region and dope, prepare hard mask layer, define n-doped region and dope on the surface of hard mask layer, prepare gate dielectric layer, prepare gate and gate interconnection.In the application, by providing a kind of preparation two-dimensional semiconductor material CMOS device method, only involves doping two-dimensional semiconductor material, not involving the transfer of two-dimensional semiconductor, process complexity is low;By doping two-dimensional semiconductor, and cooperate with the selection of source electrode, drain and gate material, the CMOS device obtained, transfer characteristic curve symmetry is good, off-state current is low, in 1.5-5V range all show correct inverting function, voltage gain is high;At the same time, the current of device is small, has significant low power consumption advantage.

Description

Technical Field

[0001] This invention relates to the field of semiconductor device fabrication technology, and in particular to a method for fabricating two-dimensional semiconductor CMOS devices based on doping, and the CMOS devices themselves. Background Technology

[0002] In recent years, two-dimensional semiconductor materials have been considered important candidates for the 1 nm node in integrated circuits due to their atomic-level thickness and excellent electrical properties. With the gradual improvement in the performance of discrete devices made of two-dimensional semiconductor materials, research is increasingly shifting from discrete devices to integrated circuits (2D ICs) made of two-dimensional semiconductor materials. CMOS is the foundation of large-scale integrated circuits, and its circuit structure consists of nFETs and pFETs, offering the advantage of low power consumption and serving as the basis for realizing large-scale integrated circuits. Currently, most reported two-dimensional semiconductor CMOS (2D CMOS) inverters use different two-dimensional semiconductor materials for their p- and n-channels, involving transfer operations and increasing the complexity of the manufacturing process.

[0003] In recent years, most research on 2D CMOS has involved issues such as incompatibility with silicon-based CMOS processes. Controlling the polarity transition of two-dimensional semiconductor materials through silicon-based CMOS-compatible processes to achieve 2D CMOS is a feasible approach. However, silicon-based CMOS primarily uses ion implantation for controlled doping, a method that easily damages atomically thin channels and is incompatible with two-dimensional semiconductor material processes. Therefore, the biggest problem currently facing research in the 2D IC field is the lack of practical processes for two-dimensional semiconductor CMOS, thus hindering the development of 2D ICs.

[0004] Therefore, developing a transfer-free method for fabricating CMOS devices based on two-dimensional semiconductor materials is a major challenge for realizing large-scale integrated circuit applications using two-dimensional semiconductor materials, and it is also a technical problem that needs to be solved in this field. Summary of the Invention

[0005] The technical problem to be solved by the present invention is to provide a method for preparing CMOS devices based on doping of two-dimensional semiconductor materials and the CMOS device itself. The preparation method involves only doping of the two-dimensional semiconductor material and does not involve the transfer of the two-dimensional semiconductor. The process is less complex, the prepared CMOS device has good symmetry of transfer characteristic curve, low off-state current, and exhibits correct inversion function in the range of 1.5-5V with high voltage gain. At the same time, the device has low current and has significant low power consumption advantages.

[0006] To address the aforementioned technical problems, a first aspect of the present invention provides a method for fabricating a CMOS device based on doping of two-dimensional semiconductor materials, comprising:

[0007] S1. The source and drain of nMOSFET and pMOSFET are fabricated on the surface of a two-dimensional semiconductor, respectively. The source and drain of nMOSFET are made of metal with a work function of 3.5-4.6eV, and the source and drain of pMOSFET are made of metal with a work function of 5-5.7eV.

[0008] S2. Etching process defines the two-dimensional semiconductor channel region;

[0009] S3. Perform p-doping treatment on the exposed two-dimensional semiconductor channel region;

[0010] S4. Prepare a hard mask layer that covers the entire CMOS device area;

[0011] S5. Define an n-doped region on the surface of the hard mask layer to expose the two-dimensional semiconductor channel region between the source and drain of the nMOSFET and perform n-doping treatment on it.

[0012] S6. Prepare the gate dielectric layer;

[0013] S7. Fabricate the gates of nMOSFET and pMOSFET on the surface of the gate dielectric layer;

[0014] S8. The through-hole etching process exposes the drain of the nMOSFET and the drain of the pMOSFET. The deposition process interconnects the gate of the nMOSFET and the gate of the pMOSFET, as well as the drain of the nMOSFET and the drain of the pMOSFET, with interconnect metal.

[0015] Preferably, the process for preparing the source and drain in step S1 is a metal deposition process;

[0016] The source and drain materials of nMOSFET are selected from one or more metals selected from Mg, Al, Y, In, Sb, Ti, and Bi; the source and drain materials of pMOSFET are selected from one or more metals selected from Au, Pt, and Pd.

[0017] Two-dimensional semiconductor materials can have 1 to 30 layers.

[0018] Preferably, the etching process in step S2 is a plasma etching process.

[0019] Preferably, the p-doping process in step S3 is a solution method, and the doping solution is selected from hydrochloric acid, ammonium tungstate, ammonium metatungstate or tungsten peroxide solution.

[0020] Preferably, the hard mask layer in step S4 includes a first dielectric layer and a second dielectric layer, wherein the material of the first dielectric layer is selected from Al2O3, SiO2, or ZrO2, and the material of the second dielectric layer is selected from HfO2 or Si3N4. The thickness of the first dielectric layer is 1nm-30nm, and the thickness of the second dielectric layer is 1nm-30nm. The hard mask layer is prepared by atomic layer deposition, in which the first dielectric layer and the second dielectric layer are deposited sequentially.

[0021] Preferably, in step S5, the hard mask layer is removed from the defined n-doped region using dry etching and / or wet etching processes.

[0022] The n-doping process is a solution method, using tetramethylammonium hydroxide solution as the doping solution.

[0023] Preferably, the process for preparing the gate dielectric layer in step S6 is atomic layer deposition, the gate dielectric layer covers the hard mask layer and the n-doped region, the material of the gate dielectric layer is a high-K dielectric material with a dielectric constant greater than 5, and the thickness of the gate dielectric layer is 5-30 nm.

[0024] Preferably, the process for preparing the gate in step S7 is a metal deposition process.

[0025] Preferably, the deposition process in step S8 is a metal deposition process, and the material used for the interconnect metal has a conductivity greater than 3 × 10⁻⁶. 7 Metallic materials with S / m.

[0026] To address the aforementioned technical problems, a second aspect of the present invention is to provide a two-dimensional semiconductor material CMOS device prepared by the aforementioned method for preparing two-dimensional semiconductor material CMOS devices based on doping.

[0027] This invention provides a method for preparing CMOS devices based on doping of two-dimensional semiconductor materials. This method involves only the doping of the two-dimensional semiconductor material and does not involve the transfer of the two-dimensional semiconductor, resulting in low process complexity. By doping the two-dimensional semiconductor material and selecting appropriate source, drain, and gate materials (nMOSFETs use metals with a work function of 3.5-4.6 eV as source and drain, and pMOSFETs use metals with a work function of 5-5.7 eV as source and drain), the resulting CMOS device exhibits good symmetry in its transfer characteristic curve, low off-state current, correct inversion function within the 1.5-5V range, and high voltage gain. Simultaneously, the device has low current consumption, demonstrating significant low-power advantages. Attached Figure Description

[0028] To more clearly illustrate the technical solution of the present invention, the accompanying drawings used in the present invention will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0029] Figure 1 This is a flowchart of the fabrication process of the CMOS device of the present invention, including a cross-sectional view and a corresponding top view;

[0030] Figure 2 These are the PMOS and NMOS transfer characteristic curves of the CMOS device A of the present invention;

[0031] Figure 3 This is the voltage transfer characteristic curve of CMOS device A of the present invention;

[0032] Figure 4 This is the voltage gain curve of CMOS device A of the present invention;

[0033] Figure 5 This is the current curve of CMOS device A of the present invention;

[0034] Figure 6 These are the PMOS and NMOS transfer characteristic curves of the CMOS device B of the present invention;

[0035] Figure 7 This is the voltage transfer characteristic curve of the CMOS device B of the present invention;

[0036] Figure 8 This is the voltage gain curve of the CMOS device B of the present invention;

[0037] Wherein, 1-substrate; 2-two-dimensional semiconductor; 3-source of nMOSFET; 4-drain of nMOSFET; 5-source of pMOSFET; 6-drain of pMOSFET; 7-p-type doped two-dimensional semiconductor material; 8-hard mask layer; 9-n-type doped two-dimensional semiconductor material; 10-gate dielectric layer; 11-gate of nMOSFET; 12-gate of pMOSFET; 13-interconnect metal. Detailed Implementation

[0038] The technical solutions of the present invention will now be clearly and completely described with reference to the accompanying drawings. Obviously, the described embodiments are only some, not all, of the embodiments of the present invention. All other embodiments obtained by those skilled in the art based on the embodiments of the present invention without creative effort are within the scope of protection of the present invention.

[0039] It should be noted that the shapes and sizes of the regions and layers shown in the accompanying drawings are merely illustrative and are not drawn to scale. Some details may be enlarged or omitted for clarity. Those skilled in the art can design regions and layers with different shapes, sizes, and relative positions according to actual needs.

[0040] Example 1: Fabrication process of CMOS devices based on two-dimensional semiconductor materials.

[0041] refer to Figure 1 This diagram illustrates a fabrication process for a CMOS device based on a two-dimensional semiconductor material according to the present invention, wherein: 1 is a substrate; 2 is a two-dimensional semiconductor; 3 is the source of an nMOSFET; 4 is the drain of an nMOSFET; 5 is the source of a pMOSFET; 6 is the drain of a pMOSFET; 7 is a p-type doped two-dimensional semiconductor material; 8 is a hard mask layer; 9 is an n-type doped two-dimensional semiconductor material; 10 is a gate dielectric layer; 11 is the gate of an nMOSFET; 12 is the gate of a pMOSFET; and 13 is an interconnect metal.

[0042] The preparation process specifically includes:

[0043] S1. The source and drain of nMOSFET and pMOSFET are fabricated on the surface of a two-dimensional semiconductor, respectively. The source and drain of nMOSFET are made of metal with a work function of 3.5-4.6eV, and the source and drain of pMOSFET are made of metal with a work function of 5-5.7eV.

[0044] S2. Etching process defines the two-dimensional semiconductor channel region;

[0045] S3. The exposed two-dimensional semiconductor channel region is p-doped to form a p-type doped two-dimensional semiconductor material.

[0046] S4. Prepare a hard mask layer that covers the entire CMOS device area;

[0047] S5. Define an n-doped region on the surface of the hard mask layer to expose the two-dimensional semiconductor channel region between the source and drain of the nMOSFET, and perform n-doping treatment on it to form an n-type doped two-dimensional semiconductor material.

[0048] S6. Prepare the gate dielectric layer;

[0049] S7. Fabricate the gates of nMOSFET and pMOSFET on the surface of the gate dielectric layer;

[0050] S8. The through-hole etching process exposes the drain of the nMOSFET and the drain of the pMOSFET. The deposition process interconnects the gate of the nMOSFET and the gate of the pMOSFET, as well as the drain of the nMOSFET and the drain of the pMOSFET, with interconnect metal.

[0051] In this invention, the method for fabricating CMOS devices using two-dimensional semiconductor materials involves only doping the two-dimensional semiconductor material and does not involve the transfer of the two-dimensional semiconductor, resulting in low process complexity. By doping the two-dimensional semiconductor and selecting appropriate source, drain, and gate materials (nMOSFETs use metals with a work function of 3.5-4.6 eV as source and drain, and pMOSFETs use metals with a work function of 5-5.7 eV as source and drain), the resulting CMOS devices exhibit good symmetry in their transfer characteristic curves, low off-state current, and correct inversion function within the 1.5-5V range, along with high voltage gain. Simultaneously, the devices have low current consumption, demonstrating significant low-power advantages.

[0052] In this invention, two-dimensional semiconductor material refers to two-dimensional semiconductor grown on a substrate. The substrate can be, for example, Al2O3, SiO2, mica, etc., and the two-dimensional semiconductor material can be, for example, MoTe2, WSe2, PdSe2, PtSe2, etc. Growing two-dimensional semiconductor material on a substrate is a relatively mature process, which will not be elaborated here. After growing two-dimensional semiconductor material on the surface of the substrate material, it can be directly applied to this invention. The range of two-dimensional semiconductor material layers is 1-30 layers.

[0053] In a more specific embodiment, the process for fabricating the source and drain in step S1 is a metal deposition process; the materials for the source and drain of the nMOSFET are selected from one or more metals chosen from Mg, Al, Y, In, Sb, Ti, and Bi; the materials for the source and drain of the pMOSFET are selected from one or more metals chosen from Au, Pt, and Pd. Understandably, the metal deposition process in this invention mainly involves depositing metal using physical vapor deposition, electron beam deposition, thermal evaporation, magnetron sputtering, etc., ultimately resulting in source and drain thicknesses of 15-50 nm. This thickness ensures effective carrier transport. It should be noted that a photolithography process is required before the metal deposition process. After defining the source and drain regions using photolithography, the metal to be deposited is deposited at the target locations, and finally, the photoresist is removed. Photolithography processes include, for example, spin-coating photoresist, then exposing a selected area, and finally developing. Furthermore, this application does not impose any restrictive requirements on the fabrication order of the source and drain of nMOSFETs or pMOSFETs. Both photolithography and metal deposition processes are conventional processes in the prior art and will not be elaborated upon here.

[0054] In a more specific embodiment, the etching process in step S2 is a plasma etching process. In this invention, the two-dimensional semiconductor channel region is defined using plasma etching. Specifically, the two-dimensional semiconductor channel is first patterned using photolithography, and then the two-dimensional semiconductor material other than the channel is removed using plasma etching. The etching time depends on the number of layers of the two-dimensional semiconductor material. Examples of plasma etching techniques include capacitively coupled plasma etching, inductively coupled plasma etching, and reactive ion etching. These are existing technologies and will not be elaborated further.

[0055] In a more specific embodiment, the p-doping process in step S3 is a solution method, and the doping solution is selected from hydrochloric acid, ammonium tungstate, ammonium metatungstate, or tungsten peroxide solution. In this invention, the solution method is used for doping the two-dimensional semiconductor material. This process is less likely to damage the two-dimensional semiconductor material, provides good doping uniformity, and is simple to operate. The device to be doped is simply immersed in the doping solution at room temperature. The immersion time depends on the doping concentration and the thickness of the two-dimensional semiconductor material, preferably 1-60 minutes. It should be noted that the selected p-doping solution is more likely to dope from a direction perpendicular to the device, that is, it is easier to dope from the top surface of the two-dimensional semiconductor than from the side surface.

[0056] In a more specific embodiment, the hard mask layer in step S4 includes a first dielectric layer and a second dielectric layer, wherein the material of the first dielectric layer is selected from Al2O3, SiO2, or ZrO2, and the material of the second dielectric layer is selected from HfO2 or Si3N4. The thickness of the first dielectric layer is 1nm-30nm, and the thickness of the second dielectric layer is 1nm-30nm. The hard mask layer is prepared by atomic layer deposition, in which the first dielectric layer and the second dielectric layer are deposited sequentially. In this specific embodiment, the hard mask layer serves to protect the two-dimensional semiconductor material in the non-target doping region. Using two dielectric layers makes it easier to control the etching depth of the hard mask layer when defining the n-type target doping region. For example, only part of the first dielectric layer can be etched, leaving a certain thickness, to avoid damaging the two-dimensional semiconductor material in the region to be doped during the etching process. The principle for selecting the materials of the first and second dielectric layers is that the second dielectric layer is not easily etched in the doping solution, while the first dielectric layer is easily etched by the doping solution. After the first dielectric layer in the target region is etched by the doping solution, the doping solution begins to dope the two-dimensional semiconductor material, while the second dielectric layer in the non-target doping region is not etched, thus protecting the first dielectric layer and preventing the two-dimensional semiconductor material in the non-target doping region from being doped.

[0057] In a more specific implementation, step S5 defines the n-doped region as removing the hard mask layer using dry etching and / or wet etching processes; the n-doping process is a solution method, using tetramethylammonium hydroxide solution as the doping solution. Specifically, for example, a photolithography process is used. First, photoresist is spin-coated onto the surface of the hard mask layer. The target doped region (n-doped region) is then exposed and developed to remove the photoresist. Next, a dry etching process (e.g., inductively coupled plasma etching) is used to remove all of the second dielectric layer and part of the first dielectric layer of the target doped region (to prevent damage to the two-dimensional semiconductor material from dry etching; the thickness of the retained first dielectric layer is not required, for example, 0.1nm, 0.2nm, 0.5nm, 1nm, as long as it protects the two-dimensional semiconductor material of the target doped region). After that, the non-target doped regions are removed. The photoresist in the target doped region is then removed by wet etching to expose the two-dimensional semiconductor material in the target doped region. The etching solution used for wet etching is, for example, tetramethylammonium hydroxide solution or hydrochloric acid, which does not damage the two-dimensional semiconductor material. Moreover, the etching rate of these etching solutions on the second dielectric layer is lower than that on the first dielectric layer, so as not to damage the second dielectric layer in the non-target doped region during the etching process. Among them, tetramethylammonium hydroxide solution is preferred as the etching solution. After the etching is completed, n-doping can be performed directly (solution doping can be achieved by immersing in tetramethylammonium hydroxide solution for 5 seconds to 60 minutes).

[0058] In a more specific embodiment, the process for preparing the gate dielectric layer in step S6 is atomic layer deposition. The gate dielectric layer covers the hard mask layer and the n-doped region. The material of the gate dielectric layer is a high-k dielectric material with a dielectric constant greater than 5, and the thickness of the gate dielectric layer is 5-30 nm. In this invention, the material of the gate dielectric layer is preferably HfO2, Al2O3, etc., and the thickness is preferably 15-60 nm.

[0059] In a more specific embodiment, the gate fabrication process in step S7 is a metal deposition process. In this specific embodiment, the process is the same as in step S1, and the gate thickness of the fabricated nMOSFET is 15-60 nm, and the gate thickness of the pMOSFET is 15-60 nm. It should be noted that the gate materials of the nMOSFET and the pMOSFET can be the same or different. When the materials are the same, they can be fabricated simultaneously; when the materials are different, they can be fabricated separately. The gate material can be, for example, metals such as gold, platinum, or palladium.

[0060] In a more specific embodiment, the deposition process in step S8 is a metal deposition process, and the material used for the interconnect metal has a conductivity greater than 3 × 10⁻⁶. 7Metal materials with a work function of S / m. In this specific embodiment, the metal deposition process is the same as step S1, and the interconnect metal thickness is 15-60 nm; in this invention, the work function of the interconnect metal is not required, but the conductivity must be greater than 3 × 10⁻⁶. 7 Metal materials with a S / m (20℃), such as Au, Cu, and Al, are used. It should be noted that in step S8, before interconnecting the drains of the nMOSFET and pMOSFET, the hard mask layer and gate dielectric layer covering the drain need to be removed using a via etching process. Then, the drains of the nMOSFET and pMOSFET are interconnected using a metal deposition process. Alternatively, the process sequence in S8 can be varied: first, the drains of the nMOSFET and pMOSFET can be exposed using a via etching process, and then the gates of the nMOSFET and pMOSFET, as well as the drains of the nMOSFET and pMOSFET, can be interconnected simultaneously using a metal deposition process. Another variation is to first interconnect the gates of the nMOSFET and pMOSFET simultaneously using a metal deposition process, then expose the drains of the nMOSFET and pMOSFET using a via etching process, and finally interconnect the drains of the nMOSFET and pMOSFET using a metal deposition process.

[0061] Example 2: Test Example.

[0062] The homogeneous top-gate CMOS device based on two-dimensional semiconductor materials in this embodiment is obtained using the fabrication process described in Embodiment 1.

[0063] CMOS Device A: The substrate is Al2O3; the two-dimensional semiconductor material is a single layer of WSe2; the source and drain of the nMOSFET are 20nm thick In, and the gate is 20nm thick Au; the source and drain of the pMOSFET are 20nm thick Pt, and the gate is 20nm thick Au; the hard mask layer is 5nm Al2O3 and 5nm HfO2; the gate dielectric layer is 20nm thick hafnium dioxide (HfO2); the interconnect metals are all 20nm thick Au. The p-doping solution uses a 100mM ammonium tungstate solution for 10 minutes, and the n-doping solution uses a 1wt% tetramethylammonium hydroxide solution for 2 minutes. Figure 2 The transfer characteristic curves of the pull-up and pull-down transistors of CMOS device A are shown. Figure 3 The voltage transfer characteristic curve of CMOS device A is shown; Figure 4 The voltage gain curve of CMOS device A is shown; Figure 5The current curve of CMOS device A is shown. It can be seen that the transfer characteristic curve has good symmetry, low off-state current, and exhibits correct inversion function in the range of 1.5-5V, with high voltage gain; at the same time, the device has low current and has significant low power consumption advantages.

[0064] CMOS Device B: The substrate is Al2O3; the two-dimensional semiconductor material is two layers of WSe2; the source and drain of the nMOSFET are 20nm thick In, and the gate is 30nm thick Au; the source and drain of the pMOSFET are 20nm thick Pd, and the gate is 30nm thick Au; the hard mask layer is 4nm Al2O3 and 3nm HfO2; the gate dielectric layer is 15nm thick hafnium dioxide (HfO2); the interconnect metals are all 20nm thick Au. The p-doping solution uses a 10mM ammonium tungstate solution for 10 min, and the n-doping solution uses a 2wt% tetramethylammonium hydroxide solution for 1 min. Figure 6 The transfer characteristic curves of the pull-up and pull-down transistors of CMOS device B are shown. Figure 7 The voltage transfer characteristic curve of CMOS device B is shown; Figure 8 The voltage gain curve of CMOS device B is shown. It can be seen that the transfer characteristic curve has good symmetry, low off-state current, and exhibits correct inversion function in the range of 1.5-5V. It also has high voltage gain and significant low power consumption advantages.

[0065] The above description is only a preferred embodiment of the present invention and is not intended to limit the present invention. Any modifications, equivalent substitutions, improvements, etc., made within the spirit and principles of the present invention should be included within the scope of protection of the present invention.

Claims

1. A method for preparing a two-dimensional semiconductor material CMOS device based on doping, characterized in that, The method comprises the following steps: S1, preparing the source and drain of nMOSFET and pMOSFET on a two-dimensional semiconductor surface, wherein the source and drain of nMOSFET are made of a metal with a work function value of 3.5-4.6 eV, and the source and drain of pMOSFET are made of a metal with a work function value of 5-5.7 eV; S2, etching process to define the two-dimensional semiconductor channel region; S3, p-doping treatment is performed on the exposed two-dimensional semiconductor channel region; S4, a hard mask layer is prepared, which covers the entire CMOS device region, wherein the hard mask layer comprises a first dielectric layer and a second dielectric layer; S5, n-doped region is defined on the surface of the hard mask layer, the second dielectric layer and part of the first dielectric layer in the target doped region are removed by dry etching process, and then the remaining first dielectric layer in the target doped region is removed by wet etching, so that the two-dimensional semiconductor channel region between the source and drain of nMOSFET is exposed, and n-doping is directly performed by using the wet etching solution as the doping solution; S6, preparing a gate dielectric layer; S7, preparing the gate of nMOSFET and pMOSFET on the surface of the gate dielectric layer; S8, via etching process exposes the drain of nMOSFET and the drain of pMOSFET, and deposition process is used to interconnect the gate of nMOSFET and the gate of pMOSFET, and the drain of nMOSFET and the drain of pMOSFET with interconnection metal.

2. The method of claim 1, wherein, The process for preparing the source and drain in step S1 is metal deposition process; The material of the source and drain of nMOSFET is selected from one or more metals in Mg, Al, Y, In, Sb, Ti and Bi, and the material of the source and drain of pMOSFET is selected from one or more metals in Au, Pt and Pd; The number of layers of the two-dimensional semiconductor material is 1-30 layers.

3. The method of claim 1, wherein, The etching process in step S2 is plasma etching process.

4. The method of claim 1, wherein, The p-doping process in step S3 is solution method, and the doping solution is selected from hydrochloric acid, ammonium tungstate, ammonium metatungstate or tungsten peroxide solution.

5. The method of claim 1, wherein, The material of the first dielectric layer in step S4 is selected from one of Al2O3, SiO2 or ZrO2, the material of the second dielectric layer is selected from HfO2 or Si3N4, the thickness of the first dielectric layer is 1-30 nm, and the thickness of the second dielectric layer is 1-30 nm; the preparation process of the hard mask layer is atomic layer deposition process, and the first dielectric layer and the second dielectric layer are deposited in sequence.

6. The method of claim 1, wherein, The doping solution in step S5 is tetramethylammonium hydroxide solution.

7. The method of claim 1, wherein, The process for preparing the gate dielectric layer in step S6 is atomic layer deposition process, the gate dielectric layer covers the hard mask layer and the n-doped region, the material of the gate dielectric layer is high-K dielectric material with a dielectric constant greater than 5, and the thickness of the gate dielectric layer is 5-30 nm.

8. The method of claim 1, wherein, The process for preparing the gate in step S7 is metal deposition process.

9. The method of claim 1, wherein, The deposition process in step S8 is a metal deposition process, and the material used for the interconnection metal is a metal material with an electrical conductivity greater than 3 x 10 7 S / m. The metal material used for the interconnection metal is a metal material with an electrical conductivity greater than 3 x 10 7 S / m.

10. A two-dimensional semiconductor CMOS device prepared by the preparation method of the CMOS device based on doped two-dimensional semiconductor material according to any one of claims 1-9.

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