Semiconductor device and manufacturing method thereof

Abstract

A semiconductor device includes: a first active pattern and a second active pattern extending in a first direction, the second active pattern being spaced apart from the first active pattern in a vertical direction; a first gate structure on the first active pattern and the second active pattern and extending in a second direction; a first cutting pattern spaced apart from the first active pattern and the second active pattern in the second direction and cutting the first gate structure; and a via pattern spaced apart from the second active pattern. The second active pattern includes: a first portion having a first width; and a second portion having a second width in the second direction, the second width being smaller than the first width. The first cut pattern includes: a first line portion; and a first protrusion between the first line portion and the second line portion, the first protrusion protruding from the first line portion. The via pattern extends vertically through the first protrusion.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims the benefit of Korean Patent Application No. 10-2024-0054076 filed on April 23, 2024, in the Korean Intellectual Property Office, the contents of which are incorporated herein by reference in their entirety. Technical Field

[0003] The present disclosure relates to a semiconductor device, and more particularly, to a semiconductor device including stacked multi-gate transistors. Background Art

[0004] One of the scaling schemes for increasing the integration density of integrated circuit devices includes a multi-gate transistor in which a fin-shaped or nanowire-shaped silicon body is formed on a substrate, and a gate is formed on a surface of the silicon body.

[0005] Because such multi-gate transistors utilize a three-dimensional channel, they can be easily scaled down. Furthermore, their current control capability can be improved without increasing their gate length. Furthermore, multi-gate transistors can effectively suppress the short channel effect (SCE), in which the potential in the channel region is affected by the drain voltage. Summary of the Invention

[0006] One aspect provides a semiconductor device with improved integration density and performance.

[0007] According to an aspect of one or more embodiments, a semiconductor device is provided, including: a first active pattern extending in a first direction; a second active pattern extending in the first direction and spaced apart from the first active pattern in a vertical direction intersecting the first direction; a first gate structure on the first and second active patterns, the first gate structure extending in a second direction intersecting the first and vertical directions; a first cutting pattern spaced apart from the first and second active patterns in a second direction, the first cutting pattern extending in the first direction and cutting the first gate structure; and a via pattern spaced apart from the second active pattern in the second direction. The second active pattern includes: a first portion having a first width in the second direction; and a second portion having a second width in the second direction, the second width being smaller than the first width. The first cutting pattern includes: a first line portion extending in the first direction; and a first protrusion between the first line portion and the second portion, the first protrusion protruding from the first line portion in the second direction; and a via pattern extending in the vertical direction and extending through the first protrusion.

[0008] According to another aspect of one or more embodiments, there is provided a semiconductor device including: a substrate including a first surface and a second surface opposite to the first surface; a first active pattern and a second active pattern sequentially stacked on the first surface in a vertical direction intersecting the first surface, the first active pattern and the second active pattern extending in a first direction and being spaced apart from each other in the vertical direction; a gate structure extending in a second direction intersecting the first direction and the vertical direction, the gate structure including a first gate electrode intersecting the first active pattern and a second gate electrode intersecting the second active pattern; a cut pattern spaced apart from the first active pattern and the second active pattern in the second direction, the cut pattern extending in the first direction and cutting the gate structure; and a via pattern spaced apart from the second active pattern in the second direction. The second active pattern includes: a first portion having a first width in the second direction; and a second portion having a second width in the second direction, the second width being smaller than the first width. The cut pattern includes: a line portion extending in the first direction; and a protrusion between the line portion and the second gate electrode, the protrusion protruding from the line portion in the second direction, and the via pattern extends in the vertical direction to extend through the protrusion and connect to the first gate electrode.

[0009] According to still another aspect of one or more embodiments, there is provided a semiconductor device including: a substrate including a first surface and a second surface opposite to the first surface; a first active pattern and a second active pattern sequentially stacked on the first surface in a vertical direction intersecting the first surface, the first active pattern and the second active pattern extending in a first direction and being spaced apart from each other in the vertical direction; a gate structure on the first active pattern and the second active pattern, the gate structure extending in a second direction intersecting the first direction and the vertical direction; a first source / drain contact on a side surface of the gate structure, the first source / drain contact connected to a first source / drain region of the first active pattern; a second source / drain contact on the side surface of the gate structure, the second source / drain contact connected to a second source / drain region of the second active pattern; a cut pattern spaced apart from the first active pattern and the second active pattern in the second direction, the cut pattern extending in the first direction and cutting the gate structure; and a via pattern spaced apart from the first active pattern and the second active pattern in the second direction. The second active pattern includes: a first portion having a first width in the second direction; and a second portion having a second width in the second direction, the second width being smaller than the first width. The cut pattern includes: a line portion extending in the first direction; and a protrusion between the line portion and the second portion, the protrusion protruding from the line portion in the second direction, and the via pattern extends in the vertical direction to extend through the protrusion and connect to at least one of the first source / drain contact or the second source / drain contact. BRIEF DESCRIPTION OF DRAWINGS

[0010] The above-described and other aspects will become more apparent by reference to the following Description taken in conjunction with the accompanying drawings wherein:

[0011] Figure 1 is an example layout diagram for illustrating a semiconductor device according to some embodiments;

[0012] Figure 2 is a cross-sectional view along a cut A-A in Figure 1 according to some embodiments;

[0013] Figure 3 is a cross-sectional view along a cut B-B in Figure 1 according to some embodiments;

[0014] Figure 4 is a cross-sectional view along a cut C-C in Figure 1 according to some embodiments;

[0015] Figure 5 is a cross-sectional view along a cut D-D in Figure 1 according to some embodiments;

[0016] Figure 6 is a cross-sectional view along a cut E-E in Figure 1 according to some embodiments;

[0017] Figure 7 is another cross-sectional view along a cut A-A in Figure 1 according to some embodiments;

[0018] Figure 8 is another cross-sectional view along a cut B-B in Figure 1 according to some embodiments;

[0019] Figure 9 is another cross-sectional view along a cut C-C in Figure 1 according to some embodiments;

[0020] Figure 10 is an example layout diagram for illustrating a semiconductor device according to some embodiments;

[0021] Figure 11 is an example layout diagram for illustrating a semiconductor device according to some embodiments;

[0022] Figure 12 is a cross-sectional view along a cut F-F in Figure 11 according to some embodiments;

[0023] Figure 13 is an example layout diagram for illustrating a semiconductor device according to some embodiments;

[0024] Figure 14 According to some embodiments Figure 13 Cross-sectional view of GG cutting in;

[0025] Figure 15 According to some embodiments Figure 13 Cross-sectional view of HH cutting in ;

[0026] Figure 16 According to some embodiments Figure 13 A cross-sectional view of the II cut in FIG; and

[0027] Figure 17 to Figure 19 1 are various example layout diagrams for illustrating semiconductor devices according to some embodiments. DETAILED DESCRIPTION

[0028] For ease of description, spatially relative terms such as "below," "beneath," "below," "above," "upper," etc. may be used herein to describe the relationship of one element or feature relative to another element or feature as shown in the accompanying drawings. It will be understood that the spatially relative terms are intended to encompass different orientations of the device in use or operation, in addition to the orientation shown in the accompanying drawings. For example, if the device in the accompanying drawings is turned over, elements described as "below" or "beneath" other elements or features would be oriented "above" the other elements or features. Thus, the example term "below" can encompass both above and below orientations. The device may be otherwise oriented (rotated 90 degrees or in other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0029] It should be understood that although the terms "first", "second" etc. can be used in this article to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Therefore, for example, without departing from the teachings of the present disclosure, the "first" element, "first" component or "first" part discussed below may also be referred to as the "second" element, "second" component or "second" part. As used in this specification, the phrase "at least one of A, B or C" includes "only A", "only B", "only C", "A and B", "A and C", "B and C" and "A, B and C" within its scope.

[0030] In the following, reference Figure 1 to Figure 19 , describing a semiconductor device according to some embodiments. Figure 1 to Figure 19 The embodiments disclosed in the present invention are merely examples, and those skilled in the art will understand that the present disclosure can be applied to various semiconductor devices including various logic elements and / or static random access memory (SRAM) elements.

[0031] Figure 1is an example layout diagram for illustrating a semiconductor device according to some embodiments. Figure 2 is a cross-sectional view along Figure 1 cut in Figure 3 is a cross-sectional view along Figure 1 cut in Figure 4 is a cross-sectional view along Figure 1 cut in Figure 5 is a cross-sectional view along Figure 1 cut in Figure 6 is a cross-sectional view along Figure 1 cut in

[0032] Referring to Figure 1 to Figure 6 , a semiconductor device can include a first region I and a second region II.

[0033] The first region I and the second region II can be sequentially stacked along a vertical direction Z. In some embodiments, transistors of the same conductivity type can be respectively formed in the first region I and the second region II. In some embodiments, transistors of different conductivity types can be respectively formed in the first region I and the second region II. In the following description, the first region I is a PFET region, and the second region II is a NFET region. However, this is merely an example, and one of ordinary skill in the art to which the present disclosure pertains will understand that the first region I can be a NFET region and the second region II can be a PFET region, or both the first region I and the second region II can be NFET regions, or both the first region I and the second region II can be PFET regions.

[0034] The semiconductor device can include a substrate 101, a first active pattern 110, a second active pattern 210, first to seventh gate structures GS1 to GS7, a first cut pattern 150, a second cut pattern 250, a first source / drain contact 162, a second source / drain contact 262, a first via pattern 182, a second via pattern 184, a first wiring structure MS1, and a second wiring structure MS2.

[0035] In some embodiments, the substrate 101 can be made of bulk silicon or silicon-on-insulator (SOI). In some embodiments, the substrate 101 can be a silicon substrate, or can include a material other than silicon, such as silicon germanium, silicon germanium on insulator (SGOI), indium antimonide, lead telluride compound, indium arsenide, indium phosphide, gallium arsenide, or gallium antimonide. In some embodiments, the substrate 101 can have a base substrate and an epitaxial layer formed on the base substrate.

[0036] In some embodiments, the substrate 101 can be an insulating substrate including an insulating material. For example, the substrate 101 can include at least one of silicon oxide, silicon oxynitride, silicon carbonitride oxide, or a combination thereof. However, embodiments of the present disclosure are not limited thereto. For example, in some embodiments, the substrate 101 can include a silicon oxide film.

[0037] The substrate 101 can include a first surface 101a and a second surface 101b opposite to each other. In the present disclosure, the first surface 101a can be referred to as a front surface of the substrate 101, and the second surface 101b can be referred to as a rear surface of the substrate 101.

[0038] The first active pattern 110 and the second active pattern 210 can be sequentially stacked on the first surface 101a of the substrate 101. The first active pattern 110 and the second active pattern 210 can be spaced apart from each other in a vertical direction Z. The first active pattern 110 can be disposed within a first region I, and the second active pattern 210 can be disposed within a second region II. Each of the first active pattern 110 and the second active pattern 210 can extend in an elongated manner in a first direction X intersecting the vertical direction Z.

[0039] In some embodiments, the first active pattern 110 can include a plurality of lower bridge patterns 111 and 112 sequentially stacked on the substrate 101 and spaced apart from each other. In some embodiments, the second active pattern 210 can include a plurality of upper bridge patterns 211 and 212 sequentially stacked on the first active pattern 110 and spaced apart from each other. Each of the first active pattern 110 and the second active pattern 210 can function as a channel region of an MBCFET including a multi-bridge channel. ® Although two bridge patterns are shown in each of the first active pattern 110 and the second active pattern 210, the number of bridge patterns included in each of the first active pattern 110 and the second active pattern 210 is merely an example and is not limited to the number shown. Figure 2 Although two bridge patterns are shown in each of the first active pattern 110 and the second active pattern 210, the number of bridge patterns included in each of the first active pattern 110 and the second active pattern 210 is merely an example and is not limited to the number shown.

[0040] In some embodiments, each of the first active pattern 110 and the second active pattern 210 can include silicon Si or germanium Ge as an elemental semiconductor material. In some embodiments, each of the first active pattern 110 and the second active pattern 210 can include a compound semiconductor, such as a Group IV-IV compound semiconductor or a Group III-V compound semiconductor. The Group IV-IV compound semiconductor can include, for example, a binary compound including two of carbon (C), silicon (Si), germanium (Ge), and tin (Sn), a ternary compound including three of them, or a compound obtained by doping a Group IV element thereto. The Group III-V compound semiconductor can include, for example, a binary compound obtained by combining one of aluminum (Al), gallium (Ga), and indium (In) as a Group III element with one of phosphorus (P), arsenic (As), and antimony (Sb) as a Group V element, a ternary compound obtained by combining two of aluminum (Al), gallium (Ga), and indium (In) as a Group III element with one of phosphorus (P), arsenic (As), and antimony (Sb) as a Group V element, or a quaternary compound obtained by combining three of aluminum (Al), gallium (Ga), and indium (In) as a Group III element with one of phosphorus (P), arsenic (As), and antimony (Sb) as a Group V element.

[0041] In some embodiments, the first active pattern 110 can include a first portion P11 and a second portion P12 having different widths. For example, the first portion P11 can have a first width W11 in the second direction Y, and the second portion P12 can have a second width W12 smaller than the first width W11 in the second direction Y. The first portion P11 and the second portion P12 can be connected to each other in the first direction X.

[0042] In some embodiments, the second active pattern 210 can include a third portion P21 and a fourth portion P22 having different widths. For example, the third portion P21 can have a third width W21 in the second direction Y, and the fourth portion P22 can have a fourth width W22 smaller than the third width W21 in the second direction Y. The third portion P21 and the fourth portion P22 can be connected to each other in the first direction X.

[0043] In some embodiments, the first portion P11 of the first active pattern 110 and the third portion P21 of the second active pattern 210 can overlap each other in the vertical direction Z. In some embodiments, the second portion P12 of the first active pattern 110 and the fourth portion P22 of the second active pattern 210 can overlap each other in the vertical direction Z.

[0044] In some embodiments, a base insulating pattern 102 can be formed between the substrate 101 and the first active pattern 110. The base insulating pattern 102 can extend in an elongated manner in the first direction X. The base insulating pattern 102 can electrically insulate the substrate 101 and the first active pattern 110 from each other. The base insulating pattern 102 can include, but is not limited to, at least one of, for example, silicon oxide, silicon oxynitride, silicon carbonitride oxide, or a combination thereof. For example, in some embodiments, the base insulating pattern 102 can include a silicon nitride film.

[0045] In some embodiments, an intermediate insulating pattern 202 can be formed between the first active pattern 110 and the second active pattern 210. The intermediate insulating pattern 202 can extend in an elongated manner in the first direction X. The intermediate insulating pattern 202 can electrically insulate the first active pattern 110 and the second active pattern 210 from each other. The intermediate insulating pattern 202 can include, but is not limited to, at least one of, for example, silicon oxide, silicon oxynitride, silicon carbonitride oxide, or a combination thereof. For example, in some embodiments, the intermediate insulating pattern 202 can include a silicon nitride film.

[0046] Each of the first to seventh gate structures GS1 to GS7 can be disposed on the first active pattern 110 and the second active pattern 210. Each of the first to seventh gate structures GS1 to GS7 can intersect the first active pattern 110 and the second active pattern 210. For example, each of the first to seventh gate structures GS1 to GS7 can extend in an elongated manner in a second direction Y intersecting the vertical direction Z and the first direction X. The first to seventh gate structures GS1 to GS7 can be spaced apart from each other in the first direction X.

[0047] In the present disclosure, adjacent gate structures can be referred to as being spaced apart by 1 gate pitch (1GP) from each other. The 1 gate pitch (1GP) can be defined as the sum of the distance between two adjacent gate structures and the width of one gate structure. Similarly, the 1 gate pitch (1GP) can be defined as the distance between the center line of one gate structure and the center line of another gate structure adjacent thereto.

[0048] The first to seventh gate structures GS1 to GS7 can intersect the first portion P11 of the first active pattern 110 and / or the second portion P12 of the first active pattern 110. For example, each of the first and seventh gate structures GS1 and GS7 can intersect the first portion P11 of the first active pattern 110. For example, each of the third to fifth gate structures GS3 to GS5 can intersect the second portion P12 of the first active pattern 110. For example, each of the second and sixth gate structures GS2 and GS6 can intersect a boundary region between the first portion P11 and the second portion P12.

[0049] The first to seventh gate structures GS1 to GS7 can intersect the third portion P21 of the second active pattern 210 and / or the fourth portion P22 of the second active pattern 210. For example, each of the first and seventh gate structures GS1 and GS7 can intersect the third portion P21 of the second active pattern 210. For example, each of the third to fifth gate structures GS3 to GS5 can intersect the fourth portion P22 of the second active pattern 210. For example, each of the second and sixth gate structures GS2 and GS6 can intersect a boundary region between the third and fourth portions P21 and P22.

[0050] In some embodiments, each of the first to seventh gate structures GS1 to GS7 can surround the first and second active patterns 110 and 210. For example, each of the bridge patterns 111, 112, 211, and 212 can extend in the first direction X to extend through the first to seventh gate structures GS1 to GS7.

[0051] Each of the first to seventh gate structures GS1 to GS7 can include the gate dielectric film 120, the first gate electrode 130, the second gate electrode 230, the gate spacer 135, and the gate capping film 137.

[0052] The gate dielectric film 120 can be interposed between the first active pattern 110 and the first gate electrode 130 and between the second active pattern 210 and the second gate electrode 230. The gate dielectric film 120 can include at least one of a dielectric material (e.g., silicon oxide, silicon oxynitride, silicon nitride, or a high dielectric constant material having a dielectric constant higher than that of silicon oxide). The high dielectric constant material can include, for example, at least one of hafnium oxide, hafnium silicon oxide, hafnium aluminum oxide, lanthanum oxide, lanthanum aluminum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, yttrium oxide, aluminum oxide, lead scandium tantalum oxide, lead zinc niobate, or a combination thereof. However, embodiments of the present disclosure are not limited thereto.

[0053] In some embodiments, the gate dielectric film 120 can include an interface film 122 and a high-k dielectric layer 124 sequentially stacked on the first and second active patterns 110 and 210.

[0054] The interface film 122 may surround each of the bridge patterns 111, 112, 211, and 212. For example, the interface film 122 may conformally extend along the periphery of each of the bridge patterns 111, 112, 211, and 212. In some embodiments, the interface film 122 may include an oxide film produced by oxidizing a surface of each of the bridge patterns 111, 112, 211, and 212. For example, when each of the bridge patterns 111, 112, 211, and 212 includes silicon (Si), the interface film 122 may include a silicon oxide film.

[0055] The high-k dielectric layer 124 may surround the periphery of the interface film 122. In addition, a portion of the high-k dielectric layer 124 may be interposed between the second gate electrode 230 and the gate spacer 135. For example, the high-k dielectric layer 124 may conformally extend along the periphery of the interface film 122 and the contours of the inner side surfaces of the gate spacer 135. The high-k dielectric layer 124 may also extend along the substrate 101, the base insulation pattern 102, and the intermediate insulation pattern 202.

[0056] In some embodiments, the high-k dielectric layer 124 may include a high-k material having a dielectric constant greater than that of silicon oxide. The high-k dielectric material may include, for example, hafnium oxide (HfO2), zirconium oxide (ZrO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), titanium oxide (TiO2), strontium titanium oxide (SrTiO3), lanthanum aluminum oxide (LaAlO3), yttrium oxide (Y2O3), hafnium oxynitride (HfO2), and nitride oxide (N). x N y ), zirconium oxynitride (ZrO x N y ), lanthanum oxynitride (La2O x N y ), aluminum oxynitride (Al2O x N y ), titanium oxynitride (TiO x N y ), strontium titanium oxynitride (SrTiO x N y ), lanthanum aluminum oxynitride (LaAlO x N y ), yttrium oxynitride (Y2O x N y ) or at least one of a combination thereof. However, the embodiments of the present disclosure are not limited thereto.

[0057] The first gate electrode 130 may be disposed in the first region I. The first gate electrode 130 may intersect the first active pattern 110 . For example, the first active pattern 110 may extend in the first direction X and extend through the first gate electrode 130 .

[0058] The second gate electrode 230 can be disposed within the second region II. The second gate electrode 230 can intersect the second active pattern 210. For example, the second active pattern 210 can extend in the first direction X and extend across the second gate electrode 230.

[0059] Each of the first gate electrode 130 and the second gate electrode 230 can include a conductive material, for example, at least one of TiN, WN, TaN, Ru, TiC, TaC, Ti, Ag, Al, TiAl, TiAlN, TiAlC, TaCN, TaSiN, Mn, Zr, W, Al, or a combination thereof. However, embodiments of the present disclosure are not limited thereto. Each of the first gate electrode 130 and the second gate electrode 230 can be formed through a replacement process. However, embodiments of the present disclosure are not limited thereto.

[0060] Each of the first gate electrode 130 and the second gate electrode 230 is illustrated as a single film. However, this is merely an example. In some embodiments, each of the first gate electrode 130 and the second gate electrode 230 can be formed by stacking a plurality of conductive films. For example, each of the first gate electrode 130 and the second gate electrode 230 can include a work function control film that controls a work function and a filling conductive film that fills a space defined by the work function control film. For example, the work function control film can include at least one of TiN, TaN, TiC, TaC, TiAlC, or a combination thereof. The filling conductive film can include, for example, W or Al.

[0061] In some embodiments, the first gate electrode 130 and the second gate electrode 230 can include different conductive materials. For example, the first gate electrode 130 and the second gate electrode 230 can include work function control films of different conductive types, respectively. For example, the first gate electrode 130 can include a p-type work function control film, and the second gate electrode 230 can include an n-type work function control film.

[0062] In some embodiments, the first gate electrode 130 and the second gate electrode 230 of some of the first to seventh gate structures GS1 to GS7 can be electrically connected to each other. For example, as Figure 4 illustrated, the first gate electrode 130 and the second gate electrode 230 of the first gate structure GS1 can be in contact with each other. In an example, as Figure 6 illustrated, the first gate electrode 130 and the second gate electrode 230 of the fifth gate structure GS5 can be in contact with each other.

[0063] In some embodiments, the first gate electrode 130 and the second gate electrode 230 of the other gate structures among the first to seventh gate structures GS1 to GS7 can be electrically insulated from each other. For example, as Figure 5As illustrated, the third gate structure GS3 can include a gate insulating pattern 146 between the first gate electrode 130 and the second gate electrode 230 thereof. The gate insulating pattern 146 can extend in an elongated manner in the second direction Y. The first gate electrode 130 and the second gate electrode 230 of the third gate structure GS3 can be insulated from each other by the gate insulating pattern 146.

[0064] The gate spacer 135 can extend along side surfaces of the first gate electrode 130 and the second gate electrode 230. Each of the first active pattern 110 and the second active pattern 210 can extend in the first direction X and across the gate spacer 135. The gate spacer 135 can include an insulating material including at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon boron oxycarbonitride, or a combination thereof. However, embodiments of the present disclosure are not limited thereto.

[0065] The gate capping film 137 can extend along an upper surface of the second gate electrode 230. The gate capping film 137 can include an insulating material including at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbonitride, silicon boron oxycarbonitride, or a combination thereof. However, embodiments of the present disclosure are not limited thereto.

[0066] The first active pattern 110 can include a first source / drain region 160. The first source / drain region 160 can be formed in the first active pattern 110 and on a side surface of each of the first gate structure GS1 to the seventh gate structure GS7. The lower bridge patterns 111 and 112 can extend across the first gate electrode 130 and the gate spacer 135 to contact the first source / drain region 160. The first source / drain region 160 can be insulated from the first gate electrode 130 by the gate spacer 135 and / or the gate dielectric film 120.

[0067] In some embodiments, the first source / drain region 160 can include an epitaxial layer doped with impurities. For example, the first source / drain region 160 can include an epitaxial pattern grown from the first active pattern 110 in an epitaxial growth method. When the first active pattern 110 is a channel region of a PFET, the first source / drain region 160 can contain a P-type impurity (e.g., B, In, Ga, or Al) or an impurity for preventing diffusion of the P-type impurity.

[0068] The second active pattern 210 can include a second source / drain region 260. The second source / drain region 260 can be formed in the second active pattern 210 and on a side surface of each of the first to seventh gate structures GS1 to GS7. The upper bridge patterns 211 and 212 can extend through the second gate electrode 230 and the gate spacer 135 to contact the second source / drain region 260. The second source / drain region 260 can be insulated from the second gate electrode 230 by the gate spacer 135 and / or the gate dielectric film 120.

[0069] In some embodiments, the second source / drain region 260 can include an epitaxial layer doped with impurities. For example, the second source / drain region 260 can include an epitaxial pattern grown from the second active pattern 210 in an epitaxial growth method. When the second active pattern 210 is a channel region of an NFET, the second source / drain region 260 can contain an N-type impurity (e.g., P, Sb, or As) or an impurity for preventing diffusion of the N-type impurity.

[0070] In some embodiments, an intermediate insulating layer 144 can be formed between the first source / drain region 160 and the second source / drain region 260. The intermediate insulating layer 144 can cover the first source / drain region 160, and the second source / drain region 260 can be formed on the intermediate insulating layer 144. The intermediate insulating layer 144 can electrically insulate the first source / drain region 160 and the second source / drain region 260 from each other. The intermediate insulating layer 144 can include, but is not limited to, at least one of silicon oxide, silicon oxynitride, silicon carbon oxynitride, or a combination thereof.

[0071] In some embodiments, an intermediate spacer 142 can be formed between the intermediate insulating pattern 202 and the intermediate insulating layer 144. The intermediate spacer 142 can extend along a side surface of the intermediate insulating pattern 202. The intermediate spacer 142 can be interposed between the first source / drain region 160 and the second source / drain region 260. The intermediate spacer 142 can include, but is not limited to, an insulating material such as at least one of silicon oxide, silicon oxynitride, silicon carbon oxynitride, or a combination thereof.

[0072] The first interlayer insulating film 240 can fill a space on an outer side surface of the gate spacer 135. The first interlayer insulating film 240 can include, for example, at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon carbon oxide, silicon boron nitride, silicon boron carbon nitride, silicon carbon oxynitride, or a low dielectric constant material having a dielectric constant less than that of silicon oxide. However, embodiments of the present disclosure are not limited thereto.

[0073] The first and second cut patterns 150 and 250 can be spaced apart from each other in the second direction Y. The first and second active patterns 110 and 210 can be interposed between the first and second cut patterns 150 and 250. The first cut pattern 150 can be spaced apart from one side of the first active pattern 110 and one side of the second active pattern 210 in the second direction Y. The second cut pattern 250 can be spaced apart from the other side of the first active pattern 110 and the other side of the second active pattern 210 in the second direction Y.

[0074] Each of the first and second cut patterns 150 and 250 can extend in an elongated manner in the first direction X and can cut the first to seventh gate structures GS1 to GS7. Each of the first and second cut patterns 150 and 250 can include an insulating material such as at least one of silicon oxide, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon boron nitride, silicon boron carbon nitride, or silicon boron carbon oxynitride, or a combination thereof. However, embodiments of the present disclosure are not limited thereto.

[0075] As shown, the uppermost surface of the first cut pattern 150 and the uppermost surface of the second cut pattern 250 are coplanar with the upper surface of the gate capping film 137 (see, e.g., FIG. 1B). Figure 5 However, this is merely an example. As long as the first and second cut patterns 150 and 250 cut only the first and second gate electrodes 130 and 230, each of the uppermost surfaces of the first and second cut patterns 150 and 250 can be higher or lower in vertical level than the upper surface of the gate capping film 137.

[0076] It is shown that each of the lowermost surface of the first cut pattern 150 and the lowermost surface of the second cut pattern 250 is lower in vertical level than the uppermost surface of the substrate 101. However, this is merely an example. As long as the first and second cut patterns 150 and 250 cut only the first and second gate electrodes 130 and 230, the lowermost surfaces of the first and second cut patterns 150 and 250 can be coplanar with the uppermost surface of the substrate 101.

[0077] In some embodiments, the first cut pattern 150 can include a first line portion 152, a first protrusion 154, and a second protrusion 156.

[0078] The first line portion 152 can extend in the first direction X to cut the first to seventh gate structures GS1 to GS7. A first distance D11 between the first portion P11 of the first active pattern 110 and the first line portion 152 in the second direction Y can be less than a second distance D12 between the second portion P12 of the first active pattern 110 and the first line portion 152 in the second direction Y. A third distance D21 between the third portion P21 of the second active pattern 210 and the first line portion 152 in the second direction Y can be less than a fourth distance D22 between the fourth portion P22 of the second active pattern 210 and the first line portion 152 in the second direction Y.

[0079] In some embodiments, a fifth distance D13 between the first active pattern 110 and the second cut pattern 250 in the second direction Y can be less than the second distance D12. For example, in some embodiments, the fifth distance D13 can be equal to the first distance D11. In some embodiments, a sixth distance D23 between the second active pattern 210 and the second cut pattern 250 in the second direction Y can be less than the fourth distance D22. For example, in some embodiments, the sixth distance D23 can be equal to the third distance D21. In the present disclosure, "equal" means not only "exactly equal" but also includes a slight difference that can occur due to a process margin or the like. In some embodiments, each of a distance between the first portion P11 of the first active pattern 110 and the second cut pattern 250 in the second direction Y and a distance between the second portion P12 of the first active pattern 110 and the second cut pattern 250 in the second direction Y can be equal to the fifth distance D13. In some embodiments, each of a distance between the third portion P21 of the second active pattern 210 and the second cut pattern 250 in the second direction Y and a distance between the fourth portion P22 of the second active pattern 210 and the second cut pattern 250 in the second direction Y can be equal to the sixth distance D23.

[0080] The first protrusion 154 can protrude from the first line portion 152 in the second direction Y, as Figure 1 illustrated. The first protrusion 154 can be interposed between the first line portion 152 and the fourth portion P22 of the second active pattern 210. A distance between the first protrusion 154 and the fourth portion P22 in the second direction Y is illustrated as being equal to the third distance D21. However, this is merely an example.

[0081] The first protrusion 154 can additionally cut the second gate electrode 230 of the third gate structure GS3. For example, the first protrusion 154 can be interposed between the second gate electrode 230 of the third gate structure GS3 and the first line portion 152. The length that the second gate electrode 230 of the third gate structure GS3 extends in the second direction Y can be less than the length that another second gate electrode (e.g., the second gate electrode 230 of each of the second gate structure GS2 and the fourth gate structure GS4) that is not cut by the first protrusion 154 extends. In Figure 5 In the example, the vertical level of the lowermost surface of the first protrusion 154 is shown as being higher than the vertical level of the lowermost surface of the gate insulating pattern 146. However, this is merely an example. As long as the first protrusion 154 cuts the second gate electrode 230, the vertical level of the lowermost surface of the first protrusion 154 can be equal to or lower than the vertical level of the lowermost surface of the gate insulating pattern 146.

[0082] In some embodiments, the first protrusion 154 can not cut the first gate electrode 130 of the third gate structure GS3. For example, the first protrusion 154 can not be interposed between the first gate electrode 130 of the third gate structure GS3 and the first line portion 152. The length that the first gate electrode 130 of the third gate structure GS3 extends in the second direction Y can be greater than the length that the second gate electrode 230 of the third gate structure GS3 extends in the second direction Y.

[0083] In some embodiments, the first protrusion 154 can be interposed between the second gate structure GS2 and the fourth gate structure GS4. For example, the first length L1 that the first protrusion 154 extends in the first direction X can be about 1 gate pitch (1GP).

[0084] The second protrusion 156 can protrude from the first line portion 152 in the second direction Y. The second protrusion 156 can be interposed between the first line portion 152 and the fourth portion P22 of the second active pattern 210. The distance between the second protrusion 156 and the fourth portion P22 in the second direction Y is shown as being equal to the third distance D21. However, this is merely an example. The second protrusion 156 can be spaced apart from the first protrusion 154 in the first direction X.

[0085] The second protrusion 156 can additionally cut the fifth gate structure GS5. For example, the second protrusion 156 can be interposed between the fifth gate structure GS5 and the first line portion 152. The length that the fifth gate structure GS5 extends in the second direction Y can be less than the length that another gate structure (e.g., each of the fourth gate structure GS4 and the sixth gate structure GS6) that is not cut by the second protrusion 156 extends.

[0086] In some embodiments, the second protrusion 156 can cut both the first gate electrode 130 and the second gate electrode 230 of the fifth gate structure GS5. For example, the second protrusion 156 can be disposed between the first gate electrode 130 of the fifth gate structure GS5 and the first line portion 152 and between the second gate electrode 230 of the fifth gate structure GS5 and the first line portion 152. In Figure 6 In some embodiments, the second protrusion 156 can cut both the first gate electrode 130 and the second gate electrode 230 of the fifth gate structure GS5. For example, the second protrusion 156 can be disposed between the first gate electrode 130 of the fifth gate structure GS5 and the first line portion 152 and between the second gate electrode 230 of the fifth gate structure GS5 and the first line portion 152. In

[0087] In some embodiments, the second protrusion 156 can be between the fourth gate structure GS4 and the sixth gate structure GS6. For example, the second length L2 by which the second protrusion 156 extends in the first direction X can be about 1 gate pitch (1GP). In some embodiments, L2 can be equal to L1.

[0088] The first source / drain contact 162 can be electrically connected to the first active pattern 110. For example, the first source / drain contact 162 can extend through the substrate 101 in the vertical direction Z, thereby contacting the first source / drain region 160.

[0089] The second source / drain contact 262 can be electrically connected to the second active pattern 210. For example, the second source / drain contact 262 can extend through the first interlayer insulating film 240 in the vertical direction Z, thereby contacting the second source / drain region 260.

[0090] The first via pattern 182 can be spaced apart from the fourth portion P22 of the second active pattern 210 in the second direction Y. The first via pattern 182 can extend through the first protrusion 154 in the vertical direction Z. In some embodiments, the first via pattern 182 can extend through the first protrusion 154 and the gate insulating pattern 146. The first via pattern 182 can include a conductive material, such as tungsten (W) or aluminum (Al). However, embodiments of the present disclosure are not limited thereto.

[0091] In some embodiments, the first via pattern 182 can contact the first gate electrode 130 of the third gate structure GS3. For example, the first via pattern 182 can extend through the first protrusion 154 and / or the gate insulating pattern 146 of the third gate structure GS3, thereby contacting an upper surface of the first gate electrode 130 of the third gate structure GS3. The first via pattern 182 can be spaced apart from the second gate electrode 230 of the third gate structure GS3 by the first protrusion 154. That is, the first via pattern 182 can be electrically connected to the first gate electrode 130 of the third gate structure GS3, and can not be electrically connected to the second gate electrode 230 of the third gate structure GS3.

[0092] The second via pattern 184 can be spaced apart from the fourth portion P22 of the second active pattern 210 in the second direction Y. The second via pattern 184 can extend through the second protrusion 156 in the vertical direction Z. In some embodiments, the second via pattern 184 can extend through the second protrusion 156 and the substrate 101. The second via pattern 184 can include a conductive material, such as W or Al. However, embodiments of the present disclosure are not limited thereto.

[0093] In some embodiments, the second via pattern 184 can contact at least one of the first active pattern 110 or the second active pattern 210.

[0094] For example, the second interlayer insulating film 170 and the first connection contact portion 172 disposed within the second interlayer insulating film 170 can be formed on the second surface 101b of the substrate 101. The first connection contact portion 172 can extend in the second direction Y. Each of the first source / drain contact portion 162 and the second via pattern 184 can be connected to the first connection contact portion 172 in the vertical direction Z. That is, the second via pattern 184 can be connected to the first source / drain region 160 through the first connection contact portion 172 and the first source / drain contact portion 162. In some embodiments, the first connection contact portion 172 can be omitted. For example, unlike the illustration, the first source / drain contact portion 162 can extend in the second direction Y, thereby directly contacting the second via pattern 184.

[0095] In some embodiments, for example, a third interlayer insulating film 270 and a second connection contact 272 provided in the third interlayer insulating film 270 can be formed on the first interlayer insulating film 240. The second connection contact 272 can extend in the second direction Y. Each of the second source / drain contact 262 and the second via pattern 184 can be connected to the second connection contact 272 in the vertical direction Z. That is, the second via pattern 184 can be connected to the second source / drain region 260 through the second connection contact 272 and the second source / drain contact 262. In some embodiments, the second connection contact 272 can be omitted. For example, unlike the illustration, the second source / drain contact 262 can extend in the second direction Y so as to directly contact the second via pattern 184.

[0096] In some embodiments, the second via pattern 184 can connect the first source / drain region 160 and the second source / drain region 260 to each other. For example, as illustrated, the first connection contact 172 can be provided at one side of the fifth gate structure GS5, and the second connection contact 272 can be provided at the other side of the fifth gate structure GS5. The second via pattern 184 can extend in the first direction X so as to connect the first connection contact 172 and the second connection contact 272 to each other.

[0097] A first wiring structure MS1 can be formed on the second surface 101b of the substrate 101. For example, the first wiring structure MS1 can include a first inter-wiring insulating film ID1 covering the second interlayer insulating film 170 and a plurality of first wiring patterns MW1 provided in the first inter-wiring insulating film ID1. The first wiring patterns MW1 can be insulated from each other by the first inter-wiring insulating film ID1.

[0098] In some embodiments, at least some of the first wiring patterns MW1 can function as power lines (e.g., V SS or V DD ).

[0099] A second wiring structure MS2 can be formed on the first surface 101a of the substrate 101. For example, the second wiring structure MS2 can include a second inter-wiring insulating film ID2 covering the third interlayer insulating film 270 and a plurality of second wiring patterns MW2 provided in the second inter-wiring insulating film ID2. The second wiring patterns MW2 can be insulated from each other by the second inter-wiring insulating film ID2.

[0100] In some embodiments, at least some of the second wiring patterns MW2 can be electrically connected to the first wiring patterns MW1 functioning as power lines.

[0101] In some embodiments, the first via pattern 182 and / or the second via pattern 184 can be electrically connected to the second wiring structure MS2. For example, the first front via 192 can be formed, thereby connecting some of the second wiring patterns MW2 and the first via pattern 182 to each other. In some embodiments, for example, the second front via 194 can be formed, thereby connecting some of the second wiring patterns MW2 and the second connection contact 272 to each other. The second via pattern 184 can be connected to the second wiring structure MS2 through the second connection contact 272 and the second front via 194.

[0102] As semiconductor devices become more highly integrated, individual circuit patterns become smaller to implement a larger number of elements in the same area. For this purpose, semiconductor devices using stacked multi-gate transistors in which multi-gate transistors in an upper region (e.g., the second region II) are stacked on top of multi-gate transistors in a lower region (e.g., the first region I) are being researched. However, in such semiconductor devices, it can be difficult to improve the integration density due to the complexity of the circuit patterns.

[0103] For example, to connect the lower region and the upper region to each other, a high via extending in an elongated manner across the lower region and the upper region can be required. However, when using a high via, the area size of the adjacent gate structure of the high via is larger than that of a via extending only in the lower region or a via extending only in the upper region. Such a structure can increase the parasitic capacitance between the high via and the gate structure, thereby degrading the performance of the semiconductor device. In addition, the high via can be disposed outside the region in which the active pattern and the gate structure are disposed in a plan view (i.e., the high via does not overlap the active pattern and the gate structure in the vertical direction Z). Such a structure can increase the area size required to implement the semiconductor device, thereby limiting the improvement of the integration density.

[0104] However, in the semiconductor device according to some embodiments, the first region I and the second region II can be connected to each other using the first via pattern 182 and / or the second via pattern 184, so that an improved integration density and performance can be achieved.

[0105] For example, as described above, the first cut pattern 150 can include a first protrusion 154 protruding toward the fourth portion P22 of the second active pattern 210. The first via pattern 182 can extend through the first protrusion 154, thereby connecting the first region I (e.g., the first gate electrode 130) and the second region II (e.g., the second wiring structure MS2) to each other. In this regard, the third portion P21 of the second active pattern 210 does not overlap the first protrusion 154 of the first cut pattern 150 in the second direction Y, such that the third portion P21 can have a relatively large width. For example, a third width W21 of the third portion P21 can be greater than a fourth width W22 of the fourth portion P22. Accordingly, a semiconductor device having improved integration density and performance can be provided.

[0106] In some embodiments, for example, as described above, the first cut pattern 150 can include a second protrusion 156 protruding toward the second portion P12 of the first active pattern 110 and the fourth portion P22 of the second active pattern 210. The second via pattern 184 can extend through the second protrusion 156, thereby connecting the first region I (e.g., the first source / drain region 160) and the second region II (e.g., the second source / drain region 260) to each other. In this regard, the first portion P11 of the first active pattern 110 and the third portion P21 of the second active pattern 210 do not overlap the second protrusion 156 in the second direction Y, such that each of the first portion P11 of the first active pattern 110 and the third portion P21 of the second active pattern 210 can have a relatively large width. For example, each of a first width W11 of the first portion P11 and a third width W21 of the third portion P21 can be greater than each of a second width W12 of the second portion P12 and a fourth width W22 of the fourth portion P22. Accordingly, a semiconductor device having improved integration density and performance can be provided.

[0107] Figure 7 is another cross-sectional view taken along Figure 1 A-A cut in FIG. 1B according to some embodiments. For ease of description, components that are briefly described with components described above using Figure 1 to Figure 6 are repeated or whose descriptions are omitted for brevity.

[0108] Referring to Figure 1 and Figure 7 In a semiconductor device according to some embodiments, each of the first to seventh gate structures GS1 to GS7 can further include the inner spacer 136.

[0109] The inner spacers 136 can be formed, for example, within the second region II, and can be formed on side surfaces of the second gate electrodes 230 and between the upper bridge patterns 211 and 212. The inner spacers 136 can be formed on side surfaces of the second gate electrodes 230 and between the middle insulating patterns 202 and the second active patterns 210. The second source / drain regions 260 can be insulated from the second gate electrodes 230 by the gate spacers 135, the inner spacers 136, and / or the gate dielectric film 120.

[0110] The inner spacers 136 are shown as not being formed within the first region I. However, this is merely an example. Unlike the illustration, in some embodiments, the inner spacers 136 can be formed in both the first region I and the second region II. In some embodiments, unlike the illustration, the inner spacers 136 can be formed only in the first region I and not in the second region II.

[0111] Figure 8 is another cross-sectional view along the B-B cut of Figure 1 In order to facilitate the description, components that are repetitive of components described above using Figure 1 to Figure 6 are briefly described or their description is omitted for the sake of brevity.

[0112] Referring to Figure 1 and Figure 8 In the semiconductor device according to some embodiments, the first via pattern 182 and / or the second via pattern 184 are electrically connected to the first wiring structure MS1.

[0113] For example, the back via 196 can be formed to connect some of the first wiring patterns MW1 to the first connection contact 172. The second via pattern 184 can be connected to the first wiring structure MS1 through the first connection contact 172 and the back via 196.

[0114] Figure 9 is another cross-sectional view along the C-C cut of Figure 1 In order to facilitate the description, components that are repetitive of components described above using Figure 1 to Figure 6 are briefly described or their description is omitted for the sake of brevity.

[0115] Referring to Figure 1 and Figure 9 In the semiconductor device according to some embodiments, the gate dielectric film 120 further extends along side surfaces of the first cut pattern 150 and side surfaces of the second cut pattern 250.

[0116] For example, the high-k dielectric layer 124 can conformally extend along a contour of the upper surface of the substrate 101, side surfaces of the first cut pattern 150, and side surfaces of the second cut pattern 250.

[0117] Figure 10 is an example layout diagram for illustrating a semiconductor device according to some embodiments. For ease of description, components that are simply described repeatedly with components described above using Figure 1 to Figure 9 or whose description is omitted for brevity.

[0118] Referring to Figure 10 , in the semiconductor device according to some embodiments, a side surface of the first active pattern 110 and / or a side surface of the second active pattern 210 can include a full surface.

[0119] For example, a side surface of the first active pattern 110 facing the first cut pattern 150 can include a first curved surface 110S1 and a second curved surface 110S2. The first curved surface 110S1 and the second curved surface 110S2 can be formed in a boundary region between the first portion P11 and the second portion P12. For example, the first curved surface 110S1 can intersect the second gate structure GS2, and the second curved surface 110S2 can intersect the sixth gate structure GS6.

[0120] In some embodiments, for example, a side surface of the second active pattern 210 facing the first cut pattern 150 can include a third curved surface 210S1 and a fourth curved surface 210S2. The third curved surface 210S1 and the fourth curved surface 210S2 can be formed in a boundary region between the third portion P21 and the fourth portion P22. For example, the third curved surface 210S1 can intersect the second gate structure GS2, and the fourth curved surface 210S2 can intersect the sixth gate structure GS6.

[0121] Figure 11 is an example layout diagram for illustrating a semiconductor device according to some embodiments. Figure 12 is a cross-sectional view along the F-F cut in Figure 11 according to some embodiments. For ease of description, components that are simply described repeatedly with components described above using Figure 1 to Figure 10 or whose description is omitted for brevity.

[0122] Referring to Figure 11 and Figure 12 , in the semiconductor device according to some embodiments, the third gate structure GS3 intersects the first portion P11 of the first active pattern 110.

[0123] In the region intersecting with the third gate structure GS3, the first portion P11 of the first active pattern 110 and the fourth portion P22 of the second active pattern 210 can overlap each other in the vertical direction Z. The first protrusion 154 can not be interposed between the first line portion 152 and the first portion P11, but can be interposed between the first line portion 152 and the fourth portion P22. Accordingly, the first portion P11 can have a relatively large width. For example, in the region intersecting with the third gate structure GS3, a first width W11 of the first portion P11 can be greater than a fourth width W22 of the fourth portion P22. Accordingly, a semiconductor device having a further improved integration density and performance can be provided.

[0124] Figure 13 is an example layout diagram illustrating a semiconductor device according to some embodiments. Figure 14 is a cross-sectional view taken along Figure 13 G-G in FIG. 1A. Figure 15 is a cross-sectional view taken along Figure 13 H-H in FIG. 1A. Figure 16 is a cross-sectional view taken along Figure 13 I-I in FIG. 1A. For ease of description, components that are simply described repeatedly with components described above using Figure 1 to Figure 10 or whose description is omitted for brevity are briefly described.

[0125] Referring to Figure 13 to Figure 16 , in a semiconductor device according to some embodiments, the fifth gate structure GS5 intersects with the first portion P11 of the first active pattern 110.

[0126] In the region intersecting with the fifth gate structure GS5, the first portion P11 of the first active pattern 110 and the fourth portion P22 of the second active pattern 210 can overlap each other in the vertical direction Z. The second protrusion 156 can not be interposed between the first line portion 152 and the first portion P11, but can be interposed between the first line portion 152 and the fourth portion P22. Accordingly, the first portion P11 can have a relatively large width. For example, in the region intersecting with the fifth gate structure GS5, a first width W11 of the first portion P11 can be greater than a fourth width W22 of the fourth portion P22. Accordingly, a semiconductor device having a further improved integration density and performance can be provided.

[0127] In some embodiments, the first source / drain contact 162 can extend through the first source / drain region 160. For example, a vertical level of an upper surface of the first source / drain contact 162 can be higher than a vertical level of an upper surface of the first source / drain region 160.

[0128] In some embodiments, the fifth gate structure GS5 can include a gate insulating pattern 146 between the first gate electrode 130 and the second gate electrode 230. The first gate electrode 130 and the second gate electrode 230 of the fifth gate structure GS5 can be insulated from each other by the gate insulating pattern 146. In Figure 16 In some embodiments, the vertical level of the lowermost surface of the second protrusion 156 can be equal to or lower than the vertical level of the lowermost surface of the gate insulating pattern 146. In

[0129] The second via pattern 184 can extend through the second protrusion 156, thereby contacting the first source / drain contact 162. For example, the first source / drain contact 162 can extend in the second direction Y, thereby directly contacting the second via pattern 184. In some embodiments, the second via pattern 184 can be insulated from the first gate electrode 130 by the gate insulating pattern 146. For example, a lower surface of the second via pattern 184 can be formed at a vertical level higher than a vertical level of a lower surface of the gate insulating pattern 146.

[0130] Figure 17 to Figure 19 are various example layout diagrams for illustrating semiconductor devices according to some embodiments. For ease of description, components that are repeated with components described above using Figure 1 to Figure 10 are omitted for brevity.

[0131] Referring to Figure 17 In a semiconductor device according to some embodiments, the first protrusion 154 can cut adjacent gate structures among the plurality of gate structures.

[0132] For example, the first protrusion 154 can be interposed between the second gate structure GS2 and the first line portion 152 and between the third gate structure GS3 and the first line portion 152. A first length L1 at which the first protrusion 154 extends in the first direction X can be equal to or greater than about 2 gate pitches (2GP).

[0133] In some embodiments, the first protrusion 154 can be interposed between the first gate structure GS1 and the fourth gate structure GS4. For example, a first length L1 at which the first protrusion 154 extends in the first direction X can be about 2 gate pitches (2GP).

[0134] Referring to Figure 18 In a semiconductor device according to some embodiments, the second protrusion 156 can cut adjacent gate structures among the plurality of gate structures.

[0135] For example, the second protrusion 156 can be between the fifth gate structure GS5 and the first line portion 152 and between the sixth gate structure GS6 and the first line portion 152. A second length L2 of the second protrusion 156 extending in the first direction X can be about 2 gate pitches (2GP) or more.

[0136] In some embodiments, the second protrusion 156 can be between the fourth gate structure GS4 and the seventh gate structure GS7. For example, a second length L2 of the second protrusion 156 extending in the first direction X can be about 2 gate pitches (2GP).

[0137] Reference Figure 19 In the semiconductor device according to some embodiments, the second cut pattern 250 can include a second line portion 252 and a third protrusion 256.

[0138] The second line portion 252 extends in the first direction X to cut the first gate structure GS1 to the seventh gate structure GS7. A fifth distance D13 between the first portion P11 of the first active pattern 110 and the second line portion 252 in the second direction Y can be less than a seventh distance D14 between the second portion P12 of the first active pattern 110 and the second line portion 252 in the second direction Y. A sixth distance D23 between the third portion P21 of the second active pattern 210 and the second line portion 252 in the second direction Y can be less than an eighth distance D24 between the fourth portion P22 of the second active pattern 210 and the second line portion 252 in the second direction Y.

[0139] The third protrusion 256 can protrude from the second line portion 252 in the second direction Y. The third protrusion 256 can be between the second line portion 252 and the fourth portion P22 of the second active pattern 210. A distance between the third protrusion 256 and the fourth portion P22 in the second direction Y is shown to be equal to the sixth distance D23. However, this is merely an example. The third protrusion 256 can not overlap the first protrusion 154 in the first direction X. In some embodiments, the third protrusion 256 can not overlap the first protrusion 154 in the second direction Y. For example, as shown, the first protrusion 154 and the third protrusion 256 can be arranged along a diagonal direction between the first direction X and the second direction Y.

[0140] The second via pattern 184 can extend through the third protrusion 256 in the vertical direction Z. In some embodiments, the second via pattern 184 can contact at least one of the first active pattern 110 or the second active pattern 210. For example, the second via pattern 184 can contact at least one of the first connection contact 172 or the second connection contact 272.

[0141] Although the embodiments have been described with reference to the drawings, the embodiments are not limited to the embodiments described and can be implemented in various different forms. It will be understood by those of ordinary skill in the art to which the present disclosure pertains that the embodiments can be implemented in other specific forms without changing the technical idea or essential characteristics of the present disclosure. Therefore, it should be understood that the above-described embodiments are not restrictive but illustrative in all aspects.

Claims

1. A semiconductor device comprising: a first active pattern extending in a first direction; a second active pattern extending in the first direction and spaced apart from the first active pattern in a vertical direction intersecting the first direction; a first gate structure over the first active pattern and the second active pattern, the first gate structure extending in a second direction intersecting the first direction and the vertical direction; a first cut pattern spaced apart from the first active pattern and the second active pattern in the second direction, the first cut pattern extending in the first direction and cutting the first gate structure; and a via pattern spaced apart from the second active pattern in the second direction, wherein the second active pattern includes: a first portion having a first width in the second direction; and a second portion having a second width in the second direction, the second width being smaller than the first width, wherein the first cut pattern includes: a first line portion extending in the first direction; and a first protrusion between the first line portion and the second portion, the first protrusion protruding from the first line portion in the second direction, and wherein the via pattern extends in the vertical direction and extends through the first protrusion. The first protrusion is between the first line portion and the first gate structure.

2. The semiconductor device of claim 1, wherein, The first gate structure includes a first gate electrode intersecting the first active pattern and a second gate electrode intersecting the second active pattern, 3. The semiconductor device of claim 2, wherein, wherein the first protrusion is omitted between the first line portion and the first gate electrode, and the first protrusion is between the first line portion and the second gate electrode. The via pattern is connected to the first gate electrode.

4. The semiconductor device of claim 3, wherein, The first active pattern includes a third portion having a third width in the second direction, the third width being larger than the second width, 5. The semiconductor device of claim 3, wherein, wherein the second portion overlaps the third portion in the vertical direction. The first active pattern includes:

6. The semiconductor device of claim 1, wherein, a third portion having a third width in the second direction; and a fourth portion having a fourth width in the second direction, the fourth width being smaller than the third width, wherein the first protrusion is between the first line portion and the fourth portion.

7. The semiconductor device according to claim 6, further comprising a source / drain contact on a side surface of the first gate structure, the source / drain contact being connected to at least one of a first source / drain region of the first active pattern or a second source / drain region of the second active pattern, and wherein, wherein the via pattern is connected to the source / drain contact. The first protrusion is between the first line portion and the first gate structure.

8. The semiconductor device of claim 6, wherein, The first cut pattern further includes a second protrusion spaced apart from the first protrusion in the first direction, the second protrusion protruding from the first line portion in the second direction.

9. The semiconductor device of claim 1, wherein, ​ 10. The semiconductor device of claim 1, further comprising a second gate structure on the first active pattern and the second active pattern, the second gate structure being spaced apart from the first gate structure in the first direction and extending in the second direction, wherein the first protrusion being between the first line portion and the first gate structure and between the first line portion and the second gate structure.

11. The semiconductor device of claim 1, further comprising a second cut pattern spaced apart from the first active pattern and the second active pattern in the second direction, the second cut pattern extending in the first direction and cutting the first gate structure, wherein the first active pattern and the second active pattern being between the first cut pattern and the second cut pattern.

12. The semiconductor device of claim 11, wherein, the second cut pattern comprising: a second line portion extending in the first direction; and a second protrusion between the second line portion and the second portion, the second protrusion protruding from the second line portion in the second direction.

13. A semiconductor device comprising: a substrate including a first surface and a second surface opposite to the first surface; a first active pattern and a second active pattern sequentially stacked on the first surface along a vertical direction intersecting the first surface, the first active pattern and the second active pattern extending in a first direction and being spaced apart from each other in the vertical direction; a gate structure extending in a second direction intersecting the first direction and the vertical direction, the gate structure including a first gate electrode intersecting the first active pattern and a second gate electrode intersecting the second active pattern; a cut pattern spaced apart from the first active pattern and the second active pattern in the second direction, the cut pattern extending in the first direction and cutting the gate structure; and a via pattern spaced apart from the second active pattern in the second direction, wherein the second active pattern includes: a first portion having a first width in the second direction; and a second portion having a second width in the second direction, the second width being smaller than the first width, wherein the cut pattern includes: a line portion extending in the first direction; and a protrusion between the line portion and the second gate electrode, the protrusion protruding from the line portion in the second direction, and wherein the via pattern extends in the vertical direction to extend through the protrusion and is connected to the first gate electrode. the first active pattern includes a third portion having a third width in the second direction, the third width being greater than the second width, 14. The semiconductor device of claim 13, wherein, wherein the second portion overlaps the third portion in the vertical direction.

15. The semiconductor device of claim 13, further comprising a gate insulating pattern between the first gate electrode and the second gate electrode, the gate insulating pattern extending in the second direction, the via pattern extending through the gate insulating pattern. wherein, ​ 16. The semiconductor device of claim 13, further comprising a wiring structure electrically connected to the via pattern on the second surface.

17. A semiconductor device, comprising: a substrate including a first surface and a second surface opposite the first surface; a first active pattern and a second active pattern sequentially stacked on the first surface along a vertical direction intersecting the first surface, the first active pattern and the second active pattern extending in a first direction and spaced apart from each other in the vertical direction; a gate structure on the first active pattern and the second active pattern, the gate structure extending in a second direction intersecting the first direction and the vertical direction; a first source / drain contact on a side surface of the gate structure, the first source / drain contact connected to a first source / drain region of the first active pattern; a second source / drain contact on a side surface of the gate structure, the second source / drain contact connected to a second source / drain region of the second active pattern; a cut pattern spaced apart from the first active pattern and the second active pattern in the second direction, the cut pattern extending in the first direction and cutting the gate structure; and a via pattern spaced apart from the first active pattern and the second active pattern in the second direction, wherein the second active pattern includes: a first portion having a first width in the second direction; and a second portion having a second width in the second direction, the second width being smaller than the first width, wherein the cut pattern includes: a line portion extending in the first direction; and a protrusion between the line portion and the second portion, the protrusion protruding from the line portion in the second direction, and wherein the via pattern extends in the vertical direction to extend through the protrusion and is connected to at least one of the first source / drain contact or the second source / drain contact. the first active pattern includes:

18. The semiconductor device of claim 17, wherein, a third portion having a third width in the second direction; and a fourth portion having a fourth width in the second direction, the fourth width being smaller than the third width, wherein the protrusion is interposed between the line portion and the fourth portion. the via pattern connects the first source / drain contact to the second source / drain contact.

19. The semiconductor device of claim 17, wherein, 20. The semiconductor device of claim 17, further comprising a wiring structure electrically connected to the via pattern on the second surface. ​

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