CMOS inverter based on itzo thin film transistor and carbon-based transistor and double-temperature double-gas atmosphere preparation method

Abstract

The application discloses a CMOS inverter based on an ITZO thin film transistor and a carbon-based transistor and a double-temperature and double-atmosphere preparation method. The application solves the problem of process incompatibility when the ITZO thin film transistor and the carbon-based transistor are monolithically integrated by using a double-temperature and double-atmosphere integration method, and the whole device is first annealed at 240-260 DEG C for 20-40 min in an air or oxygen environment, and then annealed at 300-350 DEG C for 1-1.5 h in a nitrogen environment. The performance of the ITZO thin film transistor is ensured, and the damage of the high-temperature oxygen-containing environment to the carbon-based transistor is avoided, so that the PMOS and the NMOS with good matching electrical performance are obtained, and the obtained CMOS inverter has a high gain of 276 V / V when the input voltage is 2 V, and the amplification rate of the inverter to a sinusoidal signal with an amplitude of 20 mV is more than 50 times. V dd The CMOS inverter can be applied to a flexible integrated circuit and a wearable device.

Description

Technical Field

[0001] This invention belongs to the field of metal oxide semiconductor inverter technology, specifically relating to a CMOS inverter based on ITZO thin film transistors and carbon-based transistors and a dual-temperature dual-atmosphere fabrication method. Background Technology

[0002] Zinc oxide-based metal oxide thin-film transistors (METS) have been extensively researched and applied. Indium gallium zinc oxide (IGZO) METS have been commercially used in liquid crystal displays (LCDs). Zinc oxide-based METS such as indium tin zinc oxide (ITZO), zinc oxide (ZnO), and indium zinc oxide (IZO) METS can be applied to LCDs, integrated circuits, wearable devices, and sensors. Among them, ITZO METS are NMOS devices with high mobility (10-100 cm⁻¹). 2 V -1 s -1 Its good stability makes it an ideal candidate device for further improving the performance of zinc oxide-based metal oxide thin-film transistors. Carbon-based transistors are PMOS devices with mobilities of 10-100 cm⁻¹. 2 V -1 s -1 The performance of ITZO thin-film transistors (TFTs) is well-matched with that of carbon-based transistors. Complementary metal-oxide-semiconductor (CMOS) circuits constructed using ITZO TFTs and carbon-based transistors exhibit excellent electrical performance. In the fabrication of ITZO TFTs, annealing at temperatures above 300°C in air or oxygen for at least one hour is typically required to repair defects in the ITZO film and obtain a high-performance TFT. However, prolonged high-temperature annealing in air or oxygen can cause carbon-based transistors to fail: the active layer of a carbon-based transistor is a carbon nanotube network, and the high-temperature oxygen-containing environment causes the carbon nanotubes to adsorb a large amount of oxygen and form carbon-oxygen bonds. These oxygen and carbon-oxygen bonds alter the conductivity of the carbon nanotubes, leading to irreversible damage to the carbon-based transistor. Therefore, there is a process incompatibility issue in the monolithic integration of ITZO TFTs and carbon-based transistors.

[0003] In recent years, research has been conducted on monolithically integrated CMOS inverters based on oxide thin-film transistors and carbon-based transistors, but the performance parameters of the obtained devices are not ideal. For example, in 2023, J. Zhang et al. from the Hong Kong University of Science and Technology completed the annealing of oxide thin-film transistors (Ultra-Flexible Monolithic 3D Complementary Metal-Oxide-Semiconductor Electronics) by first encapsulating carbon-based transistors and then annealing them at 120°C for 1 hour in a supercritical carbon dioxide fluid environment at 20 MPa. The CMOS inverter obtained by this method... V dd The gain at 2V is only about 20-30V / V. This is mainly because the packaging of the carbon-based transistor and the annealing in a supercritical carbon dioxide fluid environment cause a positive drift in the threshold voltage of the carbon-based transistor, resulting in a poor performance match between the oxide thin-film transistor and the carbon-based transistor, which in turn leads to poor performance of the CMOS inverter. Chinese patent CN 119698160 A discloses a complementary metal-oxide-semiconductor inverter, which consists of a carbon-based transistor and an ITZO thin-film transistor. This inverter is prepared by a high-temperature annealing process (annealing at 300-350℃ for 1-2 hours in air or oxygen atmosphere). Since long-term annealing at temperatures above 300℃ in an air environment will cause the carbon-based transistor to fail, this patent uses photosensitive polyimide to encapsulate the carbon-based transistor, which improves the temperature resistance of the carbon-based transistor to a certain extent and obtains a monolithically integrated CMOS inverter. However, photosensitive polyimide encapsulation cannot completely solve the problem of carbon-based transistor failure. The on / off ratio of the carbon-based transistor after high-temperature annealing is only 2×10. 3 The resulting CMOS inverter has a gain of only 50V / V.

[0004] Therefore, developing a new monolithic integration process for ITZO thin-film transistors and carbon-based transistors is of great significance for constructing large-scale monolithic integrated CMOS circuits based on ITZO thin-film transistors and carbon-based transistors. Summary of the Invention

[0005] To address the incompatibility issue between the monolithic integration processes of ITZO thin-film transistors and carbon-based transistors, this invention provides a CMOS inverter based on ITZO thin-film transistors and carbon-based transistors, fabricated using a dual-temperature dual-atmosphere integration method.

[0006] This invention proposes a dual-temperature, dual-atmosphere integration method for monolithic integration of ITZO thin-film transistors and carbon-based transistors. The method involves fabricating an ITZO thin film on the same substrate using RF magnetron sputtering, with indium tin oxide (ITO) as the source and drain electrodes. A carbon-based transistor is fabricated using dip-coating, with gold or palladium as the source and drain electrodes. The entire device undergoes a two-step annealing process: first, a short-duration (20-40 min) low-temperature annealing in an air or oxygen environment to allow the ITZO film to fully absorb oxygen; then, a long-duration (1-1.5 h) high-temperature annealing (300-350°C) annealing in a nitrogen environment to repair defects in the ITZO film. Compared to traditional one-step high-temperature annealing processes for ITZO thin films, this method ensures that the ITZO film can absorb sufficient oxygen for channel defect repair and avoids the carbon-based transistor failure problem caused by high-temperature annealing in air or oxygen environments during monolithic integration with the ITZO thin-film transistor. The CMOS inverter fabricated using this method exhibits high gain at a power supply voltage of 2V (…). V dd At this temperature, the gain reaches 276V / V, far exceeding the gain of existing CMOS inverters based on oxide thin-film transistors and carbon-based transistors (below 60V / V). The CMOS inverter based on ITZO thin-film transistors and carbon-based transistors, fabricated by the dual-temperature dual-atmosphere integration method provided by this invention, has broad application prospects in integrated circuits, wearable electronic devices, and IoT sensors.

[0007] The objective of this invention is achieved through the following technical solution.

[0008] This invention provides a method for fabricating a CMOS inverter based on ITZO thin-film transistors and carbon-based transistors. The method employs a dual-temperature dual-atmosphere integration process, which enables monolithic integration of ITZO thin-film transistors (NMOS) and carbon-based transistors (PMOS). This method solves the process incompatibility problem in monolithic integration of ITZO thin-film transistors and carbon-based transistors. The performance of NMOS and PMOS is well matched, and the constructed CMOS inverter exhibits good electrical performance, high gain, and is suitable for amplifying sensing signals.

[0009] This invention provides a CMOS inverter based on ITZO thin film transistors and carbon-based transistors, which is fabricated using a dual-temperature dual-atmosphere integration method. It includes monolithically integrated ITZO thin film transistors (NMOS) and carbon-based transistors (PMOS).

[0010] The ITZO thin-film transistor and / or carbon-based transistor comprises a substrate, a gate electrode layer, a gate dielectric layer, an active layer, and source / drain electrodes stacked sequentially.

[0011] The present invention discloses a method for fabricating a CMOS inverter based on ITZO thin-film transistors and carbon-based transistors, which employs a dual-temperature dual-atmosphere integration method and specifically includes the following steps:

[0012] 1) Clean the substrate and deposit electrode material on the substrate to form a gate electrode layer;

[0013] 2) A dielectric layer material is deposited above the gate electrode layer using atomic layer deposition technology to form the gate dielectric layer;

[0014] 3) Immerse the entire device in a toluene solution containing carbon nanotubes for 2-4 hours, remove it and dry it to form an irregular network of carbon nanotube film on the surface of the gate dielectric layer;

[0015] 4) The carbon nanotube thin film is patterned using photolithography and reactive ion etching to form the active layer of the carbon-based transistor;

[0016] 5) The source and drain electrodes of the carbon-based transistor are fabricated above the active layer of the carbon-based transistor, and patterned using a metal mask to form the carbon-based transistor;

[0017] 6) Prepare ITZO thin films at different locations on the same layer as the carbon-based transistor above the gate dielectric layer, and pattern them using a metal mask to form the active layer of the ITZO thin film transistor;

[0018] 7) The source and drain electrodes of the ITZO thin film transistor are fabricated above the active layer of the ITZO thin film transistor. The metal mask is used to pattern the electrodes to form the ITZO thin film transistor. There is an overlapping interconnection region between the drain electrode of the ITZO thin film transistor and the drain electrode of the carbon-based transistor.

[0019] 8) Anneal the entire device in an air or oxygen atmosphere at 240-260°C for 20-40 min; then anneal the entire device in a nitrogen atmosphere at 300-350°C for 1-1.5 h to obtain the CMOS inverter.

[0020] Preferably, the substrate in step 1) is one of glass, silicon wafer, and polyimide film; wherein the thickness of the glass and silicon wafer is 0.5-1 cm, and the thickness of the polyimide film is 3-1000 μm.

[0021] Preferably, the electrode material in step 1) is metallic aluminum, which is prepared by one of DC magnetron sputtering, thermal evaporation coating, or electron beam evaporation coating, and the thickness of the gate electrode layer is 30-100 nm.

[0022] Preferably, the dielectric layer material in step 2) is aluminum oxide, and the thickness of the gate dielectric layer is 40-200 nm.

[0023] Preferably, the thickness of the carbon nanotube film in step 3) is 5-10 nm.

[0024] Preferably, in step 5), the source and drain electrodes of the carbon-based transistor are prepared by thermal evaporation coating. The source and drain electrodes of the carbon-based transistor are either Au or Pd, and the thickness is 50-100 nm.

[0025] Preferably, in step 6), an ITZO thin film is prepared using radio frequency magnetron sputtering, where the oxygen partial pressure in the radio frequency magnetron sputtering chamber is 50%-55% and the thickness of the ITZO thin film is 20-60 nm.

[0026] Preferably, in step 7), the source and drain electrodes of the ITZO thin film transistor are prepared by DC magnetron sputtering. The source and drain electrodes of the ITZO thin film transistor are both indium tin oxide with a thickness of 50-100 nm.

[0027] Compared with the prior art, the present invention has the following advantages and beneficial effects:

[0028] 1) This invention proposes for the first time a dual-temperature, dual-atmosphere integration method to achieve monolithic integration of ITZO thin-film transistors and carbon-based transistors. The entire device is first annealed at a low temperature (240-260℃) for a short time (20-40 min) in an air or oxygen environment to allow the ITZO thin film to fully absorb oxygen. Then, it is annealed at a high temperature (300-350℃) for a long time (1-1.5 h) in a nitrogen environment to allow the ITZO thin film to complete defect repair. This method ensures that the ITZO thin film completes defect repair while avoiding the failure of carbon-based transistors caused by prolonged annealing in high-temperature air or oxygen environments, thus solving the process incompatibility problem caused by high-temperature annealing in ITZO thin-film transistor fabrication.

[0029] 2) The NMOS (ITZO thin-film transistor) and PMOS (carbon-based transistor) in the CMOS inverter fabricated by the dual-temperature dual-atmosphere integration method proposed in this invention have good performance matching. The CMOS inverter in… V dd It exhibits a high gain of 276 V / V at 2 V. Compared to single-atmosphere annealed devices, the gain is increased by 362%.

[0030] 3) In the CMOS inverter of this invention, the ITZO thin-film transistor (NMOS) and carbon-based transistor (PMOS) are directly fabricated on the same substrate without the need for transfer operations. This method offers advantages such as low fabrication cost, compatibility with back-end processes, and the ability to fabricate large areas, and is expected to be applied in fields such as flexible integrated circuits, wearable devices, and sensor signal amplification. Attached Figure Description

[0031] Figure 1This is a schematic diagram of the structure of the CMOS inverters prepared in the embodiments and comparative examples of the present invention.

[0032] Figure 2 The figures show the voltage transfer characteristic curves of the NMOS and PMOS of the CMOS inverter in Example 1.

[0033] Figure 3 The voltage transfer characteristic curve and voltage gain of the CMOS inverter in Example 1 are shown.

[0034] Figure 4 The image shows the dynamic response characteristic curve of the CMOS inverter in Example 1.

[0035] Figure 5 This is a diagram demonstrating the amplification of a sine wave signal by a CMOS inverter in Example 1.

[0036] Figure 6 The figures show the voltage transfer characteristic curves of the NMOS and PMOS of the CMOS inverter in Example 2.

[0037] Figure 7 The voltage transfer characteristic curve and voltage gain of the CMOS inverter in Example 2 are shown.

[0038] Figure 8 The voltage transfer characteristic curves of the NMOS and PMOS of the CMOS inverter in Comparative Example 1 are shown.

[0039] Figure 9 The voltage transfer characteristic curve and voltage gain of the CMOS inverter in Comparative Example 1 are shown.

[0040] Figure 10 The voltage transfer characteristic curves of the NMOS and PMOS of the CMOS inverter in Comparative Example 2 are shown.

[0041] Figure 11 The voltage transfer characteristic curve of the CMOS inverter in Comparative Example 2 is shown.

[0042] Figure 12 The voltage transfer characteristic curves of the ITZO thin-film transistor in Comparative Example 3 are shown. Detailed Implementation

[0043] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.

[0044] Example 1

[0045] A CMOS inverter based on ITZO thin-film transistors and carbon-based transistors, fabricated using a dual-temperature dual-atmosphere integration method, comprises ITZO thin-film transistors (NMOS) and carbon-based transistors (PMOS). The structure of this inverter is as follows. Figure 1 As shown, ITZO thin-film transistors and carbon-based transistors are fabricated at different locations on the same surface of the same substrate. The active layers of the ITZO thin-film transistor and the carbon-based transistor are 0.3-1 mm apart, and there is an overlapping interconnection region between the drain electrodes of the ITZO thin-film transistor and the drain electrode of the carbon-based transistor.

[0046] The ITZO thin-film transistor has the following structure: substrate 100, gate electrode layer 200, gate dielectric layer 300, and active layer 400 are stacked sequentially from bottom to top. Source electrode 501 and drain electrode 502 are on the same layer, located above the gate dielectric layer 300, and have overlapping interconnection regions with the active layer 400. A channel exists between the source electrode 501 and drain electrode 502. Substrate 100 is a glass substrate with a thickness of 0.5 cm; gate electrode layer 200 is composed of aluminum with a thickness of 50 nm; gate dielectric layer 300 is composed of aluminum oxide with a thickness of 40 nm; active layer 400 is composed of ITZO with a thickness of 40 nm; active layer 400 is a patterned ITZO thin film; source electrode 501 and drain electrode 502 are both composed of indium tin oxide with a thickness of 80 nm. The length and width of the channel between source electrode 501 and drain electrode 502 are both 300 μm.

[0047] The carbon-based transistor has a structure in which a substrate 100, a gate electrode layer 200, a gate dielectric layer 300, and an active layer 600 are stacked sequentially from bottom to top. The drain electrode 701 and the source electrode 702 are on the same layer, located above the gate dielectric layer 300, and have an overlapping interconnection region with the active layer 600. A channel exists between the drain electrode 701 and the source electrode 702. The substrate 100 is a glass substrate with a thickness of 0.5 cm; the gate electrode layer 200 is composed of aluminum with a thickness of 50 nm; the gate dielectric layer 300 is composed of aluminum oxide with a thickness of 40 nm; the active layer 600 is composed of a carbon nanotube layer with a thickness of 5 nm; the active layer 600 is a patterned, irregular network of carbon nanotube thin film; both the drain electrode 701 and the source electrode 702 are composed of gold with a thickness of 50 nm; the length and width of the channel between the drain electrode 701 and the source electrode 702 are both 100 μm.

[0048] There is an overlapping interconnection region between the drain electrode 701 of the carbon-based transistor and the drain electrode 502 of the ITZO thin-film transistor. The overlapping interconnection region refers to a partial connection between the drain electrode 701 of the carbon-based transistor and the drain electrode 502 of the ITZO thin-film transistor, which is sufficient to allow for conductive connection after overlapping.

[0049] The fabrication steps of the above CMOS inverter are as follows:

[0050] 1) Select a glass substrate with dimensions of 1 cm × 1 cm × 0.5 cm as the substrate. Clean the substrate with water and isopropanol for 20 min each, and dry it in a drying oven at 90℃ for 20 min.

[0051] 2) Using thermal evaporation deposition, a 50 nm thick Al layer is deposited on the substrate as a gate electrode layer by patterning with a metal mask.

[0052] 3) An atomic layer deposition device was used to deposit a 40 nm thick Al2O3 layer as a gate dielectric layer over the entire surface above the gate electrode;

[0053] 4) Immerse the entire device in a toluene solution containing carbon nanotubes for 2 hours, remove it and dry it, and deposit a mesh-like carbon nanotube film on top of the gate dielectric layer.

[0054] 5) Carbon nanotube films are patterned using photolithography and reactive ion etching to serve as the active layer of carbon-based transistors;

[0055] 6) Using thermal evaporation deposition method, a 50 nm thick gold layer is prepared on top of the carbon nanotube layer 600 through metal mask patterning to form the source and drain electrodes of the carbon-based transistor, thus forming a carbon-based transistor with a width-to-length ratio of 100 / 100 μm.

[0056] 7) Using radio frequency magnetron sputtering technology, a 40 nm thick ITZO thin film is prepared at different positions on the same layer as the carbon-based transistor above the gate dielectric layer by patterning with a metal mask. This serves as the active layer of the ITZO thin film transistor. The active layers of the ITZO thin film transistor and the carbon-based transistor are located at different positions on the same surface of the gate dielectric layer, with a distance of 0.8 mm between the two active layers.

[0057] 8) Using DC magnetron sputtering technology, an 80 nm thick indium tin oxide film is fabricated above the active layer of the ITZO thin film transistor by patterning a metal mask. This film serves as the source and drain electrodes of the ITZO thin film transistor, resulting in an ITZO thin film transistor with an aspect ratio of 300 / 300 μm. The drain electrodes of the ITZO thin film transistor and the carbon-based transistor have overlapping interconnection regions.

[0058] 9) Anneal the entire device in air at 250°C for 0.5 h; then anneal the entire device in nitrogen at 300°C for 1 h. The CMOS inverter is thus obtained.

[0059] The voltage transfer characteristic curves of the ITZO thin-film transistor (NMOS) in the CMOS inverter prepared in this embodiment are similar to those of the carbon-based transistor (PMOS). Figure 2 As shown, the threshold voltage of the ITZO thin-film transistor ( V th The value is 0.5V, and the mobility is ( μ FE The value is 17.1 cm. 2 V -1 s -1 Subthreshold swing ( SS ) is 163 mV dec -1 On / off ratio ( I on / I off The value is 3.4 × 10⁻⁶. 5 Carbon-based transistors V th -0.4 V, μ FE It is 11.1 cm 2 V -1 s -1 , SS 172 mV dec -1 , I on / I off 2.6 × 10 5 NMOS and PMOS have good performance matching. The voltage transfer characteristic curve and voltage gain of this CMOS inverter are as follows: Figure 3 As shown, the dynamic response characteristic curve is as follows: Figure 4 As shown, this device demonstrates its rail-to-rail voltage output capability. V dd The voltage gain at 2 V is 276 V / V, representing a 362% increase compared to the nitrogen-annealed single-atmosphere model in Comparative Example 1. This CMOS inverter can be used as a signal amplifier. Figure 5 This demonstrates the amplification capability of the CMOS inverter for a sinusoidal signal with an input amplitude of 20 mV and a frequency of 5 Hz. The amplified signal amplitude is 1.06 V, and the signal gain exceeds 50 times. Compared to the CMOS inverters fabricated by the non-dual-temperature dual-atmosphere integration method in Comparative Examples 1 and 2, this embodiment shows that the dual-temperature dual-atmosphere integration method simultaneously ensures the performance of both ITZO thin-film transistors (NMOS) and carbon-based transistors (PMOS), resulting in a CMOS inverter with excellent electrical performance.

[0060] Example 2

[0061] The preparation method is the same as in Example 1, except that the annealing temperature and time in step 9) are changed. In this example, the entire device is annealed in an air atmosphere at 250°C for 40 min; then the entire device is annealed in a nitrogen atmosphere at 350°C for 1.5 h. Thus, a CMOS inverter based on ITZO thin film transistors and carbon-based transistors, prepared by the dual-temperature dual-atmosphere integration method, is obtained.

[0062] The voltage transfer characteristic curves of the ITZO thin-film transistor (NMOS) in the CMOS inverter prepared in this embodiment are similar to those of the carbon-based transistor (PMOS). Figure 6 As shown, the ITZO thin-film transistor... V th It is 0.5 V. μ FE It is 16.6 cm 2 V -1 s -1 , SS 244 mV dec -1 , I on / I off It is 5.4 × 10 5 Carbon-based transistors V th It is -0.42 V. μ FE It is 18.2 cm. 2 V -1 s -1 , SS 137 mV dec -1 , I on / I off It is 9.7 × 10 6 NMOS and PMOS have good performance matching. The voltage transfer characteristic curve and voltage gain of this CMOS inverter are as follows: Figure 7 As shown, in V dd The voltage gain at 2 V is 225 V / V, which is 275% higher than that of nitrogen single-atmosphere annealing in Comparative Example 1.

[0063] Example 3

[0064] The preparation method is the same as in Example 1, except that the annealing temperature and time in step 9) are changed. In this example, the entire device is annealed in an air atmosphere at 260 °C for 20 min; then the entire device is annealed in a nitrogen atmosphere at 350 °C for 1.5 h. Thus, a CMOS inverter based on ITZO thin film transistors and carbon-based transistors prepared by the dual-temperature dual-atmosphere integration method is obtained.

[0065] Comparative Example 1

[0066] This comparative example uses a single nitrogen atmosphere to fabricate a CMOS inverter. The CMOS inverter was fabricated according to steps 1) to 8) in Example 1, and then annealed at 300°C in a nitrogen atmosphere for 1.5 h. The voltage transfer characteristic curves of the ITZO thin-film transistor (NMOS) and the carbon-based transistor (PMOS) in this CMOS inverter are shown below. Figure 8 As shown, the ITZO thin-film transistor... V th At -0.5 V, compared to Examples 1 and 2, the threshold voltage exhibits a severe negative drift, leading to a deterioration in the performance matching between NMOS and PMOS. The voltage transfer characteristic curve and voltage gain of the CMOS inverter in this comparative example are shown below. Figure 9 As shown, the inverter is in V dd The voltage gain at 2 V is only 59.7 V / V. Compared to the CMOS inverter in Example 1, the gain of the CMOS inverter in this comparative example is reduced by 78%.

[0067] Comparative Example 2

[0068] This comparative example uses a single-temperature dual-atmosphere fabrication of a CMOS inverter. Following steps 1) to 8) of Example 1, the CMOS inverter was fabricated, first annealed at 300°C in air for 0.5 h, and then annealed at 300°C in nitrogen for 1 h. The voltage transfer characteristic curves of the ITZO thin-film transistor (NMOS) and the carbon-based transistor (PMOS) in this CMOS inverter are shown below. Figure 10 As shown. Annealing in a high-temperature air environment at 300℃ causes the carbon-based transistor to fail, and the PMOS loses its switching characteristics. The voltage transfer characteristic curve of the CMOS inverter in this comparative example is shown below. Figure 11 As shown, the inverter is malfunctioning and cannot achieve high-low level conversion.

[0069] Comparative Example 3

[0070] This comparative example uses a single low-temperature fabrication method for ITZO thin-film transistors. The substrate, gate electrode layer, and gate dielectric layer of the ITZO thin-film transistor were fabricated according to steps 1) to 3) of Example 1, and the active layer and source / drain electrodes of the ITZO thin-film transistor were fabricated according to steps 7) and 8) of Example 1. The transistors were then annealed in air at 250°C for 1.5 h. The voltage transfer characteristic curves of the ITZO thin-film transistors are shown below. Figure 12 As shown, the device's V th It is 1.5 V. μ FE It is 0.2 cm 2 V -1 s -1 , SS 166 mVdec -1 , I on / I off It is 7.2 × 10 5 ITZO thin-film transistors were annealed in air at 250°C, but due to insufficient annealing temperature, the ITZO thin film could not complete defect repair. The mobility of the ITZO thin-film transistor was only 0.2 cm⁻¹. 2 V -1 s -1 Compared with the ITZO thin-film transistor in the CMOS inverter prepared in Example 1, the ITZO thin-film transistor in this comparative example showed a 98.8% reduction in mobility and a significant positive shift in threshold voltage. The results indicate that the ITZO thin film must be annealed at temperatures exceeding 250°C to complete defect repair and obtain an ITZO thin-film transistor with performance well-matched to carbon-based transistors.

Claims

1. A method for fabricating a CMOS inverter based on ITZO thin-film transistors and carbon-based transistors, characterized in that, The CMOS inverter is fabricated using a dual-temperature dual-atmosphere integration method and comprises a monolithically integrated ITZO thin-film transistor and a carbon-based transistor. The dual-temperature, dual-atmosphere integration method includes: annealing the monolithically integrated ITZO thin-film transistor and carbon-based transistor as a whole. The annealing process consists of two steps: first, annealing at 240-260°C for 20-40 min in an air or oxygen environment, and then annealing at 300-350°C for 1-1.5 h in a nitrogen environment; specifically, it includes the following steps: 1) Clean the substrate and deposit electrode material on the substrate to form a gate electrode layer; 2) Deposit a dielectric layer material above the gate electrode layer to form a gate dielectric layer; 3) Immerse the entire device in a solution containing carbon nanotubes, remove it and dry it to form a carbon nanotube film on the surface of the gate dielectric layer; 4) Patterning carbon nanotube films to form the active layer of carbon-based transistors; 5) The source and drain electrodes of the carbon-based transistor are fabricated above the active layer of the carbon-based transistor, and patterned using a metal mask to form the carbon-based transistor; 6) Prepare ITZO thin films at different locations on the same layer as the carbon-based transistor above the gate dielectric layer, and pattern them using a metal mask to form the active layer of the ITZO thin film transistor; 7) The source and drain electrodes of the ITZO thin film transistor are fabricated above the active layer of the ITZO thin film transistor. The metal mask is used to pattern the electrodes to form the ITZO thin film transistor. There is an overlapping interconnection region between the drain electrode of the ITZO thin film transistor and the drain electrode of the carbon-based transistor. 8) Anneal the entire device in an air or oxygen atmosphere at 240-260℃ for 20-40 min; then anneal the entire device in a nitrogen atmosphere at 300-350℃ for 1-1.5 h to obtain the CMOS inverter.

2. The preparation method according to claim 1, characterized in that, The substrate in step 1) is one of glass, silicon wafer, or polyimide film; wherein the thickness of glass and silicon wafer is 0.5-1 cm, and the thickness of polyimide film is 3-1000 μm.

3. The preparation method according to claim 1, characterized in that, The electrode material in step 1) is aluminum, which is prepared by one of the following methods: DC magnetron sputtering, thermal evaporation coating, or electron beam evaporation coating. The thickness of the gate electrode layer is 30-100 nm.

4. The preparation method according to claim 1, characterized in that, The dielectric layer material in step 2) is aluminum oxide, and the thickness of the gate dielectric layer is 40-200 nm.

5. The preparation method according to claim 1, characterized in that, The thickness of the carbon nanotube film in step 3) is 5-10 nm.

6. The preparation method according to claim 1, characterized in that, In step 5), the source and drain electrodes of the carbon-based transistor are prepared by thermal evaporation coating. The source and drain electrodes of the carbon-based transistor are either Au or Pd, and the thickness is 50-100 nm.

7. The preparation method according to claim 1, characterized in that, In step 6), an ITZO thin film is prepared using radio frequency magnetron sputtering. The oxygen partial pressure in the radio frequency magnetron sputtering chamber is 50%-55%, and the thickness of the ITZO thin film is 20-60 nm.

8. The preparation method according to claim 1, characterized in that, In step 7), the source and drain electrodes of the ITZO thin film transistor are prepared by DC magnetron sputtering. The source and drain electrodes of the ITZO thin film transistor are both indium tin oxide with a thickness of 50-100 nm.

9. A CMOS inverter based on ITZO thin-film transistors and carbon-based transistors, prepared by the method according to any one of claims 1-8.

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