An image sensor and a method of manufacturing the same

Abstract

The application provides an image sensor and a preparation method thereof, which comprises the following steps: providing a device substrate, forming a first sacrificial layer, a first epitaxial layer, a second sacrificial layer and a second epitaxial layer on the device substrate; forming a plurality of support columns penetrating through the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer and extending to the device substrate; forming a release groove; removing the first sacrificial layer to form a first cavity and removing the second sacrificial layer to form a second cavity; forming a first isolation layer in the first cavity and forming a light shielding structure in the second cavity; forming a plurality of transistors on the second epitaxial layer; forming an interlayer dielectric layer covering the second epitaxial layer and the transistors, bonding the support substrate and the interlayer dielectric layer; and forming a plurality of photodiode regions in the device substrate.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and more specifically to an image sensor and a method for fabricating the same. Background Technology

[0002] Complementary Metal Oxide Semiconductor (CMOS) image sensor (CIS) technology has been widely used in applications such as still digital cameras, digital camcorders, medical imaging devices, and automotive imaging devices. CMOS image sensors are mainly divided into two structures: front-side illumination CMOS image sensors (FSI) and back-side illumination CMOS image sensors (BSI). Compared to FSI image sensors, BSI image sensors place the photosensitive area, including the photodiode, on top of the circuitry, reducing light loss due to factors such as metal line reflection and dielectric layer absorption. This significantly increases the photoelectric conversion efficiency and noticeably improves image quality.

[0003] However, with the development of advanced manufacturing processes, the requirements for stored charge in BSI image sensors are becoming increasingly stringent. In traditional BSI image sensors, a latch-up effect exists between the source and drain of the transistors, causing crosstalk as light passes through the photodiode (PD) region and enters the floating diffuser (FD) region, thus affecting the image sensor's quality. Therefore, improving image sensor quality, avoiding the transistor latch-up effect, and mitigating crosstalk are pressing technical challenges that need to be addressed. Summary of the Invention

[0004] The summary section introduces a series of simplified concepts, which will be further explained in detail in the detailed description section. This summary section is not intended to limit the key features and essential technical features of the claimed technical solution, nor is it intended to determine the scope of protection of the claimed technical solution.

[0005] To address the existing problems, this application provides a method for fabricating an image sensor, comprising: providing a device substrate; sequentially forming a first sacrificial layer, a first epitaxial layer, a second sacrificial layer, and a second epitaxial layer on the device substrate; forming a plurality of support pillars penetrating the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, and the first sacrificial layer and extending into the device substrate; forming at least one release trench penetrating the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, and the first sacrificial layer; using the release trench as a release channel, etching away the first sacrificial layer to form a [missing information - likely a structure or feature] between the first epitaxial layer and the device substrate. A first cavity is formed, and the second sacrificial layer is etched away to form a second cavity between the first epitaxial layer and the second epitaxial layer; a first isolation layer is formed in the first cavity, and a light-shielding structure is formed in the second cavity; a plurality of transistors are formed on the second epitaxial layer, each transistor including a drain region formed in the second epitaxial layer; an interlayer dielectric layer is formed covering the second epitaxial layer and the plurality of transistors; a support substrate is provided, and the support substrate and the interlayer dielectric layer are bonded together; a plurality of photodiode regions are formed in the device substrate, wherein each photodiode region corresponds to an electrically connected drain region of one of the transistors.

[0006] For example, the image sensor includes a plurality of pixel units, each pixel unit including at least one photodiode region and at least two transistors, and a support pillar is further disposed between any two adjacent transistors in each pixel unit, the support pillar serving as an isolation structure; and / or the image sensor includes a plurality of pixel units, the drain region of at least one transistor in each pixel unit serving as a floating diffusion region, and the floating diffusion region and photodiode region of each pixel unit are spaced apart in the thickness direction of the device substrate.

[0007] For example, forming a first isolation layer in the first cavity and a light-shielding structure in the second cavity includes: depositing an isolation material layer to form a first isolation layer in the first cavity, the first isolation layer filling the first cavity, and the isolation material layer also being deposited on the surface of the second epitaxial layer facing the first epitaxial layer to form a second isolation layer covering the surface of the second epitaxial layer facing the first epitaxial layer, and the isolation material layer also being deposited on the surface of the first epitaxial layer facing the second epitaxial layer to form a third isolation layer covering the surface of the first epitaxial layer facing the second epitaxial layer; depositing a light-shielding layer to fill the portion of the second cavity located between the second isolation layer and the third isolation layer, and the light-shielding structure including the first and second isolation layers, the second and third isolation layers, and the light-shielding layer.

[0008] For example, the insulating material layer is also deposited on the sidewall of the release trench, and the light-shielding layer fills the release trench.

[0009] For example, after forming the light-shielding structure and before forming the plurality of transistors, the fabrication method further includes: forming a plurality of first conductive plugs sequentially penetrating the second epitaxial layer, the light-shielding structure, the first epitaxial layer, and the first isolation layer, wherein the plurality of first conductive plugs are spaced apart, and each first conductive plug is used to electrically connect to a predetermined photodiode region; and before bonding the support substrate and the interlayer dielectric layer, the fabrication method further includes: forming a plurality of conductive interconnect structures in the interlayer dielectric layer, wherein each conductive interconnect structure is electrically connected to at least one first conductive plug and at least one drain region of the transistor.

[0010] For example, the first conductive plug further extends along a first direction, wherein the image sensor includes a plurality of pixel units, each pixel unit including at least one photodiode region and at least two transistors, a support post is disposed between two adjacent pixel units in a second direction, and the support post further extends along the first direction, the first direction being perpendicular to the thickness direction of the device substrate; each release trench is disposed between two adjacent pixel units in the first direction, and the release trench further extends along the second direction; wherein the first direction, the second direction and the thickness direction of the device substrate are perpendicular to each other.

[0011] For example, after bonding the support substrate and the interlayer dielectric layer, before forming a plurality of photodiode regions in the device substrate, or after forming a plurality of photodiode regions in the device substrate, the method further includes: thinning the side of the device substrate opposite to the first epitaxial layer to expose the end of the support pillar away from the interlayer dielectric layer.

[0012] For example, the step of forming a plurality of photodiode regions in the device substrate is performed before the formation of the first sacrificial layer.

[0013] For example, it further includes: forming a passivation layer on the side of the device substrate opposite to the first isolation layer; forming a plurality of grid structures on the passivation layer, wherein the image sensor includes a plurality of pixel units, a grid structure is disposed between adjacent pixel units, a grid opening is formed between adjacent grid structures, and the grid opening exposes the surface of the passivation layer; embedding a color filter layer in the grid opening; and forming a plurality of microlenses on the color filter layer, the plurality of microlenses corresponding to the plurality of pixel units.

[0014] This application also provides an image sensor, which is prepared using the aforementioned preparation method.

[0015] The image sensor and its fabrication method provided in this application can effectively prevent latch-up between the source and drain of the transistor by forming an isolation layer and a light-shielding structure between the photodiode region and the floating diffusion region, thereby avoiding crosstalk between the photodiode region and the floating diffusion region and improving the quality of the image sensor. Attached Figure Description

[0016] The following drawings, which are incorporated herein by reference as part of this invention, are provided for understanding the invention. The drawings illustrate embodiments of the invention and their descriptions, serving to explain the principles of the invention.

[0017] In the attached image:

[0018] Figure 1 A flowchart illustrating an image sensor fabrication method according to a specific embodiment of this application is shown;

[0019] Figure 2 A schematic diagram of the device obtained by sequentially implementing the image sensor fabrication method in the related art is shown;

[0020] Figures 3 to 21 The diagram illustrates a schematic representation of the device obtained by sequentially implementing a method for fabricating an image sensor according to a specific embodiment of this application. Detailed Implementation

[0021] The invention will now be described more fully with reference to the accompanying drawings, which illustrate embodiments of the invention. However, the invention can be embodied in various forms and should not be construed as limited to the embodiments set forth herein. Rather, providing these embodiments will make the disclosure thorough and complete, and will fully convey the scope of the invention to those skilled in the art. In the drawings, for clarity, the dimensions and relative dimensions of layers and regions may be exaggerated. The same reference numerals denote the same elements throughout.

[0022] It should be understood that when an element or layer is referred to as "on," "adjacent to," "connected to," or "coupled to" other elements or layers, it may be directly on, adjacent to, connected to, or coupled to other elements or layers, or there may be intervening elements or layers. Conversely, when an element is referred to as "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" other elements or layers, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc., may be used to describe various elements, components, areas, layers, and / or portions, these elements, components, areas, layers, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, area, layer, or portion from another element, component, area, layer, or portion. Therefore, without departing from the teachings of this invention, the first element, component, area, layer, or portion discussed below may be referred to as the second element, component, area, layer, or portion.

[0023] Spatial relation terms such as “below,” “under,” “below,” “under,” “above,” “above,” etc., are used herein for convenience of description to describe the relationship between one element or feature shown in the figure and other elements or features. It should be understood that, in addition to the orientation shown in the figure, spatial relation terms are intended to also include different orientations of the device in use and operation. For example, if the device in the figure is flipped, then the element or feature described as “below” or “under” the other element or feature will be oriented “above” the other element or feature. Therefore, the exemplary terms “below” and “under” can include both upper and lower orientations. The device may be otherwise oriented (rotated 90 degrees or otherwise) and the spatial descriptive terms used herein will be interpreted accordingly.

[0024] The terminology used herein is for the purpose of describing particular embodiments only and is not intended to limit the invention. When used herein, the singular forms “a,” “an,” and “the” are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the terms “comprise” and / or “comprising,” when used in this specification, identify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. When used herein, the term “and / or” includes any and all combinations of the associated listed items.

[0025] To fully understand this application, detailed steps and structures will be presented in the following description to illustrate the technical solutions proposed in this application. Preferred embodiments of this application are described in detail below; however, in addition to these detailed descriptions, this application may have other implementation methods.

[0026] With the rapid development of semiconductor technology, the requirements for stored charge in BSI image sensors are becoming increasingly stringent. For example... Figure 2 As shown, in a traditional BSI image sensor, there is a latch-up effect between the source 110 and drain 120 of the transistor (i.e., a latch-up effect exists between the photodiode (PD) region and the floating diffusion (FD) region, such as... Figure 2 As indicated by the middle arrow, photons pass through the photodiode (PD) region and enter the floating diffusion (FD) region, causing crosstalk and affecting the image sensor quality. Therefore, improving the image sensor quality, avoiding transistor latch-up, and mitigating crosstalk are pressing technical problems that need to be solved.

[0027] Therefore, in view of the aforementioned technical problems, this application proposes a method for fabricating an image sensor, such as... Figure 1 As shown, it mainly includes the following steps:

[0028] Step S1: Provide a device substrate, and sequentially form a first sacrificial layer, a first epitaxial layer, a second sacrificial layer, and a second epitaxial layer on the device substrate;

[0029] Step S2: Form a plurality of support pillars that penetrate the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer and extend into the device substrate;

[0030] Step S3: Form at least one release trench that penetrates the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, and the first sacrificial layer;

[0031] Step S4: Using the release trench as a release channel, the first sacrificial layer is etched away to form a first cavity between the first epitaxial layer and the device substrate, and the second sacrificial layer is etched away to form a second cavity between the first epitaxial layer and the second epitaxial layer.

[0032] Step S5: A first isolation layer is formed in the first cavity, and a light-shielding structure is formed in the second cavity;

[0033] Step S6: A plurality of transistors are formed on the second epitaxial layer, each transistor including a drain region formed in the second epitaxial layer;

[0034] Step S7: Form an interlayer dielectric layer covering the second epitaxial layer and multiple transistors;

[0035] Step S8: Provide a support substrate and bond the support substrate and the interlayer dielectric layer;

[0036] Step S9: A plurality of photodiode regions are formed in the device substrate, wherein each photodiode region corresponds to the drain region of a transistor electrically connected to it.

[0037] The image sensor fabrication method of this application, by forming an isolation layer and a light-shielding structure between the photodiode region and the floating diffusion region respectively, can effectively prevent latch-up effect between the source and drain of the transistor, thereby avoiding crosstalk between the photodiode region and the floating diffusion region and improving the quality of the image sensor.

[0038] Below, for reference Figure 1 as well as Figures 3 to 21 The method for fabricating the image sensor of this application is described in detail, wherein, Figure 1 A flowchart illustrating a method for fabricating an image sensor according to a specific embodiment of this application is shown. Figures 3 to 21 The accompanying drawings show a schematic diagram of the device obtained by sequentially implementing the image sensor fabrication method according to a specific embodiment of the present application. Figure (a) shows a top view of the device obtained by sequentially implementing the image sensor fabrication method according to a specific embodiment of the present application, and Figure (b) shows a cross-sectional view of the device obtained by sequentially implementing the image sensor fabrication method according to a specific embodiment of the present application.

[0039] For example, the method for fabricating the image sensor of this application includes the following steps:

[0040] First, step S1 is performed to provide a device substrate, and a first sacrificial layer, a first epitaxial layer, a second sacrificial layer, and a second epitaxial layer are sequentially formed on the device substrate.

[0041] In one example, such as Figure 3 As shown, a device substrate 201 is provided. The material of the device substrate 201 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon on dielectric (SOI), silicon on dielectric stacked on dielectric (SSOI), silicon germanium on dielectric stacked on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI); or it may be a double-sided polished wafer (DSP), a ceramic substrate such as alumina, a quartz, or a glass substrate, etc. Although several examples of materials that can form a device substrate have been described herein, any material that can serve as a device substrate falls within the spirit and scope of the invention. In this embodiment, the device substrate 201 is a silicon substrate.

[0042] In one example, such as Figure 4As shown, a first sacrificial layer 202 is formed on the device substrate 201. Exemplarily, the material of the first sacrificial layer 202 includes, but is not limited to, amorphous silicon, polycrystalline silicon, silicon-germanium (SiGe), or other suitable materials. The process method for forming the first sacrificial layer 202 can be selected as needed, for example, chemical vapor deposition (CVD), molecular beam epitaxy (MBE), or other suitable epitaxial techniques, and is not specifically limited thereto. In this embodiment, the material of the first sacrificial layer 202 is silicon-germanium, and the first sacrificial layer 202 facilitates the subsequent formation of a first cavity between the device substrate 201 and the first epitaxial layer 203.

[0043] In one example, such as Figure 4 As shown, a first epitaxial layer 203 is formed on the first sacrificial layer 202. Exemplarily, the material of the first epitaxial layer 203 includes, but is not limited to, silicon, silicon germanium, silicon carbide, or other suitable epitaxial materials. The process method for forming the first epitaxial layer 203 can be selected as needed, for example, metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), molecular beam epitaxy (MBE), or other suitable techniques, and is not specifically limited thereto. In this embodiment, the material of the first epitaxial layer 203 is silicon, the same as the material of the device substrate 201. Therefore, the silicon formed by epitaxial growth can have the same crystal structure and orientation as the device substrate, which helps to maintain high-quality electronic properties.

[0044] In one example, such as Figure 4 As shown, a second sacrificial layer 204 is formed on the first epitaxial layer 203. The material of the second sacrificial layer 204 is the same as or different from that of the first sacrificial layer 202. The process for forming the second sacrificial layer 204 is the same as that for the first sacrificial layer, and will not be described in detail here. Next, a second epitaxial layer 205 is formed on the second sacrificial layer 204. The material of the second epitaxial layer 205 is the same as that of the first epitaxial layer 203, or, in some examples, the first and second epitaxial layers can be different semiconductor materials. The process for forming the second sacrificial layer 204 is the same as that for the first epitaxial layer, and will not be described in detail here. In this embodiment, the material of the second sacrificial layer 204 is silicon-germanium, and the material of the second epitaxial layer 205 is silicon. The second sacrificial layer 204 facilitates the subsequent formation of a second cavity between the first epitaxial layer 203 and the second epitaxial layer 205.

[0045] Next, step S2 is performed to form a plurality of support pillars that penetrate the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer and extend into the device substrate.

[0046] In one example, such as Figure 5 and Figure 6As shown, the step of forming a plurality of support pillars 207 that penetrate the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202 and extend into the device substrate 201 includes:

[0047] First, the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202 and the device substrate 201 are etched to form a support trench 206 that penetrates the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203 and the first sacrificial layer 202 and extends into the device substrate 201. The support trench 206 extends along a first direction that is perpendicular to the thickness direction of the device substrate 201. Specifically, a patterned photoresist layer is formed on the surface of the second epitaxial layer 205, exposing the area and position corresponding to the support trench 206. Using the photoresist layer as a mask, the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, and the device substrate 201 are etched to form multiple support trenches 206. Each support trench 206 penetrates the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, and extends into the device substrate 201. Afterward, the photoresist layer is removed. The etching of the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, the first sacrificial layer 202, and the device substrate 201 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching.

[0048] Next, support pillars 207 are formed in the support trench 206. Specifically, support material is filled into the support trench 206, wherein the support material includes, but is not limited to, silicon oxide, silicon nitride, polysilicon, or other suitable materials. The process methods for forming the support pillars 207 include, but are not limited to, chemical vapor deposition (CVD), atomic layer deposition (ALD), high-density plasma chemical vapor deposition (HDP-CVD), or physical vapor deposition (PVD), etc., and are not specifically limited thereto. The formed support pillars 207 extend along a first direction, which is perpendicular to the thickness direction of the device substrate 201. The support pillars 207 are also disposed between two adjacent pixel units formed subsequently in the second direction and between any two adjacent transistors in each pixel unit, serving as isolation structures. After forming the support pillars 207, the support material can also be planarized, for example, by using chemical mechanical polishing (CMP) to remove excess support material on the second epitaxial layer 205, so that the second epitaxial layer 205 has a flat surface. The number of support pillars can be reasonably set according to actual needs, such as one, two, three, or more. Optionally, support pillars are formed in the edge region of the second epitaxial layer to avoid the support pillars occupying too much of the device area in the middle region. In a specific example, the number of support pillars is two, and the two support pillars are spaced apart in the second direction. Preferably, multiple support pillars are disposed between two adjacent pixel units and between adjacent transistors in each pixel unit in the second direction, serving as an isolation structure. The step of forming the isolation structure by shallow trench isolation or local oxidation can be omitted in the transistor formation step. The support pillar structure of this application can provide strength support for the formation of cavities and can also be used for regional isolation, which can simplify the process and reduce costs.

[0049] Continue, execute step S3 to form at least one release trench penetrating the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, and the first sacrificial layer.

[0050] In one example, such as Figure 7As shown, the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, and the first sacrificial layer 202 are etched to form at least one release trench 240, which extends along a second direction. Specifically, a patterned photoresist layer is formed on the surface of the second epitaxial layer 205, exposing the area and position corresponding to the release trench 240 to be formed. The second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, and the first sacrificial layer 202 are etched using the photoresist layer as a mask to form at least one release trench 240, and then the photoresist layer is removed. The etching of the second epitaxial layer 205, the second sacrificial layer 204, the first epitaxial layer 203, and the first sacrificial layer 202 can be performed using dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, or other conventional etching processes, and is not specifically limited to these methods. Each release trench 240 is also disposed between two adjacent pixel units subsequently formed in a first direction, the first direction being perpendicular to the thickness direction of the device substrate 201, and the second direction being perpendicular to the first direction and also perpendicular to the thickness direction of the device substrate 201.

[0051] Next, step S4 is performed, using the release trench as a release channel, etching away the first sacrificial layer to form a first cavity between the first epitaxial layer and the device substrate, and etching away the second sacrificial layer to form a second cavity between the first epitaxial layer and the second epitaxial layer.

[0052] In one example, such as Figure 8 As shown, the first sacrificial layer 202 is etched away using the release trench 240 as the release channel to form a first cavity 208 between the first epitaxial layer 203 and the device substrate 201, and the second sacrificial layer 204 is etched away to form a second cavity 209 between the first epitaxial layer 203 and the second epitaxial layer 205. Specifically, conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, plasma etching, and wet etching can be used to remove the first sacrificial layer 202 between the first epitaxial layer 203 and the device substrate 201, and to remove the second sacrificial layer 204 between the first epitaxial layer 203 and the second epitaxial layer 205. For example, a gaseous hydrofluoric acid (VHF) etching process can be used to release the sacrificial layer, that is, gaseous hydrofluoric acid is introduced into a release trench, and the first sacrificial layer 202 and the second sacrificial layer 204 are removed by etching through the release trench, thereby forming a first cavity 208 between the first epitaxial layer 203 and the device substrate 201 and a second cavity 209 between the first epitaxial layer 203 and the second epitaxial layer 205.

[0053] Then, step S5 is performed to form a first isolation layer in the first cavity and a light-shielding structure in the second cavity.

[0054] In one example, such as Figure 9 and Figure 10 As shown, the steps of forming a first isolation layer 210 in the first cavity 208 and a light-shielding structure 211 in the second cavity 209 include:

[0055] First, an isolation material layer 20 is deposited, filling the first cavity 208 to form a first isolation layer 210. Second, the isolation material layer 20 is also deposited on the surface of the second epitaxial layer 205 facing the first epitaxial layer 203 to form a second isolation layer 2110 covering the surface of the second epitaxial layer 205 facing the first epitaxial layer 203. This isolation material layer is also deposited on the surface of the first epitaxial layer 203 facing the second epitaxial layer 205 to form a third isolation layer 2111 covering the surface of the first epitaxial layer 203 facing the second epitaxial layer 205. This isolation material layer is also deposited on a portion of the sidewalls of the support post 207 and the sidewalls of the release trench 240. Exemplarily, the material of the isolation material layer includes, but is not limited to, oxides, such as silicon oxide, etc., and is not specifically limited thereto. The process methods for forming the first isolation layer 210, the second isolation layer 2110, and the third isolation layer 2111 include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD), etc., and are not specifically limited to these methods. The isolation layers can provide a physical barrier to prevent damage caused by subsequent processing, thereby improving the reliability and stability of the device, and they can also serve an insulating function.

[0056] Next, a light-shielding layer 2112 is deposited to fill the portion of the second cavity 209 located between the second isolation layer 2110 and the third isolation layer 2111, wherein the light-shielding layer 2112 also fills the release trench 240. In one example, the release trench may be located between two adjacent pixel units in the first direction, and the release trench may extend in the second direction. By filling the light-shielding structure in the release trench 240, crosstalk problems between two adjacent pixel units in the first direction can be prevented. Exemplarily, the material of the light-shielding layer 2112 includes, but is not limited to, titanium nitride, tungsten, copper, aluminum, or other suitable light-shielding materials, and the light-shielding layer 2112 is an opaque material or a reflective material. The process methods for forming the light-shielding layer 2112 include, but are not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD), etc., and are not specifically limited thereto. By forming a first isolation layer and a light-shielding structure between the subsequently formed photodiode region and the floating diffusion region, light can be prevented from incident on the floating diffusion region, effectively preventing latch-up between the source and drain of the transistor, thereby avoiding crosstalk between the photodiode region and the floating diffusion region and improving the quality of the image sensor.

[0057] In one example, such as Figures 11 to 12As shown, after forming the light-shielding structure 211, the light-shielding layer and the isolation material layer on the second epitaxial layer 205 are removed. Specifically, the isolation material layer and the light-shielding layer on the second epitaxial layer 205 can be removed by, but not limited to, chemical mechanical polishing. Then, wet cleaning can be performed to remove the material remaining from the chemical mechanical polishing process, so as not to affect the performance of the device.

[0058] Continue, proceed to step S6, to form a plurality of transistors on the second epitaxial layer, each transistor including a drain region formed in the second epitaxial layer.

[0059] In one example, such as Figure 13 As shown, the fabrication method of this application further includes: after forming the aforementioned light-shielding structure and before forming the plurality of transistors, forming a plurality of first conductive plugs 213 that sequentially penetrate the second epitaxial layer 205, the light-shielding structure 211, the first epitaxial layer 203, and the first isolation layer 210, the step specifically includes:

[0060] First, the second epitaxial layer 205, the light-shielding structure 211, the first epitaxial layer 203, and the first isolation layer 210 are etched to form multiple contact holes, wherein the bottom of the contact holes exposes a portion of the surface of the device substrate 201. Specifically, a patterned photoresist layer is formed on the second epitaxial layer 205, exposing the area and position corresponding to the contact holes. Using the photoresist layer as a mask, the second epitaxial layer 205, the light-shielding structure 211, the first epitaxial layer 203, and the first isolation layer 210 are etched to form multiple contact holes, and then the photoresist layer is removed. The etching of the second epitaxial layer 205, the light-shielding structure 211, the first epitaxial layer 203, and the first isolation layer 210 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, without specific limitations. The formed contact holes are used to subsequently form the first conductive plug 213. Optionally, the top view shape of the contact hole can be rectangular, square, circular, or other suitable shape.

[0061] Then, before forming the first conductive plug 213, the method of this application further includes filling the contact hole with an insulating material, the insulating material covering the sidewall of the contact hole to form an insulating isolation layer 214. The insulating material includes, but is not limited to, oxides, such as silicon oxide, etc., and is not specifically limited thereto. The process methods for forming the insulating isolation layer 214 include, but are not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). The insulating isolation layer 214 can be used to electrically isolate the first conductive plug 213 from the epitaxial layer outside it.

[0062] Finally, conductive material is filled into the contact hole to form a first conductive plug 213. Exemplarily, the conductive material includes, but is not limited to, titanium nitride, tungsten, copper, aluminum, or other suitable conductive materials. The process methods for forming the first conductive plug 213 include, but are not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD), and are not specifically limited thereto. The formed first conductive plug 213 penetrates along the substrate thickness direction through the second epitaxial layer 205, the light-shielding structure 211, the first epitaxial layer 203, and the first isolation layer 210. The bottom of the first conductive plug 213 contacts the surface of the device substrate 201. Each first conductive plug 213 is subsequently used for electrical connection to a photodiode region in the device substrate. After the first conductive plug 213 is formed, a planarization process can be performed to remove excess insulating and conductive materials on the second epitaxial layer 205. For example, chemical mechanical polishing (CMP) can be used to remove excess insulating and conductive materials on the second epitaxial layer 205, so that the second epitaxial layer 205 has a flat surface and improves the reliability of the device.

[0063] Next, a plurality of transistors are formed on the second epitaxial layer, each transistor including a gate structure formed on the second epitaxial layer, and a source region and a drain region formed on both sides of the gate structure in the second epitaxial layer.

[0064] In one example, such as Figure 14 As shown, the steps for forming transistor 215 may include:

[0065] A gate structure 2150 is formed on the second epitaxial layer 205. Specifically, firstly, a gate dielectric layer is formed on the second epitaxial layer 205. The material of the gate dielectric layer includes, but is not limited to, silicon dioxide, and the method for forming the gate dielectric layer includes, but is not limited to, chemical vapor deposition (CVD) or thermal oxidation. Secondly, a gate layer is formed on the gate dielectric layer. The material of the gate layer includes, but is not limited to, polysilicon, and the method for forming the gate layer includes, but is not limited to, chemical vapor deposition (CVD) or physical vapor deposition (PVD). Finally, a patterned photoresist layer is formed on the gate layer. The patterned photoresist layer defines the region and position of the gate structure. The gate layer and the gate dielectric layer are etched using the patterned photoresist layer as a mask to form the gate structure 2150 on the second epitaxial layer 205. Afterward, the photoresist layer is removed. The etching of the gate layer and the gate dielectric layer can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching. No specific limitation is made in this regard. After forming the gate structure, sidewalls (not shown) can be formed on both sides of the gate structure. These sidewalls protect the edges of the gate structure from damage during subsequent processes. The materials used for the sidewalls include, but are not limited to, insulating materials such as silicon nitride. The gate structure is used to control the transfer of accumulated charge in the photodiode to the floating diffusion region, thereby achieving an efficient signal readout mechanism.

[0066] It is worth mentioning that the number of gate structures can be determined based on the number of transistors in the image sensor.

[0067] Next, a lightly doped region is formed in the second epitaxial layer 205 below both sides of the gate structure 2150 by ion implantation, introducing a low concentration of impurities. This lightly doped region improves the short-channel effect and enhances device reliability. Then, highly doped source regions 2151 and drain regions 2152 are formed outside the lightly doped region to provide a low-resistance path and enhance current drive capability. The ion implantation concentration of the highly doped source regions 2151 and drain regions 2152 is greater than that of the lightly doped region. Annealing is performed after ion implantation. Since ion implantation causes lattice damage to the silicon wafer, annealing can repair this damage. Furthermore, annealing can activate the implanted ions, thereby improving the performance of the image sensor.

[0068] Then, step S7 is performed to form an interlayer dielectric layer covering the second epitaxial layer and multiple transistors.

[0069] In one example, as Figure 15As shown, before forming the interlayer dielectric layer 218, the process further includes forming a dielectric layer 216 covering the transistor 215 and the second epitaxial layer 205. Exemplarily, the material of the dielectric layer 216 includes, but is not limited to, silicon dioxide, a low-dielectric-constant material, or other suitable dielectric materials. Methods for forming the dielectric layer 216 include, but are not limited to, deposition processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), and are not specifically limited thereto.

[0070] Next, a plurality of second conductive plugs 217 are formed in the dielectric layer 216, each second conductive plug 217 being electrically connected to the drain region 2152 of the transistor 215. Specifically, a patterned photoresist layer is formed on the dielectric layer 216, exposing the area and position corresponding to the second conductive plugs 217; the dielectric layer 216 is etched using the photoresist layer as a mask to form a plurality of etched holes penetrating the dielectric layer 216, and then the photoresist layer is removed; the etching of the dielectric layer 216 can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, without specific limitations. Afterwards, insulating material is filled into the etched holes, covering the sidewalls of the etched holes to form an insulating layer. The insulating material includes, but is not limited to, oxides, such as silicon oxide, without specific limitations; the process for forming the insulating layer includes, but is not limited to, chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or atomic layer deposition (ALD). Finally, conductive material is filled into the etched holes to form a second conductive plug 217. Exemplarily, the conductive material includes, but is not limited to, titanium nitride, tungsten, copper, aluminum, or other suitable conductive materials. The process method for forming the second conductive plug 217 includes, but is not limited to, physical vapor deposition (PVD), atomic layer deposition (ALD), or chemical vapor deposition (CVD), etc., and is not specifically limited thereto. The second conductive plug also extends along a first direction, and each second conductive plug 217 is electrically connected to the drain region 2152 of the transistor 215. After forming the second conductive plug 217, planarization can be performed to remove excess insulating and conductive material from the dielectric layer 216, for example, by using chemical mechanical polishing (CMP) to remove excess insulating and conductive material from the dielectric layer 216, so that the dielectric layer 216 has a flat surface, improving the reliability of the device. In one example, a conductive plug can also be formed that penetrates the dielectric layer 216 and is electrically connected to the first conductive plug 213, so that it can be part of the first conductive plug 213 to bring out the corresponding photodiode region. Then, an interlayer dielectric layer 218 is formed on the dielectric layer 216. The interlayer dielectric layer 218 may include multiple layers of interlayer dielectric material. The method for forming the interlayer dielectric layer 218 includes, but is not limited to, deposition processes such as chemical vapor deposition (CVD) or atomic layer deposition (ALD), and is not specifically limited thereto. Next, a plurality of conductive interconnect structures 219 are formed in the interlayer dielectric layer 218. Each conductive interconnect structure 219 is electrically connected to at least one first conductive plug 213 and at least one drain region of a transistor. Specifically, each conductive interconnect structure 219 is also electrically connected to at least one second conductive plug 217. The first conductive plug 213 is electrically connected to the photodiode region 231, and the second conductive plug 217 is electrically connected to the drain region 2152 of the transistor 215.For example, the material of the conductive interconnect structure 219 includes, but is not limited to, materials such as copper or aluminum, and the method of depositing the conductive interconnect structure material includes, but is not limited to, processes such as chemical vapor deposition (CVD), and there is no specific limitation in this regard.

[0071] It is worth mentioning that the conductive interconnect structure 219 may include multiple layers of metal stacked sequentially, and plugs disposed between adjacent metal layers, thereby forming a stacked conductive interconnect structure 219. Specifically, the method for forming the conductive interconnect structure can be any suitable method, which will not be elaborated here.

[0072] Continue, proceed to step S8, provide a support substrate, and bond the support substrate and the interlayer dielectric layer.

[0073] In one example, such as Figure 16 As shown, a support substrate 301 is provided. The material of the support substrate 301 includes, but is not limited to, at least one of the following materials: silicon (Si), germanium (Ge), silicon germanium (SiGe), silicon carbide (SiC), silicon germanium carbon (SiGeC), indium arsenide (InAs), gallium arsenide (GaAs), indium phosphide (InP), sapphire, or other III / V compound semiconductors; or silicon on dielectric (SOI), silicon on dielectric (SSOI), silicon germanium on dielectric (S-SiGeOI), silicon germanium on dielectric (SiGeOI), and germanium on dielectric (GeOI); or it may be a double-sided polished wafer (DSP), a ceramic substrate such as alumina, a quartz, or a glass substrate, etc. Although several examples of materials that can form the support substrate have been described herein, any material that can serve as the support substrate falls within the spirit and scope of the invention. In this embodiment, the support substrate 301 is a silicon substrate. The supporting substrate 301 and the interlayer dielectric layer 218 are bonded together. The bonding method includes, but is not limited to, silicon-oxygen bonding or hybrid bonding.

[0074] In one example, such as Figure 17As shown, after bonding the support substrate 301 and the interlayer dielectric layer 218, before forming multiple photodiode regions in the device substrate 201, or after forming multiple photodiode regions in the device substrate 201, the method further includes: thinning the side of the device substrate 201 opposite to the first epitaxial layer 203 to expose the end of the support pillar 207 away from the interlayer dielectric layer 218. Specifically, after bonding, the bonded structure is flipped, and the back side of the device substrate 201 (i.e., the side of the device substrate 201 opposite to the first epitaxial layer 203) is thinned to expose the end of the support pillar 207 away from the interlayer dielectric layer 218. The thinning method includes, but is not limited to, chemical mechanical polishing, and is not specifically limited thereto. In another example, the side of the device substrate 201 opposite to the first epitaxial layer 203 can also be thinned after forming the photodiode regions.

[0075] Finally, step S9 is performed to form multiple photodiode regions in the device substrate, wherein each photodiode region corresponds to the drain region of a transistor electrically connected to it.

[0076] In one example, such as Figure 18 As shown, multiple photodiode regions 220 are formed in the device substrate 201. Specifically, a patterned photoresist layer is formed on the device substrate 201, defining the regions of the photodiode (PD). Ion implantation is performed on the device substrate 201 using the patterned photoresist layer as a mask to form multiple photodiode regions 220 in the device substrate 201. Each photodiode region 220 is electrically connected to a first conductive plug 213, and then the photoresist layer is removed. The type and concentration of ion implantation are selected according to the actual situation and are not specifically limited. The function of the photodiode regions is to convert incident light signals into electrical signals and accumulate charge in subsequent image sensors. In this application, the photodiode regions are formed after the transistors and interconnect structures are formed, which avoids the influence of multiple process steps on the diodes, reduces noise, and improves performance.

[0077] In one example, the image sensor includes multiple pixel units, each pixel unit including at least one photodiode region 220 and at least two transistors 215, wherein the drain region 2152 of at least one transistor 215 in each pixel unit serves as a floating diffusion region (FD), and each photodiode region 220 and floating diffusion region are spaced apart in the thickness direction of the device substrate 201. By vertically placing the photodiode region and the floating diffusion region, the area of ​​the photodiode region can be increased, thereby improving the photoelectric conversion efficiency. The floating diffusion region is used to collect the charge transferred from the photodiode region and convert it into a voltage signal for critical parts of the readout circuit processing.

[0078] In one example, such as Figure 19As shown, a passivation layer 221 is formed on the side of the device substrate 201 opposite to the first isolation layer 210, and the passivation layer 221 covers the surface of the interlayer device substrate 201. Exemplarily, the material of the passivation layer 221 includes, but is not limited to, materials such as silicon dioxide or silicon oxynitride, and the method for forming the passivation layer 221 includes, but is not limited to, methods such as PECVD (plasma-enhanced chemical vapor deposition) or ALD (atomic layer deposition). The passivation layer helps reduce electrical crosstalk between adjacent pixels and reduces parasitic capacitance by optimizing the electrical properties of the metal layer, thereby improving signal transmission efficiency and image clarity.

[0079] In one example, such as Figure 19 As shown, multiple grid structures 222 are formed on the passivation layer 221, and grid openings 223 are formed between each grid structure 222. A grid structure 222 is disposed between adjacent pixel units. Specifically, firstly, a grid material layer is formed on the passivation layer 221. The material of the grid material layer includes, but is not limited to, tungsten (W), nickel (Ni), or titanium (Ti). The methods for forming the grid material layer include, but are not limited to, molecular beam epitaxy (MBE), metal-organic chemical vapor deposition (MOCVD), low-pressure chemical vapor deposition (LPCVD), and laser ablation deposition (LAD). Next, a patterned photoresist layer is formed on the grid material layer. This patterned photoresist layer defines the region and position of the grid structure 222. Using the patterned photoresist layer as a mask, the grid material layer is etched to form a grid structure 222 between adjacent pixel units. A grid opening 223 is formed between each grid structure 222, and the grid opening 223 exposes the surface of the passivation layer 221. Then, the photoresist layer is removed. The etching of the grid material layer can be performed using conventional etching processes such as dry etching, reactive ion etching (RIE), ion beam etching, and plasma etching, without specific limitations. The grid structure can enhance image performance by suppressing optical crosstalk.

[0080] In one example, such as Figure 20 As shown, a color filter layer 224 is embedded in each grid opening 223. The main function of the color filter layer 224 is to separate the incident light according to color (i.e., different wavelengths), so that each pixel can only receive light of a specific color (usually one of red, green, and blue). This is the basis for the color image sensor to generate color images. Specifically, the material of the color filter layer can be deposited in each grid opening 223 using methods such as spin coating or inkjet printing, and then subjected to processes such as baking to ensure its stability and optical performance, ultimately forming the color filter layer 224 embedded in the grid opening 223. The material of the color filter layer 224 includes, but is not limited to, dye-based resins, pigment-based resins, or inorganic materials.

[0081] In one example, such as Figure 21As shown, multiple microlenses 226 are formed on the color filter layer 224, each microlens 226 corresponding to a multiple pixel unit; for example, one pixel unit corresponds to one or more microlenses 226. Before forming the microlenses 226, an anti-reflection layer 225 is also formed on the color filter layer 224. Exemplarily, the anti-reflection layer 225 includes, but is not limited to, silicon dioxide or silicon nitride, and the process methods for forming the anti-reflection layer 225 include, but are not limited to, PECVD (plasma-enhanced chemical vapor deposition), atomic layer deposition (ALD), etc. When light enters another medium from one medium (e.g., a microlens entering a color filter layer), reflection loss occurs if the refractive index difference between the two is large. By optimizing its refractive index and thickness, the anti-reflection layer can effectively reduce this reflection loss at the interface, thereby increasing the effective light amount reaching the photodiode. By reducing reflection loss, more incident light energy can be effectively utilized by the image sensor, which directly improves the quantum efficiency and performance in low-light environments of the image sensor. The anti-reflection layer can also act as a transition layer, providing a flat surface for the microlenses, facilitating their fabrication. In other examples, an anti-reflective layer may not be formed, and there are no specific restrictions on this.

[0082] Finally, multiple microlenses 226 are formed on the color filter layer 224. Specifically, first, a photosensitive material layer suitable for fabricating microlenses (usually positive photoresist or high-temperature resin, etc.) is coated on the anti-reflection layer 225. A patterned photoresist layer is formed on the photosensitive material layer, defining the area and position of the microlenses 226. The photosensitive material layer is etched using the patterned photoresist layer as a mask to form the basic structure of the microlenses. Second, the photoresist is heated to a specific temperature, causing the remaining photoresist to melt and naturally form the desired hemispherical or near-spherical microlens structure due to surface tension. Finally, the formed microlens structure undergoes further curing treatment, such as ultraviolet curing or annealing, to form the final microlens 226. By focusing incident light, the microlenses allow more light to directly enter the photodiode, thereby compensating for this loss, improving light utilization, enhancing signal quality, and improving image quality.

[0083] It is worth mentioning that the above steps are only examples, and the order of the steps can be adjusted without conflict.

[0084] Thus, the process steps of the image sensor fabrication method according to the embodiments of this application are completed. It is understood that the image sensor fabrication method of this embodiment includes not only the above steps, but may also include other necessary steps before, during or after the above steps, all of which are included within the scope of the fabrication method of this embodiment.

[0085] In summary, the image sensor fabrication method of this application, by forming an isolation layer and a light-shielding structure between the photodiode region and the floating diffusion region respectively, can effectively prevent the latch-up effect between the source and drain of the transistor, thereby avoiding crosstalk between the photodiode region and the floating diffusion region and improving the quality of the image sensor.

[0086] This application also provides an image sensor, which can be prepared by the method of the foregoing embodiments, or by other suitable preparation methods.

[0087] The image sensor provided in this application effectively prevents latch-up between the source and drain of the transistor by forming an isolation layer and a light-shielding structure between the photodiode region and the floating diffusion region, thereby avoiding crosstalk between the photodiode region and the floating diffusion region and improving the quality of the image sensor.

[0088] Although several embodiments have been described herein, it should be understood that many other modifications and embodiments will be conceived by those skilled in the art, all of which will fall within the spirit and scope of the disclosed concept. More particularly, various modifications and changes can be made in terms of the arrangement and / or components of the subject matter within the scope of the disclosure, drawings, and appended claims. In addition to modifications and changes in components and / or arrangement, the use of alternative methods will also be obvious to those skilled in the art.

Claims

1. A method of fabricating an image sensor, characterized by, The method comprises the following steps: providing a device substrate, and sequentially forming a first sacrificial layer, a first epitaxial layer, a second sacrificial layer and a second epitaxial layer on the device substrate; forming a plurality of support columns penetrating through the second epitaxial layer, the second sacrificial layer, the first epitaxial layer, the first sacrificial layer and extending into the device substrate; forming at least one release trench penetrating through the second epitaxial layer, the second sacrificial layer, the first epitaxial layer and the first sacrificial layer; etching and removing the first sacrificial layer with the release trench as a release channel to form a first cavity between the first epitaxial layer and the device substrate, and etching and removing the second sacrificial layer to form a second cavity between the first epitaxial layer and the second epitaxial layer; forming a first isolation layer in the first cavity and forming a light shielding structure in the second cavity; forming a plurality of transistors on the second epitaxial layer, each of the transistors comprising a drain region formed in the second epitaxial layer; forming an interlayer dielectric layer covering the second epitaxial layer and the plurality of transistors; providing a support substrate, and bonding the support substrate and the interlayer dielectric layer; forming a plurality of photodiode regions in the device substrate, wherein each of the photodiode regions is electrically connected to the drain region of one of the transistors; The image sensor comprises a plurality of pixel units, and the drain region of at least one transistor in each of the pixel units serves as a floating diffusion region. The floating diffusion region and the photodiode region in each of the pixel units are arranged in a thickness direction of the device substrate.

2. The production method according to claim 1, wherein The image sensor comprises a plurality of pixel units, each of which comprises at least one photodiode region and at least two transistors. A support column is arranged between any two adjacent transistors in each of the pixel units, and the support column serves as an isolation structure.

3. The production method according to claim 1, wherein The method further comprises the following steps after forming the light shielding structure and before forming the plurality of transistors: depositing an isolation material layer to form a first isolation layer in the first cavity, the first isolation layer filling the first cavity, and the isolation material layer also being deposited on a surface of the second epitaxial layer facing the first epitaxial layer to form a second isolation layer covering the surface of the second epitaxial layer facing the first epitaxial layer, and the isolation material layer also being deposited on a surface of the first epitaxial layer facing the second epitaxial layer to form a third isolation layer covering the surface of the first epitaxial layer facing the second epitaxial layer; depositing a light shielding layer to fill a portion of the second cavity between the second isolation layer and the third isolation layer, and the light shielding structure comprising the second isolation layer, the third isolation layer and the light shielding layer.

4. The production method according to claim 3, wherein The isolation material layer is also deposited on the sidewall of the release trench, and the light shielding layer fills the release trench.

5. The production method according to claim 1, wherein The method further comprises the following steps after forming the light shielding structure and before forming the plurality of transistors: forming a plurality of first conductive plugs sequentially penetrating through the second epitaxial layer, the light-shielding structure, the first epitaxial layer and the first isolation layer, the plurality of first conductive plugs being spaced apart, each of the first conductive plugs being configured to electrically connect with a predetermined photo-diode region; and Before the support substrate and the interlayer dielectric layer are bonded, the preparation method further comprises: forming a plurality of conductive interconnection structures in the interlayer dielectric layer, each of the conductive interconnection structures being electrically connected with at least one of the first conductive plugs and at least one of the drain regions of the transistors.

6. The production method according to claim 5, wherein The first conductive plugs are further arranged to extend along a first direction, wherein the image sensor comprises a plurality of pixel units, each of the pixel units comprising at least one photo-diode region and at least two transistors, The support pillars are arranged between two adjacent pixel units in a second direction, and the support pillars are further arranged to extend along the first direction, the first direction being perpendicular to a thickness direction of the device substrate; Each of the release grooves is arranged between two adjacent pixel units in the first direction, and the release grooves are further arranged to extend along the second direction; The first direction, the second direction and the thickness direction of the device substrate are perpendicular to each other.

7. The production method according to claim 1, wherein After the support substrate and the interlayer dielectric layer are bonded, before the plurality of photo-diode regions are formed in the device substrate, or after the plurality of photo-diode regions are formed in the device substrate, the preparation method further comprises: thinning a side of the device substrate opposite to the first epitaxial layer to expose an end of the support pillars away from the interlayer dielectric layer.

8. The production method according to claim 1, wherein The step of forming the plurality of photo-diode regions in the device substrate is performed before the first sacrificial layer is formed.

9. The production method according to claim 1, wherein The preparation method further comprises: forming a passivation layer on a side of the device substrate away from the first isolation layer; a plurality of grid structures are formed on the passivation layer, wherein the image sensor comprises a plurality of pixel units, a grid structure is arranged between adjacent pixel units, a grid opening is formed between adjacent grid structures, and the grid opening exposes a surface of the passivation layer; a color filter layer is embedded in the grid opening; a plurality of microlenses are formed on the color filter layer, and the plurality of microlenses correspond to the plurality of pixel units.

10. An image sensor, comprising: The image sensor is prepared by using the preparation method according to any one of claims 1 to 9.

Images