Semiconductor device and manufacturing method thereof
By setting expansion slots and filling expansion pads in the semiconductor structure, the problem of poor contact in dynamic random access memory was solved, improving contact reliability and product yield, and achieving a simple and efficient process improvement.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- RUILI INTEGRATED CIRCUIT CO LTD
- Filing Date
- 2024-10-18
- Publication Date
- 2026-04-21
AI Technical Summary
With the miniaturization of semiconductor device structures, dynamic random access memory (DRAM) faces stringent alignment requirements during the fabrication of active regions and node contact plugs, leading to issues such as small exposed areas, poor contact, or even short circuits.
A semiconductor structure was designed that increases the contact area of the node contact plug and improves contact reliability by setting expansion slots and filling expansion pads in the node region. The expansion pads are flush with the word line structure.
It increases the contact area between the node contact plug and the node region, expands the process window, improves product yield, and the process is simple without increasing production costs too much.
Smart Images
Figure CN121908545A_ABST
Abstract
Description
Technical Field
[0001] This disclosure relates to the field of semiconductor technology, and more particularly to a semiconductor device, a dynamic random access memory, and a selection control circuit. Background Technology
[0002] The development of dynamic memory (DRAM) pursues performance indicators such as high speed, high integration density, and low power consumption. However, with the miniaturization of semiconductor device structures, ensuring product yield while maintaining critical dimensions presents increasingly significant technological barriers for existing structures. Therefore, developing more novel structures based on existing ones is a powerful means to overcome these technological barriers. Summary of the Invention
[0003] According to a first aspect of the present disclosure, a semiconductor device is provided, comprising: Substrate; active regions, which are arranged in an array within the substrate; isolation layers, which are disposed between the active regions; word line structure, which passes through the active regions and divides them into node regions and bit line regions; expansion slots, which are partially disposed in the node regions and partially disposed in the isolation layers; expansion pads, which are disposed in the expansion slots; wherein the expansion pads fill the expansion slots.
[0004] In some embodiments, the upper surface of the expansion pad is flush with the upper surface of the letter line structure.
[0005] In some embodiments, the two word line structures pass through the same active region and divide the active region into two node regions and a bit line region located between the two node regions.
[0006] In some embodiments, the semiconductor structure further includes: a bit line structure disposed on a substrate and in contact with a bit line region; a spacer structure disposed between the bit line structures; a contact hole defined by the bit line structure and the spacer structure; and a node contact plug disposed in the contact hole, the node contact plug being in at least partial contact with an expansion pad.
[0007] In some embodiments, the material of the expansion pad is polycrystalline silicon or monocrystalline silicon.
[0008] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: A substrate is provided, on which active regions are arranged in an array. An isolation layer is formed between the active regions. A word line structure passes through the active regions. The active regions are divided into node regions and bit line regions by the word line structure. An expansion trench is formed in the substrate. The expansion trench is partially formed in the node region and partially disposed in the isolation layer. An expansion pad is formed in the expansion trench and fills the expansion trench.
[0009] In some embodiments, the step of forming the expansion slot includes: A mask pattern is formed on the substrate. The mask pattern is strip-shaped and intersects with the word line structure. The bit line area is blocked by the mask pattern, exposing at least part of the node area and part of the isolation layer. The substrate with the mask pattern is etched to form an expansion trench.
[0010] In some embodiments, the etching step includes: Etch the exposed node areas; etch the exposed isolation layer.
[0011] In some embodiments, the step of forming the expansion pad includes: A layer of extended pad material is deposited, and the substrate with the extended pad material layer is planarized to form an extended pad.
[0012] In some embodiments, during the planarization process, an expansion pad material layer other than the mask pattern and expansion slot is removed simultaneously.
[0013] Adding expansion pads to semiconductor structures can increase the contact area between node contact plugs and node regions, reduce contact resistance, expand the process window, and ensure product yield. Attached Figure Description
[0014] Figure 1 , Figure 3 This is a schematic diagram of a top view of a semiconductor device according to an exemplary embodiment; Figure 2 , Figure 8 , Figure 9 , Figure 10 , Figure 15 , Figure 16 , Figure 17 This is a schematic diagram of a cross-sectional view of a semiconductor device along the direction of extension of the active region, according to an exemplary embodiment. Figure 4 , Figure 11 , Figure 12 , Figure 13 , Figure 14 A semiconductor device is shown according to a certain exemplary embodiment. Figure 3 A schematic diagram of a partial top view of area A in the middle; Figure 5 , Figure 6 , Figure 7 A semiconductor device is shown according to a certain exemplary embodiment. Figure 4 A schematic diagram of the cross-section along the Bb direction. Detailed Implementation
[0015] The technical solutions of this disclosure will be further described in detail below with reference to the accompanying drawings and embodiments. Although exemplary embodiments of this disclosure are shown in the drawings, it should be understood that this disclosure can be implemented in various forms and should not be limited to the embodiments described herein. Rather, these embodiments are provided to enable a more thorough understanding of this disclosure and to fully convey the scope of this disclosure to those skilled in the art.
[0016] The present disclosure is described in more detail below by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will become clearer from the following description and claims. It should be noted that the drawings are in a very simplified form and use non-precise proportions, and are only used to facilitate and clarify the illustration of the embodiments of the present disclosure.
[0017] It is understood that the meanings of “on”, “above” and “above” in this disclosure should be interpreted in the broadest sense, such that “on” means not only that it is “on” something without any intervening feature or layer (i.e., directly on something), but also that it is “on” something with an intervening feature or layer.
[0018] In the embodiments of this disclosure, the terms "first," "second," "third," etc., are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.
[0019] In embodiments of this disclosure, the term "layer" refers to a portion of material comprising a region having thickness. A layer may extend over the entirety of a lower or upper structure, or may have a range smaller than that of the lower or upper structure. Furthermore, a layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, a layer may be located between the top and bottom surfaces of a continuous structure, or a layer may be located between any horizontal faces at the top and bottom surfaces of the continuous structure. A layer may extend horizontally, vertically, and / or along an inclined surface. A layer may include multiple sublayers.
[0020] It should be noted that the technical solutions described in the embodiments of this disclosure can be combined arbitrarily without conflict.
[0021] In some related technologies, as the process size shrinks, the alignment requirements of different layer structures in the fabrication of dynamic random access memory (DRAM) gradually become more stringent. For example, in the fabrication of the active region and the node contact plug, the active region may be blocked by the upper bit line structure and the spacer structure, resulting in a very small exposed area or no exposure at all. This can lead to poor contact between the node contact plug and the active region, or even short circuits. Therefore, new designs are needed to solve these problems.
[0022] According to a first aspect of the embodiments of this disclosure, such as Figure 1-4As shown in 7, 15-17, a semiconductor structure 10 is provided, comprising: Substrate 100; active regions 200, which are disposed in the substrate and arranged in an array; isolation layer 300, which is disposed between the active regions; word line structure 400, which passes through the active regions and divides the active regions into node regions 201 and bit line regions 202; expansion slot 500, which is partially disposed in the node regions and partially disposed in the isolation layer; expansion pad 600, which is disposed in the expansion slot; wherein the expansion pad fills the expansion slot. Optionally, the substrate can be made of semiconductor materials such as single-crystal silicon, germanium silicon, and silicon carbide. Optionally, the active regions are insulated and separated by isolation layers, which are selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the isolation layer is composed of a stack of silicon oxide and silicon nitride. Optionally, the word line structure includes a gate electrode 401, a gate cover layer 402, and a gate insulating layer (not shown). The word line structure is disposed in the substrate, and the word line structure and the active region it passes through constitute a transistor structure. The node region and bit line region located on both sides of the word line structure respectively serve as the source and drain. Under the action of the word line structure, the transistor structure can be turned on and off. Optionally, the gate electrode is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the material of the gate electrode is titanium nitride. Optionally, the gate masking layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the gate masking layer is silicon nitride. Optionally, the gate insulating layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the gate masking layer is silicon oxide.
[0023] In some embodiments, the upper surface of the expansion pad is flush with the upper surface of the word line structure. Optionally, the expansion pad fills the expansion slot, which is partially disposed in the isolation layer and partially disposed in the node area, and contacts the corresponding word line structure. Therefore, the expansion slot is defined by the isolation layer, the node area, and the word line structure, and the expansion slot defines the size of the expansion pad.
[0024] In some embodiments, two word line structures pass through the same active region and divide the active region into two node regions and a bit line region located between the two node regions. The two word line structures and the active region they pass through constitute transistor structures respectively. The node regions and bit line regions located on both sides of the word line structures respectively serve as source and drain terminals. Under the action of the word line structures, the transistor structures can be turned on and off, and the two transistor structures share a bit line region.
[0025] In some embodiments, the semiconductor structure further includes: a bit line structure 700 disposed on a substrate and in contact with the bit line region; a spacer structure 800 disposed between the bit line structures; a contact hole 201V defined by the bit line structures and the spacer structure; and a node contact plug NC disposed in the contact hole, the node contact plug being in at least partial contact with an expansion pad. Optionally, the spacer structure is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof; preferably, the spacer structure is silicon nitride. Optionally, the node contact plug material is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped single-crystal silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the node contact plug is doped polycrystalline silicon.
[0026] In some embodiments, the bit line structure includes a bit line electrode 701, a bit line contact plug 701C, the bit line electrode being connected to the bit line region via the bit line contact plug, a bit line insulating layer 702 disposed on the bit line electrode, and bit line sidewalls 703 located on both sides of the bit line electrode and the bit line insulating layer. Optionally, the bit line electrode is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the material of the bit line electrode is tungsten (W). Optionally, the material of the bit line insulating layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the material of the bit line insulating layer is silicon nitride. Optionally, the material of the bit line sidewall is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the bit line sidewall is a laminated structure composed of silicon nitride and silicon oxide. Optionally, the bit line contact plug is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped single-crystal silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), aluminum titanium nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), aluminum tantalum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the bit line contact plug is doped or undoped polycrystalline silicon.
[0027] In some embodiments, the semiconductor structure further includes: a pad protection layer 600P covering the expansion pad, with an opening at the location where the expansion pad connects to the node contact plug. Optionally, the pad protection layer also covers at least a portion of the upper surface of the word line structure, the isolation layer, and the active region. Optionally, the material of the pad protection layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof. Preferably, the pad protection layer is a stacked structure composed of silicon nitride and silicon oxide.
[0028] In some embodiments, the material of the expansion pad is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the expansion pad is polycrystalline silicon or monocrystalline silicon. Optionally, the polycrystalline silicon or monocrystalline silicon in the expansion pad can be elemental pure silicon or silicon doped with other elements.
[0029] In some embodiments, the semiconductor structure can serve as the component structure of dynamic random access memory (DRAM). The active region and word line structure form a transistor structure, while the node region and bit line region function as source and drain, respectively. The bit line region is connected to the bit line structure, and the node region is electrically connected to the memory node. Under the influence of the word line structure, the transistor structure can be switched on and off, connecting or disconnecting the bit line structure and the memory node to achieve dynamic storage functionality. Optionally, the memory node can be a storage capacitor, a ferroelectric memory node, a resistive switching memory node, a phase-change memory node, or a magnetic junction memory node.
[0030] In some embodiments, the semiconductor structure further includes: a landing pad LP, which is partially disposed in a contact hole with a node contact plug and partially disposed on a bit line structure or a spacer structure; a lower electrode BE is connected to the landing pad in a one-to-one correspondence; an upper electrode UE covers multiple lower electrodes; and the upper electrode, the lower electrode, and the capacitor dielectric layer (not shown) between them constitute a capacitor structure CAP. The material of the landing pad is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the landing pad is a tungsten (W) and titanium nitride (TiN) stacked structure. The lower electrode material is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the lower electrode is titanium nitride (TiN). The upper electrode material is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped single-crystal silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the upper electrode is a stacked structure of titanium nitride (TiN) and doped or undoped polycrystalline silicon. The capacitor dielectric layer material is selected from high dielectric constant materials, such as: hafnium oxide (HfO2), aluminum oxide (Al2O3), lanthanum oxide (La2O3), zirconium oxide (ZrO3), tantalum oxide (Ta2O5), gadolinium oxide (Gd2O3), hafnium oxynitride (HfO2). x N y ), aluminum oxide (AlO) x N y ), Lanthanum oxide (LaO) x N y ), zirconium oxynitride (ZrO) x N y ), tantalum oxynitride (TaO) x N y ), Gadolinium oxide (GdO) x N y )wait.
[0031] According to a second aspect of the present disclosure, a method for manufacturing a semiconductor device is provided, comprising: A substrate is provided, on which active regions are arranged in an array. An isolation layer is formed between the active regions. A word line structure passes through the active regions. The active regions are divided into node regions and bit line regions by the word line structure. An expansion trench is formed in the substrate. The expansion trench is partially formed in the node region and partially disposed in the isolation layer. An expansion pad is formed in the expansion trench and fills the expansion trench.
[0032] In some embodiments, the step of forming the expansion slot includes: A mask pattern is formed on the substrate. The mask pattern 900 is strip-shaped and intersects with the word line structure. The bit line area is blocked by the mask pattern, exposing at least part of the node area and part of the isolation layer. The substrate with the mask pattern is etched to form an expansion trench.
[0033] Specifically, in conjunction with the appendix Figure 1-17 A substrate 100 is provided, in which an array of active regions and an isolation layer separating the active regions are formed in a previous process. A word line structure with spacing is formed in the substrate, passing through multiple active regions and dividing the active regions into node regions and bit line regions. The word line structure and the active regions it passes through constitute a transistor structure. The node regions and bit line regions located on both sides of the word line structure respectively function as source and drain electrodes. Under the action of the word line structure, the transistor structure can be turned on and off.
[0034] Combination Figure 1-2 The steps of forming an array of active regions on a substrate and an isolation layer that isolates the active regions from each other are as follows: Specifically, the active regions and isolation trenches are formed by patterning the substrate through a patterning process, and an isolation layer is formed in the isolation trenches.
[0035] In some embodiments, the patterning process includes forming photoresist on a substrate, exposing and developing the photoresist to form a pre-defined pattern of photoresist, and etching the substrate with the patterned photoresist to form an active region and isolation trenches.
[0036] In some embodiments, the patterning process further includes forming a hard mask on a substrate, forming photoresist on the hard mask, exposing and developing the photoresist to form a preset pattern, etching the hard mask with the patterned photoresist to transfer the preset pattern onto the hard mask, stripping the photoresist, and etching the substrate with the patterned hard mask to form an active region and isolation trenches.
[0037] In some embodiments, with the development of semiconductor fabrication processes, integration density increases and dimensions shrink. A single patterning process cannot form the predetermined width required for active regions and isolation trenches, necessitating multiple patterning processes. Examples include two-stage exposure and etching (LELE), self-aligned double patterning (SADP), or self-aligned quad patterning (SAQP). Optionally, a patterned substrate with strip-shaped spacing is first formed, and then portions of the strip-shaped patterned substrate are etched to form an array of active region patterns.
[0038] In some embodiments, the process of etching the substrate to form active regions and isolation trenches includes anisotropic etching or isotropic etching, such as dry etching or wet etching.
[0039] In some embodiments, the insulating material deposited in the isolation trench to form the isolation layer is selected from one or more of silicon oxide, aluminum oxide, silicon nitride, silicon oxynitride, silicon carbon oxycarbide, silicon carbonitride, and silicon carbonitride. Preferably, silicon nitride and silicon oxide are deposited alternately; more preferably, silicon nitride is deposited first, followed by silicon oxide.
[0040] In some embodiments, the deposition method for depositing insulating material in the isolation trench to form an isolation layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the method for depositing the insulating material is chemical vapor deposition (CVD). Preferably, the method for depositing the insulating material involves forming a material layer by chemical vapor deposition (CVD), and then planarizing the material layer using chemical mechanical polishing to remove a portion of the insulating material layer located on the surface of the active region, exposing the active region.
[0041] Combination Figure 1-2 The step of forming word line structures on a substrate involves patterning the substrate using a patterning process to form word line trenches, and then forming word line structures within the word line trenches.
[0042] Specifically, similar to the aforementioned patterning process, word line trenches are formed, which will not be elaborated here. Forming the word line structure within the word line trenches includes: sequentially forming a gate insulating layer, a gate electrode, and a gate capping layer within the word line trenches. Optionally, the method for forming the gate insulating layer includes: depositing gate insulating layer material on the substrate surface and the surface of the word line trenches. The deposition method for the gate insulating layer material is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, rapid thermal oxidation, etc. Preferably, the deposition method for the insulating material is rapid thermal oxidation. The gate insulating layer material on the substrate surface is removed, and the remaining gate insulating layer material in the word line trenches constitutes the gate insulating layer. The method for removing the gate insulating layer material on the substrate surface is selected from etching processes and chemical mechanical polishing (CMP). Optionally, a gate electrode is formed on the gate insulating layer, including depositing gate electrode material on the substrate and the gate insulating layer. The deposition method is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the gate electrode material deposition method is atomic layer deposition (ALD), removing the gate electrode material on the substrate surface and a portion of the gate electrode material in the word line trenches. The remaining portion of the gate electrode material on the gate insulating layer in the word line trenches constitutes the gate electrode. Methods for removing the gate electrode material include etching processes and chemical mechanical polishing (CMP). Optionally, the removal of a portion of the gate insulating layer material and the gate electrode material can be completed in the same step. Optionally, the method for forming the gate masking layer includes depositing a gate masking layer material in a substrate and word line trenches where gate electrodes are formed. The deposition method is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, etc. Preferably, chemical vapor deposition (CVD) is used to remove the gate masking layer material on the substrate and in the word line trenches beyond the upper surface of the substrate. The remaining gate masking layer material constitutes the gate masking layer, that is, the gate masking layer fills the remaining space of the word line trenches. The method for removing the gate masking layer material includes etching and chemical mechanical polishing (CMP).
[0043] The step of forming an extended trench on a substrate, wherein the extended trench is partially formed in the node region and partially disposed in the isolation layer, includes: forming an extended trench on the substrate surface by a patterning process, specifically, etching the exposed node region and the isolation layer by a patterning process to form the extended trench.
[0044] In some embodiments, combined with Figure 3-11As shown, a mask pattern is formed on the substrate surface. Specifically, a mask material is deposited on the substrate surface, and a patterning process is used on the mask material to form a mask pattern. The deposition method of the mask material is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc., preferably, furnace tube deposition. The mask pattern is a strip intersecting with the word line structure, and the mask pattern blocks the bit line area, forming a grid shape with the word line structure, exposing part of the node area and part of the isolation layer in the grid. An etching process is used on the exposed part of the node area and part of the isolation layer. Optionally, the etching process is used to first etch the exposed part of the node area to form a partial expansion trench 501, and then the etching process is changed to etch part of the isolation layer to form an expansion trench.
[0045] In some embodiments, the substrate material is doped or undoped single-crystal silicon, the gate masking layer material is silicon nitride, the isolation layer is silicon oxide, and the mask pattern is polycrystalline silicon. The etching process used for etching the exposed partial node region involves using a gas with a high silicon / silicon oxide selectivity ratio, such as chlorine or hydrogen bromide, to form a partial expansion trench with a depth of 5 nm-15 nm, preferably 8 nm. The etching process used for etching the partial isolation layer involves further etching the silicon oxide with dilute hydrofluoric acid to a depth of 5 nm-15 nm, preferably 8 nm. The final expanded trench depth is 5 nm-15 nm, preferably 8 nm. It is understood that after forming the partial expanded trench, during the etching process of the partial isolation layer, because the edges of the partial expanded trench are more easily etched, the etching will gradually proceed from the edges towards the isolation layer. A portion of the isolation layer surface will also be etched, but at a slightly slower rate than at the edges, thus forming an expanded trench similar to the edge of the node region.
[0046] The step of forming an expansion pad in an expansion trench and filling the expansion trench with the expansion pad includes: depositing an expansion pad material layer of 600 μm on a substrate with an expansion trench, removing the expansion pad material layer outside the expansion trench, and filling the expansion trench with the remaining expansion pad material layer to form an expansion pad. Optionally, the material of the expansion pad is selected from metals, metal nitrides, metal oxides, metal silicides, conductive carbon, doped or undoped polycrystalline silicon, doped or undoped monocrystalline silicon, and combinations thereof; such as copper (Cu), aluminum (Al), tungsten (W), titanium (Ti), titanium nitride (TiN), titanium aluminum nitride (TiAlN), titanium carbonitride (TiCN), tantalum (Ta), tantalum nitride (TaN), tantalum aluminum nitride (TaAlN), tantalum carbonitride (TaCN), ruthenium (Ru), platinum (Pt), or combinations thereof. Preferably, the expansion pad is doped or undoped polycrystalline silicon. The deposition method for the extended pad material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc., with furnace tube deposition being preferred. Methods for removing the extended pad material layer include etching processes and chemical mechanical polishing (CMP).
[0047] In some embodiments, the substrate material is doped or undoped monocrystalline silicon, the gate masking layer material is silicon nitride, the isolation layer is silicon oxide, the mask pattern is polycrystalline silicon, and the expansion pad material is polycrystalline silicon. The step of removing the expansion pad material layer other than the expansion trenches can be performed using chemical mechanical polishing (CMP). Simultaneously, the mask pattern is removed to form a planarized substrate, such as... Figure 10-11 As shown, the upper surface of the expansion pad is on the same plane as the isolation layer, word line structure, bit line area, and node area outside the expansion slot.
[0048] In some embodiments, an expansion pad protective layer is formed on the substrate in which the expansion pad is formed, such as Figure 12 As shown, optionally, the deposition method is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc., preferably chemical vapor deposition (CVD). The protective layer material of the extended pad is selected from one or more of silicon oxide, alumina, silicon nitride, silicon oxynitride, silicon oxycarbide, silicon carbonitride, and silicon carbonitride. Preferably, silicon nitride and silicon oxide are deposited alternately.
[0049] In some embodiments, combined with Figure 13-16On a substrate with an extended pad protective layer, bit line structures and spacer structures between the bit line structures are fabricated. Contact holes are formed, defined by the bit line structures and spacer structures. The extended pad protective layer exposed in the contact holes is etched to expose a portion of the extended pads. Specifically, bit line contact plugs, bit line electrodes, bit line insulating layers, and bit line sidewalls are formed sequentially, and spacer structures are formed between the bit line structures. The method for etching the extended pad protective layer is dry etching, which uses plasma to etch the substrate. Because the extended pad protective layer is relatively thin compared to the bit line structures and spacer structures, it is etched out earlier. Figure 14 and Figure 15 As shown, the extended pad is exposed. Then, a node contact plug is formed in the contact hole of the exposed extended pad, as shown. Figure 16 As shown, optionally, the method for forming the node contact plug includes depositing a node contact plug material layer on the entire surface of the substrate, etching the node contact plug material layer, and because the contact holes have a certain aspect ratio, the node contact plug material layer on the upper surface of the bit line structure and the spacer structure will be etched first, and the remaining node contact plug material layer in the contact holes forms the node contact plug. The optional deposition method for the node contact plug material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc., with furnace tube deposition being the preferred method.
[0050] In some embodiments, such as Figure 17As shown, a landing pad is formed on a substrate with node contact plugs. Part of the landing pad is formed in the contact holes and contacts the node contact plugs, while another part is formed on the surface of the bitline structure or spacer structure. Specifically, a landing pad material layer is formed on the substrate surface. A patterning process is used to form the landing pad material layer. Optionally, the method for forming the landing pad material layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc. Preferably, the formation method is chemical vapor deposition (CVD). The patterning process is similar to that described above. A storage node is formed on the substrate with the landing pad. Taking a storage capacitor as an example, a lower electrode is formed on the landing pad, a capacitor dielectric layer is formed on the lower electrode, and an upper electrode is formed on the capacitor dielectric layer. Specifically, the method for forming the lower electrode includes forming a sacrificial layer, forming capacitor grooves at corresponding positions on the sacrificial layer using a patterning process, depositing a lower electrode material layer, removing the lower electrode material layer from the upper surface of the sacrificial layer, and forming the lower electrode material layer remaining in the capacitor groove. Optionally, the material of the sacrificial layer is selected from silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or metal oxides such as tantalum oxide, hafnium oxide, aluminum oxide, and combinations thereof; preferably, the sacrificial layer is silicon oxide. The method for forming the sacrificial layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc.; preferably, the deposition method is chemical vapor deposition (CVD). Methods for removing the sacrificial layer material include etching processes and chemical mechanical polishing (CMP). Optionally, the method for forming the lower electrode is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc., preferably, the method of forming the lower electrode is atomic layer deposition (ALD). The methods for removing the lower electrode material layer include etching and chemical mechanical polishing (CMP). Optionally, the method for forming the capacitor dielectric layer is selected from physical vapor deposition (PVD), atomic layer deposition (ALD), pulsed laser deposition (PLD), chemical vapor deposition (CVD), vacuum evaporation, furnace tube deposition, etc., preferably, the method of forming the lower electrode is atomic layer deposition (ALD).
[0051] Because the expansion pad increases the available contact area between the node region and the node contact plug, it can improve the process window and increase product yield. Furthermore, the process is simple, requiring only the addition of a mask pattern layer, thus not significantly increasing production costs.
[0052] The various semiconductor devices illustrated in this specific embodiment can be used in electronic devices with storage functions. These electronic devices can be terminal devices, such as mobile phones, tablets, and smart bracelets, or personal computers (PCs), servers, workstations, etc. The storage function in these electronic devices can be implemented using the following types of memory: Dynamic Random Access Memory (DRAM), Ferroelectric Random Access Memory (FRAM), Phase-Change Memory (PCM), Magnetic Random Access Memory (MRAM), or Resistive Random Access Memory (RRAM).
[0053] The above are merely specific embodiments of this disclosure, but the scope of protection of this disclosure is not limited thereto. Any variations or substitutions that can be easily conceived by those skilled in the art within the scope of the technology disclosed in this disclosure should be included within the scope of protection of this disclosure. Therefore, the scope of protection of this disclosure should be determined by the scope of the claims.
Claims
1. A semiconductor structure, characterized in that, include: Substrate; The active region is disposed in the substrate and arranged in an array; An isolation layer is disposed between the active regions; A word line structure, wherein the word line structure passes through the active region and divides the active region into a node region and a bit line region; An expansion slot, wherein the expansion slot is partially disposed in the node area and partially disposed in the isolation layer; An expansion pad is disposed in the expansion slot; The expansion pad fills the expansion slot.
2. The semiconductor structure according to claim 1, characterized in that, The upper surface of the expansion pad is flush with the upper surface of the letter line structure.
3. The semiconductor structure according to claim 1, characterized in that, The two word line structures pass through the same active region and divide the active region into two node regions and a bit line region located between the two node regions.
4. The semiconductor structure according to claim 1, characterized in that, The semiconductor structure also includes: Bit line structure, wherein the bit line structure is disposed on the substrate and is in contact with the bit line region; An interval structure is provided between the bit line structures; The contact hole defined by the bit line structure and the spacing structure; A node contact plug is provided in the contact hole, and the node contact plug is in at least partial contact with the expansion pad.
5. The semiconductor structure according to claim 1, characterized in that, The material of the expansion pad is polycrystalline silicon or monocrystalline silicon.
6. A method for manufacturing a semiconductor structure, characterized in that, A substrate is provided, wherein an array of active regions are formed on the substrate, an isolation layer is formed between the active regions, and a word line structure passes through the active regions, wherein the active regions are divided into node regions and bit line regions by the word line structure; An expansion trench is formed on the substrate, wherein the expansion trench is partially formed in the node region and partially disposed in the isolation layer; An expansion pad is formed in the expansion groove, and the expansion pad fills the expansion groove.
7. The manufacturing method according to claim 6, characterized in that, The steps for forming the expansion slot include: A mask pattern is formed on the substrate. The mask pattern is strip-shaped and intersects with the word line structure. The bit line area is masked by the mask pattern, exposing at least part of the node area and part of the isolation layer. The substrate on which the mask pattern is formed is etched to form the extended groove.
8. The manufacturing method according to claim 7, characterized in that, The etching step includes: The exposed node regions are etched; The exposed isolation layer is etched.
9. The manufacturing method according to claim 7, characterized in that, The step of forming the expansion pad includes: A layer of extended pad material is deposited, and the substrate on which the extended pad material layer is formed is planarized to form the extended pad.
10. The manufacturing method according to claim 9, characterized in that, During the planarization process, the expansion pad material layer outside the mask pattern and the expansion groove is removed simultaneously.