Decomposition of dual qubit gates

Abstract

A gate sequence for performing quantum calculations may be generated by replacing an AshN gate with a particular dual qubit gate. The gate sequence may be generated by a classical computing system. The gate sequence generation process may include identifying, in a gate sequence, a dual qubit gate to be applied to two qubits of a quantum computing system. The dual qubit gate may be associated with Weyl coordinates x, y, and z. By utilizing the characteristics of the two qubits and Weyl coordinates, an AshN gate which is locally equivalent to the double-qubit gate can be generated. The AshN gate may be included in a gate sequence in place of the identified dual qubit gate. The gate sequence may then be applied to a quantum computing system to perform quantum computing.

Description

[0001] Priority

[0002] This application claims priority to U.S. Provisional Application No. 63 / 493,299, filed March 30, 2023, and U.S. Patent Application No. 18 / 613,924, filed March 22, 2024. The entire disclosures of all of the above applications are incorporated herein by reference. TECHNICAL FIELD

[0003] The present disclosure relates generally to quantum computing, and more specifically to decomposing arbitrary two-qubit gates into other gates. BACKGROUND

[0004] Quantum computing can solve classical intractable computational problems. However, existing quantum computing devices are limited by various sources of errors and inaccuracies. Specifically, two-qubit gate operations constitute a major source of complex errors in existing quantum computing devices. Improved implementation of two-qubit gates can improve the performance of quantum computing algorithms and advance the goal of fault-tolerant quantum computing for complex quantum computing tasks. SUMMARY

[0005] The disclosed systems and methods relate to implementing two-qubit gates using AshN dynamical decoupled driving gates (or swap gates) and single-qubit gates, if necessary, in quantum computing.

[0006] The disclosed implementations include a method for performing quantum computing. The method can include generating a sequence of gates to perform a quantum computing task. The sequence of gates can be generated by a classical computing system. The generating of the sequence of gates can include identifying, in the sequence of gates, a two-qubit gate to be applied to two qubits of a quantum computing system. The two-qubit gate can be associated with Weyl coordinates x, y, and z. The generating of the sequence of gates can include determining a dynamical decoupled driving gate that is locally equivalent to the two-qubit gate. The determining of the dynamical decoupled driving gate can include determining a gate time of the dynamical decoupled driving gate, and determining a first amplitude of a first dynamical decoupled driving associated with a first qubit of the two qubits. The first amplitude of the first dynamical decoupled driving is determined using the gate time, a sum of the y and z coordinates, and a difference of the y and z coordinates. The generating of the sequence of gates can include including the dynamical decoupled driving gate in the sequence of gates, at least partially in place of the two-qubit gate. The method can include providing instructions to apply the sequence of gates to the quantum computing system, and obtaining an output from the quantum computing system.

[0007] The disclosed implementations also include a system configured to perform the above-described method, and a computer-readable medium containing instructions for configuring a system to perform the above-described method.

[0008] The disclosed embodiment also includes a device comprising: a processor; a memory configured to store executable instructions for the processor; wherein the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method according to the above embodiment.

[0009] The disclosed embodiments further include a computer program product comprising: computer program instructions, wherein the computer program instructions enable a computer to execute the method according to the above embodiments.

[0010] The disclosed embodiments also include a computer program, which enables a computer to execute the method according to the above embodiments.

[0011] It is to be understood that both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosed embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The accompanying drawings, which constitute a part of this specification, illustrate several embodiments and, together with the description, serve to explain the principles and features of the disclosed embodiments. In the drawings:

[0013] Figure 1 Depicted are the locations of the Weyl Chamber and the Public Door.

[0014] Figure 2A Depicted is the generation of various locally inequivalent two-qubit gates using dynamically decoupled driven gates in accordance with disclosed embodiments.

[0015] Figure 2B Depicted is the generation of a two-qubit gate between an iSWAP gate and a CZ gate in a Weyl cell using an AshN gate in accordance with the disclosed embodiments.

[0016] Figure 2C Depicted is a second interactive component as a function of dynamic drive amplitude in accordance with disclosed embodiments.

[0017] Figure 2D It is shown that an AshN gate with a single decoupled drive according to the disclosed embodiments can be used to obtain (up to local equivalence) an arbitrary two-qubit gate lying in the xy plane of a Weyl cell.

[0018] Figure 3 Depicted are systems for decomposing and applying sequences of quantum gates to implement quantum computations in accordance with disclosed embodiments.

[0019] Figure 4 Depicted are exemplary methods for performing quantum computing tasks using AshN gates and single-qubit gates in accordance with disclosed embodiments. DETAILED DESCRIPTION

[0020] Reference will now be made in detail to the exemplary embodiments discussed in relation to the accompanying drawings. In some instances, like reference numerals will be used throughout the drawings and written description to refer to like or similar parts. Unless defined otherwise, technical or scientific terms have the meaning commonly understood by one of ordinary skill in the art. The disclosed embodiments are described in sufficient detail to enable those skilled in the art to practice the disclosed embodiments. It is to be understood that other embodiments can be utilized and that changes can be made without departing from the scope of the disclosed embodiments. Accordingly, the materials, methods, and examples are illustrative only and not intended to be limiting.

[0021] A quantum algorithm can be expressed in terms of a sequence of one or more quantum gates. Other sequences of quantum gates can be used to implement an arbitrary quantum gate. The particular quantum gates used to implement an arbitrary quantum gate can depend on the physical implementation of the quantum device (e.g., a particular physical implementation can be associated with one or more “native” quantum gates). The performance of an arbitrary quantum gate can depend on the performance of the native quantum gates used to implement the arbitrary quantum gate.

[0022] As noted above, two-qubit gate operations constitute a major source of complex errors in existing quantum computing devices. The disclosed embodiments involve implementing arbitrary two-qubit gates using a decoupled driving gate (i.e., an AshN gate) in combination with other single-qubit gates.

[0023] As disclosed herein, a universal quantum circuit can be implemented using AshN gates (and any necessary single-qubit gates). In some embodiments, arbitrary two-qubit gates (except for SWAP gates) can be implemented as AshN gates. The parameters of the AshN gates can be determined on a classical computing device, and the compiled sequence can be run directly on an arbitrary quantum computing device that supports a native implementation of the AshN gate. In some embodiments, the AshN gate can be implemented using two transversely coupled resonator qubits, with each qubit also subject to a microwave drive. It will be appreciated that other implementations are possible. For example, two transmon qubits can be coupled by a capacitive coupling, with each qubit having an independent microwave drive. In some embodiments, the microwave drive can be a sinusoidal wave having a fixed frequency and amplitude. As another example, the AshN gate can also be implemented using a flux drive configured to acquire a similar Hamiltonian.

[0024] Universal two-qubit gates can be mathematically expressed as elements of the special unitary group SU(4). The KAK decomposition and Weyl chamber provide mathematical tools for characterizing two-qubit gates in terms of single-qubit gates. Figure 1 The Weyl chamber and common gates (e.g., B gates, CNOT gates, CZ gates, SWAP gates, iSWAP gates, identity gates, gates, the position of the gate (either a CNOT gate, a QFT gate, or an ECP gate).

[0025] Theorem 1 (KAK decomposition). For any U ∈ SU(4), there exists a unique single-qubit rotations A0, A1, B0, B1 ∈ SU(2) and a global phase g ∈ {1, i} such that: where: the tuple is called the KAK decomposition of the unitary matrix U.

[0026] The equivalence class (denoted by ) of a unitary matrix U under local unitary transformations is characterized by an interaction coefficient η(U) that lies in a three-dimensional tetrahedron called the Weyl chamber:

[0027] Two unitary matrices U, V ∈ SU(4) are locally equivalent or denoted by U ~ V if η(U) = η(V). Let be a standard element of the equivalence class, then for all U ∈ SU(4), we have U ~ L(η(U)).

[0028] According to the disclosed embodiments, adjusting the parameters of the dynamically decoupled driving gate can obtain different two-qubit gates. Given two resonant qubits, and a dynamically decoupled driving on the second qubit, the Hamiltonian can be expressed as:

[0029]

[0030] In this example, g is the transverse coupling strength between the qubits, and Ω is the driving amplitude. The matrix exponential of the Hamiltonian can be expressed as:

[0031]

[0032] where:

[0033]

[0034] In this example, the parameters g, t, and Ω can be selected to realize a dynamically driven CZ gate (equivalent to an MS gate):

[0035]

[0036] For example, selecting:

[0037]

[0038] B(g, t, Ω) = C(g, t, Ω) = 0 can be achieved. Therefore:

[0039]

[0040] Thus:

[0041]

[0042] This in turn implies:

[0043]

[0044] The appropriate coefficients can be obtained as follows:

[0045]

[0046] Then:

[0047]

[0048] Thus:

[0049] t = π / (2g) + jπ / g

[0050] To obtain the minimum positive solution for the driving amplitude Ω and time t, j = 0, and: t = π / 2g

[0051] Then,

[0052]

[0053] This is the DDCZ gate, up to global phase.

[0054] A more complicated Hamiltonian can be used, which includes ZZ errors. In some such implementations, a dynamic decoupling drive can be applied to each qubit:

[0055]

[0056] The matrix exponential of this Hamiltonian (exp[-it / 2*H(Ω1,Ω2)]) can be obtained.

[0057] The (00,01) term of this matrix exponential can be set to zero when Ω1 and Ω2 satisfy the following relationship:

[0058]

[0059] Then, letting t = π / 2g, the appropriate amplitudes can be obtained as:

[0060]

[0061] The values of k and j can be chosen (e.g., in this case, take k = j = 1):

[0062]

[0063] These equations place bounds on the values of g and h. Real solutions exist when |g - h|, |g + h| < 4g or h e [-3g, 3g]. For such values of g and h, the exponentiated Hamiltonian is the DDCZ gate, up to global phases.

[0064] In some embodiments, the DDCZ gate can produce the same type of single-qubit phase error as the fSim gate. Such errors can be represented in a rotating reference frame as:

[0065]

[0066] These errors can be handled by absorbing them into adjacent single-qubit gates, or by using a custom compilation scheme for specific circuits (e.g., syndrome extraction).

[0067] In a simplified model of DDCZ, adding a phase shift to a single dynamic decoupling pulse can achieve the following Hamiltonian:

[0068]

[0069] The corresponding unitary matrix can be represented as:

[0070]

[0071] Using the excitation-conserving property of the iSWAP family of gates:

[0072]

[0073] Thus:

[0074]

[0075] Thus, when t = π / 2g and the achieved unitary matrix can be:

[0076]

[0077] As a further step in this derivation, in the presence of ZZ errors, a phase shift can be added to each dynamic decoupling drive pulse. Then, the Hamiltonian becomes:

[0078]

[0079] When the phase shifts of the dynamic decoupling drives are equal, their effect is the same as in the case of a single dynamic decoupling drive pulse.

[0080] For Letting t = π / 2g and using the amplitude relationship above, the resulting unitary matrix is ​​generally not locally equivalent to the DDCZ gate. The values ​​of t, Ω1, and Ω2 required to obtain the DDCZ gate may depend on and

[0081] Depending on the values ​​of g and h, different locally inequivalent gates can be obtained. Figure 2A Depicts the generation of various such locally inequivalent two-qubit gates using dynamically decoupled driven gates according to the disclosed embodiments. The axes of the graph shown are the Cartan decomposition parameters of the gates with specified values ​​of g and h.

[0082] According to the disclosed embodiment, the AshN gate may be defined as:

[0083] AshN(t,Ω):=exp[-iH(Ω)t / 2]

[0084] in:

[0085]

[0086] As shown above, the iSWAP gate and the DDCZ gate can be implemented using specific gate drive (Ω) and time (t) values:

[0087]

[0088] By the interval By internally varying the gate drive (Ω), a two-qubit gate between an iSWAP gate and a DDCZ gate can be realized in a Weyl cell. Figure 2B The generation of such a two-qubit gate between an iSWAP gate and a CZ gate in a Weyl cell using an AshN gate according to the disclosed embodiments is depicted. The axes of the graph shown are the Cartan decomposition parameters of the gate with specified values ​​of Ω and t, where Ω is in the interval Internal changes.

[0089] Specifically, if Figure 2B As shown, in the interval Internal gate drive Ω B , so that the Cartan decomposition parameter of the gate with parameter “AshN” is Therefore, there is a gate drive that can realize the B gate.

[0090] Figure 2C The second interactive component is depicted as a function of the dynamic drive amplitude according to the disclosed embodiment. The second interactive component has been normalized to π / 4, while the dynamic drive amplitude has been normalized to

[0091] Figure 2DCartan decomposition parameters for the gate "AshN"(t, Ω) are shown, with parameter t varying between 0 and π / g and parameter Ω varying between 0 and As shown, according to the disclosed embodiments, an AshN gate with a single decoupled drive can be used to obtain (up to local equivalence) any two-qubit gate that lies in the xy-plane of the Weyl chamber.

[0092] According to the disclosed embodiments, suitable values for the parameters t and Ω can be calculated directly. The Makhlin invariant can be calculated as:

[0093]

[0094] where:

[0095]

[0096] The matrix exponential of the gate "AshN"(t, Ω) can be substituted into the formula for the Makhlin invariant to obtain:

[0097]

[0098] For all g, t, Ω, G1 is a real number, so one of the Cartan interaction coefficients is zero. By projecting into the Weyl chamber defined by the formula:

[0099]

[0100] It can be seen that for all g, t, Ω, z = 0.

[0101] The Makhlin invariant can be related to the Cartan interaction coefficients as follows:

[0102]

[0103] G2 = 4 cos 2 (2x) cos 2 (2y) cos 2 (2z) - 4 sin 2 (2x) sin 2 (2y) sin 2 (2z) - cos(4x) cos(4y) cos(4z)

[0104] By setting z = 0, these relationships can be simplified to:

[0105] G1 = cos 2 (2x) cos 2 (2y)

[0106] G2 = 2 cos 2(2x) + 2cos 2 (2y) - 1

[0107] These equations can be mapped to the Makhlin invariants formula when the following conditions are met:

[0108] cos 2 (2x) = cos 2 (gt)

[0109]

[0110] As mentioned above, Thus cos(2x), cos(2y) > 0. Since these functions are positive:

[0111] cos(2x) = cos (gt)

[0112]

[0113] Thus, And

[0114]

[0115] These relations can be used to generate the entire xy-plane of the Weyl chamber. For example, take t e [0, π / (2g)], to get all x e [0, π / 4]. When t = 0, take Ω = 0, to get the point (0, 0). For a fixed t > 0, take Ω = 0, to get y = x. Then take to get y = 0. Since y is a continuous function of Ω, by changing Ω one can get all values of y e [0, x]. According to the disclosed embodiments, by setting t = π / 2g (so that x = π / 4) one can get the DDCZ gate. Then:

[0116]

[0117] To get the B gate, one can solve the above relations for x = π / 4, y = π / 8. In the first step, one can choose t to be:

[0118] t = π / 2g

[0119] And the relation:

[0120]

[0121] represents

[0122]

[0123] where, The equation can be solved numerically to give ζ0≈5.00712. Thus, to obtain the B gate, one can apply an Ashn gate with t = π / 2g and

[0124] As described herein, the Hamiltonian for a dynamically driven two-qubit gate with double driving can be

[0125]

[0126] Using the commutation relations, one can locally conjugate the Hamiltonian to X→Z, Y→X, Z→-Y to obtain

[0127]

[0128] The modified Hamiltonian H' has the invariant subspaces {|00>, |11>} and {|10>, |01>}, and the corresponding unitary matrix U(t, Ω1, Ω2):=exp{-itH'(Ω1, Ω2)} has the same space and non-zero elements. In some embodiments, U(t, Ω1, Ω2)=e -igt V0+e igt V1, where V0and V1are two SU(2) rotations acting on the subspaces spanned by {|00>, |11>} and {|10>, |01>}, respectively. Since these two subspaces are also invariant under one obtains

[0129]

[0130] Thus, in terms of local equivalence, the gate can be determined by the relative phase difference between the two blocks gt, and

[0131]

[0132] In the context of the standard Weyl chamber element:

[0133]

[0134] The standard element also has invariant subspaces spanned by {|00>, |11>} and {|10>, |01>}, and the corresponding three eigenvalues are c, sin(a+b), and sin(a-b). The Weyl chamber can be defined as where 1≥sin(a+b)≥sin(a-b)≥0. The first equality holds only for the SWAP gate. Otherwise, there exists a U(t, Ω1, Ω2) that generates a locally equivalent gate. Let t=(2kπ+c) / g, where some Then, given:

[0135]

[0136] |f(θ)|≤1, but by proper choice of k, any number in the interval (-1, 1) can be achieved. Thus, by proper choice of k and θ1 and θ2 that yield desired Ω1 and Ω2, sin(a + b) and sin(a - b) can be achieved. However, a SWAP gate cannot be achieved by such a construction because a SWAP gate requires and f(θ) = 1, which cannot be satisfied simultaneously.

[0137] Figure 3 A system 300 for determining a sequence of quantum gates to implement a quantum computation is depicted in accordance with the disclosed embodiments. The system 300 can include a classical component 310 (e.g., one or a set of classical computing devices) and a quantum component 320.

[0138] The classical component 310 can be configured to control the quantum device 320. The classical component can include a compilation module 311. The compilation module 311 can be configured to take a description of a quantum computation task (unitary matrix, quantum circuit, etc.) and determine an implementation of the quantum computation task. The implementation can be a sequence of gates. The sequence of gates can include AshN gates (and, if necessary, SWAP gates) and single-qubit gates.

[0139] In some embodiments, a gate module 313 (which can be implemented as a submodule of the compilation module 311) can be configured to determine parameters of an AshN gate that is locally equivalent to a given two-qubit gate. In some embodiments, the gate module 313 can also determine a single-qubit gate such that the combination of the single-qubit gate and the AshN gate equals the given two-qubit gate, up to global phase. The gate decomposition module 313 can obtain a two-qubit gate from the compilation module 311. In response, the gate decomposition module 313 can determine parameters of an AshN gate that is locally equivalent to the given two-qubit gate (and parameters of any single-qubit gates needed to implement the obtained two-qubit gate) and provide them to the compilation module 311.

[0140] A quantum controller 315 can be configured to directly control the quantum component 320. The quantum controller 315 can be a digital computing device (e.g., a computing device that includes a central processing unit, a graphics processing unit, an application-specific integrated circuit, a field-programmable gate array, or other suitable processor). The quantum controller 315 can configure the quantum component 320 for computation, provide quantum gates to the quantum circuit 320, and read state information from the quantum circuit 320.

[0141] The quantum controller 315 can include an instruction generation module 316. The instruction generation module 316 can be configured to provide bias drives, directly or indirectly, to the quantum circuit 320 to enable or disable interactions between qubits. The instruction generation module 316 can provide bias drives indirectly by providing instructions to a bias drive source (e.g., a waveform generator, etc.) such that the bias drive source provides the bias drives to the circuit 320. The instruction generation module 316 can apply quantum gates by providing one or more microwave pulses (or other gate drives) to qubits in the quantum component 320. In various implementations, the instruction generation module 316 can implement such gates by providing instructions to a computational drive source (e.g., a waveform generator, etc.) such that the computational drive source provides such microwave pulses (or other gate drives) to qubits in the quantum component 320. The microwave pulses can be selected or configured to implement one or more quantum gates, as described herein. The microwave pulses can be provided to the qubits using one or more coils coupled to the respective qubits. The coils can be external to the quantum component 320 or on a chip that implements the quantum component 320.

[0142] The quantum controller 315 can be configured to determine state information for the quantum component 320. In some implementations, the quantum controller 315 can measure a state of one or more qubits of the quantum component 320. The state can be measured at completion of one or more quantum operation sequences. In some implementations, the instruction generation module 316 can provide a probe signal (e.g., a microwave probe tone) to a coupled resonator of the quantum component 320 or provide instructions to a readout device (e.g., an arbitrary waveform generator) that provides the probe signal.

[0143] In various implementations, the quantum controller 315 can include a data processing module 317. The data processing module 317 can take an output signal (e.g., electrical / photonic), convert it to a discrete signal, and perform data processing (e.g., averaging, post-processing) on it to obtain a computational result. In some implementations, the data processing module 317 can include or be configured to receive information from a detector that is configured to determine an amplitude and a phase of an output signal received from a coupled resonator in response to provision of a microwave probe tone. The amplitude and phase of the output signal can be used to determine a state of a probed qubit. The disclosed implementations are not limited to any particular method of measuring a state of a qubit.

[0144] The quantum components 320 can be configured to receive commands (e.g., bias drives, quantum gates, probe signals, etc.) from the classical components 310. In some implementations, the quantum components 320 can be implemented using a superconducting quantum circuit coupled to the quantum controller 315 using at least one microwave drive line. According to the disclosed implementations, the superconducting quantum circuit can implement multiple qubits (e.g., transmon qubits, fluxonium qubits, or any other suitable type of qubit). In some implementations, the superconducting quantum circuit can be implemented using one or more chips containing qubits, each chip including at least a portion of a microwave drive line coupling the qubits to the quantum controller 315.

[0145] Figure 4 An exemplary method 400 for performing a quantum computing task using AshN gates and single-qubit gates is depicted, according to the disclosed implementations. In some implementations, the method 400 can be performed using the system 400. The method 400 can include operations performed on a conventional computing device (e.g., a mobile device, a laptop, a desktop, a workstation, a computing cluster, a cloud computing platform, etc.) and operations performed on a quantum computing device (e.g., a quantum controller managing a superconducting circuit, a trapped-ion quantum system, a topological quantum computing system, a photonic quantum computing system, etc.). The sequence of gates can be generated by the conventional computing device. The conventional computing device can provide instructions to the quantum computing device to apply the sequence of gates to an appropriate arrangement of qubits. The quantum computing device can perform the quantum computing task by applying the sequence of gates. The conventional computing device can then provide instructions to the quantum computing device to read out the results of the quantum computing task.

[0146] In step 410, the conventional computing device (e.g., the classical components 310) can obtain a description of a quantum computing task. According to the disclosed implementations, the description of the quantum computing task can include a sequence of quantum gates to be applied to a set of two or more qubits, a unitary matrix to be applied to a set of two or more qubits, a function call of a quantum algorithm, or other suitable description. The conventional computing device can receive or retrieve the description of the quantum computing task from another system or a user of the conventional computing device. For example, the user can interact with an interface provided by the conventional computing device to generate the description of the quantum computing task.

[0147] In step 420, the conventional computing device can create a sequence of AshN gates and single-qubit gates to perform the quantum computing task. If necessary, the sequence can include SWAP gates. In some implementations, the conventional computing device can create a first implementation of the quantum computing task as a sequence of arbitrary two-qubit gates. According to the disclosed implementations, each two-qubit gate can then be implemented using an AshN gate and (optionally) a single-qubit gate.

[0148] For example, when the description of the quantum computing task includes a unitary matrix, the unitary matrix can be decomposed into a sequence of gates. The sequence of gates can include two-qubit gates. The disclosed implementations are not limited to any particular method of decomposing a unitary matrix into a sequence of gates. Similarly, when the description of the quantum computing task includes a function call, a conventional computing device can obtain a sequence of gates that implements the function call. The disclosed implementations are not limited to any particular method of generating such a sequence of gates.

[0149] According to the disclosed implementations, a conventional computing device can be configured to convert one or more gates in a sequence of gates (e.g., gates received by, retrieved by, or generated by the conventional computing device) to AshN gates that are locally equivalent to the one or more gates. The conventional computing device can also be configured to generate one or more single-qubit gates to apply with the AshN gates to implement the one or more gates described above. For example, the conventional computing device can convert a sequence of gates to a corresponding sequence of AshN gates (which can also include SWAP gates and / or single-qubit gates).

[0150] In some implementations, as part of the conversion of the sequence of gates, the conventional computing device can identify a two-qubit gate. As described herein, in some implementations, a SWAP gate cannot be implemented using AshN gates. Accordingly, the conventional computing device can be configured to determine whether the two-qubit gate is a SWAP gate. In response to determining that the two-qubit gate is not a SWAP gate, the conventional computing device can determine an AshN implementation of the two-qubit gate. Accordingly, the converted sequence of gates can include both SWAP gates and AshN gates.

[0151] The conventional computing device can determine the Weyl coordinates x, y, and z of the identified two-qubit gate. For example, the conventional computing device can perform a KAK decomposition to determine the interaction coefficients of the two-qubit gate. Subsequently, the conventional computing device can determine a drive time and a drive amplitude value for each qubit. In a first step, the conventional computing device can determine a gate time using the interaction strength of the two qubits and the identified x coordinate of the two-qubit gate. The conventional computing device can determine the gate time such that the product of the interaction strength and the gate time (e.g., gt) is equivalent to the x coordinate. This equivalence can be determined by an equivalence condition. For example, when f1(gt) = f2(x), gt can be equivalent to x. For another example, when |sin(gt)| = sin(x), gt can be equivalent to x.

[0152] In some implementations, the conventional computing device can determine a set of candidate gate times that satisfy the equivalence condition (e.g., given the interaction strength). For example, when the equivalence condition is |sin(gt)| = sin(x), such candidate gate times can include t0= x / g, and so on.

[0153] In some embodiments, a conventional computing device can select a gate time from a set of candidate gate times. In some cases, the selected gate time can be the minimum gate time. In some cases, the sum of the magnitudes of the y-interaction coordinate and the z-interaction coordinate can be used to select the gate time. In some embodiments, the following function can be defined as:

[0154]

[0155] This function is closely related to the solutions of the equation tan 0 = 0. Let 0 k be the kth smallest positive solution of the equation tan 0 = 0, then, where k is the smallest integer satisfying 0 k > a. Given a set of candidate solutions {t l : |sin(t l )| = sin(x)} and l is the smallest such that 0 l > sin(y + |z|), then t l will be the optimal drive time.

[0156] In some embodiments, a conventional computing device can determine the dynamic decoupling gate drive amplitudes for two qubits. The sum of the two gate drive amplitudes can depend on the sum of the y and z interaction coordinates. The difference of the two gate drive amplitudes can depend on the difference of the y and z interaction coordinates.

[0157] For example, in some embodiments, the two gate drive amplitudes can depend on two intermediate values 0i, 0 2 > gt l In such embodiments, the conventional computing device can find 0i such that |sin(0i) / 0i|*gt l = sin(y + z), and can find |sin(0 2) / 0 2 |*gt l = sin(y - z). Due to the continuity of |sin(0) / 0|*gt l , the existence of these solutions is guaranteed. Further, the sum of the two gate drives can be chosen as and the difference of the two gate drives can be chosen as

[0158] In some embodiments, in addition to determining the implementation of an AshN gate that is locally equivalent to an identified two-qubit gate, a conventional computing device can determine one or more single-qubit gates. These single-qubit gates can act as corrections to enable the locally equivalent AshN gate to implement the original two-qubit gate.

[0159] In some cases, the implementation of an AshN gate can need to accommodate ZZ coupling between qubits. In such cases, the above-mentioned features |<0|V0|1>| and |<0|V1|1>| can be expressed in terms of local equivalence as:

[0160]

[0161] and

[0162]

[0163] As described herein, these features can be used to obtain appropriate values for gate times and drive amplitudes.

[0164] In step 430, the conventional computing device can provide instructions to the quantum computing device (e.g., quantum component 320) to apply the sequence of gates to the appropriate arrangement of qubits. The instructions can specify parameters (e.g., amplitude, phase, frequency, duration, etc.) of the microwave drive to implement the AshN gates (or SWAP gates, single-qubit gates) in the appropriate order. The quantum computing device can perform the quantum computing task by applying the sequence of gates to the qubits.

[0165] In step 440, the conventional computing device can provide instructions to the quantum computing device to read out the result of the quantum computing task. The disclosed implementations are not limited to any particular method of reading out the result of the task.

[0166] The disclosed implementations are not limited to implementations that include a quantum computing device. In some implementations, the application of the sequence of gates to the appropriate arrangement of qubits can be simulated by the original conventional computing device or another separate conventional computing device. For example, the sequence of gates can be generated on a laptop computer and a cloud computing platform can be used to stimulate the application of the sequence of gates. After the simulation is complete, the results of the simulation can be provided to the original conventional computing device.

[0167] In some implementations, a non-transitory computer-readable storage medium comprising instructions is also provided, and the instructions can be executed by a device (e.g., the disclosed encoders and decoders) for performing the above-described methods. Common forms of non-transitory media include, for example, a floppy disk, flexible disk, hard disk, solid-state drive, magnetic tape, or any other magnetic data storage medium, a CD-ROM, any other optical data storage medium, any physical medium with patterns of holes, a RAM, a PROM, and EPROM, a FLASH-EPROM or any other flash memory, NVRAM, a cache, a register, any other memory chip or cartridge, and a network version thereof. The device can include one or more processors (CPUs), input / output interfaces, network interfaces, and / or memory.

[0168] The foregoing description is presented for the purpose of illustration. It is not intended to be exhaustive or to limit the implementation to the precise form disclosed. Modifications and variations are possible in light of the detailed description and teaching provided herein. For example, the described implementations include hardware, but systems and methods consistent with the present disclosure can be implemented in hardware and software. Moreover, while certain components have been described as coupled, these components can be integrated or distributed in any suitable manner.

[0169] Moreover, although illustrative implementations have been described herein, the scope includes any and all implementations having equivalent elements, modifications, omissions, combinations, permutations, adjustments or alterations based on the disclosed implementations. The elements of the claims are not limited to the specific embodiments described herein, but include any and all implementations consistent with the language of the claims. Furthermore, the steps of the disclosed methods can be modified in any manner, including reordering steps or inserting or deleting steps, without departing from the scope of the methods.

[0170] It should be noted that relational terms herein, such as“first” and“second”, are used solely to distinguish one from another entity or action without necessarily requiring or implying any actual relationship or order between such entities or actions. Moreover, the words“comprises,”“has,”“contains,” and“includes” and other similar forms are intended to be open-ended and to mean the inclusion of one or more items, but not the exclusion of any items not specifically listed. It is noted that the terms“comprises”,“comprising”,“includes”,“including” and the like are used herein to mean that the item(s) include the item(s) listed thereafter but do not exclude the presence of one or more other item(s).

[0171] The features and advantages of the present disclosure will be apparent from the detailed description, and thus, it is intended that all systems and methods falling within the true spirit and scope of the present disclosure be covered by the appended claims. As used herein, the indefinite articles“a” and“an” means“one or more.” Similarly, the use of the plural is not necessarily intended to mean multiple, unless clearly indicated in the context of the given claim. Furthermore, since numerous modifications and changes will readily occur to those skilled in the art, it is not desired to limit the present disclosure to the exact construction and operation described herein, and accordingly, all suitable modifications and equivalents can be resorted to as falling within the scope of the present disclosure.

[0172] As used herein, unless expressly stated to the contrary, the term "or" includes all possible combinations. For example, if a database is stated as capable of including A or B, then the database is able to include A; or B; or both A and B unless specifically stated otherwise or the context clearly indicates otherwise. As a second example, if a database is stated as capable of including A, B, or C, then the database is able to include A; or B; or C; or A and B; or A and C; or B and C; or A and B and C unless specifically stated otherwise or the context clearly indicates otherwise.

[0173] It should be understood that the above-described implementations can be implemented by hardware, software (program code), or a combination of hardware and software. If implemented by software, it can be stored in the above-described computer-readable medium. When executed by a processor, the software can perform the disclosed method. The computing units and other functional units described in the present disclosure can be implemented by hardware, software, or a combination of hardware and software. Those of ordinary skill in the art will also understand that a plurality of the above-described modules / units can be combined into one module / unit, and each of the above-described modules / units can be further divided into a plurality of sub-modules / sub-units.

[0174] In the foregoing specification, implementations have been described with reference to numerous specific details that can vary from implementation to implementation. Certain alterations and modifications of the described implementations can be practiced within the scope of the disclosure. Other implementations can be apparent to those of ordinary skill in the art upon reading the foregoing specification. The specification and described implementations are to be considered exemplary only, with the true scope and spirit of the disclosure being indicated by the following claims. The sequence of steps shown in the figures is also intended to be exemplary only, and is not intended to be limiting to any particular sequence of steps. Accordingly, those skilled in the art will recognize that the steps could be performed in other sequences without departing from the disclosure.

[0175] Implementations can be further described using the following clauses:

[0176] 1. A system for performing quantum computations, comprising:

[0177] a quantum component; and a classical component comprising at least one processor and at least one non-transitory computer-readable medium containing instructions that, when executed by the at least one processor, cause the classical component to perform operations comprising: obtaining a description of a quantum computing task; generating a sequence of gates to perform the quantum computing task, the generating of the sequence of gates comprising: identifying, in the sequence of gates, a two-qubit gate to be applied to two qubits of the quantum component, the two-qubit gate being associated with Weyl coordinates x, y, and z; determining a dynamically decoupled drive gate that is locally equivalent to the two-qubit gate, the determining of the dynamically decoupled drive gate comprising: determining a gate time of the dynamically decoupled drive gate; and determining a first amplitude of a first dynamically decoupled drive associated with a first qubit of the two qubits using: the gate time; a sum of the y and z coordinates; and a difference of the y and z coordinates; including the dynamically decoupled drive gate in the sequence of gates, at least partially in place of the two-qubit gate; and providing instructions to apply the sequence of gates to the quantum component and obtaining an output from the quantum component.

[0178] 2. The system of clause 1, wherein: the gate time is determined using: an interaction strength of the two qubits; and the x coordinate.

[0179] 3. The system of clause 2, wherein: the determining of the gate time comprises: determining a minimum gate time such that, under the equivalence condition, a product of the interaction strength and the gate time is equivalent to the x coordinate.

[0180] 4. The system of any one of clauses 1 to 3, wherein: the determining of the gate time comprises: determining a set of candidate gate times, the candidate gate times satisfying the x coordinate equivalence condition; and selecting a candidate gate time from the set of candidate gate times as the gate time.

[0181] 5. The system of clause 4, wherein: the candidate gate time is selected from the set of candidate gate times using the sum of the amplitudes of the y and z coordinates.

[0182] 6. The system of any one of clauses 1 to 5, wherein: the determining of the dynamically decoupled drive gate further comprises: determining a second amplitude of a second dynamically decoupled drive associated with a second qubit of the two qubits; wherein a sum of the first amplitude and the second amplitude depends on the sum of the y and z coordinates; and a difference of the first amplitude and the second amplitude depends on the difference of the y and z coordinates.

[0183] 7. The system of any one of clauses 1 to 6, wherein: the dynamically decoupled drive gate is determined in response to determining that the two-qubit gate is not a swap gate.

[0184] 8. The system of any one of clauses 1 to 7, wherein: the one or more single-qubit gates and the dynamically decoupled drive gate in place of the two-qubit gate are included in the sequence of gates.

[0185] 9. A method for performing a quantum computation, comprising: generating, by a classical computing system, a sequence of gates to perform a quantum computation task, the generating of the sequence of gates including: identifying, in the sequence of gates, a two-qubit gate to be applied to two qubits of a quantum computing system, the two-qubit gate being associated with Weyl coordinates x, y, and z; determining a dynamically decoupled drive gate that is locally equivalent to the two-qubit gate, the determining of the dynamically decoupled drive gate including: determining a gate time for the dynamically decoupled drive gate; and determining a first amplitude of a first dynamically decoupled drive associated with a first qubit of the two qubits using: the gate time; a sum of the y and z coordinates; and a difference of the y and z coordinates; including the dynamically decoupled drive gate in the sequence of gates, at least partially in place of the two-qubit gate; and providing instructions to apply the sequence of gates to the quantum computing system and obtaining an output from the quantum computing system.

[0186] 10. The method of clause 9, wherein: the gate time is determined using: an interaction strength of the two qubits; and the x coordinate.

[0187] 11. The method of clause 10, wherein: the determining of the gate time includes: determining a minimum gate time such that, under the equivalence condition, a product of the interaction strength and the gate time is equivalent to the x coordinate.

[0188] 12. The method of any one of clauses 9 to 11, wherein: the determining of the gate time includes: determining a set of candidate gate times, the candidate gate times satisfying the x coordinate equivalence condition; and selecting a candidate gate time from the set of candidate gate times as the gate time.

[0189] 13. The method of clause 12, wherein: the candidate gate time is selected from the set of candidate gate times using the sum of the magnitudes of the y and z coordinates.

[0190] 14. The method of any one of clauses 9 to 13, wherein: the determining of the dynamically decoupled drive gate further includes: determining a second amplitude of a second dynamically decoupled drive associated with a second qubit of the two qubits; wherein a sum of the first amplitude and the second amplitude depends on the sum of the y and z coordinates; and a difference of the first amplitude and the second amplitude depends on the difference of the y and z coordinates.

[0191] 15. A non-transitory computer-readable medium containing instructions that, when executed by at least one processor of a classical computing system, cause the classical computing system to perform operations comprising: obtaining a description of a quantum computing task; generating a sequence of gates to perform the quantum computing task, the generating of the sequence of gates comprising: identifying, in the sequence of gates, a two-qubit gate to be applied to two qubits of a quantum computing system, the two-qubit gate being associated with Weyl coordinates x, y, and z; determining a dynamically decoupled drive gate that is locally equivalent to the two-qubit gate, the determining of the dynamically decoupled drive gate comprising: determining a gate time for the dynamically decoupled drive gate; and determining a first amplitude of a first dynamically decoupled drive associated with a first qubit of the two qubits using: the gate time; a sum of the y and z coordinates; and a difference of the y and z coordinates; including the dynamically decoupled drive gate in the sequence of gates, at least partially in place of the two-qubit gate; and providing instructions to apply the sequence of gates to the quantum computing system and obtaining an output from the quantum computing system.

[0192] 16. The non-transitory computer-readable medium of clause 15, wherein: the gate time is determined using: an interaction strength of the two qubits; and the x coordinate.

[0193] 17. The non-transitory computer-readable medium of clause 16, wherein: the determining of the gate time comprises: determining a minimum gate time such that, under the equivalence condition, a product of the interaction strength and the gate time is equivalent to the x coordinate.

[0194] 18. The non-transitory computer-readable medium of any one of clauses 15 to 17, wherein: the determining of the gate time comprises: determining a set of candidate gate times, the candidate gate times satisfying the x coordinate equivalence condition; and selecting a candidate gate time from the set of candidate gate times as the gate time.

[0195] 19. The non-transitory computer-readable medium of clause 18, wherein: the candidate gate time is selected from the set of candidate gate times using the sum of the magnitudes of the y and z coordinates.

[0196] 20. The non-transitory computer-readable medium of any one of clauses 15 to 19, wherein: the determining of the dynamically decoupled drive gate further comprises: determining a second amplitude of a second dynamically decoupled drive associated with a second qubit of the two qubits; wherein a sum of the first amplitude and the second amplitude depends on the sum of the y and z coordinates; and a difference of the first amplitude and the second amplitude depends on the difference of the y and z coordinates.

[0197] 21. An apparatus for performing quantum computations, comprising: a processor; a memory configured to store executable instructions of the processor; wherein the processor is configured to read the executable instructions from the memory and execute the instructions to implement a method according to any one of clauses 9 to 14.

[0198] 22. A computer program product comprising computer program instructions which enable a computer to perform the method according to any one of clauses 9 to 14.

[0199] 23. A computer program which enables a computer to perform the method according to any one of clauses 9 to 14.

[0200] In the drawings and specification, there have been disclosed exemplary embodiments. However, many variations and modifications can be made to these embodiments. Consequently, it is not intended that the present application be limited to the particular embodiments described herein, but that the present application include all embodiments falling within the scope of the appended claims.

Claims

1. A system for performing quantum computations, comprising: a quantum component; and a classical component comprising at least one processor and at least one non-transitory computer-readable medium containing instructions that, when executed by the at least one processor, cause the classical component to perform operations comprising: obtaining a description of a quantum computation task; generating a sequence of gates implementing the quantum computation task, the generating of the sequence of gates comprising: identifying, in the sequence of gates, a two-qubit gate to be applied to two qubits of the quantum component, the two-qubit gate being associated with Weyl coordinates x, y, and z; determining a dynamically decoupled driving gate locally equivalent to the two-qubit gate, the determining of the dynamically decoupled driving gate comprising: determining a gate time of the dynamically decoupled driving gate; and determining a first amplitude of a first dynamically decoupled driving associated with a first qubit of the two qubits using: the gate time; a sum of the y and z coordinates; and a difference of the y and z coordinates; including the dynamically decoupled driving gate in the sequence of gates, at least partially in place of the two-qubit gate; and providing instructions to apply the sequence of gates to the quantum component and obtaining an output from the quantum component.

2. The system of claim 1, wherein: the gate time is determined using: an interaction strength of the two qubits; and the x coordinate.

3. The system of claim 2, wherein: the determining of the gate time comprises: determining a minimum gate time such that, under an equivalence condition, a product of the interaction strength and the gate time is equivalent to the x coordinate.

4. The system of any one of claims 1 to 3, wherein: the determining of the gate time comprises: determining a set of candidate gate times that satisfy an x coordinate equivalence condition; and selecting a candidate gate time from the set of candidate gate times as the gate time.

5. The system of claim 4, wherein: the one candidate gate time is selected from the set of candidate gate times using a sum of magnitudes of the y coordinate and the z coordinate.

6. The system of any one of claims 1 to 5, wherein: the determining of the dynamically decoupled driving gate further comprises: determining a second amplitude of a second dynamically decoupled driving associated with a second qubit of the two qubits; wherein a sum of the first amplitude and the second amplitude depends on the sum of the y and z coordinates; and wherein a difference of the first amplitude and the second amplitude depends on the difference of the y and z coordinates.

7. The system of any one of claims 1 to 6, wherein: the dynamically decoupled driving gate is determined in response to determining that the two-qubit gate is not a swap gate.

8. The system of any one of claims 1 to 7, wherein: one or more single-qubit gates are included in the sequence of gates in place of the two-qubit gate along with the dynamically decoupled driving gate.

9. A method for performing quantum computations, comprising: generating, by a classical computing system, a sequence of gates to perform a quantum computing task, the generating of the sequence of gates comprising: identifying, in the sequence of gates, a two-qubit gate to be applied to two qubits of a quantum computing system, the two-qubit gate being associated with Weyl coordinates x, y, and z; determining a dynamically decoupled driving gate locally equivalent to the two-qubit gate, the determining of the dynamically decoupled driving gate comprising: determining a gate time for the dynamically decoupled driving gate; and determining a first amplitude of a first dynamically decoupled driving associated with a first qubit of the two qubits using: the gate time; a sum of the y and z coordinates; and a difference of the y and z coordinates; including the dynamically decoupled driving gate in the sequence of gates, at least partially in place of the two-qubit gate; and providing instructions to apply the sequence of gates to the quantum computing system and obtaining an output from the quantum computing system.

10. The method of claim 9, wherein: the gate time is determined using: an interaction strength of the two qubits; and the x coordinate.

11. The method of claim 10, wherein: the determining of the gate time comprises: determining a minimum gate time such that, under an equivalence condition, a product of the interaction strength and the gate time is equivalent to the x coordinate.

12. The method of any one of claims 9 to 11, wherein: the determining of the gate time comprises: determining a set of candidate gate times that satisfy an x coordinate equivalence condition; and selecting a candidate gate time from the set of candidate gate times as the gate time.

13. The method of claim 12, wherein: the one candidate gate time is selected from the set of candidate gate times using a sum of magnitudes of the y coordinate and the z coordinate.

14. The method of any one of claims 9 to 13, wherein: the determining of the dynamically decoupled driving gate further comprises: determining a second amplitude of a second dynamically decoupled driving associated with a second qubit of the two qubits; wherein a sum of the first amplitude and the second amplitude depends on the sum of the y and z coordinates; and wherein a difference of the first amplitude and the second amplitude depends on the difference of the y and z coordinates.

15. A non-transitory computer-readable medium containing instructions that, when executed by at least one processor of a classical computing system, cause the classical computing system to perform operations comprising: obtaining a description of a quantum computing task; generating a sequence of gates to implement the quantum computing task, the generating of the sequence of gates comprising: identifying, in the sequence of gates, a two-qubit gate to be applied to two qubits of a quantum computing system, the two-qubit gate being associated with Weyl coordinates x, y, and z; determining a dynamically decoupled driving gate locally equivalent to the two-qubit gate, the determining of the dynamically decoupled driving gate comprising: determining a gate time for the dynamically decoupled driving gate; and determining a first amplitude of a first dynamically decoupled driving associated with a first qubit of the two qubits using: the gate time; a sum of the y and z coordinates; and a difference of the y and z coordinates; a difference between the y and z coordinates; including the dynamically decoupled driving gate in the sequence of gates, at least partially in place of the two-qubit gate; and providing instructions to apply the sequence of gates to the quantum computing system, and obtaining an output from the quantum computing system.

16. The non-transitory computer-readable medium of claim 15, wherein: determining the gate time using: an interaction strength of the two qubits; and the x coordinate.

17. The non-transitory computer-readable medium of claim 16, wherein: determining the gate time comprises: determining a minimum gate time such that, under an equivalence condition, a product of the interaction strength and the gate time is equivalent to the x coordinate.

18. The non-transitory computer-readable medium of any one of claims 15 to 17, wherein: determining the gate time comprises: determining a set of candidate gate times that satisfy an x coordinate equivalence condition; and selecting one candidate gate time from the set of candidate gate times as the gate time.

19. The non-transitory computer-readable medium of claim 18, wherein: the one candidate gate time is selected from the set of candidate gate times using a sum of magnitudes of the y coordinate and the z coordinate.

20. The non-transitory computer-readable medium of any one of claims 15 to 19, wherein: the determining of the dynamically decoupled driving gate further comprises: determining a second amplitude of a second dynamically decoupled driving associated with a second qubit of the two qubits; wherein a sum of the first amplitude and the second amplitude depends on a sum of the y and z coordinates; and a difference between the first amplitude and the second amplitude depends on a difference between the y and z coordinates.

21. An apparatus for performing quantum computations, comprising: a processor; a memory configured to store executable instructions for the processor; wherein the processor is configured to read the executable instructions from the memory and execute the instructions to implement the method of any one of claims 9 to 14.

22. A computer program product, comprising: computer program instructions that enable a computer to perform the method of any one of claims 9 to 14.

23. A computer program, wherein, the computer program enables a computer to perform the method of any one of claims 9 to 14. the computer program enables a computer to perform the method of any one of claims 9 to 14.

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