Wheel speed detection device and chip system

Abstract

The application provides a wheel speed detection device and a chip system. The wheel speed detection device comprises a first comparator, a second comparator and a signal analyzer. The first comparator and the second comparator are respectively configured with different reference voltages. The input end of the first comparator and the input end of the second comparator are used for receiving a voltage signal generated by a same wheel speed sensor. The signal analyzer is used for analyzing wheel speed information from a first comparison signal output by the first comparator and a second comparison signal output by the second comparator. In this way, the input signal is judged by a double-comparator structure with multiple thresholds, so that sensor signals of different current levels can be uniformly recognized and analyzed, and compatible processing of various protocol sensor signals is realized. Thus, the overall system cost rising problem caused by hardware redundancy and system complexity rising in the traditional scheme is avoided, and the versatility and integration capability of the interface module are effectively improved in a low-cost manner.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of automobiles, and in particular, to a wheel speed detection device and a chip system. BACKGROUND

[0002] Wheel speed sensors, as the core sensing elements of modern vehicle active safety systems, play an irreplaceable role in Anti-lock Braking System (ABS), Electronic Stability Control (ESC), Traction Control System (TCS), and emerging autonomous driving functions. The core function is to monitor the rotational speed of the wheel in real time and convert mechanical motion into an electrical signal that can be recognized by the electronic control system. Among them, the Hall effect sensor is the mainstream, and this type of sensor is based on the principle that the change of magnetic field causes the potential difference. During the rotation of the wheel, by detecting the change of the tooth groove structure of the magnetic target wheel, a corresponding pulse current signal is generated.

[0003] Different types of wheel speed sensors present diversified communication protocol standards at the signal output end. However, the existing decoding schemes generally have the problem of single protocol support. Application-Specific Integrated Circuit (ASIC) is usually designed to optimize for a specific protocol, for example, Hall sensor dedicated ASIC mainly focuses on processing standard square wave protocol, while AK protocol needs a separate receiving chip for decoding. When the system needs to support multiple types of sensors at the same time, it often has to use multiple parallel decoding circuits, which not only significantly increases the hardware complexity, but also increases the overall system cost. SUMMARY

[0004] In order to overcome at least one of the deficiencies in the prior art, the present application provides a wheel speed detection device and a chip system, specifically comprising:

[0005] In a first aspect, the present application provides a wheel speed detection device, which comprises a first comparator, a second comparator and a signal parser.

[0006] The first comparator and the second comparator are respectively configured with different reference voltages, and the input end of the first comparator and the input end of the second comparator are used to receive the voltage signal generated by the same wheel speed sensor.

[0007] The signal parser is used to parse the wheel speed information from the first comparison signal output by the first comparator and the second comparison signal output by the second comparator.

[0008] In a second aspect, the application provides a chip system, comprising a processor and the wheel speed detection device.

[0009] Compared with the prior art, the application has the following beneficial effects:

[0010] The application provides a wheel speed detection device and a chip system. The wheel speed detection device comprises a first comparator, a second comparator and a signal analyzer. The first comparator and the second comparator are respectively configured with different reference voltages. The input end of the first comparator and the input end of the second comparator are used to receive a voltage signal generated by a same wheel speed sensor. The signal analyzer is used to analyze wheel speed information from a first comparison signal output by the first comparator and a second comparison signal output by the second comparator. In this way, the input signal is subjected to multi-threshold judgment by using a double-comparator structure, so that sensor signals of different current levels can be uniformly recognized and analyzed, and compatible processing of various protocol sensor signals is realized. Thus, the problem of rising overall system cost caused by hardware redundancy and rising system complexity in the traditional scheme is avoided, and the versatility and integration capability of the interface module are effectively improved in a low-cost manner. BRIEF DESCRIPTION OF DRAWINGS

[0011] In order to more clearly illustrate the technical solutions of the embodiments of the application, the following will briefly introduce the drawings needed to be used in the embodiments. It should be understood that the following drawings only show some of the embodiments of the application, and therefore should not be regarded as a limitation on the scope. For those skilled in the art, other related drawings can also be obtained without creative labor on the basis of these drawings.

[0012] Figure 1 A contrast diagram of various wheel speed protocols provided for the embodiments of the application;

[0013] Figure 2 A whole structure diagram of the wheel speed detection device provided for the embodiments of the application;

[0014] Figure 3 A conversion principle diagram of the current signal and the voltage signal provided for the embodiments of the application;

[0015] Figure 4 A structure diagram of the signal analyzer provided for the embodiments of the application;

[0016] Figure 5 An input signal diagram of the preprocessing module provided for the embodiments of the application;

[0017] Figure 6 One of the structure diagrams of the preprocessing module provided for the embodiments of the application;

[0018] Figure 7Structure diagram two of the preprocessing module provided by the embodiment of the present application;

[0019] Figure 8 Principle diagram of the working clock provided by the embodiment of the present application;

[0020] Figure 9 Structure diagram of the signal analysis module provided by the embodiment of the present application;

[0021] Figure 10 State change diagram provided by the embodiment of the present application;

[0022] Figure 11 Connection diagram of the interrupt module provided by the embodiment of the present application;

[0023] Figure 12 Register interaction relationship diagram provided by the embodiment of the present application. DETAILED DESCRIPTION

[0024] In order to make the purpose, technical scheme and advantages of the embodiments of the present application (hereinafter referred to as the present embodiments) clearer, the technical scheme of the present embodiments will be described clearly and completely in combination with the drawings in the present embodiments. Obviously, the described embodiments are some of the embodiments of the present application, but not all the embodiments. The components of the present embodiments described and shown in the drawings herein can be arranged and designed in various different configurations.

[0025] Therefore, the following detailed description of the embodiments of the present application provided in the drawings is not intended to limit the scope of the claimed present application, but only represents selected embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts belong to the scope of protection of the present application.

[0026] It should be noted that: similar reference numbers and letters represent similar items in the following drawings, therefore, once an item is defined in one drawing, it does not need to be further defined and explained in the subsequent drawings.

[0027] In the description of the present application, it should be noted that the terms "first", "second", "third", etc. are only used to distinguish the description and cannot be understood as indicating or implying relative importance. In addition, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "includes a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0028] In addition, in the description of the present application, it should be noted that unless otherwise explicitly specified and limited, the terms "set", "mount", "connect", "connect" should be understood broadly, for example, it can be fixedly connected, or it can be detachably connected, or integrally connected; it can be mechanically connected, or it can be electrically connected; it can be directly connected, or it can be indirectly connected through an intermediate medium, or it can be the communication inside two elements. For those skilled in the art, the specific meaning of the above terms in the present application can be understood according to the specific circumstances.

[0029] Based on the above statement, considering that the present embodiment relates to a plurality of wheel speed measurement protocols, in order to make the scheme introduced next more easily understood, the following first combines Figure 1 The plurality of wheel speed measurement protocols that the present embodiment can involve are explained and described.

[0030] The plurality of wheel speed measurement protocols described herein include the standard square wave protocol, the pulse width modulation (PWM) protocol, and the AK protocol as examples for more intuitive description. It should be noted that based on the sensors of these protocols, the present embodiment divides the output current into three levels: high, medium and low. The high current is 28mA, represented by the symbol , the medium current is 14mA, represented by the symbol , and the low current is 7mA, represented by the symbol .

[0031] The standard square wave protocol is the most basic wheel speed output form, which calculates the wheel speed by the number of pulses in a unit of time. This protocol is simple to implement and has a relatively low cost, but its limitation is that it cannot provide rotation direction information and has relatively weak anti-interference ability. The output current is divided into two nominal levels: medium current 14mA and low current 7mA. In the decoding process, the cycle of the captured pulse signal is used to accurately measure the speed.

[0032] PWM protocol, which embeds width modulation information in the pulse signal, can not only measure the wheel speed but also transmit additional information such as the rotation direction. Its advantage lies in good protocol compatibility, suitable for various types of wheel speed sensors. However, this protocol requires a dedicated decoding circuit to analyze the duty cycle of the pulse to obtain valid data. The output current is also divided into two nominal levels: medium current 14mA and low current 7mA. In the decoding process, the width and period of the pulse need to be captured simultaneously to accurately identify the speed and direction.

[0033] AK protocol, which uses current amplitude modulation technology, encodes and transmits information such as wheel speed, rotation direction, air gap state, and parity check through three levels of current changes: 7mA, 14mA, and 28mA. This protocol has strong anti-interference ability, especially suitable for complex working environments such as electric vehicles with high electromagnetic noise. However, its receiving end requires a relatively complex circuit design to convert the current signal into a voltage square wave signal that the microcontroller can recognize. In the decoding process, the current level needs to be identified first, and the timestamp information of the edge needs to be further analyzed to extract the complete data content. When the wheel is in a stationary state, the AK protocol supports a stationary protocol mode, in which the speed pulse switches to a medium current state, and the interval between adjacent pulses is about 150ms, used to feedback the wheel stationary state to the control system.

[0034] Based on the above description of various wheel speed measurement protocols, to solve the problem of single protocol support in existing decoding schemes, dedicated integrated chip solutions, discrete component combined with basic microcontroller unit (MCU) solutions, and software decoding solutions were proposed during the research process. These solutions require support for multiple types of wheel speed sensors, and all have significantly increased hardware complexity and system cost.

[0035] Firstly, in the dedicated integrated chip solution, since the protocol decoding logic is fixed inside the chip, a single chip can only handle one specific protocol type. Therefore, if you want to support multiple protocols such as standard square wave, PWM, and AK, you must configure a corresponding dedicated chip for each protocol. This parallel deployment method not only significantly increases the printed circuit board area, but also increases the bill of materials cost, and also brings challenges to supply chain management, as different chips may face different supply cycles and replacement risks.

[0036] Secondly, in the scheme of using discrete components combined with the basic MCU, although the dependence on special chips is removed, due to the differences in signal processing requirements of different protocols, especially the complex protocol such as AK protocol, the current output needs to be additionally designed with a current-voltage conversion circuit to adapt to the input interface of the MCU, which makes the front-end circuit of each channel complex and difficult to unify. In addition, due to the different processing procedures required by each protocol, for example, PWM needs to measure the pulse width, and AK protocol involves Manchester code analysis, therefore, the analog front-end and software logic need to be designed independently for each protocol, which causes the peripheral circuit to be unable to be reused, further increasing the consumption of hardware resources and the implementation difficulty of the overall system.

[0037] Finally, even in the software decoding scheme, although it has high flexibility, in order to cope with the data structure and decoding rules of different protocols, multiple decoding algorithm instances must be run, and high-precision timers are frequently used to capture edge information, combined with interrupt or DMA mechanism for data transmission. This scheme will occupy a large amount of CPU operation time and memory resources, especially for a multi-channel system, the computational load increases exponentially, which leads to the need to select a higher performance MCU, thereby increasing the overall cost of the system. At the same time, in order to ensure real-time performance, additional hardware auxiliary modules such as high-speed ADC or external interrupt controllers also indirectly exacerbate the hardware complexity and power consumption problems.

[0038] Therefore, when facing the demand of supporting multiple protocols, the existing decoding schemes cannot effectively avoid the problems of resource redundancy, circuit complexity, and cost increase, no matter through hardware replication, peripheral expansion, or software superposition.

[0039] Based on the discovery of the above technical problems, the following technical solutions are proposed after creative labor to solve or improve the above problems. It should be noted that the defects in the above prior art schemes are the result of careful research and practice, therefore, the discovery process of the above problems and the solutions proposed by the embodiments of the present application to solve the above problems should be considered as contributions to the present application in the process of invention and creation, and should not be understood as technical content known to those skilled in the art.

[0040] Therefore, the present embodiment provides a wheel speed detection device. As shown in Figure 2 The wheel speed detection device includes a first comparator 12, a second comparator 13, and a signal parser 11.

[0041] The first comparator 12 and the second comparator 13 (hereinafter referred to as double comparators) are respectively configured with different reference voltages, and the input end of the first comparator 12 and the input end of the second comparator 13 are used to receive the voltage signal generated by the same wheel speed sensor.

[0042] The signal resolver 11 is configured to resolve wheel speed information from the first comparison signal output by the first comparator 12 and the second comparison signal output by the second comparator 13.

[0043] In this way, unlike the prior art which relies on a dedicated decoding chip or independent external circuit to process a specific protocol, the wheel speed detection device in this embodiment is configured with different reference voltages for the first comparator 12 and the second comparator 13, and both of them receive voltage signals from the same wheel speed sensor, thereby achieving compatible processing of signals from sensors of multiple protocols. This avoids the problem of rising overall system cost due to hardware redundancy and rising system complexity in the conventional solution, and effectively improves the versatility and integration capability of the interface module at a low cost.

[0044] It should be understood that, considering that most wheel speed sensors directly output current signals, in this embodiment, the input of the first comparator 12 and the input of the second comparator 13 of the wheel speed detection device are configured to receive voltage signals generated by the same wheel speed sensor. For this purpose, an external passive resistor-capacitor (RC) conversion circuit can be used to convert the current signal output by the wheel speed sensor into a voltage signal for processing by the comparator. The wheel speed sensor here refers to a current-type sensor that outputs a standard square wave protocol, a PWM protocol, or an AK protocol, and its output signal represents speed information in the form of different levels of current.

[0045] Specifically, as shown in Figure 3 , in actual application, the current output signal of the wheel speed sensor 14 is converted into a voltage signal through a passive RC network composed of a resistor and a capacitor , where is used to convert the current signal (e.g., 7 mA, 14 mA, 28 mA) output by the sensor into a corresponding voltage signal , and the calculation formula is . Since the first comparator 12 and the second comparator 13 are configured with different reference voltages and , the value of must ensure that the generated can effectively cover these two reference voltage thresholds, and leave a proper margin (usually 5% to 10%) to ensure that the comparator can accurately identify the voltage level corresponding to different current states.

[0046] For the above reference voltages and The current can be generated by an internal Digital-to-Analog Converter (DAC). That is, by precisely configuring the register to adapt to different sensor specifications or compensate for temperature drift. The configuration needs to meet and reserve enough margin. In addition, for sensors that adopt standard square wave protocol or PWM protocol and support high safety levels such as ASIL D, there may be additional current information, and the output current signal in working mode will not be lower than 3.5 mA. For such sensors, the first comparator 12 can be multiplexed by register and parameter configuration to adjust the reference voltage VREFH (e.g. 5mA*R0) of the dual-comparator module to monitor the input voltage. If the voltage is lower than the set threshold, the sensor abnormal flag is set, and an interrupt is generated according to the configuration. In this way, the input voltage can be monitored to determine whether it is lower than a certain set threshold, thereby determining whether the sensor is in an abnormal working state.

[0047] It should be noted that in the wheel speed sensor for supporting PWM protocol or standard square wave protocol, since these protocols only involve two current states (e.g. 14 mA and 7 mA), there is no need to identify the high current level of 28 mA. Therefore, the comparator in the dual comparator related to the current 28 mA can be selectively turned off to reduce power consumption. At the same time, the subsequent processing logic related to this comparator, such as filtering processing, XOR operation, and edge detection modules, can also be turned off or enter low-power mode accordingly, thereby further reducing system power consumption and improving overall energy efficiency.

[0048] Further, the selection of the capacitance mainly affects the filtering characteristics and response time of the signal. A larger value can enhance the suppression ability of high-frequency noise, but will prolong the rising and falling time of the signal, affecting the capture of rapidly changing signals; while a smaller value improves the response speed, but may introduce more noise interference. Therefore, in actual implementation, adaptive selection can be made according to the specific sensor characteristics, noise level of the working environment, and required signal integrity requirements.

[0049] The above current, after being processed by the RC conversion circuit, the voltage signal is sent to the input terminals of the first comparator 12 and the second comparator 13. The two comparators judge the input signal based on their respective reference voltages and output the corresponding logic state combination. For example, under the AK protocol, when corresponding to 7 mA current, is lower than and , both comparators output low level; when corresponding to 14 mA current, Vin is higher than but lower than , only the second comparator 13 outputs a high level; while when corresponding to a 28mA current, higher than , both comparators output a high level. In this way, the signal parser 11 can accurately identify the communication protocol used by the current sensor and the speed and direction information it carries according to the state combination of the two comparison signals. In addition, as an optional implementation, if the protocol is PWM and standard square wave, the 28mA comparator can be omitted to save power consumption.

[0050] As shown in Figure 4 , the signal parser 11 includes a preprocessing module 111 and a signal parsing module 112, and the reference voltage of the first comparator 12 is greater than that of the second comparator 13.

[0051] The preprocessing module 111 is configured to perform an exclusive-OR operation on the first comparison signal and the second comparison signal to obtain a composite signal, and obtain a plurality of edge trigger signals generated by the composite signal and the first comparison signal.

[0052] The signal parsing module 112 is configured to parse wheel speed information from the plurality of edge trigger signals.

[0053] In this embodiment, the preprocessing module 111 of the wheel speed detection device is configured to perform an exclusive-OR operation on the first comparison signal and the second comparison signal to generate a composite signal, and obtain a plurality of edge trigger signals generated by the composite signal and the first comparison signal. Therefore, the preprocessing module 111 relies on two digital signals output by the dual-comparator module, which are respectively represented as and , wherein corresponds to the output state of the first comparator 12, corresponds to the output state of the second comparison signal, and the combination (00, 01, 11) of the two represents the low current (such as 7mA), the medium current (such as 14mA) and the high current (such as 28mA) state of the sensor output.

[0054] Specifically, in the application scenario of the AK protocol, in order to realize independent parsing of the Manchester encoded data bit and separate timing and decoding logic, the preprocessing module 111 combines and by performing an exclusive-OR operation to generate a composite signal , the expression of which is . This operation allows input signals at different current levels to be mapped into a composite signal with clear logic characteristics. For example:

[0055] When the low current (7mA) is ;

[0056] Medium current (14mA), ;

[0057] High current (28mA), .

[0058] Thus, The signal can effectively distinguish the medium current state from the other two states, thereby providing a clear logical basis for subsequent edge detection and decoding.

[0059] The pre-processing module 111 extracts a plurality of edge trigger signals based on the generated composite signal and the first comparison signal (for ease of comparison with the composite signal , also known as signal). Among them, The signal directly comes from the output of the first comparator 12, which is used to represent the high current state (28mA), and its rising edge is used as the main timing trigger event of the speed pulse; while The signal is used to drive the data bit analysis of the Manchester encoding (in the static protocol mode of the AK protocol, when the wheel is in a static state, The signal is always low and cannot provide an effective speed pulse trigger signal, while the sensor output is in a medium current state (14mA) ; to achieve effective recognition and reporting of the static state, The rising edge of the signal is used as an alternative trigger source, so the rising edge of the signal The rising edge of the signal will be regarded as the timing trigger event of the speed pulse). By synchronously sampling and edge detecting these two signals, a plurality of independent edge trigger signals (such as ) can be generated, which are sent to the signal analysis module 112 as key trigger sources, thereby analyzing the wheel speed information.

[0060] During the research process, it was found that some sensors directly output current signals, which need to be converted into voltage signals by external resistors before being sent to the comparator for processing; while some other sensors may have built-in first comparator 12 and second comparator 13, and can directly output digital signals after comparison processing. Therefore, in actual application, the pre-processing module 111 needs to have the ability to flexibly select the input signal path to adapt to various physical implementation methods.

[0061] Therefore, as shown in Figure 5 , the pre-processing module 111 includes a first input interface and a second input interface, and the pre-processing module 111 is connected with the output terminals of the first comparator 12 and the second comparator 13 through the first input interface; the second input interface is used to connect the wheel speed sensor 14 with the first comparator 12 and the second comparator 13.

[0062] The wheel speed detection device further comprises a mode configuration register of the preprocessing module 111, which is configured to select the first input interface and the second input interface by the preprocessing module 111.

[0063] Therefore, the preprocessing module 111 sets two input interfaces, the first input interface is used to receive the signal converted by the external RC circuit and processed by the double comparator (Vdiff) 、 ); and the second input interface is used to connect the wheel speed sensor 14 integrated with the first comparator 12 and the second comparator 13, so as to directly obtain the comparison signal (Vcomp) 、 ) outputted by the wheel speed sensor 14. In order to realize the switching control between the two input interfaces, the wheel speed detection device further comprises a mode configuration register, which is configured to determine which input interface is used by the preprocessing module 111 as the current effective signal source by software configuration.

[0064] It is found in practice that, since is the product of combinational logic, its generation depends on the synchronization of the two comparator output signals, and in actual circuits, due to the influence of factors such as XOR gate delay, comparator response time difference and wiring, a short glitch may be generated at the edge of . In contrast, is the original output directly from the comparator, with shorter path and higher stability. There is an inherent asymmetry between the two in terms of signal path length, propagation delay and stability characteristics, and this difference is particularly obvious in high-speed or high-noise environments, which may cause the subsequent edge detection to be triggered by mistake, thereby affecting the accurate analysis of the wheel speed information.

[0065] In view of this, as shown in Figure 6 , the preprocessing module 111 comprises a filtering unit 1111 and a sampling unit 1112.

[0066] The filtering unit 1111 is configured to perform XOR operation on the first comparison signal and the second comparison signal to obtain a composite signal, and perform filtering processing on the composite signal and the first comparison signal, and transmit the filtered composite signal and the filtered comparison signal to the sampling unit 1112.

[0067] The sampling unit 1112 is configured to sample the filtered composite signal and the filtered comparison signal to obtain a plurality of edge trigger signals.

[0068] Therefore, in the wheel speed detection device provided in this embodiment, the filtering unit 1111 in the preprocessing module 111 plays a crucial role in optimizing signal quality. Specifically, the filtering unit 1111 is used to filter composite signals ( ) and the first comparison signal ( Filtering is performed to remove high-frequency noise and signal glitches that may be carried during transmission, thereby improving the stability and accuracy of subsequent processing steps.

[0069] As an optional implementation, the filtering unit 1111 introduces a configurable filtering mechanism, such as an 8th-order FIR filter structure, to... and The signals are filtered separately, and each filtering parameter (such as cutoff frequency and filter coefficients) can be independently configured via registers. Specifically, in practical applications, this can be achieved by... The signal's glitches are subjected to stronger filtering to suppress signal jitter, while also... The signal employs a relatively weak filtering strategy to preserve its timing accuracy at the edges to the greatest extent possible. This asymmetric filtering method enables improved signal quality. While maintaining signal stability, it does not affect The signal is used to ensure the accuracy of velocity pulse timing.

[0070] Furthermore, it should be understood that in the wheel speed detection device provided in this embodiment, the sampling unit 1112 is an important component of the preprocessing module 111, and its core function is to synchronously sample the composite signal after filtering and the first comparison signal in order to extract various edge trigger signals that can be used for subsequent decoding.

[0071] like Figure 7 As shown, when the preprocessing module 111 provides a first input interface and a second input interface, the preprocessing module 111 further includes an interface selection unit 1114 and a protocol selection unit 1113. The interface selection unit 1114 is used to select the signal from the first input interface or the second input interface for processing based on the mode configuration information in the mode configuration register. The protocol selection unit 1113 is used to selectively process the first comparison signal and the second comparison signal based on the configuration information provided by the user in the protocol selection register.

[0072] like Figure 8 As shown, the filtered Signals and The signal is input to the sampling unit 1112 and is synchronously sampled under the driving of the working clock provided by the functional clock division module. The working clock is generated from the processor main clock via the division logic, and its frequency can be flexibly configured according to the timing requirements of different protocols, for example, in the range of 1-2 MHz, so as to ensure sufficient time resolution for signal changes under different protocols. The filtered signal is periodically sampled by the clock, which can effectively eliminate the metastable state problem introduced by signal asynchrony, improve the signal stability and ensure its consistency under the clock domain inside the module. With the signal being periodically sampled by the clock, the metastable state problem introduced by signal asynchrony can be effectively eliminated, the signal stability can be improved, and the consistency of the signal under the clock domain inside the module can be ensured.

[0073] Specifically, on the basis of completing signal synchronization, the sampling unit 1112 further identifies and captures the rising edge and falling edge events in the signal, and then generates multiple independent edge trigger signals, including but not limited to: the rising edge of the first comparison signal (denoted as ), the falling edge of the first comparison signal (denoted as ), the rising edge of the composite signal (denoted as ), and the falling edge of the composite signal (denoted as ). These multiple edge trigger signals serve as key timestamp information for driving the start, stop and latching operations of the subsequent counting unit 1121, and also provide accurate trigger conditions for the state machine conversion in the subsequent decoding unit 1122.

[0074] As shown in Figure 9 , the signal analysis module 112 includes a counting unit 1121 and a decoding unit 1122;

[0075] The decoding unit 1122 is configured to decode the wheel speed information according to the counting results of the counting unit 1121 on the multiple edge trigger signals.

[0076] In this embodiment, the wheel speed detection device supports wheel speed sensors 14 of multiple protocols, including standard square wave protocol, PWM protocol and AK protocol. The wheel speed detection device further includes a protocol selection register of the counting unit 1121 and multiple counting registers provided for the multiple protocols.

[0077] The counting unit 1121 is configured to determine a target protocol from the multiple protocols according to configuration information in the protocol selection register.

[0078] According to the target protocol, a target edge trigger signal is selected from the multiple edge trigger signals, and a target counting register corresponding to the target protocol is selected from the multiple counting registers.

[0079] The counting unit 1121 is further configured to write the statistical result of the target edge trigger signal into the target counting register.

[0080] It can be understood that the counting unit 1121 as a key hardware module for implementing multi-protocol compatible decoding, the design goal is to adapt to a variety of mainstream wheel speed sensor 14 output protocols, including standard square wave protocol, PWM protocol and AK protocol. In order to meet the differentiated needs of signal feature extraction of different protocols, the counting unit 1121 adopts a configurable and multiplexed hardware architecture, and cooperates with a plurality of special counting registers through a protocol selection register, to realize flexible processing and efficient statistics of a plurality of edge trigger signals.

[0081] In the working process of the counting unit 1121, first, according to the information configured in the protocol selection register, the specific communication protocol adopted by the wheel speed sensor 14 to be analyzed is identified. The protocol selection information is written by external software through register configuration, which is used to guide the counting unit 1121 to select the correct signal processing logic and register resource in subsequent operation. After determining the target protocol, the counting unit 1121 selects the target edge trigger signal suitable for the current protocol from a plurality of edge trigger signals according to the protocol characteristics, and selects the target counting register corresponding to the current protocol from a plurality of counting registers for storing the corresponding count value. It should be noted that the plurality of counting registers can be shared and multiplexed by a plurality of protocols, or partially multiplexed according to the protocol characteristics, or each protocol corresponds to a dedicated counting register.

[0082] Exemplarily, the plurality of counting registers in the embodiment can be three groups of counting registers with different bit widths, namely a wheel speed counter (T, 24 bits), a high level counter (t, 18 bits) and an AK decoding counter (tdec, 12 bits). Each counter has different functional roles and is dynamically enabled according to the selected protocol. Among them, the wheel speed counter is shared by AK protocol, PWM protocol and standard square wave protocol, the high level counter is shared by AK protocol and PWM protocol, and the AK decoding counter is exclusively used by AK protocol.

[0083] Under the standard square wave protocol or PWM protocol, the wheel speed counter T and the high level counter t are mainly used, wherein T is used to measure the period, and t is used to measure the pulse width (i.e. duty cycle), both of which are latched at the rising edge of the next as the start signal. The value of T is latched at the rising edge of the next , and the value of t is latched at the time.

[0084] Under the AK protocol, in addition to the wheel speed counter T, the high level counter t and the AK decoding counter tdec are also enabled, wherein the wheel speed counter T is still used to measure the speed pulse period, but is latched at the The drive; high level counter t is used to measure the duration of the high level as the time reference of Manchester decoding; AK decoding counter tdec is used to measure the transition interval within the bit interval, which is started by the falling edge of the speed pulse (as ) and reset and latch the current count value at each transition edge.

[0085] In addition, in the present embodiment, in order to meet the requirement of counting the total number of wheel speed pulses within a given time, an edge-triggered accumulation mode is also provided in the counting unit. In this mode, the wheel speed counter T is multiplexed as an accumulator for recording the number of wheel speed pulses received within a specified time length. Specifically, when the register is configured in this functional mode, different trigger signals are selected according to the type of protocol adopted, as follows:

[0086] For standard square wave protocol and PWM protocol, the wheel speed counter T is configured to be triggered by the rising edge of the signal;

[0087] For AK protocol, the counting is triggered in two ways. When it is in the non-stationary protocol mode, the wheel speed counter T is configured to be triggered by the rising edge of the signal; when it is in the stationary protocol mode, the wheel speed counter T is configured to be triggered by the rising edge of the signal.

[0088] At the same time, the wheel speed detection device also provides a dedicated timing counter for the edge-triggered accumulation mode, which is only enabled in this functional mode and is used to set the specified time length. This timing counter counts based on the system clock, and when its count value reaches the specified time length, it indicates that the given time window has ended. At this time, the wheel speed counter T will latch its current cumulative value, which is the total number of wheel speed pulses accumulated within that time period. This latched value can be read through the register, and the interrupt module can be configured to send an interrupt notification to the processor to inform the CPU of the wheel speed pulse statistics within the current time period.

[0089] Therefore, the design of the counting unit 1121 fully considers the requirements of different protocols for signal feature extraction, and achieves dynamic scheduling and functional multiplexing of hardware resources through register configuration. This structure not only improves the adaptability of the system to various wheel speed sensor 14 protocols, but also reduces the occupation of processor calculation, and reduces the complexity and power consumption of the overall system. In addition, each counter also integrates an error detection mechanism, such as generating an overflow error flag when the count overflows, further enhancing the robustness and reliability of the device in complex electromagnetic environments.

[0090] ​​​Taking the AK protocol as an example, when the target protocol is the AK protocol, the decoding unit 1122 realizes the decoding operation of the AK protocol through a hardware state machine.

[0091] The decoding unit 1122 is configured to obtain the duration of the composite signal from the counting unit 1121 when the first comparison signal generates a falling edge, and wait for a jump edge of the composite signal;

[0092] After the jump edge of the composite signal is generated, the jump time interval of the composite signal is obtained from the counting unit 1121;

[0093] If the jump time interval is equal to the duration, it is determined that it is a valid Manchester encoding edge, and the wheel speed information is decoded;

[0094] If the jump time interval is half of the duration, the next jump edge of the composite signal is continued to be waited for;

[0095] After the next jump edge of the composite signal is detected, the jump time interval of the next jump edge is obtained from the counting unit 1121;

[0096] If the jump time interval of the next jump edge is half of the duration, it is determined that it is a valid Manchester encoding edge, and the wheel speed information is decoded.

[0097] It should be understood that the hardware state machine here specifically refers to a logic structure based on a finite state transition mechanism, which aims to automatically determine the current decoding stage according to the input of various edge trigger signals and their time interval information, and perform corresponding data analysis and error detection actions according to the preset state transition rules. The hardware state machine includes eight functional states, namely IDLE, START, TOGGLE, WAIT, TOGGLE2, DECODER, ERROR and TIMEOUT.

[0098] Specifically, as shown in Figure 10 When the target protocol is the AK protocol, the falling edge of the speed pulse (usually signal) triggers the hardware state machine to enter the START state, at this time the high-level counter t in the counter module starts to latch the time reference value , that is, the duration of the current speed pulse is measured.

[0099] In the START state, the state machine waits for a jump edge trigger condition from the signal. Once the jump edge of the signal is detected, the TOGGLE state is entered, and the time interval of the occurrence of the jump edge is recorded through the AK decoding counter tdec. On this basis, the state machine will determine whether the jump edge is a valid Manchester encoding edge according to the AK decoding counter tdec and the time reference value the time interval is equal to the half of the time reference value, it is determined that the current transition edge is a compensatory one, and the state machine enters the WAIT state to wait for the arrival of the next transition edge.

[0100] In the WAIT state, the next transition edge of the signal is continuously monitored . Once a new transition edge is detected, the state machine enters the TOGGLE2 state and records the time interval of the transition edge again by the AK decoding counter. If the time interval is also equal to the half of the time reference value at this time, it is considered that the transition edge has completed the compensatory double-edge feature required by the Manchester coding, and the state machine enters the DECODER state to complete the final analysis of the data bit.

[0101] Conversely, if the time interval is neither equal to the time reference value nor equal to the half of the time reference value is detected in the TOGGLE or TOGGLE2 state, the state machine will enter the ERROR state, indicating that there is an abnormality in the format or timing in the current decoding process, and triggering the corresponding error flag and diagnosis process.

[0102] In addition, if the expected transition edge cannot be detected in time within the entire decoding period, for example, due to the interruption of sensor communication or signal loss, causing the wheel speed counter T to exceed the preset maximum allowed period value, the state machine will enter the TIMEOUT state, generate a timeout exception flag and notify the upper layer control module to respond to the fault. As can be seen, through strict state division and transition rules, the hardware state machine can effectively identify different types of Manchester coding modes, and has strong fault tolerance and real-time response characteristics, thereby ensuring the reliability and accuracy of the decoding process.

[0103] For example, in actual application, if the wheel speed sensor 14 adopts the AK protocol to output a set of data streams with Manchester coding, each bit of which contains two edge transitions, then the hardware state machine will enter the START state at the first falling edge and latch the time reference value , and then enter the TOGGLE state when the first transition edge arrives and determine whether the transition edge falls within the half of the time reference value . If so, the state machine enters the WAIT state to wait for the second transition edge, and confirms that it also occurs at the time reference value ​After half of the time point, the wheel speed detection device enters the DECODER state to complete the data bit analysis. In this way, the state machine is adapted to the characteristics of Manchester coding, and the ability to maintain stable communication in a complex electromagnetic environment is also exhibited.

[0104] The research found that in the traditional wheel speed sensor 14 signal decoding scheme, especially in the implementation mode that relies on software decoding or general peripherals for wheel speed data acquisition, the processor often needs to continuously check the status of the relevant register through the polling mechanism to determine whether a valid wheel speed information collection is completed. This mechanism not only consumes a lot of computing resources, but also may cause a delay in the response of critical control tasks, affecting the overall real-time performance of the system.

[0105] In view of this, as shown in the wheel speed detection device also includes an interrupt module 113; Figure 11

[0106] The interrupt module 113 is used to send a notification of reading wheel speed information to the connected processor in the form of an interrupt.

[0107] Therefore, when the wheel speed detection device completes the signal analysis from the wheel speed sensor 14, and outputs the corresponding comparison signal through the first comparator 12 and the second comparator 13, and then extracts the wheel speed information by the signal analyzer 11, the information is stored in the internal register, and the interrupt module 113 generates an interrupt request. The role of the interrupt module 113 is to actively notify the connected processor to read the relevant data and state information in a timely manner when a specific event occurs (for example: wheel speed count is valid, decoding error, timeout exception, etc.), rather than relying on the processor to periodically query whether the data is ready. Therefore, the processor only intervenes in the processing when there is data to read or an abnormal situation exists, thereby significantly reducing unnecessary polling operations and improving the utilization efficiency of system resources.

[0108] As shown in Figure 12 Since the registers of the preprocessing module 111, the signal analysis module 112, and the interrupt module 113 are provided with corresponding registers for user configuration and processor reading, the interaction details between these modules and registers are directly displayed in the figure.

[0109] In summary, the wheel speed detection device provided in the embodiment realizes compatible processing of three mainstream wheel speed sensor 14 protocols, namely standard square wave, PWM, and AK, without the need for independent external decoding chips or special circuits for different protocols, thereby significantly improving the protocol adaptation ability and development flexibility of the system.

[0110] ​Secondly, by highly integrating signal conditioning, protocol analysis and error diagnosis functions in the wheel speed detection device, and only needing a simple external RC circuit to realize current-voltage conversion, not only the bill of materials cost is reduced, but also the printed circuit board area occupation is reduced, and the integration and reliability of the system are further improved.

[0111] At the same time, the core decoding function is realized by hardware logic, avoiding the high consumption of processor resources in the traditional software decoding scheme, significantly saving the computing power of the processor, and reserving sufficient resource space for more complex control tasks.

[0112] In addition, in terms of signal processing stability and safety, the anti-interference ability in a complex electromagnetic environment is effectively improved through the built-in filter unit 1111, hysteresis comparison and hardware state machine mechanism, and rich error detection flags are introduced to enhance the system's diagnostic ability and fault response mechanism, meeting the high requirements of functional safety level (such as ASIL D). Finally, the wheel speed detection device adopts modular design and standard register interface, so that the module can be flexibly transplanted to different platforms, facilitating rapid deployment and reuse in the vehicle control system, and improving the development efficiency and system expansibility.

[0113] Based on the wheel speed detection device provided in the above embodiment, the embodiment further provides a chip system, which includes the wheel speed detection device in the above embodiment and a processor.

[0114] It can be understood that by co-packaging the wheel speed detection device with multi-protocol compatibility and the processor in a single chip, efficient acquisition, analysis and processing of signals from various types of wheel speed sensors 14 are realized. The chip system not only inherits the technical advantages of the aforementioned wheel speed detection device in terms of protocol adaptability, hardware resource utilization and decoding efficiency, but also further improves the safety and diagnostic coverage of the system.

[0115] In the embodiment, the chip system includes a processor and a plurality of parallel configured wheel speed detection devices, each wheel speed detection device is connected to a different wheel speed sensor 14, and independently completes signal conditioning, comparison, preprocessing and decoding operations according to the respective protocol characteristics (such as standard square wave, PWM or AK). On this basis, the chip system further introduces a multi-module comparison checking mechanism, that is, by enabling the built-in comparison logic unit through register configuration, the register data in each wheel speed detection device is read in a periodic or event-driven manner. The comparison logic unit performs consistency analysis on the obtained data, and if it is found that there is a deviation between the corresponding wheel speed count values or decoding results of different modules, it is determined that a potential fault has occurred.

[0116] Exemplarily, when multiple wheel speed detection devices simultaneously access the wheel speed sensors 14 of the four wheels of the same vehicle, the wheel speed values collected by each channel should normally be consistent within a reasonable range. Once the output wheel speed information of a certain module is inconsistent with other modules due to external interference, hardware failure or communication anomaly, the comparison logic unit will first set the global fault flag; then, record the identified problem module number in a specific register; finally, decide whether to send an interrupt request to the processor according to the user's pre-configured interrupt strategy, so as to notify the upper-layer control system to take timely measures.

[0117] It is worth noting that the chip system can be an MCU. The MCU referred to herein is an embedded control unit, and in addition to the processor and the wheel speed detection device, the core architecture can also include memory resources (such as Flash, RAM), timer / counter modules, communication interfaces, and various special-purpose peripheral modules. Under this architecture, the wheel speed detection device, as one of the configurable hardware function modules, is directly integrated into the on-chip system of the MCU and interacts with the processor through a standard bus interface.

[0118] The processor can be an integrated circuit chip with signal processing capability, and the processor can include one or more processing cores (e.g., a single-core processor or a multi-core processor). By way of example only, the processor can include a central processing unit (CPU), an application specific integrated circuit (ASIC), an application specific instruction-set processor (ASIP), a graphics processing unit (GPU), a physics processing unit (PPU), a digital signal processor (DSP), a field programmable gate array (FPGA), a programmable logic device (PLD), a controller, a microcontroller unit, a reduced instruction set computer (RISC), or a microprocessor, or any combination thereof.

[0119] The above merely provides the various embodiments of the present application, but the protection scope of the present application is not limited thereto, and any person skilled in the art can easily think of the changes or replacements within the technical range disclosed by the present application, which should be covered in the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A wheel speed detection device characterized by comprising: The wheel speed detection device comprises a first comparator, a second comparator and a signal resolver; The first comparator and the second comparator are respectively configured with different reference voltages, the input end of the first comparator and the input end of the second comparator are used for receiving a voltage signal generated by a same wheel speed sensor, and the reference voltage of the first comparator is greater than the reference voltage of the second comparator; The signal resolver is used for resolving wheel speed information from a first comparison signal output by the first comparator and a second comparison signal output by the second comparator, and the signal resolver comprises a preprocessing module and a signal resolving module; The preprocessing module is used for performing exclusive OR operation on the first comparison signal and the second comparison signal to obtain a composite signal, and obtaining a plurality of edge trigger signals generated by the composite signal and the first comparison signal; The signal resolving module is used for resolving the wheel speed information from the plurality of edge trigger signals.

2. The wheel speed detection device according to claim 1, characterized by The preprocessing module comprises a filtering unit and a sampling unit; The filtering unit is used for performing exclusive OR operation on the first comparison signal and the second comparison signal to obtain a composite signal, and performing filtering processing on the composite signal and the first comparison signal, and transmitting the obtained filtering composite signal and filtering comparison signal to the sampling unit; The sampling unit is used for sampling the filtering composite signal and the filtering comparison signal to obtain the plurality of edge trigger signals.

3. The wheel speed detection device according to claim 1, characterized by The preprocessing module comprises a first input interface and a second input interface, the preprocessing module is connected with the output ends of the first comparator and the second comparator through the first input interface, and the second input interface is used for connecting a wheel speed sensor provided with the first comparator and the second comparator; The wheel speed detection device further comprises a mode configuration register of the preprocessing module, and the mode configuration register is used for configuring the preprocessing module to select the first input interface and the second input interface.

4. The wheel speed detection apparatus according to claim 1, characterized by The signal resolving module comprises a counting unit and a decoding unit; The decoding unit is used for decoding the wheel speed information according to a counting result of the counting unit on the plurality of edge trigger signals.

5. The wheel speed detection apparatus according to claim 4, characterized by The wheel speed detection device supports wheel speed sensors of a plurality of protocols, and further comprises a protocol selection register of the counting unit and a plurality of counting registers provided for the plurality of protocols; The counting unit is used for determining a target protocol from the plurality of protocols according to configuration information in the protocol selection register; According to the target protocol, a target edge trigger signal is selected from the plurality of edge trigger signals, and a target counting register corresponding to the target protocol is selected from the plurality of counting registers; The counting unit is further used for writing a statistical result of the target plurality of edge trigger signals into the target counting register.

6. The wheel speed detection apparatus according to claim 5, characterized by The plurality of protocols comprise a standard square wave protocol, a PWM protocol and an AK protocol.

7. The wheel speed detection apparatus according to claim 6, characterized by When the target protocol is the AK protocol, the decoding unit is configured to obtain a duration of the composite signal from the counting unit when the first comparison signal generates a falling edge; and wait for a jump edge of the composite signal; When the jump edge of the composite signal is detected, the jump time interval of the composite signal is obtained from the counting unit; If the jump time interval is equal to the duration, it is determined that the valid Manchester encoding edge, and the wheel speed information is decoded; If the jump time interval is half of the duration, the next jump edge of the composite signal is continued to be waited for; When the next jump edge of the composite signal is detected, the jump time interval of the next jump edge is obtained from the counting unit; If the jump time interval of the next jump edge is half of the duration, it is determined that the valid Manchester encoding edge, and the wheel speed information is decoded.

8. The wheel speed detection apparatus according to claim 1, characterized by The wheel speed detection device further comprises an interrupt module; The interrupt module is configured to send a notification of reading the wheel speed information to a connected processor in an interrupt manner.

9. A chip system, characterized by A wheel speed detection device and a processor are provided. The wheel speed detection device comprises a wheel speed detection device according to any one of claims 1-8 and a processor.

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